--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED toggled by the Rx task. */\r
+#define mainTASK_LED ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ LED_Toggle( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* For definition of BOARD_MCK. */\r
+#ifndef __IAR_SYSTEMS_ASM__\r
+ /* Prevent chip.h being included when this file is included from the IAR\r
+ port layer assembly file. */\r
+ #include "board.h"\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( BOARD_MCK << 1UL )\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 46 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* The full demo always has tasks to run so the tick will never be turned off.\r
+The blinky demo will use the default tickless idle implementation to turn the\r
+tick off. */\r
+#define configUSE_TICKLESS_IDLE 0\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 7 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ\r
+ * standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. As the interrupt is shared the nesting achieved is not as deep\r
+ * as normal when this test is executed, but still worth while.\r
+ *\r
+ * TC2 channel 0 provides a much higher frequency timer that tests the nesting\r
+ * of interrupts that don't use the FreeRTOS API. For convenience, the high\r
+ * frequency timer also keeps a count of the number of time it executes, and the\r
+ * count is used as the time base for the run time stats (which can be viewed\r
+ * through the CLI).\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 3 (normally 4, if the first two timers used\r
+ * separate interrupts).\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
+#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
+\r
+/* The channels used in TC0 for generating the three interrupts. */\r
+#define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */\r
+\r
+/* The bit within the RC_SR register that indicates an RC compare. */\r
+#define tmrRC_COMPARE ( 1UL << 4UL )\r
+\r
+/* The high frequency interrupt given a priority above the maximum at which\r
+interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
+timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY\r
+#define tmrHIGHER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/* For convenience the high frequency timer increments a variable that is then\r
+used as the time base for the run time stats. */\r
+volatile uint32_t ulHighFrequencyTimerCounts = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;\r
+\r
+ /* Enable the TC clocks. */\r
+ PMC_EnablePeripheral( ID_TC0 );\r
+ PMC_EnablePeripheral( ID_TC1 );\r
+\r
+ /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger\r
+ on RC compare. This is part of the IntQTimer test. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger\r
+ on RC compare. This is part of the IntQTimer test. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure and enable TC0 interrupt on RC compare. */ \r
+ NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TC0_IRQn );\r
+ NVIC_EnableIRQ( TC0_IRQn );\r
+ \r
+ /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on\r
+ RC compare. This is the very high frequency timer. */\r
+ TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_2_FREQUENCY * ulDivider );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure and enable TC1 interrupt on RC compare */ \r
+// NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );\r
+// NVIC_ClearPendingIRQ( TC1_IRQn );\r
+// NVIC_EnableIRQ( TC1_IRQn );\r
+\r
+ TC_Start( TC0, tmrTC0_CHANNEL_0 );\r
+ TC_Start( TC0, tmrTC0_CHANNEL_1 );\r
+// TC_Start( TC1, tmrTC1_CHANNEL_0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TC0_Handler( void )\r
+{\r
+ /* Read will clear the status bit. */\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TC1_Handler( void )\r
+{\r
+volatile uint32_t ulDummy;\r
+\r
+ /* Dummy read to clear status bit. */\r
+ ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR;\r
+ NVIC_ClearPendingIRQ( TC1_IRQn );\r
+\r
+ /* Keep a count of the number of interrupts to use as a time base for the\r
+ run-time stats. */\r
+ ulHighFrequencyTimerCounts++;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+BaseType_t xTimer0Handler( void );\r
+BaseType_t xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+__asm void vRegTest1Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vRegTest2Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ \r
+ /* Yield to increase test coverage. */\r
+ movs r0, #0x01\r
+ ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+ lsl r0, r0, #28 /* Shift to PendSV bit */\r
+ str r0, [r1]\r
+ dsb\r
+ \r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#include <FreeRTOSConfig.h>\r
+\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Implementation\r
+ PUBLIC vRegTest2Implementation\r
+ PUBLIC vRegTestClearFlopRegistersToParameterValue\r
+ PUBLIC ulRegTestCheckFlopRegistersContainParameterValue\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest1Implementation\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop:\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+vRegTest2Implementation\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop:\r
+\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+\r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+\r
+ /* Yield to increase test coverage. */\r
+ movs r0, #0x01\r
+ ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+ lsl r0, r0, #28 /* Shift to PendSV bit */\r
+ str r0, [r1]\r
+ dsb\r
+\r
+ pop { r0-r1 }\r
+\r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTestClearFlopRegistersToParameterValue\r
+\r
+ /* Clobber the auto saved registers. */\r
+ vmov d0, r0, r0\r
+ vmov d1, r0, r0\r
+ vmov d2, r0, r0\r
+ vmov d3, r0, r0\r
+ vmov d4, r0, r0\r
+ vmov d5, r0, r0\r
+ vmov d6, r0, r0\r
+ vmov d7, r0, r0\r
+ bx lr\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ulRegTestCheckFlopRegistersContainParameterValue\r
+\r
+ vmov r1, s0\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s1\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s2\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s3\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s4\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s5\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s6\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s7\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s8\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s9\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s10\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s11\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s12\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s13\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s14\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s15\r
+ cmp r0, r1\r
+ bne return_error\r
+\r
+return_pass\r
+ mov r0, #1\r
+ bx lr\r
+\r
+return_error\r
+ mov r0, #0\r
+ bx lr\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "TaskNotify.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The initial priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* The LED used by the check timer. */\r
+#define mainCHECK_LED ( 0 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main() to run the full demo (as opposed to the blinky demo) when\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file, but the\r
+ * entry points are kept in the C file for the convenience of checking the task\r
+ * parameter.\r
+ */\r
+static void prvRegTestTaskEntry1( void *pvParameters );\r
+extern void vRegTest1Implementation( void );\r
+static void prvRegTestTaskEntry2( void *pvParameters );\r
+extern void vRegTest2Implementation( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks has not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartInterruptSemaphoreTasks();\r
+ vStartTaskNotifyTask();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 0UL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 1UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 10UL;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 11UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 13UL;\r
+ }\r
+ \r
+ if( xAreTaskNotificationTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 14UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 15UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 16UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ LED_Toggle( mainCHECK_LED );\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry1( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest1Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry2( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest2Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+\r
+/*\r
+ * Auto generated Run-Time-Environment Component Configuration File\r
+ * *** Do not modify ! ***\r
+ *\r
+ * Project: 'RTOSDemo' \r
+ * Target: 'SRAM' \r
+ */\r
+\r
+#ifndef RTE_COMPONENTS_H\r
+#define RTE_COMPONENTS_H\r
+\r
+\r
+#endif /* RTE_COMPONENTS_H */\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
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+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>26</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>7.30.3.8061</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>ARMSIM_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCores</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreMaster</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticorePort</name>\r
+ <state>53461</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreWorkspace</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveProject</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveConfiguration</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>22</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>21</version>\r
+ <state>41</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>6</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>3</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>5.10.0.159</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>7.30.4.8186</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>default None</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>21</version>\r
+ <state>41</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>21</version>\r
+ <state>41</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>31</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>__SAMV71Q21__</state>\r
+ <state>sram</state>\r
+ <state>TRACE_LEVEL=4</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>00000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\libboard_samv7-ek</state>\r
+ <state>$PROJ_DIR$\libchip_samv7</state>\r
+ <state>$PROJ_DIR$\libchip_samv7\include\samv7</state>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\Full_Demo</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Source\portable\IAR\ARM_CM7\r0p1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>.text</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCNoLiteralPool</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategySlave</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCGuardCalls</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state>__SAM4S16C__</state>\r
+ <state>sram</state>\r
+ <state>__ASSEMBLY__</state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmNoLiteralPool</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>2</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo.bin</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>16</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IlinkOutputFile</name>\r
+ <state>RTOSDemo.out</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDebugInfoEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkConfigDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkMapFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogInitialization</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogModule</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogSection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogVeneer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile</name>\r
+ <state>$PROJ_DIR$\libboard_samv7-ek\resources\IAR\samv71q21_sram.icf</state>\r
+ </option>\r
+ <option>\r
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+ <state></state>\r
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+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
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+ <state></state>\r
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+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
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+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
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+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>__iar_program_start</state>\r
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+ <option>\r
+ <name>DoFill</name>\r
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+ <name>CrcSize</name>\r
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+ <version>0</version>\r
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+ <name>CrcInitialValue</name>\r
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+ <option>\r
+ <name>IlinkBE8Slave</name>\r
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+ <name>IlinkBufferedTerminalOutput</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
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+ <option>\r
+ <name>CrcFullSize</name>\r
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+ <option>\r
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+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
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+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
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+ <name>IlinkCrcUseAsInput</name>\r
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+ <name>IlinkCmsis</name>\r
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+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>CrcAlgorithm</name>\r
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+ <name>CrcUnitSize</name>\r
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+ <option>\r
+ <name>IlinkThreadsSlave</name>\r
+ <state>1</state>\r
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+ <settings>\r
+ <name>IARCHIVE</name>\r
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+ <option>\r
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+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
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+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
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+ </settings>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
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+ <debug>0</debug>\r
+ <settings>\r
+ <name>General</name>\r
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+ <debug>0</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
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+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Release\Obj</state>\r
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+ <option>\r
+ <name>ListPath</name>\r
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+ <name>Input variant</name>\r
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+ <state>Full formatting.</state>\r
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+ <name>Output variant</name>\r
+ <version>2</version>\r
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+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
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+ <version>0</version>\r
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+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
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+ <option>\r
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+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>default None</state>\r
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+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>0</state>\r
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+ <name>GEndianModeBE</name>\r
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+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
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+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
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+ <option>\r
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+ <option>\r
+ <name>GBECoreSlave</name>\r
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+ <name>OGUseCmsis</name>\r
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+ <name>OGUseCmsisDspLib</name>\r
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+ <name>GRuntimeLibThreads</name>\r
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+ </settings>\r
+ <settings>\r
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+ <state>3</state>\r
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+ <version>0</version>\r
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+ <name>CCOptLevelSlave</name>\r
+ <state>3</state>\r
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+ <name>CCPosIndRwpi</name>\r
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+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
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+ <name>IccCppInlineSemantics</name>\r
+ <state>0</state>\r
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+ <name>IccCmsis</name>\r
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+ <name>CCOptStrategySlave</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
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+ <name>CCGuardCalls</name>\r
+ <state>1</state>\r
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+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
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+ <version>9</version>\r
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+ <name>AEndian</name>\r
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+ <name>OBJCOPY</name>\r
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+</project>\r
+\r
+\r
--- /dev/null
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+ <Define>__SAMV71Q21__, NDEBUG</Define>
+ <Undefine></Undefine>
+ <IncludePath>.\;.\libchip_samv7\include\cmsis\CMSIS;.\libboard_samv7-ek;.\libchip_samv7;.\libboard_samv7-ek\include;.\libchip_samv7\include\samv7;..\..\Source\include;..\RTOSDemo;..\..\Source\portable\RVDS\ARM_CM7\r0p1;..\Common\include;.\Full_Demo</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20400000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>.\libboard_samv7-ek\resources\mdk\sram.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Atmel_Libboard</GroupName>
+ <Files>
+ <File>
+ <FileName>board_lowlevel.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libboard_samv7-ek\source\board_lowlevel.c</FilePath>
+ </File>
+ <File>
+ <FileName>led.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libboard_samv7-ek\source\led.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_sam.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libboard_samv7-ek\resources\mdk\startup_sam.c</FilePath>
+ </File>
+ <File>
+ <FileName>dbg_console.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libboard_samv7-ek\source\dbg_console.c</FilePath>
+ </File>
+ <File>
+ <FileName>workaround.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\libboard_samv7-ek\resources\mdk\workaround.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_sam.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libboard_samv7-ek\resources\system_sam.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Blinky_Demo\main_blinky.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\RegTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueueTimer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\IntQueueTimer.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Atmel_Libchip</GroupName>
+ <Files>
+ <File>
+ <FileName>pio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\pio.c</FilePath>
+ </File>
+ <File>
+ <FileName>pmc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\pmc.c</FilePath>
+ </File>
+ <File>
+ <FileName>tc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\tc.c</FilePath>
+ </File>
+ <File>
+ <FileName>wdt.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\wdt.c</FilePath>
+ </File>
+ <File>
+ <FileName>supc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\supc.c</FilePath>
+ </File>
+ <File>
+ <FileName>pio_capture.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\libchip_samv7\source\pio_capture.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM7\r0p1\port.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common_Demo_Tasks</GroupName>
+ <Files>
+ <File>
+ <FileName>BlockQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\death.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>EventGroupsDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\EventGroupsDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>QueueOverwrite.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\QueueOverwrite.c</FilePath>
+ </File>
+ <File>
+ <FileName>QueueSet.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\QueueSet.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>TaskNotify.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\TaskNotify.c</FilePath>
+ </File>
+ <File>
+ <FileName>TimerDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\IntQueue.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntSemTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\IntSemTest.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.40.0" condition="CMSIS Core">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/>
+ <targetInfos>
+ <targetInfo name="SRAM"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files/>
+ </RTE>
+
+</Project>
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \page samv7_Xplained_ultra_board_desc SAMV7_Xplained_Ultra - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the SAMV7_Xplained_Ultra board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - For SAMV7_Xplained_Ultra information, see \subpage samv7_Xplained_ultra_board_info.\r
+ * - For operating frequency information, see \subpage samv7_Xplained_ultra_opfreq.\r
+ * - For using portable PIO definitions, see \subpage samv7_Xplained_ultra_piodef.\r
+ * - For on-board memories, see \subpage samv7_Xplained_ultra_mem.\r
+ * - Several USB definitions are included here, see \subpage samv7_Xplained_ultra_usb.\r
+ * - For External components, see \subpage samv7_Xplained_ultra_extcomp.\r
+ * - For Individual chip definition, see \subpage samv7_Xplained_ultra_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * SAMV7_Xplained_Ultra board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of SAMV7_Xplained_Ultra characteristics, PIOs and\r
+ * external components interface.\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include "include/board_lowlevel.h"\r
+#include "include/board_memories.h"\r
+#include "include/omnivision.h"\r
+#include "include/ov.h"\r
+#include "include/led.h"\r
+#include "include/gmii.h"\r
+#include "include/gmacb_phy.h"\r
+#include "include/dbg_console.h"\r
+#include "include/bmp.h"\r
+#include "include/hamming.h"\r
+#include "include/lcdd.h"\r
+#include "include/ili9488_reg.h"\r
+#include "include/ili9488.h"\r
+#include "include/frame_buffer.h"\r
+#include "include/lcd_color.h"\r
+#include "include/lcd_draw.h"\r
+#include "include/lcd_font10x14.h"\r
+#include "include/lcd_font.h"\r
+#include "include/lcd_gimp_image.h"\r
+#include "include/wav.h"\r
+#include "include/wm8904.h"\r
+#include "include/CS2100.h"\r
+#include "include/s25fl1.h"\r
+#include "include/omnivision.h"\r
+#include "include/ovyuv.h"\r
+//#include "include/s25fl1_qspi.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_board_info "SAMV7_Xplained_Ultra - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "SAMV7-EK"\r
+#define NO_PUSHBUTTON\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_opfreq "SAMV7_Xplained_Ultra - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_MAINOSC\r
+ * - \ref BOARD_MCK\r
+ */\r
+\r
+/** Frequency of the board main oscillator */\r
+#define BOARD_MAINOSC 12000000\r
+\r
+/** Master clock frequency (when using board_lowlevel.c) */\r
+\r
+#define BOARD_MCK 132000000\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_piodef "SAMV7_Xplained_Ultra - PIO definitions"\r
+ * This pages lists all the pio definitions contained in board.h. The constants\r
+ * are named using the following convention: PIN_* for a constant which defines\r
+ * a single Pin instance (but may include several PIOs sharing the same\r
+ * controller), and PINS_* for a list of Pin instances.\r
+ *\r
+ * UART\r
+ * - \ref PINS_UART\r
+ *\r
+ * EBI\r
+ * - \ref PIN_EBI_DATA_BUS\r
+ * - \ref PIN_EBI_NRD\r
+ * - \ref PIN_EBI_NWE\r
+ * - \ref PIN_EBI_NCS0\r
+ * - \ref PIN_EBI_PSRAM_ADDR_BUS\r
+ * - \ref PIN_EBI_PSRAM_NBS\r
+ * - \ref PIN_EBI_A1\r
+ * - \ref PIN_EBI_LCD_CS\r
+ * - \ref PIN_EBI_LCD_RS\r
+ *\r
+ * LEDs\r
+ * - \ref PIN_LED_0\r
+ * - \ref PIN_LED_1\r
+ * - \ref PIN_LED_2\r
+ * - \ref PIN_LED_3\r
+ * - \ref PINS_LEDS\r
+ *\r
+ * MCI\r
+ * - \ref PINS_MCI\r
+ *\r
+ * Push buttons\r
+ * - \ref PIN_PUSHBUTTON_0\r
+ * - \ref PIN_PUSHBUTTON_1\r
+ * - \ref PIN_PUSHBUTTON_2\r
+ * - \ref PIN_PUSHBUTTON_3\r
+ * - \ref PINS_PUSHBUTTONS\r
+ * - \ref PUSHBUTTON_BP0\r
+ * - \ref PUSHBUTTON_BP1\r
+ * - \ref PUSHBUTTON_BP2\r
+ * - \ref PUSHBUTTON_BP3\r
+ *\r
+ * PWMC\r
+ * - \ref PIN_PWMC_PWMH0\r
+ * - \ref PIN_PWMC_PWMH1\r
+ * - \ref PIN_PWM_LED0\r
+ * - \ref PIN_PWM_LED1\r
+ * - \ref CHANNEL_PWM_LED0\r
+ * - \ref CHANNEL_PWM_LED1\r
+ *\r
+ * SPI\r
+ * - \ref PIN_SPI_MISO\r
+ * - \ref PIN_SPI_MOSI\r
+ * - \ref PIN_SPI_SPCK\r
+ * - \ref PINS_SPI\r
+ * - \ref PIN_SPI_NPCS0_PA11\r
+ *\r
+ * PCK0\r
+ * - \ref PIN_PCK0\r
+ *\r
+ * PIO PARALLEL CAPTURE\r
+ * - \ref PIN_PIODCEN1\r
+ * - \ref PIN_PIODCEN2\r
+ *\r
+ * TWI\r
+ * - \ref TWI_V3XX\r
+ * - \ref PIN_TWI_TWD0\r
+ * - \ref PIN_TWI_TWCK0\r
+ * - \ref PINS_TWI0\r
+ *\r
+ * USART0\r
+ * - \ref PIN_USART0_RXD\r
+ * - \ref PIN_USART0_TXD\r
+ * - \ref PIN_USART0_CTS\r
+ * - \ref PIN_USART0_RTS\r
+ * - \ref PIN_USART0_SCK\r
+ *\r
+ * USB\r
+ * - \ref PIN_USB_VBUS\r
+ *\r
+ * NandFlash\r
+ * - \ref PIN_EBI_NANDOE\r
+ * - \ref PIN_EBI_NANDWE\r
+ * - \ref PIN_EBI_NANDCLE\r
+ * - \ref PIN_EBI_NANDALE\r
+ * - \ref PIN_EBI_NANDIO\r
+ * - \ref BOARD_NF_CE_PIN\r
+ * - \ref BOARD_NF_RB_PIN\r
+ * - \ref PINS_NANDFLASH\r
+ */\r
+\r
+\r
+/** SSC pin Transmitter Data (TD) */\r
+#define PIN_SSC_TD {PIO_PD26B_TD, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SSC pin Transmitter Clock (TK) */\r
+#define PIN_SSC_TK {PIO_PB1D_TK, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT}\r
+/** SSC pin Transmitter FrameSync (TF) */\r
+#define PIN_SSC_TF {PIO_PB0D_TF, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT}\r
+/** SSC pin RD */\r
+#define PIN_SSC_RD {PIO_PA10C_RD, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** SSC pin RK */\r
+#define PIN_SSC_RK {PIO_PA22A_RK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pin RF */\r
+#define PIN_SSC_RF {PIO_PD24B_RF, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/** SSC pins definition for codec. */\r
+#define PINS_SSC_CODEC {PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF, PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF}\r
+\r
+\r
+/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */\r
+#define PINS_UART0 {PIO_PA9A_URXD0 | PIO_PA10A_UTXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** UART pins (UTXD4 and URXD4) definitions, PD19,18. */\r
+#define PINS_UART4 {PIO_PD18C_URXD4 | PIO_PD19C_UTXD4, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+\r
+/** EBI Data Bus pins */\r
+#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** EBI NRD pin */\r
+#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** EBI NWE pin */\r
+#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** EBI NCS0 pin */\r
+#define PIN_EBI_NCS0 {1 << 14, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+\r
+/** EBI A1 pin */\r
+#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/* LCD CS pin (NCS3) */\r
+#define PIN_EBI_LCD_CS {1 << 18, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP}\r
+/* LCD RS pin (A1) */\r
+#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+\r
+#define LED_YELLOW0 0\r
+#define LED_YELLOW1 1\r
+\r
+/** LED #0 pin definition (BLUE). */\r
+#define PIN_LED_0 {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/** LED #0 pin definition (AMBER). */\r
+#define PIN_LED_1 {PIO_PC9, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS {PIN_LED_0, PIN_LED_1}\r
+\r
+\r
+/** List of all SDRAM pin definitions. */\r
+#define PIN_SDRAM_D0_7 {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_D8_13 {0x0000003F, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_D14_15 {0x00018000, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_A0_9 {0x3FF00000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_SDA10 {0x00002000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+//#define PIN_SDRAM_A11 {0x80000000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+#define PIN_SDRAM_CAS {0x00020000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_RAS {0x00010000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_SDCKE {0x00004000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_SDCK {0x00800000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_SDSC {0x00008000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_NBS0 {0x00040000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_SDRAM_NBS1 {0x00008000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_SDWE {0x20000000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}\r
+#define PIN_SDRAM_BA0 {0x00100000, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+\r
+#define BOARD_SDRAM_PINS PIN_SDRAM_D0_7, PIN_SDRAM_D8_13 , PIN_SDRAM_D14_15,\\r
+ PIN_SDRAM_A0_9, PIN_SDRAM_SDA10, PIN_SDRAM_BA0, \\r
+ PIN_SDRAM_CAS, PIN_SDRAM_RAS, PIN_SDRAM_SDCKE,PIN_SDRAM_SDCK,\\r
+ PIN_SDRAM_SDSC,PIN_SDRAM_NBS0 ,PIN_SDRAM_NBS1,PIN_SDRAM_SDWE\r
+/**\r
+ * Push button #0 definition.\r
+ * Attributes = pull-up + debounce + interrupt on rising edge.\r
+ */\r
+#define PIN_PUSHBUTTON_0 {PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+/**\r
+ * Push button #1 definition.\r
+ * Attributes = pull-up + debounce + interrupt on rising edge.\r
+ */\r
+#define PIN_PUSHBUTTON_1 {PIO_PB12, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_0, PIN_PUSHBUTTON_1}\r
+\r
+\r
+/** Push button #0 index. */\r
+#define PUSHBUTTON_BP0 0\r
+/** Push button #1 index. */\r
+#define PUSHBUTTON_BP1 1\r
+/** Push button #2 index. */\r
+#define PUSHBUTTON_BP2 2\r
+/** Push button #3 index. */\r
+#define PUSHBUTTON_BP3 3\r
+\r
+/** PWMC PWM0 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH0 {PIO_PD20A_PWMH0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** PWMC PWM1 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH1 {PIO_PD21A_PWMH1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** PWM pins definition for LED0 */\r
+#define PIN_PWM_LED0 PIN_PWMC_PWMH0\r
+/** PWM pins definition for LED1 */\r
+#define PIN_PWM_LED1 PIN_PWMC_PWMH1\r
+/** PWM channel for LED0 */\r
+#define CHANNEL_PWM_LED0 0\r
+/** PWM channel for LED1 */\r
+#define CHANNEL_PWM_LED1 1\r
+\r
+/** SPI MISO pin definition. */\r
+#define PIN_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI MOSI pin definition. */\r
+#define PIN_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI SPCK pin definition. */\r
+#define PIN_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI chip select pin definition. */\r
+#define PIN_SPI_NPCS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT}\r
+#define PIN_SPI_NPCS1 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+#define PIN_SPI_NPCS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/** List of SPI pin definitions (MISO, MOSI & SPCK). */\r
+#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK\r
+\r
+/** PCK0 */\r
+//#define PIN_PCK0 {PIO_PB12D_PCK0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT}\r
+#define PIN_PCK0 {PIO_PB13B_PCK0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PCK1 */\r
+#define PIN_PCK1 {PIO_PA17B_PCK1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/** PCK2 */\r
+#define PIN_PCK2 {PIO_PA18B_PCK2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+\r
+/** PIO PARALLEL CAPTURE */\r
+/** Parallel Capture Mode Data Enable1 */\r
+#define PIN_PIODCEN1 PIO_PA15\r
+/** Parallel Capture Mode Data Enable2 */\r
+#define PIN_PIODCEN2 PIO_PA16\r
+\r
+/** TWI ver 3.xx */\r
+#define TWI_V3XX\r
+/** TWI0 data pin */\r
+#define PIN_TWI_TWD0 {PIO_PA3A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 clock pin */\r
+#define PIN_TWI_TWCK0 {PIO_PA4A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 pins */\r
+#define PINS_TWI0 {PIN_TWI_TWD0, PIN_TWI_TWCK0}\r
+/** TWI1 data pin */\r
+#define PIN_TWI_TWD1 {PIO_PB4A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI1 clock pin */\r
+#define PIN_TWI_TWCK1 {PIO_PB5A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A,PIO_DEFAULT}\r
+/** TWI1 pins */\r
+#define PINS_TWI1 {PIN_TWI_TWD1, PIN_TWI_TWCK1}\r
+\r
+/** USART0 pin RX */\r
+#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** USART0 pin TX */\r
+#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** USART0 pin CTS */\r
+#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** USART0 pin RTS */\r
+#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** USART0 pin SCK */\r
+#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, PIO_PERIPH_C,PIO_DEFAULT}\r
+\r
+/** USART1 pin RX */\r
+#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** USART1 pin TX */\r
+#define PIN_USART1_TXD {1<<22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** USART1 pin CTS */\r
+#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** USART1 pin RTS */\r
+#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** USART1 pin ENABLE */\r
+#define PIN_USART1_EN {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/** USART1 pin SCK */\r
+#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/** USART2 pin RX */\r
+#define PIN_USART2_RXD {PIO_PD15B_RXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** USART2 pin TX */\r
+#define PIN_USART2_TXD {PIO_PD16B_TXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** USART2 pin CTS */\r
+#define PIN_USART2_CTS {PIO_PD19B_CTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** USART2 pin RTS */\r
+#define PIN_USART2_RTS {PIO_PD18B_RTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** USART2 pin SCK */\r
+#define PIN_USART2_SCK {PIO_PD17B_SCK2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/** USB VBus monitoring pin definition. */\r
+#define PIN_USB_VBUS {PIO_PC16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+\r
+/** NandFlash pins definition: OE. */\r
+#define PIN_EBI_NANDOE {PIO_PC9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: WE. */\r
+#define PIN_EBI_NANDWE {PIO_PC10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: CLE. */\r
+#define PIN_EBI_NANDCLE {PIO_PC17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: ALE. */\r
+#define PIN_EBI_NANDALE {PIO_PC16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: DATA. */\r
+#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** Nandflash chip enable pin definition. */\r
+#define BOARD_NF_CE_PIN {PIO_PC14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/** Nandflash ready/busy pin definition. */\r
+#define BOARD_NF_RB_PIN {0, 0, 0, 0, 0}\r
+\r
+/** Nandflash controller peripheral pins definition. */\r
+#define PINS_NANDFLASH {PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, \\r
+ PIN_EBI_NANDOE, PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_usb "SAMV7_Xplained_Ultra - GMAC"\r
+ */\r
+\r
+\r
+/** PHY address */\r
+#define BOARD_GMAC_PHY_ADDR 1\r
+/** PHY Component */\r
+#define BOARD_GMAC_PHY_COMP_KSZ8061RNB 1\r
+/** Board GMAC power control - ALWAYS ON */\r
+#define BOARD_GMAC_POWER_ALWAYS_ON\r
+/** Board GMAC work mode - RMII/MII ( 1 / 0 ) */\r
+#define BOARD_GMAC_MODE_RMII 1\r
+\r
+/** The PIN list of PIO for GMAC */\r
+#define BOARD_GMAC_PINS { (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | PIO_PD3A_GTX1 | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | PIO_PD6A_GRX1 | PIO_PD7A_GRXER | PIO_PD8A_GMDC | PIO_PD9A_GMDIO ), \\r
+ PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}, \\r
+ {PIO_PC30, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP},\\r
+ {PIO_PA29, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+\r
+ /** The PIN list of PIO for GMAC */\r
+#define BOARD_GMAC_RESET_PIN {PIO_PC10, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_PULLUP}\r
+\r
+/** The runtime pin configure list for GMAC */\r
+#define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS\r
+\r
+\r
+#define PIN_ISI_D0 {PIO_PD22D_ISI_D0, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D1 {PIO_PD21D_ISI_D1, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D2 {PIO_PB3D_ISI_D2, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D3 {PIO_PA9B_ISI_D3, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP}\r
+#define PIN_ISI_D4 {PIO_PA5B_ISI_D4, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP}\r
+#define PIN_ISI_D5 {PIO_PD11D_ISI_D5, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D6 {PIO_PD12D_ISI_D6, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D7 {PIO_PA27D_ISI_D7, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D8 {PIO_PD27D_ISI_D8, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+#define PIN_ISI_D9 {PIO_PD28D_ISI_D9, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP}\r
+\r
+#define BOARD_ISI_VSYNC {PIO_PD25D_ISI_VSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT}\r
+#define BOARD_ISI_HSYNC {PIO_PD24D_ISI_HSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT}\r
+#define BOARD_ISI_PCK {PIO_PA24D_ISI_PCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT}\r
+\r
+#define BOARD_ISI_PINS PIN_ISI_D0,PIN_ISI_D1,PIN_ISI_D2,PIN_ISI_D3,PIN_ISI_D4,\\r
+ PIN_ISI_D5,PIN_ISI_D6,PIN_ISI_D7,PIN_ISI_D8,PIN_ISI_D9,\\r
+ BOARD_ISI_VSYNC ,BOARD_ISI_HSYNC ,BOARD_ISI_PCK\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_usb "SAMV7_Xplained_Ultra - USB device"\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_USB_BMATTRIBUTES\r
+ * - \ref CHIP_USB_UDP\r
+ * - \ref CHIP_USB_PULLUP_INTERNAL\r
+ * - \ref CHIP_USB_NUMENDPOINTS\r
+ * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE\r
+ * - \ref CHIP_USB_ENDPOINTS_BANKS\r
+ */\r
+\r
+/**\r
+ * USB attributes configuration descriptor (bus or self powered,\r
+ * remote wakeup)\r
+ */\r
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+\r
+/** Indicates chip has an UDP Full Speed. */\r
+#define CHIP_USB_UDP\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 10\r
+\r
+/** Endpoints max paxcket size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) ((i == 0) ? 64 : 1024)\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i) \\r
+ ((i == 0) ? 1 : \\r
+ ((i == 1) ? 3 : \\r
+ ((i == 2) ? 3 : 2)))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_extcomp "SAMV7_Xplained_Ultra - External components"\r
+ * This page lists the definitions related to external on-board components\r
+ * located in the board.h file for the SAMV7_Xplained_Ultra.\r
+ *\r
+ * SD Card\r
+ * - \ref BOARD_SD_PINS\r
+ * - \ref BOARD_SD_PIN_CD\r
+ *\r
+ * LCD\r
+ * - \ref BOARD_LCD_ILI9325\r
+ * - \ref BOARD_LCD_PINS\r
+ * - \ref BOARD_BACKLIGHT_PIN\r
+ * - \ref BOARD_LCD_BASE\r
+ * - \ref BOARD_LCD_RS\r
+ * - \ref BOARD_LCD_WIDTH\r
+ * - \ref BOARD_LCD_HEIGHT\r
+ *\r
+ * TouchScreen\r
+ * - \ref BOARD_TSC_ADS7843\r
+ * - \ref PIN_TCS_IRQ\r
+ * - \ref PIN_TCS_BUSY\r
+ * - \ref BOARD_TSC_SPI_BASE\r
+ * - \ref BOARD_TSC_SPI_ID\r
+ * - \ref BOARD_TSC_SPI_PINS\r
+ * - \ref BOARD_TSC_NPCS\r
+ * - \ref BOARD_TSC_NPCS_PIN\r
+ *\r
+ * SmartCard\r
+ * - \ref SMARTCARD_CONNECT_PIN\r
+ * - \ref PIN_ISO7816_RSTMC\r
+ * - \ref PINS_ISO7816\r
+ */\r
+\r
+\r
+/** Indicates board has an ILI9325 external component to manage LCD. */\r
+#define BOARD_LCD_ILI9488\r
+\r
+ /** SPI MISO pin definition. */\r
+#define LCD_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI MOSI pin definition. */\r
+#define LCD_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI SPCK pin definition. */\r
+#define LCD_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** SPI chip select pin definition. */\r
+#define LCD_SPI_NPCS {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT}\r
+\r
+/** LCD pins definition. */\r
+#define BOARD_LCD_PINS {LCD_SPI_MISO, LCD_SPI_MOSI, LCD_SPI_SPCK, LCD_SPI_NPCS}\r
+\r
+/** Backlight pin definition. */\r
+\r
+#define BOARD_LCD_BACKLIGHT_PIN {PIO_PA0A_PWMC0_PWMH0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/** PWMC PWM0 pin definition: Output Low. */\r
+#define LCD_PIN_RESET {PIO_PD28, PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT}\r
+\r
+/** PWM channel for LED0 */\r
+#define CHANNEL_PWM_LCD 0\r
+\r
+/** Display width in pixels. */\r
+#define BOARD_LCD_WIDTH 320\r
+/** Display height in pixels. */\r
+#define BOARD_LCD_HEIGHT 480\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_mem "SAMV7_Xplained_Ultra - Memories"\r
+ * This page lists definitions related to internal & external on-board memories.\r
+ *\r
+ * \section NandFlash\r
+ * - \ref BOARD_NF_COMMAND_ADDR\r
+ * - \ref BOARD_NF_ADDRESS_ADDR\r
+ * - \ref BOARD_NF_DATA_ADDR\r
+ *\r
+ * \section NorFlash\r
+ * - \ref BOARD_NORFLASH_ADDR\r
+ * - \ref BOARD_NORFLASH_DFT_BUS_SIZE\r
+ */\r
+\r
+/** Address for transferring command bytes to the nandflash. */\r
+#define BOARD_NF_COMMAND_ADDR 0x60400000\r
+/** Address for transferring address bytes to the nandflash. */\r
+#define BOARD_NF_ADDRESS_ADDR 0x60200000\r
+/** Address for transferring data bytes to the nandflash. */\r
+#define BOARD_NF_DATA_ADDR 0x60000000\r
+\r
+/** Address for transferring command bytes to the norflash. */\r
+#define BOARD_NORFLASH_ADDR 0x60000000\r
+/** Default NOR bus size after power up reset */\r
+#define BOARD_NORFLASH_DFT_BUS_SIZE 8\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page samv7_Xplained_ultra_chipdef "SAMV7_Xplained_Ultra - Individual chip definition"\r
+ * This page lists the definitions related to different chip's definition\r
+ *\r
+ * \section USART\r
+ * - \ref BOARD_PIN_USART_RXD\r
+ * - \ref BOARD_PIN_USART_TXD\r
+ * - \ref BOARD_PIN_USART_CTS\r
+ * - \ref BOARD_PIN_USART_RTS\r
+ * - \ref BOARD_PIN_USART_EN\r
+ * - \ref BOARD_USART_BASE\r
+ * - \ref BOARD_ID_USART\r
+ */\r
+\r
+/** Rtc */\r
+#define BOARD_RTC_ID ID_RTC\r
+\r
+/** TWI ID for QTouch application to use */\r
+#define BOARD_ID_TWI_AT42 ID_TWI0\r
+/** TWI Base for QTouch application to use */\r
+#define BOARD_BASE_TWI_AT42 TWI0\r
+/** TWI pins for QTouch application to use */\r
+#define BOARD_PINS_TWI_AT42 PINS_TWI0\r
+\r
+/** USART RX pin for application */\r
+#define BOARD_PIN_USART_RXD PIN_USART1_RXD\r
+/** USART TX pin for application */\r
+#define BOARD_PIN_USART_TXD PIN_USART1_TXD\r
+/** USART CTS pin for application */\r
+#define BOARD_PIN_USART_CTS PIN_USART1_CTS\r
+/** USART RTS pin for application */\r
+#define BOARD_PIN_USART_RTS PIN_USART1_RTS\r
+/** USART ENABLE pin for application */\r
+#define BOARD_PIN_USART_EN PIN_USART1_EN\r
+/** USART Base for application */\r
+#define BOARD_USART_BASE USART1\r
+/** USART ID for application */\r
+#define BOARD_ID_USART ID_USART1\r
+\r
+\r
+\r
+/** MCI0 Card detect pin definition. (PE5) */\r
+#define BOARD_MCI_PIN_CD {PIO_PD18, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP}\r
+\r
+/** MCI0 Clock . */\r
+#define BOARD_MCI_PIN_CK {PIO_PA25D_MCCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT}\r
+\r
+\r
+/** MCI0 Solt A IO pins definition. (PC4-PC13) */\r
+#define BOARD_MCI_PINS_SLOTA {(PIO_PA30C_MCDA0 | PIO_PA31C_MCDA1 | PIO_PA26C_MCDA2 | PIO_PA27C_MCDA3 | PIO_PA28C_MCCDA),\\r
+ PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+\r
+\r
+/** MCI pins that shall be configured to access the SD card. */\r
+#define BOARD_SD_PINS {BOARD_MCI_PINS_SLOTA, BOARD_MCI_PIN_CK}\r
+/** MCI Card Detect pin. */\r
+#define BOARD_SD_PIN_CD BOARD_MCI_PIN_CD\r
+ /** Total number of MCI interface */\r
+#define BOARD_NUM_MCI 1\r
+\r
+/** Total number of MCI interface */\r
+#define BOARD_NUM_MCI 1\r
+\r
+\r
+#define PINS_QSPI_IO { (PIO_PA11A_QCS | PIO_PA13A_QIO0 | PIO_PA12A_QIO1 | PIO_PA17A_QIO2 | PIO_PA14A_QSCK), \\r
+ PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+#define PINS_QSPI_IO3 { PIO_PD31A_QIO3, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+#define PINS_QSPI {PINS_QSPI_IO, PINS_QSPI_IO3}\r
+\r
+\r
+#endif /* #ifndef _BOARD_H_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation WM8904 driver.\r
+ *\r
+ */\r
+\r
+#ifndef CS2100_H\r
+#define CS2100_H\r
+\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define CS2100_SLAVE_ADDRESS 0x4E\r
+\r
+/** ID and Rev register*/\r
+#define CS2100_REG_ID 0x01\r
+\r
+/** VMID control 0 register*/\r
+#define CS2100_REG_CTRL 0x02\r
+\r
+/** MIC Bias control 0 register*/\r
+#define CS2100_REG_DEV_CFG1 0x03\r
+\r
+/** Bias control 1 register*/\r
+#define CS2100_REG_CFG 0x05\r
+\r
+/** Power management control 0 register*/\r
+#define CS2100_REG_32_BIT_RATIO_1 0x06\r
+/** Power management control 0 register*/\r
+#define CS2100_REG_32_BIT_RATIO_2 0x07\r
+/** Power management control 0 register*/\r
+#define CS2100_REG_32_BIT_RATIO_3 0x08\r
+/** Power management control 0 register*/\r
+#define CS2100_REG_32_BIT_RATIO_4 0x09\r
+/** Power management control 2 register*/\r
+#define CS2100_REG_FUNC_CFG1 0x16\r
+/** Power management control 3 register*/\r
+#define CS2100_REG_FUNC_CFG2 0x17\r
+/** Power management control 3 register*/\r
+#define CS2100_REG_FUNC_CFG3 0x1E\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint16_t CS2100_Read(Twid *pTwid, uint32_t device, uint32_t regAddr);\r
+extern void CS2100_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data);\r
+extern uint8_t CS2100_Init(Twid *pTwid, uint32_t device, uint32_t PCK);\r
+#endif // CS2100_H\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the AT25 SPI driver.\r
+ *\r
+ */\r
+\r
+#ifndef AT25_SPI_H\r
+#define AT25_SPI_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <board.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define AT25_Size(pAt25) ((pAt25)->pDesc->size)\r
+#define AT25_PageSize(pAt25) ((pAt25)->pDesc->pageSize)\r
+#define AT25_BlockSize(pAt25) ((pAt25)->pDesc->blockSize)\r
+#define AT25_Name(pAt25) ((pAt25)->pDesc->name)\r
+#define AT25_ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF)\r
+#define AT25_PageNumber(pAt25) (AT25_Size(pAt25) / AT25_PageSize(pAt25))\r
+#define AT25_BlockNumber(pAt25) (AT25_Size(pAt25) / AT25_BlockSize(pAt25))\r
+#define AT25_PagePerBlock(pAt25) (AT25_BlockSize(pAt25) / AT25_PageSize(pAt25))\r
+#define AT25_BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Device is protected, operation cannot be carried out. */\r
+#define AT25_ERROR_PROTECTED 1\r
+/** Device is busy executing a command. */\r
+#define AT25_ERROR_BUSY 2\r
+/** There was a problem while trying to program page data. */\r
+#define AT25_ERROR_PROGRAM 3\r
+/** There was an SPI communication error. */\r
+#define AT25_ERROR_SPI 4\r
+\r
+/** Device ready/busy status bit. */\r
+#define AT25_STATUS_RDYBSY (1 << 0)\r
+/** Device is ready. */\r
+#define AT25_STATUS_RDYBSY_READY (0 << 0)\r
+/** Device is busy with internal operations. */\r
+#define AT25_STATUS_RDYBSY_BUSY (1 << 0)\r
+/** Write enable latch status bit. */\r
+#define AT25_STATUS_WEL (1 << 1)\r
+/** Device is not write enabled. */\r
+#define AT25_STATUS_WEL_DISABLED (0 << 1)\r
+/** Device is write enabled. */\r
+#define AT25_STATUS_WEL_ENABLED (1 << 1)\r
+/** Software protection status bitfield. */\r
+#define AT25_STATUS_SWP (3 << 2)\r
+/** All sectors are software protected. */\r
+#define AT25_STATUS_SWP_PROTALL (3 << 2)\r
+/** Some sectors are software protected. */\r
+#define AT25_STATUS_SWP_PROTSOME (1 << 2)\r
+/** No sector is software protected. */\r
+#define AT25_STATUS_SWP_PROTNONE (0 << 2)\r
+/** Write protect pin status bit. */\r
+#define AT25_STATUS_WPP (1 << 4)\r
+/** Write protect signal is not asserted. */\r
+#define AT25_STATUS_WPP_NOTASSERTED (0 << 4)\r
+/** Write protect signal is asserted. */\r
+#define AT25_STATUS_WPP_ASSERTED (1 << 4)\r
+/** Erase/program error bit. */\r
+#define AT25_STATUS_EPE (1 << 5)\r
+/** Erase or program operation was successful. */\r
+#define AT25_STATUS_EPE_SUCCESS (0 << 5)\r
+/** Erase or program error detected. */\r
+#define AT25_STATUS_EPE_ERROR (1 << 5)\r
+/** Sector protection registers locked bit. */\r
+#define AT25_STATUS_SPRL (1 << 7)\r
+/** Sector protection registers are unlocked. */\r
+#define AT25_STATUS_SPRL_UNLOCKED (0 << 7)\r
+/** Sector protection registers are locked. */\r
+#define AT25_STATUS_SPRL_LOCKED (1 << 7)\r
+\r
+/** Read array command code. */\r
+#define AT25_READ_ARRAY 0x0B\r
+/** Read array (low frequency) command code. */\r
+#define AT25_READ_ARRAY_LF 0x03\r
+/** Block erase command code (4K block). */\r
+#define AT25_BLOCK_ERASE_4K 0x20\r
+/** Block erase command code (32K block). */\r
+#define AT25_BLOCK_ERASE_32K 0x52\r
+/** Block erase command code (64K block). */\r
+#define AT25_BLOCK_ERASE_64K 0xD8\r
+/** Chip erase command code 1. */\r
+#define AT25_CHIP_ERASE_1 0x60\r
+/** Chip erase command code 2. */\r
+#define AT25_CHIP_ERASE_2 0xC7\r
+/** Byte/page program command code. */\r
+#define AT25_BYTE_PAGE_PROGRAM 0x02\r
+/** Sequential program mode command code 1. */\r
+#define AT25_SEQUENTIAL_PROGRAM_1 0xAD\r
+/** Sequential program mode command code 2. */\r
+#define AT25_SEQUENTIAL_PROGRAM_2 0xAF\r
+/** Write enable command code. */\r
+#define AT25_WRITE_ENABLE 0x06\r
+/** Write disable command code. */\r
+#define AT25_WRITE_DISABLE 0x04\r
+/** Protect sector command code. */\r
+#define AT25_PROTECT_SECTOR 0x36\r
+/** Unprotect sector command code. */\r
+#define AT25_UNPROTECT_SECTOR 0x39\r
+/** Read sector protection registers command code. */\r
+#define AT25_READ_SECTOR_PROT 0x3C\r
+/** Read status register command code. */\r
+#define AT25_READ_STATUS 0x05\r
+/** Write status register command code. */\r
+#define AT25_WRITE_STATUS 0x01\r
+/** Read manufacturer and device ID command code. */\r
+#define AT25_READ_JEDEC_ID 0x9F\r
+/** Deep power-down command code. */\r
+#define AT25_DEEP_PDOWN 0xB9\r
+/** Resume from deep power-down command code. */\r
+#define AT25_RES_DEEP_PDOWN 0xAB\r
+\r
+\r
+/** SPI Flash Manufacturer JEDEC ID */\r
+#define ATMEL_SPI_FLASH 0x1F\r
+#define ST_SPI_FLASH 0x20\r
+#define WINBOND_SPI_FLASH 0xEF\r
+#define MACRONIX_SPI_FLASH 0xC2\r
+#define SST_SPI_FLASH 0xBF\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Describes a serial firmware flash device parameters. */\r
+typedef struct _At25Desc {\r
+\r
+ /** Device string name. */\r
+ const char *name;\r
+ /** JEDEC ID of device. */\r
+ unsigned int jedecId;\r
+ /** Size of device in bytes. */\r
+ unsigned int size;\r
+ /** Size of one page in bytes. */\r
+ unsigned int pageSize;\r
+ /** Block erase size in bytes. */\r
+ unsigned int blockSize;\r
+ /** Block erase command. */\r
+ unsigned int blockEraseCmd;\r
+\r
+} At25Desc;\r
+\r
+/**\r
+ * Serial flash driver structure. Holds the current state of the driver,\r
+ * including the current command and the descriptor for the underlying device.\r
+ */\r
+typedef struct _At25 {\r
+\r
+ /** Pointer to the underlying SPI driver. */\r
+ Spid *pSpid;\r
+ /** Current SPI command sent to the SPI driver. */\r
+ SpidCmd command;\r
+ /** Pointer to a descriptor for the serial firmware flash device. */\r
+ const At25Desc *pDesc;\r
+ /** Command buffer. */\r
+ unsigned int pCmdBuffer[2];\r
+\r
+} At25;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void AT25_Configure(At25 *pAt25, Spid *pSpid, unsigned char cs);\r
+\r
+extern unsigned char AT25_SendCommand(\r
+ At25 *pAt25,\r
+ unsigned char cmd,\r
+ unsigned char cmdSize,\r
+ unsigned char *pData,\r
+ unsigned int dataSize,\r
+ unsigned int address,\r
+ SpidCallback callback,\r
+ void *pArgument);\r
+\r
+extern unsigned char AT25_IsBusy(At25 *pAt25);\r
+\r
+extern const At25Desc * AT25_FindDevice(\r
+ At25 *pAt25,\r
+ unsigned int jedecId);\r
+\r
+#endif /*#ifndef AT25_SPI_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the AT25 Serialflash driver.\r
+ *\r
+ */\r
+\r
+#ifndef AT25D_H\r
+#define AT25D_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "at25_spi.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void AT25D_WaitReady(At25 *pAt25);\r
+\r
+extern unsigned int AT25D_ReadJedecId(At25 *pAt25);\r
+\r
+extern void AT25D_EnableWrite(At25 *pAt25);\r
+\r
+extern void AT25D_DisableWrite(At25 *pAt25);\r
+extern unsigned char AT25D_Unprotect(At25 *pAt25);\r
+\r
+extern unsigned char AT25D_EraseChip(At25 *pAt25);\r
+\r
+extern unsigned char AT25D_EraseBlock(At25 *pAt25, unsigned int address);\r
+extern unsigned char AT25D_Erase64KBlock(At25 *pAt25, unsigned int address);\r
+\r
+extern unsigned char AT25D_Write(\r
+ At25 *pAt25,\r
+ unsigned char *pData,\r
+ unsigned int size,\r
+ unsigned int address);\r
+\r
+extern unsigned char AT25D_Read(\r
+ At25 *pAt25,\r
+ unsigned char *pData,\r
+ unsigned int size,\r
+ unsigned int address);\r
+\r
+#endif // #ifndef AT25D_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * \section Purpose\r
+ *\r
+ * Utility for BMP\r
+ *\r
+ */\r
+\r
+#ifndef BMP_H\r
+#define BMP_H\r
+\r
+/** BMP magic number ('BM'). */\r
+#define BMP_TYPE 0x4D42\r
+\r
+/** headerSize must be set to 40 */\r
+#define BITMAPINFOHEADER 40\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported types\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#pragma pack( 1 )\r
+\r
+/** BMP (Windows) Header Format */\r
+typedef struct _BMPHeader\r
+{\r
+ /* signature, must be 4D42 hex */\r
+ uint16_t type;\r
+ /* size of BMP file in bytes (unreliable) */\r
+ uint32_t fileSize;\r
+ /* reserved, must be zero */\r
+ uint16_t reserved1;\r
+ /* reserved, must be zero */\r
+ uint16_t reserved2;\r
+ /* offset to start of image data in bytes */\r
+ uint32_t offset;\r
+ /* size of BITMAPINFOHEADER structure, must be 40 */\r
+ uint32_t headerSize;\r
+ /* image width in pixels */\r
+ uint32_t width;\r
+ /* image height in pixels */\r
+ uint32_t height;\r
+ /* number of planes in the image, must be 1 */\r
+ uint16_t planes;\r
+ /* number of bits per pixel (1, 4, 8, 16, 24, 32) */\r
+ uint16_t bits;\r
+ /* compression type (0=none, 1=RLE-8, 2=RLE-4) */\r
+ uint32_t compression;\r
+ /* size of image data in bytes (including padding) */\r
+ uint32_t imageSize;\r
+ /* horizontal resolution in pixels per meter (unreliable) */\r
+ uint32_t xresolution;\r
+ /* vertical resolution in pixels per meter (unreliable) */\r
+ uint32_t yresolution;\r
+ /* number of colors in image, or zero */\r
+ uint32_t ncolours;\r
+ /* number of important colors, or zero */\r
+ uint32_t importantcolours;\r
+\r
+} BMPHeader;\r
+\r
+#pragma pack()\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern uint8_t BMP_IsValid(void *file);\r
+extern uint32_t BMP_GetFileSize(void *file);\r
+extern uint8_t BMP_Decode( void *file, uint8_t *buffer, uint32_t width, uint32_t height, uint8_t bpp );\r
+extern void WriteBMPheader( uint32_t* pAddressHeader, uint32_t bmpHSize, uint32_t bmpVSize, uint8_t nbByte_Pixels );\r
+extern void BMP_displayHeader(uint32_t* pAddressHeader);\r
+extern void RGB565toBGR555( uint8_t *fileSource, uint8_t *fileDestination, uint32_t width, uint32_t height, uint8_t bpp );\r
+\r
+#endif //#ifndef BMP_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the low-level initialization function.\r
+ *\r
+ */\r
+\r
+#ifndef BOARD_LOWLEVEL_H\r
+#define BOARD_LOWLEVEL_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void LowLevelInit( void ) ;\r
+extern void _SetupMemoryRegion( void );\r
+\r
+#endif /* BOARD_LOWLEVEL_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for memories configuration on board.\r
+ *\r
+ */\r
+\r
+#ifndef BOARD_MEMORIES_H\r
+#define BOARD_MEMORIES_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void BOARD_ConfigureNandFlash( Smc* pSmc ) ;\r
+extern void BOARD_ConfigureNorFlash( Smc* pSmc ) ;\r
+extern void BOARD_ConfigurePSRAM( Smc* pSmc ) ;\r
+extern void BOARD_ConfigureSdram( void );\r
+extern uint32_t ExtRAM_Validation(uint32_t baseAddr, uint32_t size);\r
+#endif /* #ifndef BOARD_MEMORIES_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Include function prototype for the uart console.\r
+ */\r
+\r
+#ifndef _DBG_CONSOLE_\r
+#define _DBG_CONSOLE_\r
+\r
+#include <stdint.h>\r
+\r
+extern void DBG_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ;\r
+extern void DBG_PutChar( uint8_t uc ) ;\r
+extern uint32_t DBG_GetChar( void ) ;\r
+extern uint32_t DBG_IsRxReady( void ) ;\r
+\r
+\r
+extern void DBG_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ;\r
+extern void DBG_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ;\r
+extern uint32_t DBG_GetInteger( int32_t* pdwValue ) ;\r
+extern uint32_t DBG_GetIntegerMinMax( int32_t* pdwValue, int32_t dwMin, int32_t dwMax ) ;\r
+extern uint32_t DBG_GetHexa32( uint32_t* pdwValue ) ;\r
+\r
+#endif /* _DBG_CONSOLE_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface of frame buffer driver.\r
+ *\r
+ */\r
+\r
+#ifndef _FRAME_BUFFER_\r
+#define _FRAME_BUFFER_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void FB_SetFrameBuffer(LcdColor_t *pBuffer, uint8_t ucWidth, uint8_t ucHeight);\r
+extern void FB_SetColor(uint32_t color);\r
+extern uint32_t FB_DrawLine ( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 );\r
+extern uint32_t FB_DrawPixel( uint32_t x, uint32_t y );\r
+extern uint32_t FB_DrawCircle( uint32_t x, uint32_t y, uint32_t r );\r
+extern uint32_t FB_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwRadius);\r
+extern uint32_t FB_DrawRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 );\r
+extern uint32_t FB_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 );\r
+extern uint32_t FB_DrawPicture( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2, const void *pBuffer );\r
+#endif /* #ifndef _FRAME_BUFFER_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup gmacb_module Ethernet GMACB Driver\r
+ *@{\r
+ * Implement GEMAC PHY driver, that initialize the PHY to prepare for\r
+ * ethernet transfer.\r
+ *\r
+ * \section Usage\r
+ * -# EMAC related pins and Driver should be initialized at first.\r
+ * -# Initialize GMACB Driver instance by invoking GMACB_Init().\r
+ * -# Initialize PHY connected via GMACB_InitPhy(), PHY address is\r
+ * automatically adjusted by attempt to read.\r
+ * -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so\r
+ * connection established.\r
+ *\r
+ *\r
+ * Related files:\n\r
+ * \ref gmacb.h\n\r
+ * \ref gmacb.c\n\r
+ * \ref gmii.h.\n\r
+ *\r
+ */\r
+/**@}*/\r
+\r
+#ifndef _GMACB_PHY_H\r
+#define _GMACB_PHY_H\r
+\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Definitions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** The reset length setting for external reset configuration */\r
+#define GMACB_RESET_LENGTH 0xD\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+ \r
+ \r
+/** The DM9161 instance */\r
+typedef struct _GMacb {\r
+ sGmacd *pGmacd; /**< Driver */\r
+ /** The retry & timeout settings */\r
+ uint32_t retryMax;\r
+ /** PHY address ( pre-defined by pins on reset ) */\r
+ uint8_t phyAddress;\r
+} GMacb;\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax);\r
+\r
+extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress);\r
+\r
+extern uint8_t GMACB_InitPhy(GMacb *pMacb, \r
+ uint32_t mck,\r
+ const Pin *pResetPins,\r
+ uint32_t nbResetPins,\r
+ const Pin *pEmacPins,\r
+ uint32_t nbEmacPins);\r
+\r
+extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb);\r
+\r
+extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings);\r
+\r
+extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size);\r
+\r
+extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size);\r
+\r
+extern void GMACB_DumpRegisters(GMacb *pMacb);\r
+\r
+extern uint8_t GMACB_ResetPhy(GMacb *pMacb);\r
+\r
+#endif // #ifndef _GMACB_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2008, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _GMII_DEFINE_H\r
+#define _GMII_DEFINE_H\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+/// Definitions\r
+//-----------------------------------------------------------------------------\r
+//IEEE defined Registers\r
+#define GMII_BMCR 0x0 // Basic Mode Control Register\r
+#define GMII_BMSR 0x1 // Basic Mode Status Register\r
+#define GMII_PHYID1R 0x2 // PHY Idendifier Register 1\r
+#define GMII_PHYID2R 0x3 // PHY Idendifier Register 2\r
+#define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register\r
+#define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register\r
+#define GMII_ANER 0x6 // Auto-negotiation Expansion Register\r
+#define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register\r
+#define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register\r
+#define GMII_AFEC0R 0x11 // AFE Control 0 Register\r
+#define GMII_AFEC3R 0x14 // AFE Control 3 Register\r
+#define GMII_RXERCR 0x15 // RXER Couter Register\r
+#define GMII_OMSSR 0x17 // Operation Mode Strap Status Register\r
+#define GMII_ECR 0x18 // Expanded Control Register\r
+#define GMII_ICSR 0x1B // Interrupt Control/Status Register\r
+#define GMII_FC 0x1C // Function Control\r
+#define GMII_LCSR 0x1D // LinkMD® Control/Status Register\r
+#define GMII_PC1R 0x1E // PHY Control 1 Register\r
+#define GMII_PC2R 0x1F // PHY Control 2 Register\r
+\r
+\r
+// PHY ID Identifier Register\r
+#define GMII_LSB_MASK 0x0U\r
+// definitions: MII_PHYID1\r
+#define GMII_OUI_MSB 0x0022\r
+// definitions: MII_PHYID2\r
+#define GMII_OUI_LSB 0x1572 // KSZ8061 PHY Id2\r
+\r
+\r
+\r
+// Basic Mode Control Register (BMCR)\r
+// Bit definitions: MII_BMCR\r
+#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation\r
+#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation\r
+#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps\r
+#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable\r
+#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation\r
+#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation\r
+#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation\r
+#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation\r
+// Reserved 7 // Read as 0, ignore on write\r
+#define GMII_SPEED_SELECT_MSB (1 << 6) // \r
+// Reserved 5 to 0 // Read as 0, ignore on write\r
+\r
+\r
+// Basic Mode Status Register (BMSR)\r
+// Bit definitions: MII_BMSR\r
+#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable\r
+#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable\r
+#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable\r
+#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable\r
+#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable\r
+// Reserved 10 to 9 // Read as 0, ignore on write\r
+#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15\r
+// Reserved 7\r
+#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression\r
+#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete\r
+#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault\r
+#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability\r
+#define GMII_LINK_STATUS (1 << 2) // Link Status\r
+#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect\r
+#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability\r
+\r
+\r
+// Auto-negotiation Advertisement Register (ANAR)\r
+// Auto-negotiation Link Partner Ability Register (ANLPAR)\r
+// Bit definitions: MII_ANAR, MII_ANLPAR\r
+#define GMII_NP (1 << 15) // Next page Indication\r
+// Reserved 7\r
+#define GMII_RF (1 << 13) // Remote Fault\r
+// Reserved 12 // Write as 0, ignore on read\r
+#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)\r
+ // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) \r
+#define GMII_T4 (1 << 9) // 100BASE-T4 Support\r
+#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support\r
+#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support\r
+#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support\r
+#define GMII_10_HDX (1 << 5) // 10BASE-T Support\r
+// Selector 4 to 0 // Protocol Selection Bits\r
+#define GMII_AN_IEEE_802_3 0x00001\r
+\r
+\r
+\r
+#endif // #ifndef _MII_DEFINE_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _HAMMING_\r
+#define _HAMMING_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Defines\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * These are the possible errors when trying to verify a block of data encoded\r
+ * using a Hamming code:\r
+ *\r
+ * \section Errors\r
+ * - Hamming_ERROR_SINGLEBIT\r
+ * - Hamming_ERROR_ECC\r
+ * - Hamming_ERROR_MULTIPLEBITS\r
+ */\r
+\r
+/** A single bit was incorrect but has been recovered. */\r
+#define Hamming_ERROR_SINGLEBIT 1\r
+\r
+/** The original code has been corrupted. */\r
+#define Hamming_ERROR_ECC 2\r
+\r
+/** Multiple bits are incorrect in the data and they cannot be corrected. */\r
+#define Hamming_ERROR_MULTIPLEBITS 3\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+extern void Hamming_Compute256x( const uint8_t* pucData, uint32_t dwSize, uint8_t* pucCode ) ;\r
+\r
+extern uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) ;\r
+\r
+#endif /* _HAMMING_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface of ILI9325 driver.\r
+ *\r
+ */\r
+\r
+#ifndef _ILI9488_H_\r
+#define _ILI9488_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdint.h>\r
+typedef uint32_t LcdColor_t ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+//#define LCD_SPI_3\r
+\r
+/* ILI9325 ID code */\r
+#define ILI9488_DEVICE_CODE 0x9488\r
+\r
+#define ILI9488_LCD_WIDTH 320\r
+#define ILI9488_LCD_HEIGHT 480\r
+#define ILI9488_SELF_TEST_OK 0xC0\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+typedef volatile uint8_t REG8;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Marcos\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** LCD index register address */\r
+#define ILI9488_CMD(x) (uint16_t)(x & 0x00FF)\r
+/** ILI9488 status register address */\r
+#define ILI9488_PARAM(x) (uint16_t)(x | 0x100)\r
+ \r
+\r
+#define ILI9488_cs 1\r
+\r
+/* Pixel cache used to speed up communication */\r
+#define LCD_DATA_CACHE_SIZE BOARD_LCD_WIDTH\r
+//extern LcdColor_t gLcdPixelCache[LCD_DATA_CACHE_SIZE];\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void ILI9488_WriteSingle( LcdColor_t data );\r
+extern void ILI9488_WriteRAM_Prepare( void );\r
+extern void ILI9488_WriteRAM( LcdColor_t dwColor );\r
+extern void ILI9488_ReadRAM_Prepare( void );\r
+extern void ILI9488_WriteRAMBuffer( const LcdColor_t *pBuf, uint32_t size);\r
+extern void ILI9488_SetCursor(uint16_t x, uint16_t y);\r
+extern uint32_t ILI9488_ReadRAM( void );\r
+extern uint32_t ILI9488_Initialize( void );\r
+extern void ILI9488_On( void );\r
+extern void ILI9488_Off( void );\r
+extern void ILI9488_PowerDown( void );\r
+extern void ILI9488_SetWindow( uint16_t dwX, uint16_t dwY, uint16_t dwWidth, uint16_t dwHeight );\r
+extern void ILI9488_SetDisplayLandscape( uint8_t dwRGB, uint8_t LandscaprMode );\r
+extern void ILI9488_SetDisplayPortrait( uint8_t dwRGB );\r
+extern void ILI9488_SetVerticalScrollWindow( uint16_t dwStartAdd, uint16_t dwHeight );\r
+extern void ILI9488_VerticalScroll( uint16_t wY );\r
+extern void ILI9488_SetPartialImage1( uint32_t dwDisplayPos, uint32_t dwStart, uint32_t dwEnd );\r
+extern void ILI9488_SetPartialImage2( uint32_t dwDisplayPos, uint32_t dwStart, uint32_t dwEnd );\r
+extern void ILI9488_TestPattern( void );\r
+extern uint32_t ILI9488_SetColor( uint32_t dwRgb24Bits );\r
+extern void ILI9488_ExitScrollMode(void );\r
+extern void ILI9488_SetPartialWindow( uint16_t Start, uint16_t End);\r
+#endif /* #ifndef ILI9488 */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief IL9488 display controller register and bitfield definitions\r
+ *\r
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef ILI9488_REG_H_INCLUDED\r
+#define ILI9488_REG_H_INCLUDED\r
+\r
+/* Level 1 Commands (from the display Datasheet) */\r
+#define ILI9488_CMD_NOP 0x00\r
+#define ILI9488_CMD_SOFTWARE_RESET 0x01\r
+#define ILI9488_CMD_READ_DISP_ID 0x04\r
+#define ILI9488_CMD_READ_ERROR_DSI 0x05\r
+#define ILI9488_CMD_READ_DISP_STATUS 0x09\r
+#define ILI9488_CMD_READ_DISP_POWER_MODE 0x0A\r
+#define ILI9488_CMD_READ_DISP_MADCTRL 0x0B\r
+#define ILI9488_CMD_READ_DISP_PIXEL_FORMAT 0x0C\r
+#define ILI9488_CMD_READ_DISP_IMAGE_MODE 0x0D\r
+#define ILI9488_CMD_READ_DISP_SIGNAL_MODE 0x0E\r
+#define ILI9488_CMD_READ_DISP_SELF_DIAGNOSTIC 0x0F\r
+#define ILI9488_CMD_ENTER_SLEEP_MODE 0x10\r
+#define ILI9488_CMD_SLEEP_OUT 0x11\r
+#define ILI9488_CMD_PARTIAL_MODE_ON 0x12\r
+#define ILI9488_CMD_NORMAL_DISP_MODE_ON 0x13\r
+#define ILI9488_CMD_DISP_INVERSION_OFF 0x20\r
+#define ILI9488_CMD_DISP_INVERSION_ON 0x21\r
+#define ILI9488_CMD_PIXEL_OFF 0x22\r
+#define ILI9488_CMD_PIXEL_ON 0x23\r
+#define ILI9488_CMD_DISPLAY_OFF 0x28\r
+#define ILI9488_CMD_DISPLAY_ON 0x29\r
+#define ILI9488_CMD_COLUMN_ADDRESS_SET 0x2A\r
+#define ILI9488_CMD_PAGE_ADDRESS_SET 0x2B\r
+#define ILI9488_CMD_MEMORY_WRITE 0x2C\r
+#define ILI9488_CMD_MEMORY_READ 0x2E\r
+#define ILI9488_CMD_PARTIAL_AREA 0x30\r
+#define ILI9488_CMD_VERT_SCROLL_DEFINITION 0x33\r
+#define ILI9488_CMD_TEARING_EFFECT_LINE_OFF 0x34\r
+#define ILI9488_CMD_TEARING_EFFECT_LINE_ON 0x35\r
+#define ILI9488_CMD_MEMORY_ACCESS_CONTROL 0x36\r
+#define ILI9488_CMD_VERT_SCROLL_START_ADDRESS 0x37\r
+#define ILI9488_CMD_IDLE_MODE_OFF 0x38\r
+#define ILI9488_CMD_IDLE_MODE_ON 0x39\r
+#define ILI9488_CMD_COLMOD_PIXEL_FORMAT_SET 0x3A\r
+#define ILI9488_CMD_WRITE_MEMORY_CONTINUE 0x3C\r
+#define ILI9488_CMD_READ_MEMORY_CONTINUE 0x3E\r
+#define ILI9488_CMD_SET_TEAR_SCANLINE 0x44\r
+#define ILI9488_CMD_GET_SCANLINE 0x45\r
+#define ILI9488_CMD_WRITE_DISPLAY_BRIGHTNESS 0x51\r
+#define ILI9488_CMD_READ_DISPLAY_BRIGHTNESS 0x52\r
+#define ILI9488_CMD_WRITE_CTRL_DISPLAY 0x53\r
+#define ILI9488_CMD_READ_CTRL_DISPLAY 0x54\r
+#define ILI9488_CMD_WRITE_CONTENT_ADAPT_BRIGHTNESS 0x55\r
+#define ILI9488_CMD_READ_CONTENT_ADAPT_BRIGHTNESS 0x56\r
+#define ILI9488_CMD_WRITE_MIN_CAB_LEVEL 0x5E\r
+#define ILI9488_CMD_READ_MIN_CAB_LEVEL 0x5F\r
+#define ILI9488_CMD_READ_ABC_SELF_DIAG_RES 0x68\r
+#define ILI9488_CMD_READ_ID1 0xDA\r
+#define ILI9488_CMD_READ_ID2 0xDB\r
+#define ILI9488_CMD_READ_ID3 0xDC\r
+\r
+/* Level 2 Commands (from the display Datasheet) */\r
+#define ILI9488_CMD_INTERFACE_MODE_CONTROL 0xB0\r
+#define ILI9488_CMD_FRAME_RATE_CONTROL_NORMAL 0xB1\r
+#define ILI9488_CMD_FRAME_RATE_CONTROL_IDLE_8COLOR 0xB2\r
+#define ILI9488_CMD_FRAME_RATE_CONTROL_PARTIAL 0xB3\r
+#define ILI9488_CMD_DISPLAY_INVERSION_CONTROL 0xB4\r
+#define ILI9488_CMD_BLANKING_PORCH_CONTROL 0xB5\r
+#define ILI9488_CMD_DISPLAY_FUNCTION_CONTROL 0xB6\r
+#define ILI9488_CMD_ENTRY_MODE_SET 0xB7\r
+#define ILI9488_CMD_BACKLIGHT_CONTROL_1 0xB9\r
+#define ILI9488_CMD_BACKLIGHT_CONTROL_2 0xBA\r
+#define ILI9488_CMD_HS_LANES_CONTROL 0xBE\r
+#define ILI9488_CMD_POWER_CONTROL_1 0xC0\r
+#define ILI9488_CMD_POWER_CONTROL_2 0xC1\r
+#define ILI9488_CMD_POWER_CONTROL_NORMAL_3 0xC2\r
+#define ILI9488_CMD_POWER_CONTROL_IDEL_4 0xC3\r
+#define ILI9488_CMD_POWER_CONTROL_PARTIAL_5 0xC4\r
+#define ILI9488_CMD_VCOM_CONTROL_1 0xC5\r
+#define ILI9488_CMD_CABC_CONTROL_1 0xC6\r
+#define ILI9488_CMD_CABC_CONTROL_2 0xC8\r
+#define ILI9488_CMD_CABC_CONTROL_3 0xC9\r
+#define ILI9488_CMD_CABC_CONTROL_4 0xCA\r
+#define ILI9488_CMD_CABC_CONTROL_5 0xCB\r
+#define ILI9488_CMD_CABC_CONTROL_6 0xCC\r
+#define ILI9488_CMD_CABC_CONTROL_7 0xCD\r
+#define ILI9488_CMD_CABC_CONTROL_8 0xCE\r
+#define ILI9488_CMD_CABC_CONTROL_9 0xCF\r
+#define ILI9488_CMD_NVMEM_WRITE 0xD0\r
+#define ILI9488_CMD_NVMEM_PROTECTION_KEY 0xD1\r
+#define ILI9488_CMD_NVMEM_STATUS_READ 0xD2\r
+#define ILI9488_CMD_READ_ID4 0xD3\r
+#define ILI9488_CMD_ADJUST_CONTROL_1 0xD7\r
+#define ILI9488_CMD_READ_ID_VERSION 0xD8\r
+#define ILI9488_CMD_POSITIVE_GAMMA_CORRECTION 0xE0\r
+#define ILI9488_CMD_NEGATIVE_GAMMA_CORRECTION 0xE1\r
+#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_1 0xE2\r
+#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_2 0xE3\r
+#define ILI9488_CMD_SET_IMAGE_FUNCTION 0xE9\r
+#define ILI9488_CMD_ADJUST_CONTROL_2 0xF2\r
+#define ILI9488_CMD_ADJUST_CONTROL_3 0xF7\r
+#define ILI9488_CMD_ADJUST_CONTROL_4 0xF8\r
+#define ILI9488_CMD_ADJUST_CONTROL_5 0xF9\r
+#define ILI9488_CMD_SPI_READ_SETTINGS 0xFB\r
+#define ILI9488_CMD_ADJUST_CONTROL_6 0xFC\r
+#define ILI9488_CMD_ADJUST_CONTROL_7 0xFF\r
+\r
+#endif /* ILI9488_REGS_H_INCLUDED */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef COLOR_H\r
+#define COLOR_H\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * RGB 24-bits color table definition.\r
+ *\r
+ */\r
+\r
+/*\r
+ * RGB 24 Bpp\r
+ * RGB 888\r
+ * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0\r
+ */\r
+\r
+#define COLOR_BLACK 0x000000\r
+#define COLOR_WHITE 0xFFFFFF\r
+\r
+#define COLOR_BLUE 0x0000FF\r
+#define COLOR_GREEN 0x00FF00\r
+#define COLOR_RED 0xFF0000\r
+\r
+#define COLOR_NAVY 0x000080\r
+#define COLOR_DARKBLUE 0x00008B\r
+#define COLOR_DARKGREEN 0x006400\r
+#define COLOR_DARKCYAN 0x008B8B\r
+#define COLOR_CYAN 0x00FFFF\r
+#define COLOR_TURQUOISE 0x40E0D0\r
+#define COLOR_INDIGO 0x4B0082\r
+#define COLOR_DARKRED 0x800000\r
+#define COLOR_OLIVE 0x808000\r
+#define COLOR_GRAY 0x808080\r
+#define COLOR_SKYBLUE 0x87CEEB\r
+#define COLOR_BLUEVIOLET 0x8A2BE2\r
+#define COLOR_LIGHTGREEN 0x90EE90\r
+#define COLOR_DARKVIOLET 0x9400D3\r
+#define COLOR_YELLOWGREEN 0x9ACD32\r
+#define COLOR_BROWN 0xA52A2A\r
+#define COLOR_DARKGRAY 0xA9A9A9\r
+#define COLOR_SIENNA 0xA0522D\r
+#define COLOR_LIGHTBLUE 0xADD8E6\r
+#define COLOR_GREENYELLOW 0xADFF2F\r
+#define COLOR_SILVER 0xC0C0C0\r
+#define COLOR_LIGHTGREY 0xD3D3D3\r
+#define COLOR_LIGHTCYAN 0xE0FFFF\r
+#define COLOR_VIOLET 0xEE82EE\r
+#define COLOR_AZUR 0xF0FFFF\r
+#define COLOR_BEIGE 0xF5F5DC\r
+#define COLOR_MAGENTA 0xFF00FF\r
+#define COLOR_TOMATO 0xFF6347\r
+#define COLOR_GOLD 0xFFD700\r
+#define COLOR_ORANGE 0xFFA500\r
+#define COLOR_SNOW 0xFFFAFA\r
+#define COLOR_YELLOW 0xFFFF00\r
+\r
+#define BLACK 0x0000\r
+#define BLUE 0x001F\r
+#define RED 0xF800\r
+#define GREEN 0x07E0\r
+#define WHITE 0xFFFF\r
+\r
+#define BLUE_LEV( level) ( (level)&BLUE ) // level is in [0; 31]\r
+#define GREEN_LEV(level) ( (((level)*2)<<5)&GREEN ) // level is in [0; 31]\r
+#define RED_LEV( level) ( ((level)<<(5+6))&RED ) // level is in [0; 31]\r
+#define GRAY_LEV( level) ( BLUE_LEV(level) | GREEN_LEV(level) | RED_LEV(level) ) // level is in [0; 31]\r
+\r
+ \r
+#define RGB_24_TO_18BIT(RGB) (((RGB >>18) << 18) | (((RGB & 0x00FF00) >>10) << 10) | (RGB & 0x0000FC))\r
+#define RGB_16_TO_18BIT(RGB) (((((RGB >>11)*63)/31) << 18) | (RGB & 0x00FC00) | (((RGB & 0x00001F)*63)/31) )\r
+#define BGR_TO_RGB_18BIT(RGB) ((RGB & 0xFF0000) | ((RGB & 0x00FF00) >> 8 ) | ( (RGB & 0x0000FC) >> 16 ))\r
+\r
+#define BGR_16_TO_18BITRGB(RGB) BGR_TO_RGB_18BIT(RGB_16_TO_18BIT(RGB))\r
+ \r
+#endif /* #define COLOR_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /**\r
+ * \file\r
+ *\r
+ * Interface for draw function on LCD.\r
+ *\r
+ */\r
+\r
+#ifndef DRAW_H\r
+#define DRAW_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+#include "lcd_gimp_image.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Horizontal direction line definition */\r
+#define DIRECTION_HLINE 0\r
+/** Vertical direction line definition */\r
+#define DIRECTION_VLINE 1\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void LCDD_Fill( uint32_t color ) ;\r
+\r
+extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t c ) ;\r
+\r
+extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) ;\r
+\r
+extern void LCDD_DrawLine( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 , uint32_t color ) ;\r
+\r
+extern uint32_t LCDD_DrawLineBresenham( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 , uint32_t color);\r
+\r
+extern void LCDD_DrawRectangle( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;\r
+\r
+extern void LCDD_DrawRectangleWithFill( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;\r
+\r
+extern uint32_t LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color ) ;\r
+\r
+extern uint32_t LCD_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwRadius, uint32_t color);\r
+\r
+extern void LCDD_DrawString( uint32_t x, uint32_t y, const uint8_t *pString, uint32_t color ) ;\r
+\r
+extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) ;\r
+\r
+extern void LCDD_GetStringSize( const uint8_t *pString, uint32_t *pWidth, uint32_t *pHeight ) ;\r
+\r
+extern void LCDD_DrawImage( uint32_t x, uint32_t y, const LcdColor_t *pImage, uint32_t width, uint32_t height ) ;\r
+\r
+extern void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage );\r
+\r
+extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;\r
+\r
+#endif /* #ifndef DRAW_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for draw font on LCD.\r
+ *\r
+ */\r
+\r
+/**\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * The font.h files declares a font structure and a LCDD_DrawChar function\r
+ * that must be implemented by a font definition file to be used with the\r
+ * LCDD_DrawString method of draw.h.\r
+ *\r
+ * The font10x14.c implements the necessary variable and function for a 10x14\r
+ * font.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Declare a gFont global variable with the necessary Font information.\r
+ * -# Implement an LCDD_DrawChar function which displays the specified\r
+ * character on the LCD.\r
+ * -# Use the LCDD_DrawString method defined in draw.h to display a complete\r
+ * string.\r
+ */\r
+\r
+#ifndef _LCD_FONT_\r
+#define _LCD_FONT_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/** \brief Describes the font (width, height, supported characters, etc.) used by\r
+ * the LCD driver draw API.\r
+ */\r
+typedef struct _Font {\r
+ /* Font width in pixels. */\r
+ uint8_t width;\r
+ /* Font height in pixels. */\r
+ uint8_t height;\r
+} Font;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Global variable describing the font being instancied. */\r
+extern const Font gFont;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) ;\r
+\r
+extern void LCD_DrawString( uint32_t dwX, uint32_t dwY, const uint8_t *pString, uint32_t color );\r
+\r
+extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor ) ;\r
+\r
+#endif /* #ifndef LCD_FONT_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /**\r
+ * \file\r
+ *\r
+ * Font 10x14 table definition.\r
+ *\r
+ */\r
+\r
+#ifndef _LCD_FONT_10x14_\r
+#define _LCD_FONT_10x14_\r
+\r
+#include <stdint.h>\r
+\r
+/** Char set of font 10x14 */\r
+extern const uint8_t pCharset10x14[] ;\r
+\r
+#endif /* #ifdef _LCD_FONT_10x14_ */\r
--- /dev/null
+#ifndef _GIMP_IMAGE_\r
+#define _GIMP_IMAGE_\r
+\r
+#include <stdint.h>\r
+\r
+typedef struct _SGIMPImage\r
+{\r
+ uint32_t dwWidth;\r
+ uint32_t dwHeight;\r
+ uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */ \r
+ uint8_t* pucPixel_data ;\r
+} SGIMPImage ;\r
+\r
+#endif // _GIMP_IMAGE_\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for LCD driver.\r
+ *\r
+ */ \r
+\r
+#ifndef LCDD_H\r
+#define LCDD_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void LCDD_Initialize(void);\r
+\r
+extern void LCDD_On(void);\r
+\r
+extern void LCDD_Off(void);\r
+\r
+extern void LCDD_SetBacklight (uint32_t step);\r
+\r
+#endif /* #ifndef LCDD_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ * \r
+ * Small set of functions for simple and portable LED usage.\r
+ * \r
+ * \section Usage\r
+ * \r
+ * -# Configure one or more LEDs using LED_Configure and\r
+ * LED_ConfigureAll.\r
+ * -# Set, clear and toggle LEDs using LED_Set, LED_Clear and\r
+ * LED_Toggle.\r
+ * \r
+ * LEDs are numbered starting from 0; the number of LEDs depend on the\r
+ * board being used. All the functions defined here will compile properly\r
+ * regardless of whether the LED is defined or not; they will simply\r
+ * return 0 when a LED which does not exist is given as an argument.\r
+ * Also, these functions take into account how each LED is connected on to\r
+ * board; thus, \ref LED_Set might change the level on the corresponding pin\r
+ * to 0 or 1, but it will always light the LED on; same thing for the other\r
+ * methods.\r
+ */\r
+\r
+#ifndef _LED_\r
+#define _LED_\r
+\r
+#include <stdint.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern uint32_t LED_Configure( uint32_t dwLed ) ;\r
+\r
+extern uint32_t LED_Set( uint32_t dwLed ) ;\r
+\r
+extern uint32_t LED_Clear( uint32_t dwLed ) ;\r
+\r
+extern uint32_t LED_Toggle( uint32_t dwLed ) ;\r
+\r
+#endif /* #ifndef LED_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _MATH_\r
+#define _MATH_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+extern uint32_t min( uint32_t dwA, uint32_t dwB ) ;\r
+extern uint32_t absv( int32_t lValue ) ;\r
+extern uint32_t power( uint32_t dwX, uint32_t dwY ) ;\r
+\r
+#endif /* #ifndef _MATH_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef OMNIVISION_H\r
+#define OMNIVISION_H\r
+\r
+\r
+/*---------------------------------------------------------------------------\r
+ * TYPE\r
+ *---------------------------------------------------------------------------*/\r
+/** define a structure for ovxxxx register initialization values */\r
+struct ov_reg\r
+{\r
+ /* Register to be written */\r
+ uint16_t reg;\r
+ /* Value to be written in the register */\r
+ uint8_t val;\r
+};\r
+\r
+\r
+/*---------------------------------------------------------------------------\r
+ * DEFINITAION\r
+ *---------------------------------------------------------------------------*/\r
+#define OV_2640 0x00\r
+#define OV_2643 0x01\r
+#define OV_5640 0x02\r
+#define OV_7740 0x03\r
+#define OV_9740 0x04\r
+#define OV_UNKNOWN 0xFF\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern uint8_t ov_init(Twid *pTwid);\r
+extern void ov_DumpRegisters8(Twid *pTwid);\r
+extern void ov_DumpRegisters16(Twid *pTwid);\r
+extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist);\r
+extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist);\r
+extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData);\r
+extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData);\r
+extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val);\r
+extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val);\r
+extern void isOV5640_AF_InitDone(Twid *pTwid);\r
+extern uint32_t ov_5640_AF_single(Twid *pTwid);\r
+extern uint32_t ov_5640_AF_continue(Twid *pTwid);\r
+extern uint32_t ov_5640_AFPause(Twid *pTwid);\r
+extern uint32_t ov_5640_AFrelease(Twid *pTwid);\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifndef OV_H\r
+#define OV_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Captor capture size */\r
+struct capture_size {\r
+ uint32_t width;\r
+ uint32_t height;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth);\r
+extern void ov_5640Afc_Firmware(Twid *pTwid);\r
+#endif\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _YUV_H_\r
+#define _YUV_H_\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include <board.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported variable\r
+ *---------------------------------------------------------------------------*/\r
+extern const struct ov_reg ov2640_yuv_vga[];\r
+extern const struct ov_reg ov2640_yuv_qvga[];\r
+\r
+extern const struct ov_reg ov2643_yuv_vga[];\r
+extern const struct ov_reg ov2643_yuv_swvga[];\r
+extern const struct ov_reg ov2643_yuv_uxga[];\r
+\r
+extern const struct ov_reg ov5640_yuv_vga[];\r
+extern const struct ov_reg ov5640_yuv_sxga[];\r
+extern const struct ov_reg ov5640_afc[];\r
+\r
+extern const struct ov_reg ov7740_yuv_vga[];\r
+extern const struct ov_reg ov9740_yuv_sxga[];\r
+extern const struct ov_reg ov9740_yuv_vga[];\r
+\r
+#endif // #ifndef _YUV_H_\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the S25fl1 Serialflash driver.\r
+ *\r
+ */\r
+\r
+#ifndef S25FL1_H\r
+#define S25FL1_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define Size(pAt25) ((pAt25)->pDesc->size)\r
+#define PageSize(pAt25) ((pAt25)->pDesc->pageSize)\r
+#define BlockSize(pAt25) ((pAt25)->pDesc->blockSize)\r
+#define Name(pAt25) ((pAt25)->pDesc->name)\r
+#define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF)\r
+#define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25))\r
+#define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25))\r
+#define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25))\r
+#define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Device is protected, operation cannot be carried out. */\r
+#define ERROR_PROTECTED 1\r
+/** Device is busy executing a command. */\r
+#define ERROR_BUSY 2\r
+/** There was a problem while trying to program page data. */\r
+#define ERROR_PROGRAM 3\r
+/** There was an SPI communication error. */\r
+#define ERROR_SPI 4\r
+\r
+/** Device ready/busy status bit. */\r
+#define STATUS_RDYBSY (1 << 0)\r
+/** Device is ready. */\r
+#define STATUS_RDYBSY_READY (0 << 0)\r
+/** Device is busy with internal operations. */\r
+#define STATUS_RDYBSY_BUSY (1 << 0)\r
+/** Write enable latch status bit. */\r
+#define STATUS_WEL (1 << 1)\r
+/** Device is not write enabled. */\r
+#define STATUS_WEL_DISABLED (0 << 1)\r
+/** Device is write enabled. */\r
+#define STATUS_WEL_ENABLED (1 << 1)\r
+/** Software protection status bitfield. */\r
+#define STATUS_SWP (3 << 2)\r
+/** All sectors are software protected. */\r
+#define STATUS_SWP_PROTALL (3 << 2)\r
+/** Some sectors are software protected. */\r
+#define STATUS_SWP_PROTSOME (1 << 2)\r
+/** No sector is software protected. */\r
+#define STATUS_SWP_PROTNONE (0 << 2)\r
+/** Write protect pin status bit. */\r
+#define STATUS_WPP (1 << 4)\r
+/** Write protect signal is not asserted. */\r
+#define STATUS_WPP_NOTASSERTED (0 << 4)\r
+/** Write protect signal is asserted. */\r
+#define STATUS_WPP_ASSERTED (1 << 4)\r
+/** Erase/program error bit. */\r
+#define STATUS_EPE (1 << 5)\r
+/** Erase or program operation was successful. */\r
+#define STATUS_EPE_SUCCESS (0 << 5)\r
+/** Erase or program error detected. */\r
+#define STATUS_EPE_ERROR (1 << 5)\r
+/** Sector protection registers locked bit. */\r
+#define STATUS_SPRL (1 << 7)\r
+/** Sector protection registers are unlocked. */\r
+#define STATUS_SPRL_UNLOCKED (0 << 7)\r
+/** Sector protection registers are locked. */\r
+#define STATUS_SPRL_LOCKED (1 << 7)\r
+ \r
+/** Quad enable bit */\r
+#define STATUS_QUAD_ENABLE (1 << 1)\r
+ /** Quad enable bit */\r
+#define STATUS_WRAP_ENABLE (0 << 4)\r
+ \r
+#define STATUS_WRAP_BYTE (1 << 5)\r
+\r
+/** Read array command code. */\r
+#define READ_ARRAY 0x0B\r
+/** Read array (low frequency) command code. */\r
+#define READ_ARRAY_LF 0x03\r
+/** Fast Read array command code. */\r
+#define READ_ARRAY_DUAL 0x3B\r
+/** Fast Read array command code. */\r
+#define READ_ARRAY_QUAD 0x6B \r
+/** Fast Read array command code. */\r
+#define READ_ARRAY_DUAL_IO 0xBB\r
+/** Fast Read array command code. */\r
+#define READ_ARRAY_QUAD_IO 0xEB \r
+/** Block erase command code (4K block). */\r
+#define BLOCK_ERASE_4K 0x20\r
+/** Block erase command code (32K block). */\r
+#define BLOCK_ERASE_32K 0x52\r
+/** Block erase command code (64K block). */\r
+#define BLOCK_ERASE_64K 0xD8\r
+/** Chip erase command code 1. */\r
+#define CHIP_ERASE_1 0x60\r
+/** Chip erase command code 2. */\r
+#define CHIP_ERASE_2 0xC7\r
+/** Byte/page program command code. */\r
+#define BYTE_PAGE_PROGRAM 0x02\r
+/** Sequential program mode command code 1. */\r
+#define SEQUENTIAL_PROGRAM_1 0xAD\r
+/** Sequential program mode command code 2. */\r
+#define SEQUENTIAL_PROGRAM_2 0xAF\r
+/** Write enable command code. */\r
+#define WRITE_ENABLE 0x06\r
+/** Write disable command code. */\r
+#define WRITE_DISABLE 0x04\r
+/** Protect sector command code. */\r
+#define PROTECT_SECTOR 0x36\r
+/** Unprotect sector command code. */\r
+#define UNPROTECT_SECTOR 0x39\r
+/** Read sector protection registers command code. */\r
+#define READ_SECTOR_PROT 0x3C\r
+/** Read status register command code. */\r
+#define READ_STATUS 0x05\r
+/** Write status register command code. */\r
+#define WRITE_STATUS 0x01\r
+/** Read manufacturer and device ID command code. */\r
+#define READ_JEDEC_ID 0x9F\r
+/** Deep power-down command code. */\r
+#define DEEP_PDOWN 0xB9\r
+/** Resume from deep power-down command code. */\r
+#define RES_DEEP_PDOWN 0xAB\r
+/** Resume from deep power-down command code. */\r
+#define SOFT_RESET_ENABLE 0x66\r
+/** Resume from deep power-down command code. */\r
+#define SOFT_RESET 0x99\r
+/** Resume from deep power-down command code. */\r
+#define WRAP_ENABLE 0x77\r
+ \r
+\r
+\r
+/** SPI Flash Manufacturer JEDEC ID */\r
+#define ATMEL_SPI_FLASH 0x1F\r
+#define ST_SPI_FLASH 0x20\r
+#define WINBOND_SPI_FLASH 0xEF\r
+#define MACRONIX_SPI_FLASH 0xC2\r
+#define SST_SPI_FLASH 0xBF\r
+\r
+\r
+\r
+\r
+/**\r
+\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern unsigned int S25FL1D_ReadJedecId(void);\r
+\r
+extern void S25FL1D_InitFlashInterface(void);\r
+\r
+extern void S25FL1D_SoftReset(void);\r
+\r
+extern unsigned char S25FL1D_Unprotect(void);\r
+\r
+extern unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size);\r
+\r
+extern void S25FL1D_EnableQuadMode(void);\r
+\r
+extern void S25FL1D_EnableWrap(uint8_t ByetAlign);\r
+\r
+extern unsigned char S25FL1D_EraseChip(void);\r
+\r
+extern unsigned char S25FL1D_EraseSector( unsigned int address);\r
+\r
+extern unsigned char S25FL1D_Erase64KBlock( unsigned int address);\r
+\r
+extern unsigned char S25FL1D_Write(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address);\r
+\r
+extern unsigned char S25FL1D_Read(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address);\r
+\r
+extern unsigned char S25FL1D_ReadDual(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address);\r
+\r
+extern unsigned char S25FL1D_ReadQuad(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address);\r
+\r
+extern unsigned char S25FL1D_ReadQuadIO(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address,\r
+ uint8_t ContMode);\r
+\r
+#endif // #ifndef S25FL1_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the S25fl1 SPI driver.\r
+ *\r
+ */\r
+\r
+#ifndef S25FL1_SPI_H\r
+#define S25FL1_SPI_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <board.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define S25FL1_Size(pS25fl1) ((pS25fl1)->pDesc->size)\r
+#define S25FL1_PageSize(pS25fl1) ((pS25fl1)->pDesc->pageSize)\r
+#define S25FL1_BlockSize(pS25fl1) ((pS25fl1)->pDesc->blockSize)\r
+#define S25FL1_Name(pS25fl1) ((pS25fl1)->pDesc->name)\r
+#define S25FL1_ManId(pS25fl1) (((pS25fl1)->pDesc->jedecId) & 0xFF)\r
+#define S25FL1_PageNumber(pS25fl1) (S25FL1_Size(pS25FL1) / S25FL1_PageSize(pS25fl1))\r
+#define S25FL1_BlockNumber(pS25fl1) (S25FL1_Size(pS25fl1) / S25FL1_BlockSize(pS25fl1))\r
+#define S25FL1_PagePerBlock(pS25fl1) (S25FL1_BlockSize(pS25fl1) / S25FL1_PageSize(pS25fl1))\r
+#define S25FL1_BlockEraseCmd(pS25fl1) ((pS25fl1)->pDesc->blockEraseCmd)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Device is protected, operation cannot be carried out. */\r
+#define S25FL1_ERROR_PROTECTED 1\r
+/** Device is busy executing a command. */\r
+#define S25FL1_ERROR_BUSY 2\r
+/** There was a problem while trying to program page data. */\r
+#define S25FL1_ERROR_PROGRAM 3\r
+/** There was an SPI communication error. */\r
+#define S25FL1_ERROR_SPI 4\r
+\r
+/** Device ready/busy status bit. */\r
+#define S25FL1_STATUS_RDYBSY (1 << 0)\r
+/** Device is ready. */\r
+#define S25FL1_STATUS_RDYBSY_READY (0 << 0)\r
+/** Device is busy with internal operations. */\r
+#define S25FL1_STATUS_RDYBSY_BUSY (1 << 0)\r
+/** Write enable latch status bit. */\r
+#define S25FL1_STATUS_WEL (1 << 1)\r
+/** Device is not write enabled. */\r
+#define S25FL1_STATUS_WEL_DISABLED (0 << 1)\r
+/** Device is write enabled. */\r
+#define S25FL1_STATUS_WEL_ENABLED (1 << 1)\r
+/** Software protection status bitfield. */\r
+#define S25FL1_STATUS_SWP (3 << 2)\r
+/** All sectors are software protected. */\r
+#define S25FL1_STATUS_SWP_PROTALL (3 << 2)\r
+/** Some sectors are software protected. */\r
+#define S25FL1_STATUS_SWP_PROTSOME (1 << 2)\r
+/** No sector is software protected. */\r
+#define S25FL1_STATUS_SWP_PROTNONE (0 << 2)\r
+/** Write protect pin status bit. */\r
+#define S25FL1_STATUS_WPP (1 << 4)\r
+/** Write protect signal is not asserted. */\r
+#define S25FL1_STATUS_WPP_NOTASSERTED (0 << 4)\r
+/** Write protect signal is asserted. */\r
+#define S25FL1_STATUS_WPP_ASSERTED (1 << 4)\r
+/** Erase/program error bit. */\r
+#define S25FL1_STATUS_EPE (1 << 5)\r
+/** Erase or program operation was successful. */\r
+#define S25FL1_STATUS_EPE_SUCCESS (0 << 5)\r
+/** Erase or program error detected. */\r
+#define S25FL1_STATUS_EPE_ERROR (1 << 5)\r
+/** Sector protection registers locked bit. */\r
+#define S25FL1_STATUS_SPRL (1 << 7)\r
+/** Sector protection registers are unlocked. */\r
+#define S25FL1_STATUS_SPRL_UNLOCKED (0 << 7)\r
+/** Sector protection registers are locked. */\r
+#define S25FL1_STATUS_SPRL_LOCKED (1 << 7)\r
+\r
+/** Read array command code. */\r
+#define S25FL1_READ_ARRAY 0x0B\r
+/** Read array (low frequency) command code. */\r
+#define S25FL1_READ_ARRAY_LF 0x03\r
+/** Block erase command code (4K block). */\r
+#define S25FL1_BLOCK_ERASE_4K 0x20\r
+/** Block erase command code (32K block). */\r
+#define S25FL1_BLOCK_ERASE_32K 0x52\r
+/** Block erase command code (64K block). */\r
+#define S25FL1_BLOCK_ERASE_64K 0xD8\r
+/** Chip erase command code 1. */\r
+#define S25FL1_CHIP_ERASE_1 0x60\r
+/** Chip erase command code 2. */\r
+#define S25FL1_CHIP_ERASE_2 0xC7\r
+/** Byte/page program command code. */\r
+#define S25FL1_BYTE_PAGE_PROGRAM 0x02\r
+/** Sequential program mode command code 1. */\r
+#define S25FL1_SEQUENTIAL_PROGRAM_1 0xAD\r
+/** Sequential program mode command code 2. */\r
+#define S25FL1_SEQUENTIAL_PROGRAM_2 0xAF\r
+/** Write enable command code. */\r
+#define S25FL1_WRITE_ENABLE 0x06\r
+/** Write disable command code. */\r
+#define S25FL1_WRITE_DISABLE 0x04\r
+/** Protect sector command code. */\r
+#define S25FL1_PROTECT_SECTOR 0x36\r
+/** Unprotect sector command code. */\r
+#define S25FL1_UNPROTECT_SECTOR 0x39\r
+/** Read sector protection registers command code. */\r
+#define S25FL1_READ_SECTOR_PROT 0x3C\r
+/** Read status register command code. */\r
+#define S25FL1_READ_STATUS 0x05\r
+/** Write status register command code. */\r
+#define S25FL1_WRITE_STATUS 0x01\r
+/** Read manufacturer and device ID command code. */\r
+#define S25FL1_READ_JEDEC_ID 0x9F\r
+/** Deep power-down command code. */\r
+#define S25FL1_DEEP_PDOWN 0xB9\r
+/** Resume from deep power-down command code. */\r
+#define S25FL1_RES_DEEP_PDOWN 0xAB\r
+\r
+/* Enter 4-BYTE ADDRESS mode */\r
+#define S25FL1_ENTER_4ADDR_MODE 0xB7\r
+/* Exit 4-BYTE ADDRESS mode */\r
+#define S25FL1_EXIT_4ADDR_MODE 0xE9\r
+\r
+/** SPI Flash Manufacturer JEDEC ID */\r
+#define ATMEL_SPI_FLASH 0x1F\r
+#define ST_SPI_FLASH 0x20\r
+#define WINBOND_SPI_FLASH 0xEF\r
+#define MACRONIX_SPI_FLASH 0xC2\r
+#define SST_SPI_FLASH 0xBF\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Describes a serial firmware flash device parameters. */\r
+typedef struct _S25fl1Desc {\r
+\r
+ /** Device string name. */\r
+ const char *name;\r
+ /** JEDEC ID of device. */\r
+ uint32_t jedecId;\r
+ /** Size of device in bytes. */\r
+ uint32_t size;\r
+ /** Size of one page in bytes. */\r
+ uint32_t pageSize;\r
+ /** Block erase size in bytes. */\r
+ uint32_t blockSize;\r
+ /** Block erase command. */\r
+ uint32_t blockEraseCmd;\r
+\r
+} S25fl1Desc;\r
+\r
+/**\r
+ * Serial flash driver structure. Holds the current state of the driver,\r
+ * including the current command and the descriptor for the underlying device.\r
+ */\r
+typedef struct _S25fl1 {\r
+\r
+ /** Pointer to the underlying QSPI driver. */\r
+ Qspid *pQspid;\r
+ /** Current command sent to the QSPI driver. */\r
+ QspidCmd command;\r
+ /** Pointer to a descriptor for the serial firmware flash device. */\r
+ const S25fl1Desc *pDesc;\r
+ /** Qspi Command buffer. */\r
+ qspiFrame CmdBuffer;\r
+ /** Polling mode */\r
+ uint32_t pollingMode;\r
+ /** Support for 4 byte address mode */\r
+ uint32_t fourbytemode;\r
+} S25fl1;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void S25fl1_Configure(S25fl1 *pS25fl1,\r
+ Qspid *pQspid,\r
+ uint8_t cs,\r
+ uint8_t polling);\r
+\r
+extern uint8_t S25fl1_SendCommand(\r
+ S25fl1 *pS25fl1,\r
+ uint8_t cmd,\r
+ uint8_t cmdSize,\r
+ uint8_t *pData,\r
+ uint32_t dataSize,\r
+ uint32_t address,\r
+ QspidCallback callback,\r
+ void *pArgument);\r
+\r
+extern uint8_t S25fl1_IsBusy(S25fl1 *pS25fl1);\r
+\r
+extern const S25fl1Desc * S25fl1_FindDevice(\r
+ S25fl1 *pS25fl1,\r
+ uint32_t jedecId);\r
+\r
+#endif /*#ifndef S25FL1_SPI_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file syscalls.h\r
+ *\r
+ * Implementation of newlib syscall.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+#include <sys/types.h>\r
+#include <sys/stat.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern caddr_t _sbrk ( int incr ) ;\r
+\r
+extern int link( char *old, char *new ) ;\r
+\r
+extern int _close( int file ) ;\r
+\r
+extern int _fstat( int file, struct stat *st ) ;\r
+\r
+extern int _isatty( int file ) ;\r
+\r
+extern int _lseek( int file, int ptr, int dir ) ;\r
+\r
+extern int _read(int file, char *ptr, int len) ;\r
+\r
+extern int _write( int file, char *ptr, int len ) ;\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Methods and definitions for Global time tick and wait functions.\r
+ *\r
+ * Defines a common and simpliest use of Time Tick, to increase tickCount\r
+ * every 1ms, the application can get this value through GetTickCount().\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Configure the System Tick with TimeTick_Configure() when MCK changed\r
+ * \note\r
+ * Must be done before any invoke of GetTickCount(), Wait() or Sleep().\r
+ * -# Uses GetTickCount to get current tick value.\r
+ * -# Uses Wait to wait several ms.\r
+ * -# Uses Sleep to enter wait for interrupt mode to wait several ms.\r
+ *\r
+ */\r
+\r
+#ifndef _TIMETICK_\r
+#define _TIMETICK_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;\r
+\r
+extern void TimeTick_Increment( uint32_t dwInc ) ;\r
+\r
+extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick);\r
+\r
+extern uint32_t GetTickCount( void ) ;\r
+\r
+extern void Wait( volatile uint32_t dwMs ) ;\r
+\r
+extern void Sleep( volatile uint32_t dwMs ) ;\r
+\r
+#endif /* _TIMETICK_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef WAV_H\r
+#define WAV_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Standard WAV file header information. */\r
+typedef struct _WavHeader\r
+{\r
+ /* Contains the letters "RIFF" in ASCII form. */\r
+ unsigned int chunkID;\r
+ /* Size of the rest of the chunk following this number.*/\r
+ unsigned int chunkSize;\r
+ /* Contains the letters "WAVE".*/\r
+ unsigned int format;\r
+ /* Contains the letters "fmt ".*/\r
+ unsigned int subchunk1ID;\r
+ /* 16 for PCM. This is the size of the rest of the Subchunk which follows this number.*/\r
+ unsigned int subchunk1Size;\r
+ /* PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression.*/\r
+ unsigned short audioFormat;\r
+ /* Mono = 1, Stereo = 2, etc.*/\r
+ unsigned short numChannels;\r
+ /* 8000, 44100, etc.*/\r
+ unsigned int sampleRate;\r
+ /* SampleRate * NumChannels * BitsPerSample/8*/\r
+ unsigned int byteRate;\r
+ /* NumChannels * BitsPerSample/8*/\r
+ unsigned short blockAlign; \r
+ /* 8 bits = 8, 16 bits = 16, etc.*/\r
+ unsigned short bitsPerSample;\r
+ /* Contains the letters "data".*/\r
+ unsigned int subchunk2ID;\r
+ /* Number of bytes in the data.*/\r
+ unsigned int subchunk2Size;\r
+\r
+} WavHeader;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern unsigned char WAV_IsValid(const WavHeader *header);\r
+\r
+extern void WAV_DisplayInfo(const WavHeader *header);\r
+\r
+#endif //#ifndef WAV_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation WM8904 driver.\r
+ *\r
+ */\r
+\r
+#ifndef WM8904_H\r
+#define WM8904_H\r
+\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+#define WM8904_CSB_STATE (0x0 << 0)\r
+\r
+/** Slave address */\r
+#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE\r
+#define CS2100_SLAVE_ADDRESS 0x4E\r
+\r
+\r
+/** Reset register*/\r
+#define WM8904_REG_RESET 0x00\r
+\r
+/** Bias control 0 register*/\r
+#define WM8904_REG_BIAS_CTRL0 0x04\r
+\r
+/** VMID control 0 register*/\r
+#define WM8904_REG_VMID_CTRL0 0x05\r
+\r
+/** MIC Bias control 0 register*/\r
+#define WM8904_REG_MICBIAS_CTRL0 0x06\r
+\r
+/** Bias control 1 register*/\r
+#define WM8904_REG_BIAS_CTRL1 0x07\r
+\r
+/** Power management control 0 register*/\r
+#define WM8904_REG_POWER_MANG0 0x0C\r
+/** Power management control 2 register*/\r
+#define WM8904_REG_POWER_MANG2 0x0E\r
+/** Power management control 3 register*/\r
+#define WM8904_REG_POWER_MANG3 0x0F\r
+/** Power management control 6 register*/\r
+#define WM8904_REG_POWER_MANG6 0x12\r
+\r
+/** Clock rate0 register*/\r
+#define WM8904_REG_CLOCK_RATE0 0x14\r
+/** Clock rate1 register*/\r
+#define WM8904_REG_CLOCK_RATE1 0x15\r
+\r
+/** Clock rate2 register*/\r
+#define WM8904_REG_CLOCK_RATE2 0x16\r
+\r
+/** Audio interface0 register*/\r
+#define WM8904_REG_AUD_INF0 0x18\r
+\r
+/** Audio interface1 register*/\r
+#define WM8904_REG_AUD_INF1 0x19\r
+/** Audio interface2 register*/\r
+#define WM8904_REG_AUD_INF2 0x1A\r
+/** Audio interface3 register*/\r
+#define WM8904_REG_AUD_INF3 0x1B\r
+\r
+/** ADC digital 0 register*/\r
+#define WM8904_REG_ADC_DIG0 0x20\r
+/** ADC digital 1 register*/\r
+#define WM8904_REG_ADC_DIG1 0x21\r
+\r
+/** Analogue left input 0 register*/\r
+#define WM8904_REG_ANALOGUE_LIN0 0x2C\r
+/** Analogue right input 0 register*/\r
+#define WM8904_REG_ANALOGUE_RIN0 0x2D\r
+\r
+/** Analogue left input 1 register*/\r
+#define WM8904_REG_ANALOGUE_LIN1 0x2E\r
+/** Analogue right input 1 register*/\r
+#define WM8904_REG_ANALOGUE_RIN1 0x2F\r
+\r
+/** Analogue left output 1 register*/\r
+#define WM8904_REG_ANALOGUE_LOUT1 0x39\r
+/** Analogue right output 1 register*/\r
+#define WM8904_REG_ANALOGUE_ROUT1 0x3A\r
+\r
+/** Analogue left output 2 register*/\r
+#define WM8904_REG_ANALOGUE_LOUT2 0x3B\r
+/** Analogue right output 2 register*/\r
+#define WM8904_REG_ANALOGUE_ROUT2 0x3C\r
+\r
+/** Analogue output 12 ZC register*/\r
+#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D\r
+\r
+/** DC servo 0 register*/\r
+#define WM8904_REG_DC_SERVO0 0x43\r
+\r
+/** Analogue HP 0 register*/\r
+#define WM8904_REG_ANALOGUE_HP0 0x5A\r
+\r
+/** Charge pump 0 register*/\r
+#define WM8904_REG_CHARGE_PUMP0 0x62\r
+\r
+/** Class W 0 register*/\r
+#define WM8904_REG_CLASS0 0x68\r
+\r
+/** FLL control 1 register*/\r
+#define WM8904_REG_FLL_CRTL1 0x74\r
+/** FLL control 2 register*/\r
+#define WM8904_REG_FLL_CRTL2 0x75\r
+/** FLL control 3 register*/\r
+#define WM8904_REG_FLL_CRTL3 0x76\r
+/** FLL control 4 register*/\r
+#define WM8904_REG_FLL_CRTL4 0x77\r
+/** FLL control 5 register*/\r
+#define WM8904_REG_FLL_CRTL5 0x78\r
+\r
+/** DUMMY register*/\r
+#define WM8904_REG_END 0xFF\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr);\r
+extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data);\r
+extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK);\r
+extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value);\r
+extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device);\r
+#endif // WM8904_H\r
+\r
+\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x80000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20440000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x80000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x801FFFFF -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or\r
+// condition of any kind, either express, implied or\r
+// statutory. This includes without limitation any warranty\r
+// or condition with respect to merchantability or fitness\r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// User setup file for CSPY debugger.\r
+// ---------------------------------------------------------\r
+\r
+/*********************************************************************\r
+*\r
+* execUserReset()\r
+*/\r
+execUserReset()\r
+{\r
+ __message "------------------------------ execUserReset ---------------------------------";\r
+ __message "-------------------------------Set PC Reset ----------------------------------";\r
+\r
+ __hwReset(0);\r
+\r
+ // peripheral reset RSTC_CR\r
+ __writeMemory32(0xA5000004,0x400e1400,"Memory");\r
+}\r
+\r
+/*********************************************************************\r
+*\r
+* execUserPreload()\r
+*/\r
+execUserPreload()\r
+{\r
+ __message "------------------------------ execUserPreload ---------------------------------";\r
+\r
+ __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset\r
+\r
+ // peripheral reset RSTC_CR\r
+ __writeMemory32(0xA5000004,0x400e1400,"Memory");\r
+}\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support - ROUSSET -\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or\r
+// condition of any kind, either express, implied or\r
+// statutory. This includes without limitation any warranty\r
+// or condition with respect to merchantability or fitness\r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// User setup file for CSPY debugger.\r
+// ---------------------------------------------------------\r
+\r
+\r
+\r
+__var __mac_i;\r
+\r
+/*********************************************************************\r
+*\r
+* execUserReset()\r
+*/\r
+execUserReset()\r
+{\r
+ __message "------------------------------ execUserReset ---------------------------------";\r
+ __message "-------------------------------Set PC Reset ----------------------------------";\r
+\r
+ __hwReset(0);\r
+\r
+ // peripheral reset RSTC_CR\r
+ __writeMemory32(0xA5000004,0x400e1400,"Memory");\r
+\r
+}\r
+\r
+execGPNVMBit()\r
+{\r
+ __writeMemory32(0x400E0C04,((0x5Au << 24) | (((0xffffu << 8) & ((0x1) << 8))) | (((0xffu << 0) & ((0x0B) << 0))) ),"Memory");\r
+}\r
+/*********************************************************************\r
+*\r
+* execUserPreload()\r
+*/\r
+execUserPreload()\r
+{\r
+ __message "------------------------------ execUserPreload ---------------------------------";\r
+\r
+ __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset\r
+\r
+ // peripheral reset RSTC_CR\r
+ __writeMemory32(0xA5000004,0x400e1400,"Memory");\r
+ //* Get the Chip ID\r
+ __mac_i=__readMemory32(0x400E0940,"Memory");\r
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X;\r
+}\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00500000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00500000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00500000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20440000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20480000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00500000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x00600000 -1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_region_ITCM_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ITCM_end__ = 0x00400000-1;\r
+define symbol __ICFEDIT_intvec_start__ = 0x20400000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_DTCM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_DTCM_end__ = 0x20400000-1;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20400000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20460000 -1;\r
+\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
+define symbol __ICFEDIT_size_heap__ = 0x2000;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in RAM_region { readonly };\r
+place in RAM_region { readwrite, block CSTACK, block HEAP };\r
+\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#include "sam.h"\r
+\r
+typedef void (*intfunc) (void);\r
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;\r
+\r
+void __iar_program_start(void);\r
+int __low_level_init(void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* Cortex-M4 core handlers */\r
+#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak WDT0_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak EFC_Handler=Dummy_Handler\r
+#pragma weak UART0_Handler=Dummy_Handler\r
+#pragma weak UART1_Handler=Dummy_Handler\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#ifdef _SAM_PIOC_INSTANCE_\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#endif /* _SAM_PIOC_INSTANCE_ */\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak USART2_Handler=Dummy_Handler\r
+#pragma weak PIOD_Handler=Dummy_Handler\r
+#ifdef _SAM_PIOE_INSTANCE_\r
+#pragma weak PIOE_Handler=Dummy_Handler\r
+#endif /* _SAM_PIOE_INSTANCE_ */\r
+#ifdef _SAM_HSMCI_INSTANCE_\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#endif /* _SAM_HSMCI_INSTANCE_ */\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak SPI0_Handler=Dummy_Handler\r
+#pragma weak SSC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#pragma weak AFEC0_Handler=Dummy_Handler\r
+#ifdef _SAM_DACC_INSTANCE_\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#endif /* _SAM_DACC_INSTANCE_ */\r
+#pragma weak PWM0_Handler=Dummy_Handler\r
+#pragma weak ICM_Handler=Dummy_Handler\r
+#pragma weak ACC_Handler=Dummy_Handler\r
+#pragma weak USBHS_Handler=Dummy_Handler\r
+#pragma weak CAN0_Handler=Dummy_Handler\r
+#pragma weak CAN1_Handler=Dummy_Handler\r
+#pragma weak GMAC_Handler=Dummy_Handler\r
+#pragma weak GMACQ1_Handler=Dummy_Handler\r
+#pragma weak GMACQ2_Handler=Dummy_Handler\r
+#pragma weak AFEC1_Handler=Dummy_Handler\r
+#ifdef _SAM_TWI2_INSTANCE_\r
+#pragma weak TWI2_Handler=Dummy_Handler\r
+#endif /* _SAM_TWI2_INSTANCE_ */\r
+#pragma weak SPI1_Handler=Dummy_Handler\r
+#pragma weak QSPI_Handler=Dummy_Handler\r
+#pragma weak UART2_Handler=Dummy_Handler\r
+#pragma weak UART3_Handler=Dummy_Handler\r
+#pragma weak UART4_Handler=Dummy_Handler\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC6_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC7_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC8_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#pragma weak TC9_Handler=Dummy_Handler\r
+#pragma weak TC10_Handler=Dummy_Handler\r
+#pragma weak TC11_Handler=Dummy_Handler\r
+#pragma weak MLB_Handler=Dummy_Handler\r
+#pragma weak AES_Handler=Dummy_Handler\r
+#pragma weak TRNG_Handler=Dummy_Handler\r
+#pragma weak XDMAC_Handler=Dummy_Handler\r
+#pragma weak ISI_Handler=Dummy_Handler\r
+#pragma weak PWM1_Handler=Dummy_Handler\r
+#pragma weak FPU_Handler=Dummy_Handler\r
+#ifdef _SAM_SDRAMC_INSTANCE_\r
+#pragma weak SDRAMC_Handler=Dummy_Handler\r
+#endif /* _SAM_SDRAMC_INSTANCE_ */\r
+#pragma weak WDT1_Handler=Dummy_Handler\r
+#pragma weak CCF_Handler=Dummy_Handler\r
+#pragma weak CCW_Handler=Dummy_Handler\r
+\r
+/* Exception Table */\r
+#pragma language = extended\r
+#pragma segment = "CSTACK"\r
+\r
+/* The name "__vector_table" has special meaning for C-SPY: */\r
+/* it is where the SP start value is found, and the NVIC vector */\r
+/* table register (VTOR) is initialized to this address if != 0 */\r
+\r
+#pragma section = ".intvec"\r
+#pragma location = ".intvec"\r
+const intvec_elem __vector_table[] =\r
+{\r
+ { .__ptr = __sfe( "CSTACK" ) },\r
+ __iar_program_start,\r
+ NMI_Handler,\r
+ HardFault_Handler,\r
+ MemManage_Handler,\r
+ BusFault_Handler,\r
+ UsageFault_Handler,\r
+ (0UL), (0UL), (0UL), (0UL), /* Reserved */\r
+ SVC_Handler,\r
+ DebugMon_Handler,\r
+ (0UL), /* Reserved */\r
+ PendSV_Handler,\r
+ SysTick_Handler,\r
+\r
+ SUPC_Handler, /* 0 Supply Controller */\r
+ RSTC_Handler, /* 1 Reset Controller */\r
+ RTC_Handler, /* 2 Real Time Clock */\r
+ RTT_Handler, /* 3 Real Time Timer */\r
+ WDT0_Handler, /* 4 Watchdog Timer 0 */\r
+ PMC_Handler, /* 5 Power Management Controller */\r
+ EFC_Handler, /* 6 Enhanced Embedded Flash Controller */\r
+ UART0_Handler, /* 7 UART 0 */\r
+ UART1_Handler, /* 8 UART 1 */\r
+ (0UL), /* 9 Reserved */\r
+ PIOA_Handler, /* 10 Parallel I/O Controller A */\r
+ PIOB_Handler, /* 11 Parallel I/O Controller B */\r
+ PIOC_Handler, /* 12 Parallel I/O Controller C */\r
+ USART0_Handler, /* 13 USART 0 */\r
+ USART1_Handler, /* 14 USART 1 */\r
+ USART2_Handler, /* 15 USART 2 */\r
+ PIOD_Handler, /* 16 Parallel I/O Controller D */\r
+ PIOE_Handler, /* 17 Parallel I/O Controller E */ \r
+ HSMCI_Handler, /* 18 Multimedia Card Interface */\r
+ TWI0_Handler, /* 19 Two Wire Interface 0 HS */\r
+ TWI1_Handler, /* 20 Two Wire Interface 1 HS */\r
+ SPI0_Handler, /* 21 Serial Peripheral Interface 0 */\r
+ SSC_Handler, /* 22 Synchronous Serial Controller */\r
+ TC0_Handler, /* 23 Timer/Counter 0 */\r
+ TC1_Handler, /* 24 Timer/Counter 1 */\r
+ TC2_Handler, /* 25 Timer/Counter 2 */\r
+ TC3_Handler, /* 26 Timer/Counter 3 */\r
+ TC4_Handler, /* 27 Timer/Counter 4 */\r
+ TC5_Handler, /* 28 Timer/Counter 5 */\r
+ AFEC0_Handler, /* 29 Analog Front End 0 */\r
+ DACC_Handler, /* 30 Digital To Analog Converter */\r
+ PWM0_Handler, /* 31 Pulse Width Modulation 0 */\r
+ ICM_Handler, /* 32 Integrity Check Monitor */\r
+ ACC_Handler, /* 33 Analog Comparator */\r
+ USBHS_Handler, /* 34 USB Host / Device Controller */\r
+ CAN0_Handler, /* 35 CAN Controller 0 */\r
+ (0UL), /* 36 Reserved */\r
+ CAN1_Handler, /* 37 CAN Controller 1 */\r
+ (0UL), /* 38 Reserved */\r
+ GMAC_Handler, /* 39 Ethernet MAC */\r
+ AFEC1_Handler, /* 40 Analog Front End 1 */\r
+ TWI2_Handler, /* 41 Two Wire Interface 2 HS */\r
+ SPI1_Handler, /* 42 Serial Peripheral Interface 1 */\r
+ QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */\r
+ UART2_Handler, /* 44 UART 2 */\r
+ UART3_Handler, /* 45 UART 3 */\r
+ UART4_Handler, /* 46 UART 4 */\r
+ TC6_Handler, /* 47 Timer/Counter 6 */\r
+ TC7_Handler, /* 48 Timer/Counter 7 */\r
+ TC8_Handler, /* 49 Timer/Counter 8 */\r
+ TC9_Handler, /* 50 Timer/Counter 9 */\r
+ TC10_Handler, /* 51 Timer/Counter 10 */\r
+ TC11_Handler, /* 52 Timer/Counter 11 */\r
+ MLB_Handler, /* 53 MediaLB */\r
+ (0UL), /* 54 Reserved */\r
+ (0UL), /* 55 Reserved */\r
+ AES_Handler, /* 56 AES */\r
+ TRNG_Handler, /* 57 True Random Generator */\r
+ XDMAC_Handler, /* 58 DMA */\r
+ ISI_Handler, /* 59 Camera Interface */\r
+ PWM1_Handler, /* 60 Pulse Width Modulation 1 */\r
+ FPU_Handler, /* 61 Floating Point Unit */\r
+ SDRAMC_Handler, /* 62 SDRAM Controller */\r
+ WDT1_Handler, /* 63 Watchdog Timer 1 */\r
+ CCW_Handler, /* 64 ARM Cache ECC Warning */\r
+ CCF_Handler, /* 65 ARM Cache ECC Fault */\r
+ GMACQ1_Handler, /* 66 GMAC Queue 1 Handler */\r
+ GMACQ2_Handler /* 67 GMAC Queue 2 Handler */\r
+};\r
+\r
+void LowLevelInit(void);\r
+\r
+#if 0\r
+/** \brief TCM memory enable\r
+\r
+ The function enables TCM memories\r
+ */\r
+__STATIC_INLINE void TCM_Enable(void) \r
+{\r
+\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk);\r
+ SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk);\r
+ __DSB();\r
+ __ISB();\r
+}\r
+#endif\r
+/**------------------------------------------------------------------------------\r
+ * This is the code that gets called on processor reset. To initialize the\r
+ * device.\r
+ *------------------------------------------------------------------------------*/\r
+int __low_level_init(void)\r
+{\r
+ uint32_t *pSrc = __section_begin(".intvec"); \r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+#ifdef ENABLE_TCM\r
+ //TCM_Enable();\r
+#endif \r
+ LowLevelInit();\r
+ return 1; /* if return 0, the data sections will not be initialized */\r
+}\r
+\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
--- /dev/null
+; * ----------------------------------------------------------------------------\r
+; * ATMEL Microcontroller Software Support\r
+; * ----------------------------------------------------------------------------\r
+; * Copyright (c) 2009, Atmel Corporation\r
+; *\r
+; * All rights reserved.\r
+; *\r
+; * Redistribution and use in source and binary forms, with or without\r
+; * modification, are permitted provided that the following conditions are met:\r
+; *\r
+; * - Redistributions of source code must retain the above copyright notice,\r
+; * this list of conditions and the disclaimer below.\r
+; *\r
+; * Atmel's name may not be used to endorse or promote products derived from\r
+; * this software without specific prior written permission.\r
+; *\r
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+; * ----------------------------------------------------------------------------\r
+\r
+; *------------------------------------------------------------------------------\r
+; * Linker scatter for running in internal FLASH on the SAMV71\r
+; *----------------------------------------------------------------------------*/\r
+\r
+; /* vector is put at very begin adress of FLASH, the preserved size is 0x100 */\r
+\r
+LR_IROM1 0x40000000 0x00200000 ; load region size_region\r
+{\r
+ ER_IROM1 0x40000000 0x400 ;0x00200000 ; load address = execution address;\r
+ {\r
+ *.o (vectors, +FIRST)\r
+ }\r
+ \r
+ ER_IROM2 +0\r
+ {\r
+ *.o\r
+ *(InRoot$$Sections)\r
+ .ANY (+RO)\r
+ }\r
+\r
+ RW_IRAM1 0x20400000 0x0005E000 ; RW data\r
+ {\r
+ .ANY (+RW +ZI)\r
+ }\r
+\r
+ ; Configure Stack and Heap\r
+ ARM_LIB_HEAP 0x2045E000 EMPTY 0x1000\r
+ {\r
+ }\r
+\r
+ ARM_LIB_STACK 0x20405FFC EMPTY -0x1000\r
+ {\r
+ } \r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ * This file Configures the target-dependent low level functions for character I/O.\r
+ */\r
+\r
+#include "board.h"\r
+#include "dbg_console.h"\r
+#include <stdio.h>\r
+\r
+/* Disable semihosting */\r
+#pragma import(__use_no_semihosting_swi)\r
+\r
+struct __FILE { int handle;} ;\r
+FILE __stdout;\r
+FILE __stderr;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Outputs a character.\r
+ *------------------------------------------------------------------------------*/\r
+int fputc(int ch, FILE *f)\r
+{\r
+ if ((f == stdout) || (f == stderr))\r
+ {\r
+ DBG_PutChar(ch) ;\r
+ return ch ;\r
+ }\r
+ else\r
+ {\r
+ return EOF ;\r
+ }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Returns the error status accumulated during file I/O.\r
+ *------------------------------------------------------------------------------*/\r
+int ferror( FILE *f )\r
+{\r
+ return EOF ;\r
+}\r
+\r
+\r
+void _ttywrch( int ch )\r
+{\r
+ DBG_PutChar( (uint8_t)ch ) ;\r
+}\r
+\r
+void _sys_exit(int return_code)\r
+{\r
+ while ( 1 ) ; /* endless loop */\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Low level functions I/O for assert().\r
+ *------------------------------------------------------------------------------*/\r
+void __assert_puts(const char *str)\r
+{\r
+ printf("%s", str);\r
+}\r
+\r
--- /dev/null
+// ----------------------------------------------------------------------------\r
+// ATMEL Microcontroller Software Support\r
+// ----------------------------------------------------------------------------\r
+// Copyright (c) 2010, Atmel Corporation\r
+//\r
+// All rights reserved.\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions are met:\r
+//\r
+// - Redistributions of source code must retain the above copyright notice,\r
+// this list of conditions and the disclaimer below.\r
+//\r
+// Atmel's name may not be used to endorse or promote products derived from\r
+// this software without specific prior written permission.\r
+//\r
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+// ----------------------------------------------------------------------------\r
+\r
+//----------------------------------------------------------------------------\r
+// File Name : samv7-sram.ini\r
+// Object : Generic Macro File for KEIL\r
+//----------------------------------------------------------------------------\r
+\r
+SP = *((unsigned int *) 0x20400000);\r
+PC = *((unsigned int *) 0x20400004);\r
--- /dev/null
+; * ----------------------------------------------------------------------------\r
+; * ATMEL Microcontroller Software Support\r
+; * ----------------------------------------------------------------------------\r
+; * Copyright (c) 2009, Atmel Corporation\r
+; *\r
+; * All rights reserved.\r
+; *\r
+; * Redistribution and use in source and binary forms, with or without\r
+; * modification, are permitted provided that the following conditions are met:\r
+; *\r
+; * - Redistributions of source code must retain the above copyright notice,\r
+; * this list of conditions and the disclaimer below.\r
+; *\r
+; * Atmel's name may not be used to endorse or promote products derived from\r
+; * this software without specific prior written permission.\r
+; *\r
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+; * ----------------------------------------------------------------------------\r
+\r
+; *------------------------------------------------------------------------------\r
+; * Linker scatter for running in internal SRAM on the SAM3S4\r
+; *----------------------------------------------------------------------------*/\r
+LR_IRAM1 0x20400000 0x00040000 ; load region size_region\r
+{\r
+ Vector_region 0x20400000 0x0005E000 \r
+ {\r
+ startup_sam.o (vectors, +First)\r
+ }\r
+\r
+ Code_region +0\r
+ {\r
+ .ANY (+RO, +RW, +ZI)\r
+ }\r
+\r
+ ; Configure Stack and Heap\r
+ ARM_LIB_HEAP 0x2045E000 EMPTY 0x1000\r
+ {\r
+ }\r
+\r
+ ARM_LIB_STACK 0x20460000 EMPTY -0x1000\r
+ {\r
+ } \r
+}\r
+\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#include "sam.h"\r
+\r
+typedef void (*intfunc) (void);\r
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;\r
+\r
+extern int Image$$ARM_LIB_STACK$$ZI$$Limit ;\r
+extern int Image$$Vector_region$$Base ;\r
+extern int Image$$Vector_region$$Limit ;\r
+\r
+extern void __main( void ) ;\r
+static void Reset_Handler( void ) ;\r
+\r
+int __low_level_init(void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+void NMI_Handler(void);\r
+\r
+/* Cortex-M7 core handlers */\r
+//#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak WDT0_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak EFC_Handler=Dummy_Handler\r
+#pragma weak UART0_Handler=Dummy_Handler\r
+#pragma weak UART1_Handler=Dummy_Handler\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#ifdef _SAM_PIOC_INSTANCE_\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#endif /* _SAM_PIOC_INSTANCE_ */\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak USART2_Handler=Dummy_Handler\r
+#pragma weak PIOD_Handler=Dummy_Handler\r
+#ifdef _SAM_PIOE_INSTANCE_\r
+#pragma weak PIOE_Handler=Dummy_Handler\r
+#endif /* _SAM_PIOE_INSTANCE_ */\r
+#ifdef _SAM_HSMCI_INSTANCE_\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#endif /* _SAM_HSMCI_INSTANCE_ */\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak SPI0_Handler=Dummy_Handler\r
+#pragma weak SSC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#ifdef _SAM_TC1_INSTANCE_\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
+#pragma weak AFEC0_Handler=Dummy_Handler\r
+#ifdef _SAM_DACC_INSTANCE_\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#endif /* _SAM_DACC_INSTANCE_ */\r
+#pragma weak PWM0_Handler=Dummy_Handler\r
+#pragma weak ICM_Handler=Dummy_Handler\r
+#pragma weak ACC_Handler=Dummy_Handler\r
+#pragma weak USBHS_Handler=Dummy_Handler\r
+#pragma weak CAN0_Handler=Dummy_Handler\r
+#pragma weak CAN1_Handler=Dummy_Handler\r
+#pragma weak GMAC_Handler=Dummy_Handler\r
+#pragma weak GMACQ1_Handler=Dummy_Handler\r
+#pragma weak GMACQ2_Handler=Dummy_Handler\r
+#pragma weak AFEC1_Handler=Dummy_Handler\r
+#ifdef _SAM_TWI2_INSTANCE_\r
+#pragma weak TWI2_Handler=Dummy_Handler\r
+#endif /* _SAM_TWI2_INSTANCE_ */\r
+#pragma weak SPI1_Handler=Dummy_Handler\r
+#pragma weak QSPI_Handler=Dummy_Handler\r
+#pragma weak UART2_Handler=Dummy_Handler\r
+#pragma weak UART3_Handler=Dummy_Handler\r
+#pragma weak UART4_Handler=Dummy_Handler\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC6_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC7_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#ifdef _SAM_TC2_INSTANCE_\r
+#pragma weak TC8_Handler=Dummy_Handler\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
+#pragma weak TC9_Handler=Dummy_Handler\r
+#pragma weak TC10_Handler=Dummy_Handler\r
+#pragma weak TC11_Handler=Dummy_Handler\r
+#pragma weak MLB_Handler=Dummy_Handler\r
+#pragma weak AES_Handler=Dummy_Handler\r
+#pragma weak TRNG_Handler=Dummy_Handler\r
+#pragma weak XDMAC_Handler=Dummy_Handler\r
+#pragma weak ISI_Handler=Dummy_Handler\r
+#pragma weak PWM1_Handler=Dummy_Handler\r
+#pragma weak FPU_Handler=Dummy_Handler\r
+#ifdef _SAM_SDRAMC_INSTANCE_\r
+#pragma weak SDRAMC_Handler=Dummy_Handler\r
+#endif /* _SAM_SDRAMC_INSTANCE_ */\r
+#pragma weak WDT1_Handler=Dummy_Handler\r
+#pragma weak CCF_Handler=Dummy_Handler\r
+#pragma weak CCW_Handler=Dummy_Handler\r
+\r
+\r
+/* The name "__vector_table" has special meaning for C-SPY: */\r
+/* it is where the SP start value is found, and the NVIC vector */\r
+/* table register (VTOR) is initialized to this address if != 0 */\r
+#pragma arm section rodata = "vectors"\r
+const intvec_elem __vector_table[] =\r
+{\r
+ (intfunc)&Image$$ARM_LIB_STACK$$ZI$$Limit,\r
+ Reset_Handler,\r
+ NMI_Handler,\r
+ HardFault_Handler,\r
+ MemManage_Handler,\r
+ BusFault_Handler,\r
+ UsageFault_Handler,\r
+ (0UL), (0UL), (0UL), (0UL), /* Reserved */\r
+ SVC_Handler,\r
+ DebugMon_Handler,\r
+ (0UL), /* Reserved */\r
+ PendSV_Handler,\r
+ SysTick_Handler,\r
+\r
+ SUPC_Handler, /* 0 Supply Controller */\r
+ RSTC_Handler, /* 1 Reset Controller */\r
+ RTC_Handler, /* 2 Real Time Clock */\r
+ RTT_Handler, /* 3 Real Time Timer */\r
+ WDT0_Handler, /* 4 Watchdog Timer 0 */\r
+ PMC_Handler, /* 5 Power Management Controller */\r
+ EFC_Handler, /* 6 Enhanced Embedded Flash Controller */\r
+ UART0_Handler, /* 7 UART 0 */\r
+ UART1_Handler, /* 8 UART 1 */\r
+ (0UL), /* 9 Reserved */\r
+ PIOA_Handler, /* 10 Parallel I/O Controller A */\r
+ PIOB_Handler, /* 11 Parallel I/O Controller B */\r
+ PIOC_Handler, /* 12 Parallel I/O Controller C */\r
+ USART0_Handler, /* 13 USART 0 */\r
+ USART1_Handler, /* 14 USART 1 */\r
+ USART2_Handler, /* 15 USART 2 */\r
+ PIOD_Handler, /* 16 Parallel I/O Controller D */\r
+ PIOE_Handler, /* 17 Parallel I/O Controller E */ \r
+ HSMCI_Handler, /* 18 Multimedia Card Interface */\r
+ TWI0_Handler, /* 19 Two Wire Interface 0 HS */\r
+ TWI1_Handler, /* 20 Two Wire Interface 1 HS */\r
+ SPI0_Handler, /* 21 Serial Peripheral Interface 0 */\r
+ SSC_Handler, /* 22 Synchronous Serial Controller */\r
+ TC0_Handler, /* 23 Timer/Counter 0 */\r
+ TC1_Handler, /* 24 Timer/Counter 1 */\r
+ TC2_Handler, /* 25 Timer/Counter 2 */\r
+ TC3_Handler, /* 26 Timer/Counter 3 */\r
+ TC4_Handler, /* 27 Timer/Counter 4 */\r
+ TC5_Handler, /* 28 Timer/Counter 5 */\r
+ AFEC0_Handler, /* 29 Analog Front End 0 */\r
+ DACC_Handler, /* 30 Digital To Analog Converter */\r
+ PWM0_Handler, /* 31 Pulse Width Modulation 0 */\r
+ ICM_Handler, /* 32 Integrity Check Monitor */\r
+ ACC_Handler, /* 33 Analog Comparator */\r
+ USBHS_Handler, /* 34 USB Host / Device Controller */\r
+ CAN0_Handler, /* 35 CAN Controller 0 */\r
+ (0UL), /* 36 Reserved */\r
+ CAN1_Handler, /* 37 CAN Controller 1 */\r
+ (0UL), /* 38 Reserved */\r
+ GMAC_Handler, /* 39 Ethernet MAC */\r
+ AFEC1_Handler, /* 40 Analog Front End 1 */\r
+ TWI2_Handler, /* 41 Two Wire Interface 2 HS */\r
+ SPI1_Handler, /* 42 Serial Peripheral Interface 1 */\r
+ QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */\r
+ UART2_Handler, /* 44 UART 2 */\r
+ UART3_Handler, /* 45 UART 3 */\r
+ UART4_Handler, /* 46 UART 4 */\r
+ TC6_Handler, /* 47 Timer/Counter 6 */\r
+ TC7_Handler, /* 48 Timer/Counter 7 */\r
+ TC8_Handler, /* 49 Timer/Counter 8 */\r
+ TC9_Handler, /* 50 Timer/Counter 9 */\r
+ TC10_Handler, /* 51 Timer/Counter 10 */\r
+ TC11_Handler, /* 52 Timer/Counter 11 */\r
+ MLB_Handler, /* 53 MediaLB */\r
+ (0UL), /* 54 Reserved */\r
+ (0UL), /* 55 Reserved */\r
+ AES_Handler, /* 56 AES */\r
+ TRNG_Handler, /* 57 True Random Generator */\r
+ XDMAC_Handler, /* 58 DMA */\r
+ ISI_Handler, /* 59 Camera Interface */\r
+ PWM1_Handler, /* 60 Pulse Width Modulation 1 */\r
+ FPU_Handler, /* 61 Floating Point Unit */\r
+ SDRAMC_Handler, /* 62 SDRAM Controller */\r
+ WDT1_Handler, /* 63 Watchdog Timer 1 */\r
+ CCW_Handler, /* 64 ARM Cache ECC Warning */\r
+ CCF_Handler, /* 65 ARM Cache ECC Fault */\r
+ GMACQ1_Handler, /* 66 GMAC Queue 1 Handler */\r
+ GMACQ2_Handler /* 67 GMAC Queue 2 Handler */\r
+};\r
+#pragma arm section\r
+\r
+\r
+void LowLevelInit(void);\r
+/**------------------------------------------------------------------------------\r
+ * This is the code that gets called on processor reset. To initialize the\r
+ * device.\r
+ *------------------------------------------------------------------------------*/\r
+int __low_level_init(void)\r
+{\r
+// uint32_t *pSrc = __section_begin(".intvec");\r
+ LowLevelInit();\r
+// SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+ \r
+ SCB_EnableICache(); \r
+ SCB_EnableDCache();\r
+ \r
+ \r
+ \r
+ return 1; /* if return 0, the data sections will not be initialized */\r
+}\r
+\r
+/** \brief TCM memory enable\r
+\r
+ The function enables TCM memories\r
+ */\r
+\r
+/* Correct errors in early version core_cm7.h */\r
+#undef SCB_ITCMCR_RETEN_Msk\r
+#undef SCB_ITCMCR_RMW_Msk\r
+#undef SCB_ITCMCR_EN_Msk\r
+#define SCB_ITCMCR_RETEN_Msk (0x1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+#define SCB_ITCMCR_RMW_Msk (0x1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+#define SCB_ITCMCR_EN_Msk (0x1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */\r
+\r
+\r
+__STATIC_INLINE void TCM_Enable(void) \r
+{\r
+\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ITCMCR = ( SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk);\r
+ SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk);\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/**------------------------------------------------------------------------------\r
+ * This is the code that gets called on processor reset. To initialize the\r
+ * device.\r
+ *------------------------------------------------------------------------------*/\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc = (uint32_t*)&Image$$Vector_region$$Base ;\r
+\r
+ /* Low level Initialize */\r
+ LowLevelInit() ;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+ SCB_EnableICache(); \r
+ SCB_EnableDCache(); \r
+\r
+ /* Branch to main function */\r
+ __main() ;\r
+\r
+ /* Will not execute, but removes warning about TCM_Enable() not being called. */\r
+ ( void ) TCM_Enable;\r
+\r
+ /* Infinite loop */\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
+void NMI_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
--- /dev/null
+ AREA WORKAROUND,CODE,READONLY\r
+ EXTERN __vector_table\r
+ LDR r0,=__vector_table\r
+ ALIGN\r
+ END\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#include "sam.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock Settings (120MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0x13U) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fU) \\r
+ | CKGR_PLLAR_DIVA(0x1U))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY_PASSWD /* Key to unlock MOR register */\r
+\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
+#if defined(ID_EFC1)\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(5);\r
+#endif\r
+\r
+ /* Initialize main oscillator */\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
+\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
+ }\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+// case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>\r
+ CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>\r
+ CKGR_PLLAR_DIVA_Pos));\r
+ } else {\r
+ // SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>\r
+ // CKGR_PLLBR_MULB_Pos) + 1U);\r
+ // SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>\r
+ // CKGR_PLLBR_DIVB_Pos));\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk)\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+#if !defined(ID_EFC1)\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_4) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ } else {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
+ }\r
+#else\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_4) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ } else {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(5);\r
+ }\r
+#endif\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation WM8904 driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ uint16_t value;\r
+ uint8_t address;\r
+}CS2100_PARA;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Read data from CS2100 Register.\r
+ *\r
+ * \param pTwid Pointer to twi driver structure\r
+ * \param device Twi slave address.\r
+ * \param regAddr Register address to read.\r
+ * \return value in the given register.\r
+ */\r
+uint16_t CS2100_Read(Twid *pTwid,\r
+ uint32_t device,\r
+ uint32_t regAddr)\r
+{\r
+ uint16_t bitsDataRegister;\r
+ uint8_t Tdata[2]={0,0};\r
+\r
+ TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0);\r
+ bitsDataRegister = (Tdata[0] << 8) | Tdata[1];\r
+ return bitsDataRegister;\r
+}\r
+\r
+/**\r
+ * \brief Write data to WM8904 Register.\r
+ *\r
+ * \param pTwid Pointer to twi driver structure\r
+ * \param device Twi slave address.\r
+ * \param regAddr Register address to read.\r
+ * \param data Data to write\r
+ */\r
+void CS2100_Write(Twid *pTwid,\r
+ uint32_t device,\r
+ uint32_t regAddr,\r
+ uint16_t data)\r
+{\r
+ uint8_t tmpData[2];\r
+ \r
+ tmpData[0] = (data & 0xff00) >> 8;\r
+ tmpData[1] = data & 0xff;\r
+ TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0);\r
+}\r
+\r
+uint8_t CS2100_Init(Twid *pTwid, uint32_t device, uint32_t PCK)\r
+{\r
+ uint16_t data = 0;\r
+\r
+ // Reset (write Reg@0x0 to reset)\r
+ CS2100_Write(pTwid, device, 0, 0xFFFF);\r
+\r
+ for(data=0;data<1000;data++);\r
+ //wait ready \r
+ while(data!=0x8904)\r
+ data=CS2100_Read(pTwid, device, 0);\r
+\r
+ \r
+\r
+ \r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \r
+ * \addtogroup at25_spi_module AT25 SPI driver\r
+ * \ingroup at25d_module\r
+ *\r
+ * The AT25 serial firmware dataflash driver is based on top of the\r
+ * corresponding Spi driver. A Dataflash structure instance has to be\r
+ * initialized using the AT25_Configure() function. Then a command can be send \r
+ * to the serial flash using the SPI_SendCommand() function. \r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li>Initializes an AT25 instance and configures SPI chip select pin\r
+ * using AT25_Configure(). </li>\r
+ * <li>Detect DF and returns DF description corresponding to the device\r
+ * connected using AT25D_ReadJedecId() and AT25_FindDevice().\r
+ * This function shall be called by the application before AT25_SendCommand().</li>\r
+ * <li> Sends a command to the DF through the SPI using AT25_SendCommand().\r
+ * The command is identified by its command code and the number of\r
+ * bytes to transfer.</li>\r
+ * <li> Example code for sending command to write a page to DF.</li>\r
+ * \code\r
+ * // Program page\r
+ * error = AT25_SendCommand(pAt25, AT25_BYTE_PAGE_PROGRAM, 4,\r
+ * pData, writeSize, address, 0, 0);\r
+ * \endcode\r
+ * <li> Example code for sending command to read a page from DF.\r
+ * If data needs to be received, then a data buffer must be\r
+ * provided.</li>\r
+ * \code\r
+ * // Start a read operation\r
+ * error = AT25_SendCommand(pAt25, AT25_READ_ARRAY_LF,\r
+ * 4, pData, size, address, 0, 0);\r
+ * \endcode\r
+ * <li> This function does not block; its optional callback will\r
+ * be invoked when the transfer completes.</li>\r
+ * <li> Check the AT25 driver is ready or not by polling AT25_IsBusy().</li>\r
+ * </ul>\r
+ *\r
+ * Related files :\n\r
+ * \ref at25_spi.c\n\r
+ * \ref at25_spi.h.\n\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the AT25 SPI driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <board.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** SPI clock frequency used in Hz. */\r
+#define SPCK 1000000\r
+\r
+/** SPI chip select configuration value. */\r
+#define CSR (SPI_CSR_NCPHA | \\r
+ SPID_CSR_DLYBCT(BOARD_MCK, 100) | \\r
+ SPID_CSR_DLYBS(BOARD_MCK, 10) | \\r
+ SPID_CSR_SCBR(BOARD_MCK, SPCK))\r
+\r
+/** Number of recognized dataflash. */\r
+#define NUMDATAFLASH (sizeof(at25Devices) / sizeof(At25Desc))\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Array of recognized serial firmware dataflash chips. */\r
+static const At25Desc at25Devices[] = {\r
+ /* name, Jedec ID, size, page size, block size, block erase command */\r
+ {"AT25DF041A" , 0x0001441F, 512 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF161" , 0x0002461F, 2 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT26DF081A" , 0x0001451F, 1 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT26DF0161" , 0x0000461F, 2 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT26DF161A" , 0x0001461F, 2 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF321" , 0x0000471F, 4 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF321A" , 0x0001471F, 4 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF512B" , 0x0001651F, 64 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF512B" , 0x0000651F, 64 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT25DF021" , 0x0000431F, 256 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"AT26DF641" , 0x0000481F, 8 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ /* Manufacturer: ST */\r
+ {"M25P05" , 0x00102020, 64 * 1024, 256, 32 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P10" , 0x00112020, 128 * 1024, 256, 32 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P20" , 0x00122020, 256 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P40" , 0x00132020, 512 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P80" , 0x00142020, 1 * 1024 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P16" , 0x00152020, 2 * 1024 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P32" , 0x00162020, 4 * 1024 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"M25P64" , 0x00172020, 8 * 1024 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ /* Manufacturer: Windbond */\r
+ {"W25X10" , 0x001130EF, 128 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"W25X20" , 0x001230EF, 256 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"W25X40" , 0x001330EF, 512 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"W25X80" , 0x001430EF, 1 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ /* Manufacturer: Macronix */\r
+ {"MX25L512" , 0x001020C2, 64 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"MX25L3205" , 0x001620C2, 4 * 1024 * 1024, 256, 64 * 1024, AT25_BLOCK_ERASE_64K},\r
+ {"MX25L6405" , 0x001720C2, 8 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"MX25L8005" , 0x001420C2, 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ /* Other */\r
+ {"SST25VF040" , 0x008D25BF, 512 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"SST25VF080" , 0x008E25BF, 1 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"SST25VF032" , 0x004A25BF, 4 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K},\r
+ {"SST25VF064" , 0x004B25BF, 8 * 1024 * 1024, 256, 4 * 1024, AT25_BLOCK_ERASE_4K}\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initializes an AT25 driver instance with the given SPI driver and chip\r
+ * select value.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param pSpid Pointer to an SPI driver instance.\r
+ * \param cs Chip select value to communicate with the serial flash.\r
+ */\r
+void AT25_Configure(At25 *pAt25, Spid *pSpid, unsigned char cs)\r
+{\r
+ SpidCmd *pCommand;\r
+\r
+ assert(pAt25);\r
+ assert(pSpid);\r
+ assert(cs < 4);\r
+\r
+ /* Configure the SPI chip select for the serial flash */\r
+ SPID_ConfigureCS(pSpid, cs, CSR);\r
+\r
+ /* Initialize the AT25 fields */\r
+ pAt25->pSpid = pSpid;\r
+ pAt25->pDesc = 0;\r
+\r
+ /* Initialize the command structure */\r
+ pCommand = &(pAt25->command);\r
+ pCommand->pCmd = (unsigned char *) pAt25->pCmdBuffer;\r
+ pCommand->callback = 0;\r
+ pCommand->pArgument = 0;\r
+ pCommand->spiCs = cs;\r
+}\r
+\r
+/**\r
+ * \brief Is serial flash driver busy.\r
+ *\r
+ * \param pAt25 Pointer to an At25 driver instance.\r
+ *\r
+ * \return 1 if the serial flash driver is currently busy executing a command;\r
+ * otherwise returns 0.\r
+ */\r
+unsigned char AT25_IsBusy(At25 *pAt25)\r
+{\r
+ return SPID_IsBusy(pAt25->pSpid);\r
+}\r
+\r
+/**\r
+ * \brief Sends a command to the serial flash through the SPI. The command is made up\r
+ * of two parts: the first is used to transmit the command byte and optionally,\r
+ * address and dummy bytes. The second part is the data to send or receive.\r
+ * This function does not block: it returns as soon as the transfer has been\r
+ * started. An optional callback can be invoked to notify the end of transfer.\r
+ *\r
+ * \param pAt25 Pointer to an At25 driver instance.\r
+ * \param cmd Command byte.\r
+ * \param cmdSize Size of command (command byte + address bytes + dummy bytes).\r
+ * \param pData Data buffer.\r
+ * \param dataSize Number of bytes to send/receive.\r
+ * \param address Address to transmit.\r
+ * \param callback Optional user-provided callback to invoke at end of transfer.\r
+ * \param pArgument Optional argument to the callback function.\r
+ *\r
+ * \return 0 if successful; otherwise, returns AT25_ERROR_BUSY if the AT25\r
+ * driver is currently executing a command, or AT25_ERROR_SPI if the command\r
+ * cannot be sent because of a SPI error.\r
+ */\r
+unsigned char AT25_SendCommand(\r
+ At25 *pAt25,\r
+ unsigned char cmd,\r
+ unsigned char cmdSize,\r
+ unsigned char *pData,\r
+ unsigned int dataSize,\r
+ unsigned int address,\r
+ SpidCallback callback,\r
+ void *pArgument)\r
+\r
+{\r
+ SpidCmd *pCommand;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Check if the SPI driver is available */\r
+ if (AT25_IsBusy(pAt25)) {\r
+\r
+ return AT25_ERROR_BUSY;\r
+ }\r
+\r
+ /* Store command and address in command buffer */\r
+ pAt25->pCmdBuffer[0] = (cmd & 0x000000FF)\r
+ | ((address & 0x0000FF) << 24)\r
+ | ((address & 0x00FF00) << 8)\r
+ | ((address & 0xFF0000) >> 8);\r
+\r
+ /* Update the SPI transfer descriptor */\r
+ pCommand = &(pAt25->command);\r
+ pCommand->cmdSize = cmdSize;\r
+ pCommand->pData = pData;\r
+ pCommand->dataSize = dataSize;\r
+ pCommand->callback = callback;\r
+ pCommand->pArgument = pArgument;\r
+\r
+ /* Start the SPI transfer */\r
+ if (SPID_SendCommand(pAt25->pSpid, pCommand)) {\r
+\r
+ return AT25_ERROR_SPI;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Tries to detect a serial firmware flash device given its JEDEC identifier.\r
+ * The JEDEC id can be retrieved by sending the correct command to the device.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param jedecId JEDEC identifier of device.\r
+ *\r
+ * \return the corresponding AT25 descriptor if found; otherwise returns 0.\r
+ */\r
+const At25Desc * AT25_FindDevice(At25 *pAt25, unsigned int jedecId)\r
+{\r
+ unsigned int i = 0;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Search if device is recognized */\r
+ pAt25->pDesc = 0;\r
+ while ((i < NUMDATAFLASH) && !(pAt25->pDesc)) {\r
+\r
+ if ((jedecId & 0xFF00FFFF) == (at25Devices[i].jedecId & 0xFF00FFFF)) {\r
+\r
+ pAt25->pDesc = &(at25Devices[i]);\r
+ }\r
+\r
+ i++;\r
+ }\r
+\r
+ return pAt25->pDesc;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \addtogroup external_component External Component\r
+ *\r
+ * \addtogroup at25d_module AT25 driver\r
+ * \ingroup external_component\r
+ * The AT25 serial dataflash driver is based on the corresponding AT25 SPI driver.\r
+ * A AT25 instance has to be initialized using the Dataflash levle function\r
+ * AT25_Configure(). AT25 Dataflash can be automatically detected using\r
+ * the AT25_FindDevice() function. Then AT25 dataflash operations such as\r
+ * read, write and erase DF can be launched using AT25_SendCommand function\r
+ * with corresponding AT25 command set.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Reads a serial flash device ID using AT25D_ReadJedecId().</li>\r
+ * <li> Reads data from the At25 at the specified address using AT25D_Read().</li>\r
+ * <li> Writes data on the At25 at the specified address using AT25D_Write().</li>\r
+ * <li> Erases all chip using AT25D_EraseBlock().</li>\r
+ * <li> Erases a specified block using AT25D_EraseBlock().</li>\r
+ * <li> Poll until the At25 has completed of corresponding operations using\r
+ * AT25D_WaitReady().</li>\r
+ * <li> Retrieves and returns the At25 current using AT25D_ReadStatus().</li>\r
+ * </ul>\r
+ *\r
+ * Related files :\n\r
+ * \ref at25d.c\n\r
+ * \ref at25d.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the AT25 Serialflash driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <board.h>\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Wait for transfer to finish calling the SPI driver ISR. (interrupts are disabled)\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+static void AT25D_Wait(At25 *pAt25)\r
+{\r
+ /* Wait for transfer to finish */\r
+ while (AT25_IsBusy(pAt25))\r
+ SPID_Handler(pAt25->pSpid);\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the status register of the serial flash.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+static unsigned char AT25D_ReadStatus(At25 *pAt25)\r
+{\r
+ unsigned char error, status;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Issue a status read command */\r
+ error = AT25_SendCommand(pAt25, AT25_READ_STATUS, 1, &status, 1, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Writes the given value in the status register of the serial flash device.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param status Status to write.\r
+ */\r
+static void AT25D_WriteStatus(At25 *pAt25, unsigned char status)\r
+{\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Issue a write status command */\r
+ error = AT25_SendCommand(pAt25, AT25_WRITE_STATUS, 1, &status, 1, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Waits for the serial flash device to become ready to accept new commands.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+void AT25D_WaitReady(At25 *pAt25)\r
+{\r
+ unsigned char ready = 0;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Read status register and check busy bit */\r
+ while (!ready) {\r
+\r
+ ready = ((AT25D_ReadStatus(pAt25) & AT25_STATUS_RDYBSY) == AT25_STATUS_RDYBSY_READY);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the serial flash device ID.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+unsigned int AT25D_ReadJedecId(At25 *pAt25)\r
+{\r
+ unsigned char error;\r
+ unsigned int id = 0;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Issue a read ID command */\r
+ error = AT25_SendCommand(pAt25, AT25_READ_JEDEC_ID, 1,\r
+ (unsigned char *) &id, 3, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+\r
+ return id;\r
+}\r
+\r
+/**\r
+ * \brief Enables critical writes operation on a serial flash device, such as sector\r
+ * protection, status register, etc.\r
+ *\r
+ * \para pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+void AT25D_EnableWrite(At25 *pAt25)\r
+{\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Issue a write enable command */\r
+ error = AT25_SendCommand(pAt25, AT25_WRITE_ENABLE, 1, 0, 0, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+}\r
+\r
+/**\r
+ * \brief Disables write operation on a serial flash device.\r
+ *\r
+ * \para pAt25 Pointer to an AT25 driver instance.\r
+ */\r
+void AT25D_DisableWrite(At25 *pAt25)\r
+{\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Issue a write enable command */\r
+ error = AT25_SendCommand(pAt25, AT25_WRITE_DISABLE, 1, 0, 0, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+}\r
+\r
+/**\r
+ * \brief Unprotects the contents of the serial flash device.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ *\r
+ * \return 0 if the device has been unprotected; otherwise returns\r
+ * AT25_ERROR_PROTECTED.\r
+ */\r
+unsigned char AT25D_Unprotect(At25 *pAt25)\r
+{\r
+ unsigned char status;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Get the status register value to check the current protection */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & AT25_STATUS_SWP) == AT25_STATUS_SWP_PROTNONE) {\r
+\r
+ /* Protection already disabled */\r
+ return 0;\r
+ }\r
+\r
+ /* Check if sector protection registers are locked */\r
+ if ((status & AT25_STATUS_SPRL) == AT25_STATUS_SPRL_LOCKED) {\r
+\r
+ /* Unprotect sector protection registers by writing the status reg. */\r
+ AT25D_EnableWrite(pAt25);\r
+ AT25D_WriteStatus(pAt25, 0);\r
+ }\r
+\r
+ /* Perform a global unprotect command */\r
+ AT25D_EnableWrite(pAt25);\r
+\r
+ AT25D_WriteStatus(pAt25, 0);\r
+\r
+ /* Check the new status */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & (AT25_STATUS_SPRL | AT25_STATUS_SWP)) != 0) {\r
+\r
+ return AT25_ERROR_PROTECTED;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Erases all the content of the memory chip.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ *\r
+ * \return 0 if the device has been unprotected; otherwise returns\r
+ * AT25_ERROR_PROTECTED.\r
+ */\r
+unsigned char AT25D_EraseChip(At25 *pAt25)\r
+{\r
+ unsigned char status;\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Check that the flash is unprotected */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & AT25_STATUS_SWP) != AT25_STATUS_SWP_PROTNONE) {\r
+ return AT25_ERROR_PROTECTED;\r
+ }\r
+\r
+ /* Enable critical write operation */\r
+ AT25D_EnableWrite(pAt25);\r
+\r
+ /* Erase the chip */\r
+ error = AT25_SendCommand(pAt25, AT25_CHIP_ERASE_2, 1, 0, 0, 0, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ *\brief Erases the specified block of the serial firmware dataflash.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param address Address of the block to erase.\r
+ *\r
+ * \return 0 if successful; otherwise returns AT25_ERROR_PROTECTED if the\r
+ * device is protected or AT25_ERROR_BUSY if it is busy executing a command.\r
+ */\r
+unsigned char AT25D_EraseBlock(At25 *pAt25, unsigned int address)\r
+{\r
+ unsigned char status;\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Check that the flash is ready and unprotected */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & AT25_STATUS_RDYBSY) != AT25_STATUS_RDYBSY_READY) {\r
+ TRACE_ERROR("AT25D_EraseBlock : Flash busy\n\r");\r
+ return AT25_ERROR_BUSY;\r
+ }\r
+ else if ((status & AT25_STATUS_SWP) != AT25_STATUS_SWP_PROTNONE) {\r
+ TRACE_ERROR("AT25D_EraseBlock : Flash protected\n\r");\r
+ return AT25_ERROR_PROTECTED;\r
+ }\r
+\r
+ /* Enable critical write operation */\r
+ AT25D_EnableWrite(pAt25);\r
+\r
+ /* Start the block erase command */\r
+ error = AT25_SendCommand(pAt25, AT25_BlockEraseCmd(pAt25), 4, 0, 0, address, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ *\brief Erases the specified 64KB block of the serial firmware dataflash.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param address Address of the block to erase.\r
+ *\r
+ * \return 0 if successful; otherwise returns AT25_ERROR_PROTECTED if the\r
+ * device is protected or AT25_ERROR_BUSY if it is busy executing a command.\r
+ */\r
+unsigned char AT25D_Erase64KBlock(At25 *pAt25, unsigned int address)\r
+{\r
+ unsigned char status;\r
+ unsigned char error;\r
+\r
+ assert(pAt25);\r
+\r
+ /* Check that the flash is ready and unprotected */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & AT25_STATUS_RDYBSY) != AT25_STATUS_RDYBSY_READY) {\r
+ TRACE_ERROR("AT25D_EraseBlock : Flash busy\n\r");\r
+ return AT25_ERROR_BUSY;\r
+ }\r
+ else if ((status & AT25_STATUS_SWP) != AT25_STATUS_SWP_PROTNONE) {\r
+ TRACE_ERROR("AT25D_EraseBlock : Flash protected\n\r");\r
+ return AT25_ERROR_PROTECTED;\r
+ }\r
+\r
+ /* Enable critical write operation */\r
+ AT25D_EnableWrite(pAt25);\r
+\r
+ /* Start the block erase command */\r
+ error = AT25_SendCommand(pAt25, AT25_BLOCK_ERASE_64K, 4, 0, 0, address, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Writes data at the specified address on the serial firmware dataflash. The\r
+ * page(s) to program must have been erased prior to writing. This function\r
+ * handles page boundary crossing automatically.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes in buffer.\r
+ * \param address Write address.\r
+ *\r
+ * \return 0 if successful; otherwise, returns AT25_ERROR_PROGRAM is there has\r
+ * been an error during the data programming.\r
+ */\r
+unsigned char AT25D_Write(\r
+ At25 *pAt25,\r
+ unsigned char *pData,\r
+ unsigned int size,\r
+ unsigned int address)\r
+{\r
+ unsigned int pageSize;\r
+ unsigned int writeSize;\r
+ unsigned char error;\r
+ unsigned char status;\r
+ unsigned int i = 0;\r
+\r
+ assert(pAt25);\r
+ assert(pData);\r
+\r
+ /* Retrieve device page size */\r
+ pageSize = AT25_PageSize(pAt25);\r
+\r
+ /* Program one page after the other */\r
+ while (size > 0) {\r
+ /* Compute number of bytes to program in page */\r
+ writeSize = min(size, pageSize - (address % pageSize));\r
+\r
+ /* Enable critical write operation */\r
+ AT25D_EnableWrite(pAt25);\r
+\r
+ /* Program page */\r
+ if (AT25_ManId(pAt25) == SST_SPI_FLASH) {\r
+\r
+ error = AT25_SendCommand(pAt25, AT25_SEQUENTIAL_PROGRAM_1, 4,\r
+ pData, 2, address, 0, 0);\r
+ \r
+ assert(!error);\r
+ \r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+\r
+ for (i = 2; i < pageSize; i += 2) {\r
+ error = AT25_SendCommand(pAt25, AT25_SEQUENTIAL_PROGRAM_1, 1,\r
+ pData + i, 2, 0, 0, 0);\r
+\r
+ assert(!error);\r
+ \r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+ }\r
+ \r
+ }\r
+ else {\r
+ error = AT25_SendCommand(pAt25, AT25_BYTE_PAGE_PROGRAM, 4,\r
+ pData, writeSize, address, 0, 0);\r
+\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+ /* Poll the Serial flash status register until the operation is achieved */\r
+ AT25D_WaitReady(pAt25);\r
+\r
+ }\r
+ \r
+ /* Make sure that write was without error */\r
+ status = AT25D_ReadStatus(pAt25);\r
+ if ((status & AT25_STATUS_EPE) == AT25_STATUS_EPE_ERROR) {\r
+\r
+ return AT25_ERROR_PROGRAM;\r
+ }\r
+\r
+ pData += writeSize;\r
+ size -= writeSize;\r
+ address += writeSize;\r
+ }\r
+\r
+ /* Enable critical write operation */\r
+ AT25D_DisableWrite(pAt25);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Reads data from the specified address on the serial flash.\r
+ *\r
+ * \param pAt25 Pointer to an AT25 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes to read.\r
+ * \param address Read address.\r
+ *\r
+ * \return 0 if successful; otherwise, fail.\r
+ */\r
+unsigned char AT25D_Read(\r
+ At25 *pAt25,\r
+ unsigned char *pData,\r
+ unsigned int size,\r
+ unsigned int address)\r
+{\r
+ unsigned char error;\r
+\r
+ /* Start a read operation */\r
+ error = AT25_SendCommand(pAt25, AT25_READ_ARRAY_LF, 4, pData, size, address, 0, 0);\r
+ assert(!error);\r
+\r
+ /* Wait for transfer to finish */\r
+ AT25D_Wait(pAt25);\r
+\r
+ return error;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Provides the low-level initialization function that called on chip startup.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/* Default memory map\r
+ Address range Memory region Memory type Shareability Cache policy\r
+ 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT\r
+ 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA\r
+ 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -\r
+ 0x60000000- 0x7FFFFFFF External RAM Normal Non-shareable WBWA\r
+ 0x80000000- 0x9FFFFFFF WTb\r
+ 0xA0000000- 0xBFFFFFFF External device Devicea Shareable\r
+ 0xC0000000- 0xDFFFFFFF Non-shareablea\r
+ 0xE0000000- 0xE00FFFFF Private Peripheral Bus Strongly ordered Shareablea -\r
+ 0xE0100000- 0xFFFFFFFF Vendor-specific device Device Non-shareablea -\r
+ */\r
+\r
+/**\r
+ * \brief Setup a memory region.\r
+ */\r
+void _SetupMemoryRegion( void )\r
+{\r
+\r
+ return;\r
+\r
+#ifdef BELOW_CODE_REMOVED_FOR_REASON_STATED_IN_WARNING_MESSAGE_ABOVE\r
+ uint32_t dwRegionBaseAddr;\r
+ uint32_t dwRegionAttr;\r
+\r
+\r
+/* ITCM memory region --- Normal */\r
+/* #define ITCM_START_ADDRESS 0x00000000UL\r
+ #define ITCM_END_ADDRESS 0x00400000UL\r
+*/\r
+ dwRegionBaseAddr =\r
+ ITCM_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_DEFAULT_ITCM_REGION;\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_PRIVILEGED_READ_WRITE |\r
+ MPU_TEX_WRITE_THROUGH |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+/* Internal flash privilege memory region --- Normal */\r
+/* #define IFLASH_START_ADDRESS 0x00400000UL\r
+ #define IFLASH_END_ADDRESS 0x00600000UL\r
+*/\r
+ dwRegionBaseAddr =\r
+ IFLASH_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_DEFAULT_IFLASH_REGION; //2\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_FULL_ACCESS |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_TEX_WRITE_THROUGH |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+\r
+ /* DTCM memory region */\r
+ dwRegionBaseAddr =\r
+ DTCM_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_DEFAULT_DTCM_REGION; //3\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_PRIVILEGED_READ_WRITE |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_REGION_BUFFERABLE |\r
+ MPU_TEX_WRITE_BACK_ALLOCATE |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+\r
+ /* SRAM memory privilege region */\r
+ dwRegionBaseAddr =\r
+ SRAM_PRIVILEGE_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_DEFAULT_PRAM_REGION; //4\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_FULL_ACCESS |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_REGION_BUFFERABLE |\r
+ MPU_REGION_SHAREABLE |\r
+ MPU_TEX_WRITE_BACK_ALLOCATE|\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(SRAM_PRIVILEGE_END_ADDRESS - SRAM_PRIVILEGE_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+ /* SRAM memory un-privilege region */\r
+ dwRegionBaseAddr =\r
+ SRAM_UNPRIVILEGE_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_DEFAULT_UPRAM_REGION; //5\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_PRIVILEGED_READ_WRITE |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_REGION_BUFFERABLE |\r
+ MPU_TEX_WRITE_BACK_ALLOCATE|\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(SRAM_UNPRIVILEGE_END_ADDRESS - SRAM_UNPRIVILEGE_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+\r
+/* Peripheral memory region ---- Device */\r
+/* #define PERIPHERALS_START_ADDRESS 0x40000000UL\r
+ #define PERIPHERALS_END_ADDRESS 0x400E2000UL\r
+*/\r
+ dwRegionBaseAddr =\r
+ PERIPHERALS_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_PERIPHERALS_REGION; //6\r
+\r
+ dwRegionAttr = MPU_AP_FULL_ACCESS |\r
+ MPU_REGION_EXECUTE_NEVER |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+/* USBHS_ram memory region -External device */\r
+/* #define USBHSRAM_START_ADDRESS 0xA0100000UL\r
+ #define USBHSRAM_END_ADDRESS 0xA0200000UL\r
+*/\r
+ dwRegionBaseAddr =\r
+ USBHSRAM_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_USBHSRAM_REGION; //7\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_FULL_ACCESS |\r
+ MPU_REGION_EXECUTE_NEVER |\r
+ MPU_REGION_SHAREABLE |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+/* QSPI memory region -External RAM -- normal */\r
+/* #define QSPI_START_ADDRESS 0x80000000UL\r
+ #define QSPI_END_ADDRESS 0x9FFFFFFFUL\r
+*/\r
+ dwRegionBaseAddr =\r
+ QSPI_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_QSPIMEM_REGION;\r
+\r
+ dwRegionAttr =\r
+ MPU_AP_FULL_ACCESS |\r
+ MPU_REGION_EXECUTE_NEVER |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_REGION_BUFFERABLE |\r
+ MPU_TEX_WRITE_BACK_ALLOCATE|\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+#ifdef SDRAM_VALID\r
+ /* SDRAM memory region */\r
+ dwRegionBaseAddr =\r
+ SDRAM_START_ADDRESS |\r
+ MPU_REGION_VALID |\r
+ MPU_SDRAM_REGION;\r
+\r
+ dwRegionAttr =\r
+ MPU_REGION_READ_WRITE |\r
+ MPU_REGION_CACHEABLE |\r
+ MPU_REGION_BUFFERABLE |\r
+ MPU_RASR_SRD_Msk |\r
+ MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |\r
+ MPU_REGION_ENABLE;\r
+\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+#endif\r
+\r
+ /* Enable the memory management fault , Bus Fault, Usage Fault exception */\r
+ SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk);\r
+\r
+ /* Enable the MPU region */\r
+ MPU_Enable( MPU_ENABLE | MPU_BGENABLE );\r
+#endif /* BELOW_CODE_REMOVED_FOR_REASON_STATED_IN_WARNING_MESSAGE_ABOVE */\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Performs the low-level initialization of the chip.\r
+ * This includes EFC and master clock configuration.\r
+ * It also enable a low level on the pin NRST triggers a user reset.\r
+ */\r
+extern WEAK void LowLevelInit( void )\r
+{\r
+ /* Set 6 FWS for Embedded Flash Access */\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(6);\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) /* Main Oscillator Selection */\r
+ {\r
+ SUPC_SelectExtCrystal32K();\r
+ PMC_DisableAllClocks();\r
+ PMC_SetMckSelection(PMC_MCKR_CSS_SLOW_CLK, PMC_MCKR_PRES_CLK_1);\r
+ /* Then, enable Main XTAL oscillator */\r
+ PMC_EnableExtOsc();\r
+ PMC_SelectExtOsc();\r
+ PMC_SetMckSelection(PMC_MCKR_CSS_MAIN_CLK, PMC_MCKR_PRES_CLK_1);\r
+ /* wait Main CLK Ready */\r
+ while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY));\r
+ /* Then, cofigure PLLA and switch clock */\r
+ PMC_ConfigureMckWithPlla(0x16, 0x1, PMC_MCKR_PRES_CLK_1);\r
+ PMC->PMC_MCKR |= 1 << 8;\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+ }\r
+\r
+ _SetupMemoryRegion();\r
+\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of memories configuration on board.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures the EBI for NandFlash access.\r
+ */\r
+extern void BOARD_ConfigureNandFlash( Smc* pSmc )\r
+{\r
+ /* Enable peripheral clock */\r
+ PMC_EnablePeripheral( ID_SMC ) ;\r
+\r
+ /* NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0) */\r
+ // MATRIX->MATRIX_SFR[5] = 1;\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_SETUP = \r
+ SMC_SETUP_NWE_SETUP(0)\r
+ | SMC_SETUP_NCS_WR_SETUP(1)\r
+ | SMC_SETUP_NRD_SETUP(0)\r
+ | SMC_SETUP_NCS_RD_SETUP(1);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_PULSE = \r
+ SMC_PULSE_NWE_PULSE(2)\r
+ | SMC_PULSE_NCS_WR_PULSE(3)\r
+ | SMC_PULSE_NRD_PULSE(4)\r
+ | SMC_PULSE_NCS_RD_PULSE(4);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_CYCLE = \r
+ SMC_CYCLE_NWE_CYCLE(4)\r
+ | SMC_CYCLE_NRD_CYCLE(7);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_MODE = \r
+ SMC_MODE_READ_MODE\r
+ | SMC_MODE_WRITE_MODE;\r
+}\r
+\r
+/**\r
+ * \brief Configures the EBI for %NorFlash access.\r
+ */\r
+extern void BOARD_ConfigureNorFlash( Smc* pSmc )\r
+{\r
+ /* Enable peripheral clock */\r
+ PMC_EnablePeripheral( ID_SMC ) ;\r
+\r
+ /* Configure SMC, NCS0 is assigned to a norflash */\r
+ pSmc->SMC_CS_NUMBER[0].SMC_SETUP = \r
+ SMC_SETUP_NWE_SETUP(2)\r
+ | SMC_SETUP_NCS_WR_SETUP(0)\r
+ | SMC_SETUP_NRD_SETUP(0)\r
+ | SMC_SETUP_NCS_RD_SETUP(0);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_PULSE = \r
+ SMC_PULSE_NWE_PULSE(6)\r
+ | SMC_PULSE_NCS_WR_PULSE(0xA)\r
+ | SMC_PULSE_NRD_PULSE(0xA)\r
+ | SMC_PULSE_NCS_RD_PULSE(0xA);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_CYCLE = \r
+ SMC_CYCLE_NWE_CYCLE(0xA)\r
+ | SMC_CYCLE_NRD_CYCLE(0xA);\r
+\r
+ pSmc->SMC_CS_NUMBER[0].SMC_MODE = \r
+ SMC_MODE_READ_MODE\r
+ | SMC_MODE_WRITE_MODE\r
+ | SMC_MODE_EXNW_MODE_DISABLED\r
+ | SMC_MODE_TDF_CYCLES(0x1);\r
+}\r
+\r
+/**\r
+ * \brief An accurate one-to-one comparison is necessary between PSRAM and SMC waveforms for\r
+ * a complete SMC configuration.\r
+ * \note The system is running at 48 MHz for the EBI Bus.\r
+ * Please refer to the "AC Characteristics" section of the customer product datasheet.\r
+ */\r
+extern void BOARD_ConfigurePSRAM( Smc* pSmc )\r
+{\r
+ uint32_t dwTmp ;\r
+\r
+ /* Enable peripheral clock */\r
+ PMC_EnablePeripheral( ID_SMC ) ;\r
+\r
+ /* Configure SMC, NCS1 is assigned to a external PSRAM */\r
+ /**\r
+ * PSRAM IS66WV51216BLL\r
+ * 55 ns Access time\r
+ * tdoe = 25 ns max\r
+ * SMC1 (timing SAM3S read mode SMC) = 21 ns of setup\r
+ * 21 + 55 = 76 ns => at least 5 cycles at 64 MHz\r
+ * Write pulse width minimum = 45 ns (PSRAM)\r
+ */\r
+ pSmc->SMC_CS_NUMBER[1].SMC_SETUP = \r
+ SMC_SETUP_NWE_SETUP( 1 )\r
+ | SMC_SETUP_NCS_WR_SETUP( 0 )\r
+ | SMC_SETUP_NRD_SETUP( 2 )\r
+ | SMC_SETUP_NCS_RD_SETUP( 0 ) ;\r
+\r
+ pSmc->SMC_CS_NUMBER[1].SMC_PULSE = \r
+ SMC_PULSE_NWE_PULSE( 3 )\r
+ | SMC_PULSE_NCS_WR_PULSE( 4 )\r
+ | SMC_PULSE_NRD_PULSE( 3 )\r
+ | SMC_PULSE_NCS_RD_PULSE( 5 ) ;\r
+\r
+ /* NWE_CYCLE: The total duration of the write cycle.\r
+ NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD\r
+ = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD\r
+ (tWC) Write Cycle Time min. 70ns\r
+NRD_CYCLE: The total duration of the read cycle.\r
+NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD\r
+= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD\r
+(tRC) Read Cycle Time min. 70ns. */\r
+ pSmc->SMC_CS_NUMBER[1].SMC_CYCLE = \r
+ SMC_CYCLE_NWE_CYCLE( 4 )\r
+ | SMC_CYCLE_NRD_CYCLE( 5 ) ;\r
+\r
+ dwTmp = SMC->SMC_CS_NUMBER[0].SMC_MODE;\r
+ pSmc->SMC_CS_NUMBER[1].SMC_MODE = dwTmp\r
+ | SMC_MODE_READ_MODE\r
+ | SMC_MODE_WRITE_MODE;\r
+}\r
+\r
+\r
+uint32_t ExtRAM_Validation(uint32_t baseAddr, uint32_t size)\r
+{\r
+ uint32_t i;\r
+ uint32_t *ptr = (uint32_t *) baseAddr;\r
+\r
+ for (i = 0; i < size << 2; ++i) {\r
+\r
+ if (i & 1) {\r
+ ptr[i] = 0x55AA55AA | (1 << i);\r
+ }\r
+ else {\r
+ ptr[i] = 0xAA55AA55 | (1 << i);\r
+ }\r
+ }\r
+\r
+ for (i = 0; i < size << 2; ++i) {\r
+ if (i & 1) {\r
+ if (ptr[i] != (0x55AA55AA | (1 << i))) {\r
+ return 0;\r
+ }\r
+ }\r
+ else {\r
+ if (ptr[i] != (0xAA55AA55 | (1 << i))) {\r
+ return 0;\r
+ }\r
+ }\r
+ }\r
+ return 1;\r
+}\r
+\r
+\r
+#define SDRAM_BA0 (1 << 20)\r
+#define SDRAM_BA1 (1 << 21)\r
+\r
+/**\r
+ * \brief Configures the EBI for Sdram (IS42S16100E-7B) access.\r
+ */\r
+\r
+\r
+void BOARD_ConfigureSdram( void )\r
+{\r
+ const Pin pinsSdram[] = {BOARD_SDRAM_PINS};\r
+ volatile uint32_t i;\r
+ volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR;\r
+\r
+ /* Configure PIO */\r
+ PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));\r
+ PMC_EnablePeripheral(ID_SDRAMC);\r
+ *((uint32_t *)0x40088124) = 0x10;\r
+\r
+ /* 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number\r
+ of columns, rows, CAS latency, and the data bus width. */\r
+ SDRAMC->SDRAMC_CR = \r
+ SDRAMC_CR_NC_COL8 // 8 column bits \r
+ | SDRAMC_CR_NR_ROW11 // 12 row bits (4K)\r
+ | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 2\r
+ | SDRAMC_CR_NB_BANK2 // 2 banks\r
+ | SDRAMC_CR_DBW // 16 bit\r
+ | SDRAMC_CR_TWR(2)\r
+ | SDRAMC_CR_TRC_TRFC(9) // 63ns min\r
+ | SDRAMC_CR_TRP(3) // Command period (PRE to ACT) 21 ns min\r
+ | SDRAMC_CR_TRCD(3) // Active Command to read/Write Command delay time 21ns min \r
+ | SDRAMC_CR_TRAS(6) // Command period (ACT to PRE) 42ns min \r
+ | SDRAMC_CR_TXSR(10U); //Exit self-refresh to active time 70ns Min\r
+\r
+ /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array\r
+ self refresh (PASR) must be set in the Low Power Register. */\r
+\r
+ /* 3. The SDRAM memory type must be set in the Memory Device Register.*/\r
+ SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;\r
+\r
+ /* 4. A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.*/\r
+ for (i = 0; i < 100000; i++);\r
+\r
+ /* 5. (1)A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode\r
+ Register and perform a write access to any SDRAM address.*/\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;\r
+ *pSdram = 0;\r
+ for (i = 0; i < 100000; i++);\r
+ /* 6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in\r
+ the Mode Register and perform a write access to any SDRAM address. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;\r
+ *pSdram = 0;\r
+ for (i = 0; i < 100000; i++);\r
+ /* 7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register\r
+ and perform a write access to any SDRAM location eight times.*/\r
+ for (i = 0 ; i< 8; i++) {\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *pSdram = 0;\r
+ }\r
+ for (i = 0; i < 100000; i++);\r
+ /*8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular\r
+ CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a write\r
+ access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a\r
+ 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be\r
+ done at the address 0x70000000.*/\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;\r
+ *pSdram = 0;\r
+\r
+ for (i = 0; i < 100000; i++);\r
+ /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the\r
+ SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and\r
+ perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1.\r
+ For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write\r
+ access should be done at the address 0x70800000 or 0x70400000. */\r
+ //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;\r
+ // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0;\r
+\r
+ /* 10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write\r
+ access at any location in the SDRAM. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;\r
+ *pSdram = 0;\r
+ for (i = 0; i < 100000; i++);\r
+ /* 11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay\r
+ between refresh cycles). The SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. With a 100 MHz\r
+ frequency, the Refresh Timer Counter Register must be set with the value 1562(15.625 ¦Ìs x 100 MHz) or\r
+ 781(7.81 ¦Ìs x 100 MHz). */\r
+ // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ìs\r
+ SDRAMC->SDRAMC_TR = 2011; //1562;\r
+ SDRAMC->SDRAMC_CR1 |= 1<<8;\r
+ /* After initialization, the SDRAM devices are fully functional. */\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implements UART console.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Console baudrate always using 115200. */\r
+\r
+\r
+#define CONSOLE_BAUDRATE 115200\r
+\r
+#ifdef SSC_AUDIO\r
+/** Usart Hw interface used by the console (UART4). */\r
+#warning Please use UART4 pins for debug consol as UART0 pins are used in SSC audio for SAMv7 Xplained ultra board\r
+#define CONSOLE_UART UART4\r
+\r
+/** Pins description corresponding to Rxd,Txd, (UART pins) */\r
+#define CONSOLE_PINS {PINS_UART4}\r
+\r
+#define CONSOLE_ID ID_UART4\r
+#else\r
+/** Usart Hw interface used by the console (UART0). */\r
+#define CONSOLE_UART UART0\r
+\r
+/** Pins description corresponding to Rxd,Txd, (UART pins) */\r
+#define CONSOLE_PINS {PINS_UART0}\r
+\r
+#define CONSOLE_ID ID_UART0\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Is Console Initialized. */\r
+static uint8_t _ucIsConsoleInitialized=0 ;\r
+\r
+/**\r
+ * \brief Configures an USART peripheral with the specified parameters.\r
+ *\r
+ * \param baudrate Baudrate at which the USART should operate (in Hz).\r
+ * \param masterClock Frequency of the system master clock (in Hz).\r
+ */\r
+extern void DBG_Configure( uint32_t baudrate, uint32_t masterClock)\r
+{\r
+ \r
+ const Pin pPins[] = CONSOLE_PINS ;\r
+ Uart *pUart = CONSOLE_UART ;\r
+\r
+ unsigned int mode;\r
+\r
+ /* Configure PIO */\r
+ PIO_Configure( pPins, PIO_LISTSIZE( pPins ) ) ;\r
+ PMC_EnablePeripheral(CONSOLE_ID);\r
+\r
+ mode = UART_MR_CHMODE_NORMAL | UART_MR_PAR_NO;\r
+ \r
+\r
+ // Reset & disable receiver and transmitter, disable interrupts\r
+ pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RSTSTA;\r
+ pUart->UART_IDR = 0xFFFFFFFF;\r
+ \r
+ \r
+ pUart->UART_BRGR = (masterClock / baudrate) / 16 ;\r
+\r
+ // Configure mode register\r
+ pUart->UART_MR = (mode );\r
+\r
+ // Enable receiver and transmitter\r
+ pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;\r
+ _ucIsConsoleInitialized = 1 ;\r
+\r
+ /* Disable buffering for printf(). */\r
+#if ( defined (__GNUC__) && !defined (__SAMBA__) )\r
+ setvbuf(stdout, (char *)NULL, _IONBF, 0);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Outputs a character on the UART line.\r
+ *\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \param c Character to send.\r
+ */\r
+extern void DBG_PutChar( uint8_t c )\r
+{\r
+ Uart *pUart=CONSOLE_UART ;\r
+\r
+ if ( !_ucIsConsoleInitialized )\r
+ {\r
+ DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK);\r
+ }\r
+\r
+ // Wait for the transmitter to be ready\r
+ while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0);\r
+ \r
+ // Send character\r
+ pUart->UART_THR = c;\r
+ \r
+ // Wait for the transfer to complete\r
+ while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Input a character from the UART line.\r
+ *\r
+ * \note This function is synchronous\r
+ * \return character received.\r
+ */\r
+extern uint32_t DBG_GetChar( void )\r
+{\r
+ Uart *pUart= CONSOLE_UART ;\r
+\r
+ if ( !_ucIsConsoleInitialized )\r
+ {\r
+ DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK);\r
+ }\r
+\r
+ while ((pUart->UART_SR & UART_SR_RXRDY) == 0);\r
+ return pUart->UART_RHR;\r
+}\r
+\r
+/**\r
+ * \brief Check if there is Input from UART line.\r
+ *\r
+ * \return true if there is Input.\r
+ */\r
+extern uint32_t DBG_IsRxReady( void )\r
+{\r
+ Uart *pUart=CONSOLE_UART ;\r
+\r
+ if ( !_ucIsConsoleInitialized )\r
+ {\r
+ DBG_Configure( CONSOLE_BAUDRATE, BOARD_MCK ) ;\r
+ }\r
+\r
+ return (pUart->UART_SR & UART_SR_RXRDY);\r
+}\r
+\r
+/**\r
+ * Displays the content of the given frame on the UART0.\r
+ *\r
+ * \param pucFrame Pointer to the frame to dump.\r
+ * \param dwSize Buffer size in bytes.\r
+ */\r
+extern void DBG_DumpFrame( uint8_t* pucFrame, uint32_t dwSize )\r
+{\r
+ uint32_t dw ;\r
+\r
+ for ( dw=0 ; dw < dwSize ; dw++ )\r
+ {\r
+ printf( "%02X ", pucFrame[dw] ) ;\r
+ }\r
+\r
+ printf( "\n\r" ) ;\r
+}\r
+\r
+/**\r
+ * Displays the content of the given buffer on the UART0.\r
+ *\r
+ * \param pucBuffer Pointer to the buffer to dump.\r
+ * \param dwSize Buffer size in bytes.\r
+ * \param dwAddress Start address to display\r
+ */\r
+extern void DBG_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress )\r
+{\r
+ uint32_t i ;\r
+ uint32_t j ;\r
+ uint32_t dwLastLineStart ;\r
+ uint8_t* pucTmp ;\r
+\r
+ for ( i=0 ; i < (dwSize / 16) ; i++ )\r
+ {\r
+ printf( "0x%08X: ", (unsigned int)(dwAddress + (i*16)) ) ;\r
+ pucTmp = (uint8_t*)&pucBuffer[i*16] ;\r
+\r
+ for ( j=0 ; j < 4 ; j++ )\r
+ {\r
+ printf( "%02X%02X%02X%02X ", pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3] ) ;\r
+ pucTmp += 4 ;\r
+ }\r
+\r
+ pucTmp=(uint8_t*)&pucBuffer[i*16] ;\r
+\r
+ for ( j=0 ; j < 16 ; j++ )\r
+ {\r
+ DBG_PutChar( *pucTmp++ ) ;\r
+ }\r
+\r
+ printf( "\n\r" ) ;\r
+ }\r
+\r
+ if ( (dwSize%16) != 0 )\r
+ {\r
+ dwLastLineStart=dwSize - (dwSize%16) ;\r
+\r
+ printf( "0x%08X: ", (unsigned int)(dwAddress + dwLastLineStart) ) ;\r
+ for ( j=dwLastLineStart ; j < dwLastLineStart+16 ; j++ )\r
+ {\r
+ if ( (j!=dwLastLineStart) && (j%4 == 0) )\r
+ {\r
+ printf( " " ) ;\r
+ }\r
+\r
+ if ( j < dwSize )\r
+ {\r
+ printf( "%02X", pucBuffer[j] ) ;\r
+ }\r
+ else\r
+ {\r
+ printf(" ") ;\r
+ }\r
+ }\r
+\r
+ printf( " " ) ;\r
+ for ( j=dwLastLineStart ; j < dwSize ; j++ )\r
+ {\r
+ DBG_PutChar( pucBuffer[j] ) ;\r
+ }\r
+\r
+ printf( "\n\r" ) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * Reads an integer\r
+ *\r
+ * \param pdwValue Pointer to a integer variable to contain the input value.\r
+ *\r
+ * \return success(1) or failure(0)\r
+ */\r
+extern uint32_t DBG_GetInteger( int32_t* pdwValue )\r
+{\r
+ uint8_t ucKey ;\r
+ uint8_t ucNum = 0 ;\r
+ int32_t dwValue = 0 ;\r
+ int32_t sign = 1 ;\r
+\r
+ while ( 1 )\r
+ {\r
+ ucKey=DBG_GetChar() ;\r
+ DBG_PutChar( ucKey ) ;\r
+\r
+ if ( ((ucKey == '-') || (ucKey == '+')) && (ucNum == 0) )\r
+ {\r
+ if (ucKey == '-')\r
+ {\r
+ sign = -1;\r
+ }\r
+ else\r
+ {\r
+ sign = 1;\r
+ }\r
+ ucNum++;\r
+ }\r
+ else\r
+ {\r
+ if ( ucKey >= '0' && ucKey <= '9' )\r
+ {\r
+ dwValue = (dwValue * 10) + (ucKey - '0');\r
+ ucNum++;\r
+ }\r
+ else\r
+ {\r
+ if ( ucKey == 0x0D || ucKey == ' ' )\r
+ {\r
+ if ( ucNum == 0 )\r
+ {\r
+ printf( "\n\rWrite a number and press ENTER or SPACE!\n\r" ) ;\r
+ return 0 ;\r
+ }\r
+ else\r
+ {\r
+ printf( "\n\r" ) ;\r
+ *pdwValue = dwValue * sign;\r
+\r
+ return 1 ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ printf( "\n\r'%c' not a number or sign(+/-)!\n\r", ucKey ) ;\r
+\r
+ return 0 ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Reads an integer and check the value\r
+ *\r
+ * \param pdwValue Pointer to a integer variable to contain the input value.\r
+ * \param dwMin Minimum value\r
+ * \param dwMax Maximum value\r
+ *\r
+ * \return success(1) or failure(0)\r
+ */\r
+extern uint32_t DBG_GetIntegerMinMax( int32_t* pdwValue, int32_t dwMin, int32_t dwMax )\r
+{\r
+ int32_t dwValue = 0 ;\r
+\r
+ if ( DBG_GetInteger( &dwValue ) == 0 )\r
+ {\r
+ return 0 ;\r
+ }\r
+\r
+ if ( dwValue < dwMin || dwValue > dwMax )\r
+ {\r
+ printf( "\n\rThe number have to be between %d and %d\n\r", (int)dwMin, (int)dwMax ) ;\r
+\r
+ return 0 ;\r
+ }\r
+\r
+ printf( "\n\r" ) ;\r
+\r
+ *pdwValue = dwValue ;\r
+\r
+ return 1 ;\r
+}\r
+\r
+/**\r
+ * Reads an hexadecimal number\r
+ *\r
+ * \param pdwValue Pointer to the uint32_t variable to contain the input value.\r
+ */\r
+extern uint32_t DBG_GetHexa32( uint32_t* pdwValue )\r
+{\r
+ uint8_t ucKey ;\r
+ uint32_t dw = 0 ;\r
+ uint32_t dwValue = 0 ;\r
+\r
+ for ( dw=0 ; dw < 8 ; dw++ )\r
+ {\r
+ ucKey = DBG_GetChar() ;\r
+ DBG_PutChar( ucKey ) ;\r
+\r
+ if ( ucKey >= '0' && ucKey <= '9' )\r
+ {\r
+ dwValue = (dwValue * 16) + (ucKey - '0') ;\r
+ }\r
+ else\r
+ {\r
+ if ( ucKey >= 'A' && ucKey <= 'F' )\r
+ {\r
+ dwValue = (dwValue * 16) + (ucKey - 'A' + 10) ;\r
+ }\r
+ else\r
+ {\r
+ if ( ucKey >= 'a' && ucKey <= 'f' )\r
+ {\r
+ dwValue = (dwValue * 16) + (ucKey - 'a' + 10) ;\r
+ }\r
+ else\r
+ {\r
+ printf( "\n\rIt is not a hexa character!\n\r" ) ;\r
+\r
+ return 0 ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ printf("\n\r" ) ;\r
+ *pdwValue = dwValue ;\r
+\r
+ return 1 ;\r
+}\r
+\r
+#if defined __ICCARM__ /* IAR Ewarm 5.41+ */\r
+/**\r
+ * \brief Outputs a character on the UART.\r
+ *\r
+ * \param c Character to output.\r
+ *\r
+ * \return The character that was output.\r
+ */\r
+extern WEAK signed int putchar( signed int c )\r
+{\r
+ DBG_PutChar( c ) ;\r
+\r
+ return c ;\r
+}\r
+\r
+extern WEAK int puts(const char *ptr )\r
+{\r
+ \r
+ for ( ; *ptr != 0 ; ptr++ )\r
+ {\r
+ DBG_PutChar( *ptr ) ;\r
+ }\r
+ \r
+ return 0;\r
+\r
+}\r
+#endif // defined __ICCARM__\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Definitions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** Default max retry count */\r
+#define GMACB_RETRY_MAX 300000\r
+\r
+/** Default max retry count */\r
+#define GACB_RETRY_MAX 1000000\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Local functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * Wait PHY operation complete.\r
+ * Return 1 if the operation completed successfully.\r
+ * May be need to re-implemented to reduce CPU load.\r
+ * \param retry: the retry times, 0 to wait forever until complete.\r
+ */\r
+static uint8_t GMACB_WaitPhy( Gmac *pHw, uint32_t retry )\r
+{\r
+ volatile uint32_t retry_count = 0;\r
+\r
+ while (!GMAC_IsIdle(pHw))\r
+ {\r
+ if(retry == 0) continue;\r
+ retry_count ++;\r
+ if (retry_count >= retry)\r
+ {\r
+ return 0;\r
+ }\r
+ }\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * Read PHY register.\r
+ * Return 1 if successfully, 0 if timeout.\r
+ * \param pHw HW controller address\r
+ * \param PhyAddress PHY Address\r
+ * \param Address Register Address\r
+ * \param pValue Pointer to a 32 bit location to store read data\r
+ * \param retry The retry times, 0 to wait forever until complete.\r
+ */\r
+static uint8_t GMACB_ReadPhy(Gmac *pHw,\r
+ uint8_t PhyAddress,\r
+ uint8_t Address,\r
+ uint32_t *pValue,\r
+ uint32_t retry)\r
+{\r
+ GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0);\r
+ if ( GMACB_WaitPhy(pHw, retry) == 0 )\r
+ {\r
+ TRACE_ERROR("TimeOut GMACB_ReadPhy\n\r");\r
+ return 0;\r
+ }\r
+ *pValue = GMAC_PHYData(pHw);\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * Write PHY register\r
+ * Return 1 if successfully, 0 if timeout.\r
+ * \param pHw HW controller address\r
+ * \param PhyAddress PHY Address\r
+ * \param Address Register Address\r
+ * \param Value Data to write ( Actually 16 bit data )\r
+ * \param retry The retry times, 0 to wait forever until complete.\r
+ */\r
+static uint8_t GMACB_WritePhy(Gmac *pHw,\r
+ uint8_t PhyAddress,\r
+ uint8_t Address,\r
+ uint32_t Value,\r
+ uint32_t retry)\r
+{\r
+ GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value);\r
+ if ( GMACB_WaitPhy(pHw, retry) == 0 )\r
+ {\r
+ TRACE_ERROR("TimeOut GMACB_WritePhy\n\r");\r
+ return 0;\r
+ }\r
+ return 1;\r
+}\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Find a valid PHY Address ( from 0 to 31 ).\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \return 0xFF when no valid PHY Address found.\r
+ */\r
+static uint8_t GMACB_FindValidPhy(GMacb *pMacb)\r
+{\r
+ sGmacd *pDrv = pMacb->pGmacd;\r
+ Gmac *pHw = pDrv->pHw;\r
+\r
+ uint32_t retryMax;\r
+ uint32_t value=0;\r
+ uint8_t rc;\r
+ uint8_t phyAddress;\r
+ uint8_t cnt;\r
+\r
+ TRACE_DEBUG("GMACB_FindValidPhy\n\r");\r
+\r
+ GMAC_EnableMdio(pHw);\r
+ phyAddress = pMacb->phyAddress;\r
+ retryMax = pMacb->retryMax;\r
+\r
+ /* Check current phyAddress */\r
+ rc = phyAddress;\r
+ if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) == 0 ) {\r
+ TRACE_ERROR("GMACB PROBLEM\n\r");\r
+ }\r
+ TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);\r
+\r
+ /* Find another one */\r
+ if (value != GMII_OUI_MSB) {\r
+\r
+ rc = 0xFF;\r
+ for(cnt = 0; cnt < 32; cnt ++) {\r
+\r
+ phyAddress = (phyAddress + 1) & 0x1F;\r
+ if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) == 0 ) {\r
+ TRACE_ERROR("MACB PROBLEM\n\r");\r
+ }\r
+ TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);\r
+ if (value == GMII_OUI_MSB) {\r
+\r
+ rc = phyAddress;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ if (rc != 0xFF) {\r
+ TRACE_INFO("** Valid PHY Found: %d\n\r", rc);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax);\r
+ TRACE_DEBUG("_PHYID1R : 0x%X, addr: %d\n\r", value, phyAddress);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID2R, &value, retryMax);\r
+ TRACE_DEBUG("_EMSR : 0x%X, addr: %d\n\r", value, phyAddress);\r
+ }\r
+ GMAC_DisableMdio(pHw);\r
+ return rc;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Dump all the useful registers.\r
+ * \param pMacb Pointer to the MACB instance\r
+ */\r
+void GMACB_DumpRegisters(GMacb *pMacb)\r
+{\r
+ sGmacd *pDrv = pMacb->pGmacd;\r
+ Gmac *pHw = pDrv->pHw;\r
+\r
+ uint8_t phyAddress;\r
+ uint32_t retryMax;\r
+ uint32_t value;\r
+\r
+ TRACE_INFO("GMACB_DumpRegisters\n\r");\r
+\r
+ GMAC_EnableMdio(pHw);\r
+ phyAddress = pMacb->phyAddress;\r
+ retryMax = pMacb->retryMax;\r
+\r
+ TRACE_INFO("GMII MACB @ %d) Registers:\n\r", phyAddress);\r
+\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);\r
+ TRACE_INFO(" _BMCR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);\r
+ TRACE_INFO(" _BMSR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax);\r
+ TRACE_INFO(" _PHYID1 : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID2R, &value, retryMax);\r
+ TRACE_INFO(" _PHYID2 : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &value, retryMax);\r
+ TRACE_INFO(" _ANAR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &value, retryMax);\r
+ TRACE_INFO(" _ANLPAR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ANER, &value, retryMax);\r
+ TRACE_INFO(" _ANER : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ANNPR, &value, retryMax);\r
+ TRACE_INFO(" _ANNPR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPNPAR, &value, retryMax);\r
+ TRACE_INFO(" _ANLPNPAR : 0x%X\n\r", value);\r
+\r
+ TRACE_INFO(" \n\r");\r
+\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_RXERCR, &value, retryMax);\r
+ TRACE_INFO(" _RXERCR : 0x%X\n\r", value);\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_ICSR, &value, retryMax);\r
+ TRACE_INFO(" _ICSR : 0x%X\n\r", value);\r
+ TRACE_INFO(" \n\r");\r
+\r
+ GMAC_DisableMdio(pHw);\r
+}\r
+\r
+/**\r
+ * \brief Setup the maximum timeout count of the driver.\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \param toMax Timeout maxmum count.\r
+ */\r
+void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax)\r
+{\r
+ pMacb->retryMax = toMax;\r
+}\r
+\r
+/**\r
+ * \brief Initialize the MACB instance.\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \param phyAddress The PHY address used to access the PHY\r
+ */\r
+void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress)\r
+{\r
+ pMacb->pGmacd = pGmacd;\r
+ pMacb->phyAddress = phyAddress;\r
+ /* Initialize timeout by default */\r
+ pMacb->retryMax = GMACB_RETRY_MAX;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Issue a SW reset to reset all registers of the PHY.\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \return 1 if successfully, 0 if timeout.\r
+ */\r
+uint8_t GMACB_ResetPhy(GMacb *pMacb)\r
+{\r
+ sGmacd *pDrv = pMacb->pGmacd;\r
+ Gmac *pHw = pDrv->pHw;\r
+ uint32_t retryMax;\r
+ uint32_t bmcr = GMII_RESET;\r
+ uint8_t phyAddress;\r
+ uint32_t timeout = 10;\r
+ uint8_t ret = 1;\r
+\r
+ TRACE_INFO(" GMACB_ResetPhy\n\r");\r
+\r
+ phyAddress = pMacb->phyAddress;\r
+ retryMax = pMacb->retryMax;\r
+\r
+ GMAC_EnableMdio(pHw);\r
+ bmcr = GMII_RESET;\r
+ GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, bmcr, retryMax);\r
+\r
+ do {\r
+ GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &bmcr, retryMax);\r
+ timeout--;\r
+ } while ((bmcr & GMII_RESET) && timeout);\r
+\r
+ GMAC_DisableMdio(pHw);\r
+\r
+ if (!timeout) {\r
+ ret = 0;\r
+ }\r
+\r
+ return( ret );\r
+}\r
+\r
+/**\r
+ * \brief Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs\r
+ * This should be called only once to initialize the PHY pre-settings.\r
+ * The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups).\r
+ * The COL pin is used to select MII mode on reset (pulled up for Reduced MII)\r
+ * The RXDV pin is used to select test mode on reset (pulled up for test mode)\r
+ * The above pins should be predefined for corresponding settings in resetPins\r
+ * The GMAC peripheral pins are configured after the reset done.\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \param mck Main clock setting to initialize clock\r
+ * \param resetPins Pointer to list of PIOs to configure before HW RESET\r
+ * (for PHY power on reset configuration latch)\r
+ * \param nbResetPins Number of PIO items that should be configured\r
+ * \param emacPins Pointer to list of PIOs for the EMAC interface\r
+ * \param nbEmacPins Number of PIO items that should be configured\r
+ * \return 1 if RESET OK, 0 if timeout.\r
+ */\r
+uint8_t GMACB_InitPhy(GMacb *pMacb,\r
+ uint32_t mck,\r
+ const Pin *pResetPins,\r
+ uint32_t nbResetPins,\r
+ const Pin *pGmacPins,\r
+ uint32_t nbGmacPins)\r
+{\r
+ sGmacd *pDrv = pMacb->pGmacd;\r
+ Gmac *pHw = pDrv->pHw;\r
+ uint8_t rc = 1;\r
+ uint8_t phy;\r
+\r
+ /* Perform RESET */\r
+ TRACE_DEBUG("RESET PHY\n\r");\r
+\r
+ if (pResetPins) {\r
+ /* Configure PINS */\r
+ PIO_Configure(pResetPins, nbResetPins);\r
+ TRACE_INFO(" Hard Reset of GMACD Phy\n\r");\r
+ PIO_Clear(pResetPins);\r
+ Wait(100);\r
+ PIO_Set(pResetPins);\r
+ }\r
+ /* Configure GMAC runtime pins */\r
+ if (rc) {\r
+\r
+ PIO_Configure(pGmacPins, nbGmacPins);\r
+ rc = GMAC_SetMdcClock(pHw, mck );\r
+ if (!rc) {\r
+ TRACE_ERROR("No Valid MDC clock\n\r");\r
+ return 0;\r
+ }\r
+\r
+ /* Check PHY Address */\r
+ phy = GMACB_FindValidPhy(pMacb);\r
+ if (phy == 0xFF) {\r
+ TRACE_ERROR("PHY Access fail\n\r");\r
+ return 0;\r
+ }\r
+ if(phy != pMacb->phyAddress) {\r
+ pMacb->phyAddress = phy;\r
+ GMACB_ResetPhy(pMacb);\r
+ }\r
+ }\r
+ else {\r
+ TRACE_ERROR("PHY Reset Timeout\n\r");\r
+ }\r
+ return rc;\r
+}\r
+\r
+/**\r
+ * \brief Issue a Auto Negotiation of the PHY\r
+ * \param pMacb Pointer to the MACB instance\r
+ * \return 1 if successfully, 0 if timeout.\r
+ */\r
+uint8_t GMACB_AutoNegotiate(GMacb *pMacb)\r
+{\r
+ sGmacd *pDrv = pMacb->pGmacd;\r
+ Gmac *pHw = pDrv->pHw;\r
+ uint32_t retryMax;\r
+ uint32_t value;\r
+ uint32_t phyAnar;\r
+ uint32_t phyAnalpar;\r
+ uint32_t retryCount= 0;\r
+ uint8_t phyAddress;\r
+ uint8_t rc = 1;\r
+ uint32_t duplex, speed;\r
+ phyAddress = pMacb->phyAddress;\r
+ retryMax = pMacb->retryMax;\r
+\r
+ GMAC_EnableMdio(pHw);\r
+\r
+ if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID1R, &value, retryMax)) \r
+ {\r
+ TRACE_ERROR("Pb GEMAC_ReadPhy Id1\n\r");\r
+ rc = 0;\r
+ goto AutoNegotiateExit;\r
+ }\r
+ TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress);\r
+ if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID2R, &phyAnar, retryMax)) \r
+ {\r
+ TRACE_ERROR("Pb GMACB_ReadPhy Id2\n\r");\r
+ rc = 0;\r
+ goto AutoNegotiateExit;\r
+ }\r
+ TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar);\r
+\r
+ if( ( value == GMII_OUI_MSB )\r
+ && ( ((phyAnar)&(~GMII_LSB_MASK)) == GMII_OUI_LSB ) )\r
+ {\r
+ TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F));\r
+ TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0xF));\r
+ }\r
+ else \r
+ {\r
+ TRACE_ERROR("Problem OUI value\n\r");\r
+ }\r
+\r
+ /* Set the Auto_negotiation Advertisement Register, MII advertising for Next page\r
+ 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */\r
+ rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &phyAnar, retryMax);\r
+ if (rc == 0) \r
+ {\r
+ goto AutoNegotiateExit;\r
+ }\r
+ phyAnar = GMII_TX_FDX | GMII_TX_HDX |\r
+ GMII_10_FDX | GMII_10_HDX | GMII_AN_IEEE_802_3;\r
+ rc = GMACB_WritePhy(pHw,phyAddress, GMII_ANAR, phyAnar, retryMax);\r
+ if (rc == 0) \r
+ {\r
+ goto AutoNegotiateExit;\r
+ }\r
+\r
+ /* Read & modify control register */\r
+ rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);\r
+ if (rc == 0) \r
+ {\r
+ goto AutoNegotiateExit;\r
+ }\r
+\r
+ /* Check AutoNegotiate complete */\r
+ value |= GMII_AUTONEG | GMII_RESTART_AUTONEG;\r
+ rc = GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, value, retryMax);\r
+ if (rc == 0) \r
+ {\r
+ goto AutoNegotiateExit;\r
+ }\r
+ TRACE_DEBUG(" _BMCR: 0x%X\n\r", value);\r
+\r
+ // Check AutoNegotiate complete\r
+ while (1) \r
+ {\r
+ rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);\r
+ if (rc == 0)\r
+ {\r
+ TRACE_ERROR("rc==0\n\r");\r
+ goto AutoNegotiateExit;\r
+ }\r
+ /* Done successfully */\r
+ if (value & GMII_AUTONEG_COMP) \r
+ {\r
+ printf("AutoNegotiate complete\n\r");\r
+ break;\r
+ }\r
+ /* Timeout check */\r
+ if (retryMax)\r
+ {\r
+ if (++ retryCount >= retryMax)\r
+ {\r
+ GMACB_DumpRegisters(pMacb);\r
+ TRACE_ERROR("TimeOut\n\r");\r
+ rc = 0;\r
+ goto AutoNegotiateExit; \r
+ }\r
+ }\r
+ }\r
+\r
+ /*Set local link mode */\r
+ while(1)\r
+ {\r
+ rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &phyAnalpar, retryMax);\r
+ if (rc == 0) \r
+ {\r
+ goto AutoNegotiateExit;\r
+ }\r
+ /* Setup the GMAC link speed */\r
+ if ((phyAnar & phyAnalpar) & GMII_TX_FDX) \r
+ {\r
+ /* set RGMII for 1000BaseTX and Full Duplex */\r
+ duplex = GMAC_DUPLEX_FULL;\r
+ speed = GMAC_SPEED_100M;\r
+ break;\r
+ }\r
+ else if ((phyAnar & phyAnalpar) & GMII_10_FDX) \r
+ {\r
+ /* set RGMII for 1000BaseT and Half Duplex*/\r
+ duplex = GMAC_DUPLEX_FULL;\r
+ speed = GMAC_SPEED_10M;\r
+ break;\r
+ }\r
+ else if ((phyAnar & phyAnalpar) & GMII_TX_HDX) \r
+ {\r
+ /* set RGMII for 100BaseTX and half Duplex */\r
+ duplex = GMAC_DUPLEX_HALF;\r
+ speed = GMAC_SPEED_100M;\r
+ break;\r
+ }\r
+ else if ((phyAnar & phyAnalpar) & GMII_10_HDX) \r
+ {\r
+ // set RGMII for 10BaseT and half Duplex\r
+ duplex = GMAC_DUPLEX_HALF;\r
+ speed = GMAC_SPEED_10M;\r
+ break;\r
+ }\r
+ }\r
+ TRACE_INFO("GMAC_EnableRGMII duplex %u, speed %u\n\r",duplex,speed);\r
+\r
+ GMACB_ReadPhy(pHw,phyAddress, GMII_PC1R, &value, retryMax);\r
+ GMACB_ReadPhy(pHw,phyAddress, GMII_PC2R, &value, retryMax);\r
+ GMACB_ReadPhy(pHw,phyAddress, GMII_ICSR, &value, retryMax);\r
+ /* Setup GMAC mode */\r
+ GMAC_EnableRGMII(pHw, duplex, speed);\r
+\r
+AutoNegotiateExit:\r
+ GMAC_DisableMdio(pHw);\r
+ return rc;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Internal function\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Counts and return the number of bits set to '1' in the given byte.\r
+ * \param byte Byte to count.\r
+ */\r
+static uint8_t CountBitsInByte(uint8_t byte)\r
+{\r
+ uint8_t count = 0;\r
+\r
+ while (byte > 0)\r
+ {\r
+ if (byte & 1)\r
+ {\r
+ count++;\r
+ }\r
+ byte >>= 1;\r
+ }\r
+\r
+ return count;\r
+}\r
+\r
+/**\r
+ * Counts and return the number of bits set to '1' in the given hamming code.\r
+ * \param code Hamming code.\r
+ */\r
+static uint8_t CountBitsInCode256(uint8_t *code)\r
+{\r
+ return CountBitsInByte(code[0]) + CountBitsInByte(code[1]) + CountBitsInByte(code[2]);\r
+}\r
+\r
+/**\r
+ * Calculates the 22-bit hamming code for a 256-bytes block of data.\r
+ * \param data Data buffer to calculate code for.\r
+ * \param code Pointer to a buffer where the code should be stored.\r
+ */\r
+static void Compute256(const uint8_t *data, uint8_t *code)\r
+{\r
+ uint32_t i;\r
+ uint8_t columnSum = 0;\r
+ uint8_t evenLineCode = 0;\r
+ uint8_t oddLineCode = 0;\r
+ uint8_t evenColumnCode = 0;\r
+ uint8_t oddColumnCode = 0;\r
+\r
+ // Xor all bytes together to get the column sum;\r
+ // At the same time, calculate the even and odd line codes\r
+ for (i=0; i < 256; i++)\r
+ {\r
+ columnSum ^= data[i];\r
+\r
+ // If the xor sum of the byte is 0, then this byte has no incidence on\r
+ // the computed code; so check if the sum is 1.\r
+ if ((CountBitsInByte(data[i]) & 1) == 1)\r
+ {\r
+ // Parity groups are formed by forcing a particular index bit to 0\r
+ // (even) or 1 (odd).\r
+ // Example on one byte:\r
+ //\r
+ // bits (dec) 7 6 5 4 3 2 1 0\r
+ // (bin) 111 110 101 100 011 010 001 000\r
+ // '---'---'---'----------.\r
+ // |\r
+ // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |\r
+ // P2' ooooooo eeeeeee ooooooo eeeeeee P2 |\r
+ // P1' ooo eee ooo eee ooo eee ooo eee P1 |\r
+ // |\r
+ // We can see that: |\r
+ // - P4 -> bit 2 of index is 0 --------------------'\r
+ // - P4' -> bit 2 of index is 1.\r
+ // - P2 -> bit 1 of index if 0.\r
+ // - etc...\r
+ // We deduce that a bit position has an impact on all even Px if\r
+ // the log2(x)nth bit of its index is 0\r
+ // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)\r
+ // and on all odd Px' if the log2(x)nth bit of its index is 1\r
+ // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)\r
+ //\r
+ // As such, we calculate all the possible Px and Px' values at the\r
+ // same time in two variables, evenLineCode and oddLineCode, such as\r
+ // evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1\r
+ // oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1'\r
+ //\r
+ evenLineCode ^= (255 - i);\r
+ oddLineCode ^= i;\r
+ }\r
+ }\r
+\r
+ // At this point, we have the line parities, and the column sum. First, We\r
+ // must caculate the parity group values on the column sum.\r
+ for (i=0; i < 8; i++)\r
+ {\r
+ if (columnSum & 1)\r
+ {\r
+ evenColumnCode ^= (7 - i);\r
+ oddColumnCode ^= i;\r
+ }\r
+ columnSum >>= 1;\r
+ }\r
+\r
+ // Now, we must interleave the parity values, to obtain the following layout:\r
+ // Code[0] = Line1\r
+ // Code[1] = Line2\r
+ // Code[2] = Column\r
+ // Line = Px' Px P(x-1)- P(x-1) ...\r
+ // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit\r
+ code[0] = 0;\r
+ code[1] = 0;\r
+ code[2] = 0;\r
+\r
+ for (i=0; i < 4; i++)\r
+ {\r
+ code[0] <<= 2;\r
+ code[1] <<= 2;\r
+ code[2] <<= 2;\r
+\r
+ // Line 1\r
+ if ((oddLineCode & 0x80) != 0)\r
+ {\r
+ code[0] |= 2;\r
+ }\r
+\r
+ if ((evenLineCode & 0x80) != 0)\r
+ {\r
+ code[0] |= 1;\r
+ }\r
+\r
+ // Line 2\r
+ if ((oddLineCode & 0x08) != 0)\r
+ {\r
+ code[1] |= 2;\r
+ }\r
+\r
+ if ((evenLineCode & 0x08) != 0)\r
+ {\r
+ code[1] |= 1;\r
+ }\r
+\r
+ // Column\r
+ if ((oddColumnCode & 0x04) != 0)\r
+ {\r
+ code[2] |= 2;\r
+ }\r
+\r
+ if ((evenColumnCode & 0x04) != 0)\r
+ {\r
+ code[2] |= 1;\r
+ }\r
+\r
+ oddLineCode <<= 1;\r
+ evenLineCode <<= 1;\r
+ oddColumnCode <<= 1;\r
+ evenColumnCode <<= 1;\r
+ }\r
+\r
+ // Invert codes (linux compatibility)\r
+ code[0] = (~(uint32_t)code[0]);\r
+ code[1] = (~(uint32_t)code[1]);\r
+ code[2] = (~(uint32_t)code[2]);\r
+\r
+ TRACE_DEBUG("Computed code = %02X %02X %02X\n\r",\r
+ code[0], code[1], code[2]);\r
+}\r
+\r
+/**\r
+ * Verifies and corrects a 256-bytes block of data using the given 22-bits\r
+ * hamming code.\r
+ *\r
+ * \param data Data buffer to check.\r
+ * \param originalCode Hamming code to use for verifying the data.\r
+ *\r
+ * \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.\r
+ */\r
+static uint8_t Verify256( uint8_t* pucData, const uint8_t* pucOriginalCode )\r
+{\r
+ /* Calculate new code */\r
+ uint8_t computedCode[3] ;\r
+ uint8_t correctionCode[3] ;\r
+\r
+ Compute256( pucData, computedCode ) ;\r
+\r
+ /* Xor both codes together */\r
+ correctionCode[0] = computedCode[0] ^ pucOriginalCode[0] ;\r
+ correctionCode[1] = computedCode[1] ^ pucOriginalCode[1] ;\r
+ correctionCode[2] = computedCode[2] ^ pucOriginalCode[2] ;\r
+\r
+ TRACE_DEBUG( "Correction code = %02X %02X %02X\n\r", correctionCode[0], correctionCode[1], correctionCode[2] ) ;\r
+\r
+ // If all bytes are 0, there is no error\r
+ if ( (correctionCode[0] == 0) && (correctionCode[1] == 0) && (correctionCode[2] == 0) )\r
+ {\r
+ return 0 ;\r
+ }\r
+\r
+ /* If there is a single bit error, there are 11 bits set to 1 */\r
+ if ( CountBitsInCode256( correctionCode ) == 11 )\r
+ {\r
+ // Get byte and bit indexes\r
+ uint8_t byte ;\r
+ uint8_t bit ;\r
+ \r
+ byte = correctionCode[0] & 0x80;\r
+ byte |= (correctionCode[0] << 1) & 0x40;\r
+ byte |= (correctionCode[0] << 2) & 0x20;\r
+ byte |= (correctionCode[0] << 3) & 0x10;\r
+\r
+ byte |= (correctionCode[1] >> 4) & 0x08;\r
+ byte |= (correctionCode[1] >> 3) & 0x04;\r
+ byte |= (correctionCode[1] >> 2) & 0x02;\r
+ byte |= (correctionCode[1] >> 1) & 0x01;\r
+\r
+ bit = (correctionCode[2] >> 5) & 0x04;\r
+ bit |= (correctionCode[2] >> 4) & 0x02;\r
+ bit |= (correctionCode[2] >> 3) & 0x01;\r
+\r
+ /* Correct bit */\r
+ TRACE_DEBUG("Correcting byte #%d at bit %d\n\r", byte, bit ) ;\r
+ pucData[byte] ^= (1 << bit) ;\r
+\r
+ return Hamming_ERROR_SINGLEBIT ;\r
+ }\r
+\r
+ /* Check if ECC has been corrupted */\r
+ if ( CountBitsInCode256( correctionCode ) == 1 )\r
+ {\r
+ return Hamming_ERROR_ECC ;\r
+ }\r
+ /* Otherwise, this is a multi-bit error */\r
+ else\r
+ {\r
+ return Hamming_ERROR_MULTIPLEBITS ;\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Computes 3-bytes hamming codes for a data block whose size is multiple of\r
+ * 256 bytes. Each 256 bytes block gets its own code.\r
+ * \param data Data to compute code for.\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ */\r
+void Hamming_Compute256x( const uint8_t *pucData, uint32_t dwSize, uint8_t* puCode )\r
+{\r
+ TRACE_DEBUG("Hamming_Compute256x()\n\r");\r
+\r
+ while ( dwSize > 0 )\r
+ {\r
+ Compute256( pucData, puCode ) ;\r
+\r
+ pucData += 256;\r
+ puCode += 3;\r
+ dwSize -= 256;\r
+ }\r
+}\r
+\r
+/**\r
+ * Verifies 3-bytes hamming codes for a data block whose size is multiple of\r
+ * 256 bytes. Each 256-bytes block is verified with its own code.\r
+ *\r
+ * \return 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either Hamming_ERROR_ECC\r
+ * or Hamming_ERROR_MULTIPLEBITS.\r
+ *\r
+ * \param data Data buffer to verify.\r
+ * \param size Size of the data in bytes.\r
+ * \param code Original codes.\r
+ */\r
+uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode )\r
+{\r
+ uint8_t error ;\r
+ uint8_t result = 0 ;\r
+\r
+ TRACE_DEBUG( "Hamming_Verify256x()\n\r" ) ;\r
+\r
+ while ( dwSize > 0 )\r
+ {\r
+ error = Verify256( pucData, pucCode ) ;\r
+\r
+ if ( error == Hamming_ERROR_SINGLEBIT )\r
+ {\r
+ result = Hamming_ERROR_SINGLEBIT ;\r
+ }\r
+ else\r
+ {\r
+ if ( error )\r
+ {\r
+ return error ;\r
+ }\r
+ }\r
+\r
+ pucData += 256;\r
+ pucCode += 3;\r
+ dwSize -= 256;\r
+ }\r
+\r
+ return result ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of ILI9488 driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "board.h"\r
+\r
+#include <string.h>\r
+#include <stdio.h>\r
+\r
+#ifdef BOARD_LCD_ILI9488\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define ILI9488 SPI0\r
+#define ILI9488_ID ID_SPI0\r
+\r
+/** Pio pins to configure. */\r
+static const Pin ILI9488_Reset[] = LCD_PIN_RESET;\r
+\r
+static const Pin ILI9488_Pwm[] = BOARD_LCD_BACKLIGHT_PIN;\r
+\r
+/** Pins to configure for the application. */\r
+static const Pin spi_pins[] = BOARD_LCD_PINS;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+static void ILI9488_InitInterface(void)\r
+{\r
+\r
+ PIO_Configure(ILI9488_Reset, PIO_LISTSIZE(ILI9488_Reset)); \r
+ PIO_Configure(spi_pins, PIO_LISTSIZE(spi_pins));\r
+\r
+\r
+ PIO_Configure(ILI9488_Pwm, PIO_LISTSIZE(ILI9488_Pwm));\r
+ /* Enable PWM peripheral clock */\r
+ PMC_EnablePeripheral(ID_PWM0);\r
+\r
+ /* Set clock A and clock B */\r
+ // set for 14.11 KHz for CABC control\r
+ // mode = PWM_CLK_PREB(0x0A) | (PWM_CLK_DIVB(110)) | \r
+ // PWM_CLK_PREA(0x0A) | (PWM_CLK_DIVA(110));\r
+ PWMC_ConfigureClocks(PWM0, 14200, 0, BOARD_MCK);\r
+\r
+ /* Configure PWM channel 1 for LED0 */\r
+ PWMC_DisableChannel(PWM0, CHANNEL_PWM_LCD);\r
+\r
+ PWMC_ConfigureChannel(PWM0, CHANNEL_PWM_LCD, PWM_CMR_CPRE_CLKA,0,PWM_CMR_CPOL);\r
+ PWMC_SetPeriod(PWM0, CHANNEL_PWM_LCD, 16);\r
+ PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, 8);\r
+ PWMC_EnableChannel(PWM0, CHANNEL_PWM_LCD);\r
+\r
+ SPI_Configure(ILI9488, ILI9488_ID, (SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS( ILI9488_cs )));\r
+ SPI_ConfigureNPCS( ILI9488, ILI9488_cs, \r
+ SPI_CSR_CPOL | SPI_CSR_BITS_9_BIT | \r
+ SPI_DLYBS(100, BOARD_MCK) | SPI_DLYBCT(100, BOARD_MCK) |\r
+ SPI_SCBR( 35000000, BOARD_MCK) ) ; \r
+\r
+ SPI_Enable(ILI9488);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Send Command to ILI9488.\r
+ *\r
+ * \param reg Command Register address.\r
+ *\r
+ */\r
+static void ILI9488_SendCmd( uint8_t reg )\r
+{ \r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_CMD(reg)); \r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Write Parameter to ILI9488 Register.\r
+ *\r
+ * \param data Data to be written.\r
+ */\r
+static void ILI9488_WriteReg( uint8_t data )\r
+{\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data));\r
+}\r
+\r
+/**\r
+ * \brief Write 16 bit Parameter to ILI9488 Register.\r
+ *\r
+ * \param data Data to be written.\r
+ */\r
+static void ILI9488_WriteReg16( uint16_t data )\r
+{\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(((data & 0xFF00) >> 0x08)));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM((data & 0xFF)));\r
+}\r
+\r
+/**\r
+ * \brief Write 24 bit Parameter to ILI9488 Register.\r
+ *\r
+ * \param data Data to be written.\r
+ */\r
+static void ILI9488_WriteReg24( uint32_t data )\r
+{\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(((data & 0xFF0000) >> 0x10)));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(((data & 0xFF00) >> 0x08)));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM((data & 0xFF)));\r
+}\r
+\r
+/**\r
+ * \brief Write 32 bit Parameter to ILI9488 Register.\r
+ *\r
+ * \param data Data to be written.\r
+ */\r
+static void ILI9488_WriteReg32( uint32_t data )\r
+{\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM((data >> 0x18) & 0xFF));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(((data >> 0x10) & 0x00FF)));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(((data >> 0x08) & 0x0000FF)));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM((data & 0x000000FF)));\r
+}\r
+\r
+/**\r
+ * \brief Read data from ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Readed data.\r
+ */\r
+static uint8_t ILI9488_ReadReg( uint8_t reg)\r
+{\r
+ uint8_t value;\r
+\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_CMD(reg));\r
+ while(SPI_IsFinished(ILI9488) !=1);\r
+ SPI_Read(ILI9488);\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(0xFF));\r
+ while(SPI_IsFinished(ILI9488) !=1);\r
+ value = (uint8_t)SPI_Read(ILI9488);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(0);\r
+\r
+ return value;\r
+\r
+} \r
+/**\r
+ * \brief Read data from ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Readed data.\r
+ */\r
+static uint16_t ILI9488_ReadReg16( uint8_t reg)\r
+{\r
+ uint16_t value;\r
+ uint8_t SPI_CNT = 0x81;\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value = (ILI9488_ReadReg(reg) << 0x08);\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value |= ILI9488_ReadReg(reg);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(0);\r
+\r
+ return value;\r
+\r
+}\r
+\r
+/**\r
+ * \brief Read data from ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Readed data.\r
+ */\r
+static uint32_t ILI9488_ReadReg24( uint8_t reg)\r
+{\r
+ uint32_t value=0;\r
+ uint8_t SPI_CNT = 0x81;\r
+\r
+ //Set ILI9488 count to 0\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT);\r
+\r
+ // Send Command\r
+ value = (ILI9488_ReadReg(reg) << 0x10);\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+\r
+ value |= (ILI9488_ReadReg(reg) << 0x08);\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value |= ILI9488_ReadReg(reg);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(0);\r
+\r
+\r
+ return value;\r
+\r
+\r
+}\r
+\r
+/**\r
+ * \brief Read data from ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Readed data.\r
+ */\r
+static uint32_t ILI9488_ReadReg32( uint8_t reg)\r
+{\r
+ uint32_t value;\r
+ uint8_t SPI_CNT = 0x81;\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT);\r
+ value = ILI9488_ReadReg(reg) ;\r
+ value <<= 24;\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value |= (ILI9488_ReadReg(reg) << 16);\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value |= (ILI9488_ReadReg(reg) << 8);\r
+\r
+ SPI_CNT++;\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(SPI_CNT); \r
+ value |= ILI9488_ReadReg(reg);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SPI_READ_SETTINGS);\r
+ ILI9488_WriteReg(0);\r
+\r
+ return value;\r
+}\r
+\r
+static void ILI9488_NOP(void)\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_NOP);\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * \brief Write data to ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ * \param data Data to be written.\r
+ */\r
+void ILI9488_WriteSingle( LcdColor_t data )\r
+{\r
+\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+ ILI9488_WriteReg24(data);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Prpare to write data to ILI9488 Register.\r
+ *\r
+ */\r
+void ILI9488_WriteRAM_Prepare(void)\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+}\r
+\r
+/**\r
+ * \brief Prpare to write data to ILI9488 Register.\r
+ *\r
+ */\r
+void ILI9488_ReadRAM_Prepare(void)\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_READ);\r
+}\r
+\r
+/**\r
+ * \brief Write data to ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ * \param data Data to be written.\r
+ */\r
+void ILI9488_WriteRAM( LcdColor_t data )\r
+{ \r
+ ILI9488_WriteReg24(data); \r
+}\r
+\r
+\r
+/**\r
+ * \brief Write data to ILI9488 Register.\r
+ *\r
+ * \param reg Register address.\r
+ * \param data Data to be written.\r
+ */\r
+void ILI9488_WriteRAMBuffer( const LcdColor_t *pBuf, uint32_t size)\r
+{\r
+ uint32_t addr ;\r
+\r
+\r
+ for ( addr = 0 ; addr < size ; addr++ )\r
+ {\r
+ ILI9488_WriteRAM(pBuf[addr]);\r
+ }\r
+}\r
+\r
+void ILI9488_SetCursor(uint16_t x, uint16_t y)\r
+{\r
+ /* Set Horizontal Address Start Position */\r
+ ILI9488_SendCmd(ILI9488_CMD_COLUMN_ADDRESS_SET); \r
+ ILI9488_WriteReg16(x);\r
+ ILI9488_WriteReg16(x+1);\r
+ ILI9488_NOP();\r
+\r
+\r
+ /* Set Horizontal Address End Position */\r
+ ILI9488_SendCmd(ILI9488_CMD_PAGE_ADDRESS_SET);\r
+ ILI9488_WriteReg16(y);\r
+ ILI9488_WriteReg16(y+1);\r
+ ILI9488_NOP();\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Initialize the ILI9488 controller.\r
+ */\r
+extern uint32_t ILI9488_Initialize( void )\r
+{\r
+ uint32_t chipid;\r
+\r
+ ILI9488_InitInterface();\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SOFTWARE_RESET); \r
+ Wait(200);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_SLEEP_OUT);\r
+ Wait(200);\r
+\r
+ // make it tRGB and reverse the column order\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_ACCESS_CONTROL);\r
+ ILI9488_WriteReg(0x48);\r
+ Wait(100);\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_CABC_CONTROL_9); // set PWm to 14.11 KHz\r
+ ILI9488_WriteReg(0x04);\r
+\r
+ // ILI9488_SendCmd(ILI9488_CMD_COLMOD_PIXEL_FORMAT_SET); // set 16bit/pixel\r
+ // ILI9488_WriteReg(0x05);\r
+\r
+ /* Check ILI9488 chipid */\r
+ chipid = ILI9488_ReadReg24(ILI9488_CMD_READ_ID4); /* Driver Code Read */\r
+ if ( chipid != ILI9488_DEVICE_CODE )\r
+ {\r
+ printf( "Read ILI9488 chip ID (0x%04x) error, skip initialization.\r\n", chipid ) ;\r
+ assert(0);\r
+ return 1 ;\r
+ }\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_NORMAL_DISP_MODE_ON);\r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_ON);\r
+\r
+ return 0 ;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * \brief Turn on the ILI9488.\r
+ */\r
+extern void ILI9488_On( void )\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_PIXEL_OFF);\r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_ON);\r
+ ILI9488_SendCmd(ILI9488_CMD_NORMAL_DISP_MODE_ON);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Turn off the ILI9488.\r
+ */\r
+extern void ILI9488_Off( void )\r
+{ \r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_OFF);\r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_OFF);\r
+}\r
+\r
+/**\r
+ * \brief Power down the ILI9488.\r
+ */\r
+extern void ILI9488_PowerDown( void )\r
+{\r
+\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * \brief Set a partial display window\r
+ *\r
+ * Initialize a partial window on ILI9488\r
+ * \param Start Starting address of window.\r
+ * \param End End address of window.\r
+ * \return 0 for successfull operation.\r
+ */\r
+extern void ILI9488_SetPartialWindow( uint16_t Start, uint16_t End)\r
+{\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_POWER_CONTROL_PARTIAL_5);\r
+ ILI9488_WriteReg(0x44 ) ;\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_PARTIAL_AREA);\r
+ ILI9488_WriteReg16(Start ) ;\r
+ ILI9488_WriteReg16(End) ;\r
+\r
+ ILI9488_SendCmd(ILI9488_CMD_PARTIAL_MODE_ON);\r
+ Wait(10);\r
+\r
+\r
+}\r
+\r
+\r
+\r
+extern void ILI9488_SetWindow( uint16_t dwX, uint16_t dwY, uint16_t dwWidth, uint16_t dwHeight )\r
+{\r
+ uint16_t ColStart, ColEnd, RowStart, RowEnd;\r
+\r
+ ColStart = dwX ;\r
+ ColEnd = dwWidth;\r
+\r
+ RowStart = dwY ;\r
+ RowEnd = dwHeight;\r
+\r
+ if ( ( ColEnd > (ILI9488_LCD_WIDTH)) || ( RowEnd > (ILI9488_LCD_HEIGHT))) \r
+ {\r
+ printf("\n\rWindow too large\n\r");\r
+ assert(1);\r
+ }\r
+\r
+ if ( ( ColEnd < ColStart) || ( RowEnd < RowStart) )\r
+ {\r
+ printf("\n\rWindow's hight or width is not large enough\n\r");\r
+ assert(1); \r
+ }\r
+ /* Set Horizontal Address Start Position */\r
+ ILI9488_SendCmd(ILI9488_CMD_COLUMN_ADDRESS_SET); \r
+ ILI9488_WriteReg16(ColStart);\r
+ ILI9488_WriteReg16(ColEnd);\r
+ ILI9488_NOP();\r
+\r
+\r
+ /* Set Horizontal Address End Position */\r
+ ILI9488_SendCmd(ILI9488_CMD_PAGE_ADDRESS_SET);\r
+ ILI9488_WriteReg16(RowStart);\r
+ ILI9488_WriteReg16(RowEnd);\r
+ ILI9488_NOP();\r
+\r
+}\r
+\r
+extern void ILI9488_SetDisplayLandscape( uint8_t dwRGB, uint8_t LandscaprMode )\r
+{\r
+ uint8_t Value;\r
+ if(LandscaprMode)\r
+ {\r
+ if(dwRGB)\r
+ {\r
+ Value = 0xA8;\r
+ }\r
+ else\r
+ {\r
+ Value = 0xA0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(dwRGB)\r
+ {\r
+ Value = 0xE8;\r
+ }\r
+ else\r
+ {\r
+ Value = 0xE0;\r
+ }\r
+ }\r
+ // make it tRGB and reverse the column order\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_ACCESS_CONTROL);\r
+ ILI9488_WriteReg(Value);\r
+ Wait(50);\r
+\r
+ ILI9488_SetWindow( 0, 0, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT ) ;\r
+}\r
+\r
+extern void ILI9488_SetDisplayPortrait( uint8_t dwRGB )\r
+{\r
+ uint8_t Value;\r
+ if(dwRGB)\r
+ {\r
+ Value = 0x48;\r
+ }\r
+ else\r
+ {\r
+ Value = 0x40;\r
+ }\r
+ // make it tRGB and reverse the column order\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_ACCESS_CONTROL);\r
+ ILI9488_WriteReg(Value);\r
+ Wait(50);\r
+\r
+ ILI9488_SetWindow( 0, 0, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT) ;\r
+}\r
+\r
+\r
+extern void ILI9488_SetVerticalScrollWindow( uint16_t dwStartAdd, uint16_t dwHeight )\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_VERT_SCROLL_DEFINITION);\r
+ ILI9488_WriteReg16(dwStartAdd-1);\r
+ ILI9488_WriteReg16(dwStartAdd);\r
+ ILI9488_WriteReg16((dwStartAdd + dwHeight + 1));\r
+}\r
+\r
+\r
+extern void ILI9488_VerticalScroll( uint16_t wY )\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_VERT_SCROLL_START_ADDRESS);\r
+ ILI9488_WriteReg16(wY);\r
+}\r
+\r
+\r
+\r
+extern void ILI9488_ExitScrollMode(void )\r
+{\r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_OFF);\r
+ ILI9488_SendCmd(ILI9488_CMD_NORMAL_DISP_MODE_ON);\r
+ ILI9488_SendCmd(ILI9488_CMD_DISPLAY_ON);\r
+}\r
+\r
+\r
+extern void ILI9488_TestPattern(void)\r
+{\r
+ uint32_t i, data;\r
+\r
+ ILI9488_SetWindow( 0, 0, 319, 479 ) ; \r
+\r
+ data = COLOR_WHITE;\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+ for(i = 0; i< (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++)\r
+ {\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 16));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 8));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data & 0xFF));\r
+ }\r
+\r
+ ILI9488_SetWindow( 50, 50, 300, 300 ) ; \r
+ data = COLOR_BLUE;\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+ for(i = 0; i< (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++)\r
+ {\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 16));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 8));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data & 0xFF));\r
+ }\r
+\r
+ ILI9488_SetWindow( 150, 150, 300, 300 ) ; \r
+ data = COLOR_GREEN;\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+ for(i = 0; i< (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++)\r
+ {\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 16));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 8));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data & 0xFF));\r
+ }\r
+\r
+ ILI9488_SetWindow(200, 200, 300, 300 ) ; \r
+ data = COLOR_RED;\r
+ ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE);\r
+ for(i = 0; i< (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++)\r
+ {\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 16));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data >> 8));\r
+ SPI_Write(ILI9488, ILI9488_cs, ILI9488_PARAM(data & 0xFF));\r
+ }\r
+\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of draw function on LCD, Include draw text, image\r
+ * and basic shapes (line, rectangle, circle).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+\r
+static LcdColor_t gLcdPixelCache[LCD_DATA_CACHE_SIZE];\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Convert 24 bit RGB color into 5-6-5 rgb color space.\r
+ *\r
+ * Initialize the LcdColor_t cache with the color pattern.\r
+ * \param x 24-bits RGB color.\r
+ * \return 0 for successfull operation.\r
+ */\r
+static uint32_t LCD_SetColor( uint32_t dwRgb24Bits )\r
+{\r
+ uint32_t i ;\r
+\r
+ /* Fill the cache with selected color */\r
+ for ( i = 0 ; i < LCD_DATA_CACHE_SIZE ; ++i )\r
+ {\r
+ gLcdPixelCache[i] = dwRgb24Bits ;\r
+ }\r
+\r
+ return 0;\r
+} \r
+\r
+/**\r
+ * \brief Check Box coordinates. Return upper left and bottom right coordinates.\r
+ *\r
+ * \param pX1 X-coordinate of upper-left corner on LCD.\r
+ * \param pY1 Y-coordinate of upper-left corner on LCD.\r
+ * \param pX2 X-coordinate of lower-right corner on LCD.\r
+ * \param pY2 Y-coordinate of lower-right corner on LCD.\r
+ */\r
+static void CheckBoxCoordinates( uint32_t *pX1, uint32_t *pY1, uint32_t *pX2, uint32_t *pY2 )\r
+{\r
+ uint32_t dw;\r
+\r
+ if ( *pX1 >= BOARD_LCD_WIDTH )\r
+ {\r
+ *pX1 = BOARD_LCD_WIDTH-1 ;\r
+ }\r
+ if ( *pX2 >= BOARD_LCD_WIDTH )\r
+ {\r
+ *pX2 = BOARD_LCD_WIDTH-1 ;\r
+ }\r
+ if ( *pY1 >= BOARD_LCD_HEIGHT )\r
+ {\r
+ *pY1 = BOARD_LCD_HEIGHT-1 ;\r
+ }\r
+ if ( *pY2 >= BOARD_LCD_HEIGHT )\r
+ {\r
+ *pY2 = BOARD_LCD_HEIGHT-1 ;\r
+ }\r
+ if (*pX1 > *pX2)\r
+ {\r
+ dw = *pX1;\r
+ *pX1 = *pX2;\r
+ *pX2 = dw;\r
+ }\r
+ if (*pY1 > *pY2)\r
+ {\r
+ dw = *pY1;\r
+ *pY1 = *pY2;\r
+ *pY2 = dw;\r
+ }\r
+}\r
+/**\r
+ * \brief Fills the given LCD buffer with a particular color.\r
+ *\r
+ * \param color Fill color.\r
+ */\r
+void LCDD_Fill( uint32_t dwColor )\r
+{\r
+ uint32_t dw ;\r
+\r
+ // LCD_SetCursor( 0, 0 ) ;\r
+ ILI9488_WriteRAM_Prepare() ;\r
+\r
+ for ( dw = BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT; dw > 0; dw-- )\r
+ {\r
+ ILI9488_WriteRAM( dwColor ) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draw a pixel on LCD of given color.\r
+ *\r
+ * \param x X-coordinate of pixel.\r
+ * \param y Y-coordinate of pixel.\r
+ * \param color Pixel color.\r
+ */\r
+extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t color )\r
+{\r
+ ILI9488_SetCursor( x, y ) ;\r
+ ILI9488_WriteRAM_Prepare() ;\r
+ ILI9488_WriteRAM( color ) ;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Read a pixel from LCD.\r
+ *\r
+ * \param x X-coordinate of pixel.\r
+ * \param y Y-coordinate of pixel.\r
+ *\r
+ * \return color Readed pixel color.\r
+ */\r
+extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y )\r
+{\r
+ uint32_t color;\r
+\r
+ ILI9488_SetCursor(x, y);\r
+ ILI9488_ReadRAM_Prepare();\r
+ color = ILI9488_ReadRAM();\r
+\r
+ return color;\r
+}\r
+\r
+/*\r
+ * \brief Draw a line on LCD, horizontal and vertical line are supported.\r
+ *\r
+ * \param x X-coordinate of line start.\r
+ * \param y Y-coordinate of line start.\r
+ * \param length line length.\r
+ * \param direction line direction: 0 - horizontal, 1 - vertical.\r
+ * \param color Pixel color.\r
+ */\r
+extern void LCDD_DrawLine( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 , uint32_t color )\r
+{\r
+ if (( dwY1 == dwY2 ) || (dwX1 == dwX2))\r
+ {\r
+ LCDD_DrawRectangleWithFill( dwX1, dwY1, dwX2, dwY2, color );\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawLineBresenham( dwX1, dwY1, dwX2, dwY2 , color) ;\r
+ }\r
+\r
+}\r
+\r
+\r
+\r
+/*\r
+ * \brief Draw a line on LCD, which is not horizontal or vertical.\r
+ *\r
+ * \param x X-coordinate of line start.\r
+ * \param y Y-coordinate of line start.\r
+ * \param length line length.\r
+ * \param direction line direction: 0 - horizontal, 1 - vertical.\r
+ * \param color LcdColor_t color.\r
+ */\r
+extern uint32_t LCDD_DrawLineBresenham( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 , uint32_t color)\r
+{\r
+ int dx, dy ;\r
+ int i ;\r
+ int xinc, yinc, cumul ;\r
+ int x, y ;\r
+\r
+ x = dwX1 ;\r
+ y = dwY1 ;\r
+ dx = dwX2 - dwX1 ;\r
+ dy = dwY2 - dwY1 ;\r
+\r
+ xinc = ( dx > 0 ) ? 1 : -1 ;\r
+ yinc = ( dy > 0 ) ? 1 : -1 ;\r
+ dx = ( dx > 0 ) ? dx : -dx ;\r
+ dy = ( dy > 0 ) ? dy : -dy ;\r
+\r
+ LCDD_DrawPixel(x , y , color);\r
+\r
+ if ( dx > dy )\r
+ {\r
+ cumul = dx / 2 ;\r
+ for ( i = 1 ; i <= dx ; i++ )\r
+ {\r
+ x += xinc ;\r
+ cumul += dy ;\r
+\r
+ if ( cumul >= dx )\r
+ {\r
+ cumul -= dx ;\r
+ y += yinc ;\r
+ }\r
+ LCDD_DrawPixel(x , y , color);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ cumul = dy / 2 ;\r
+ for ( i = 1 ; i <= dy ; i++ )\r
+ {\r
+ y += yinc ;\r
+ cumul += dx ;\r
+\r
+ if ( cumul >= dy )\r
+ {\r
+ cumul -= dy ;\r
+ x += xinc ;\r
+ }\r
+\r
+ LCDD_DrawPixel(x , y , color);\r
+ }\r
+ }\r
+\r
+ return 0 ;\r
+}\r
+\r
+/*\r
+ * \brief Draws a rectangle on LCD, at the given coordinates.\r
+ *\r
+ * \param x X-coordinate of upper-left rectangle corner.\r
+ * \param y Y-coordinate of upper-left rectangle corner.\r
+ * \param width Rectangle width in pixels.\r
+ * \param height Rectangle height in pixels.\r
+ * \param color Rectangle color.\r
+ */\r
+extern void LCDD_DrawRectangle( uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t color )\r
+{\r
+\r
+ LCDD_DrawRectangleWithFill(x, y, width, y, color);\r
+ LCDD_DrawRectangleWithFill(x, height, width, height, color);\r
+\r
+ LCDD_DrawRectangleWithFill(x, y, x, height, color);\r
+ LCDD_DrawRectangleWithFill(width, y, width, height, color);\r
+}\r
+\r
+/*\r
+ * \brief Draws a rectangle with fill inside on LCD, at the given coordinates.\r
+ *\r
+ * \param x X-coordinate of upper-left rectangle corner.\r
+ * \param y Y-coordinate of upper-left rectangle corner.\r
+ * \param width Rectangle width in pixels.\r
+ * \param height Rectangle height in pixels.\r
+ * \param color Rectangle color.\r
+ */\r
+extern void LCDD_DrawRectangleWithFill( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor )\r
+{\r
+ uint32_t size, blocks;\r
+\r
+ CheckBoxCoordinates(&dwX, &dwY, &dwWidth, &dwHeight);\r
+ LCD_SetColor(dwColor);\r
+ ILI9488_SetWindow( dwX, dwY, dwWidth, dwHeight ) ;\r
+\r
+ size = (dwWidth - dwX + 1) * (dwHeight - dwY + 1);\r
+\r
+ /* Send pixels blocks => one LCD IT / block */\r
+ blocks = size / LCD_DATA_CACHE_SIZE;\r
+\r
+ ILI9488_WriteRAM_Prepare() ;\r
+\r
+ while (blocks--)\r
+ {\r
+ ILI9488_WriteRAMBuffer(gLcdPixelCache, LCD_DATA_CACHE_SIZE);\r
+ }\r
+ /* Send remaining pixels */\r
+ ILI9488_WriteRAMBuffer(gLcdPixelCache, size % LCD_DATA_CACHE_SIZE);\r
+ ILI9488_SetWindow( 0, 0, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT ) ;\r
+ // LCD_SetCursor( 0, 0 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Draws a circle on LCD, at the given coordinates.\r
+ *\r
+ * \param x X-coordinate of circle center.\r
+ * \param y Y-coordinate of circle center.\r
+ * \param r circle radius.\r
+ * \param color circle color.\r
+ */\r
+extern uint32_t LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color )\r
+{\r
+ signed int d; /* Decision Variable */\r
+ uint32_t curX; /* Current X Value */\r
+ uint32_t curY; /* Current Y Value */\r
+\r
+ d = 3 - (r << 1);\r
+ curX = 0;\r
+ curY = r;\r
+\r
+ while (curX <= curY)\r
+ {\r
+ LCDD_DrawPixel(x + curX, y + curY, color);\r
+ LCDD_DrawPixel(x + curX, y - curY, color);\r
+ LCDD_DrawPixel(x - curX, y + curY, color);\r
+ LCDD_DrawPixel(x - curX, y - curY, color);\r
+ LCDD_DrawPixel(x + curY, y + curX, color);\r
+ LCDD_DrawPixel(x + curY, y - curX, color);\r
+ LCDD_DrawPixel(x - curY, y + curX, color);\r
+ LCDD_DrawPixel(x - curY, y - curX, color);\r
+\r
+ if (d < 0) {\r
+ d += (curX << 2) + 6;\r
+ }\r
+ else {\r
+ d += ((curX - curY) << 2) + 10;\r
+ curY--;\r
+ }\r
+ curX++;\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+extern uint32_t LCD_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwRadius, uint32_t color)\r
+{\r
+ signed int d ; /* Decision Variable */\r
+ uint32_t dwCurX ; /* Current X Value */\r
+ uint32_t dwCurY ; /* Current Y Value */\r
+ uint32_t dwXmin, dwYmin;\r
+\r
+ if (dwRadius == 0)\r
+ {\r
+ return 0;\r
+ }\r
+ d = 3 - (dwRadius << 1) ;\r
+ dwCurX = 0 ;\r
+ dwCurY = dwRadius ;\r
+\r
+ while ( dwCurX <= dwCurY )\r
+ {\r
+ dwXmin = (dwCurX > dwX) ? 0 : dwX-dwCurX;\r
+ dwYmin = (dwCurY > dwY) ? 0 : dwY-dwCurY;\r
+ LCDD_DrawRectangleWithFill( dwXmin, dwYmin, dwX+dwCurX, dwYmin ,color) ;\r
+ LCDD_DrawRectangleWithFill( dwXmin, dwY+dwCurY, dwX+dwCurX, dwY+dwCurY, color ) ;\r
+ dwXmin = (dwCurY > dwX) ? 0 : dwX-dwCurY;\r
+ dwYmin = (dwCurX > dwY) ? 0 : dwY-dwCurX;\r
+ LCDD_DrawRectangleWithFill( dwXmin, dwYmin, dwX+dwCurY, dwYmin, color ) ;\r
+ LCDD_DrawRectangleWithFill( dwXmin, dwY+dwCurX, dwX+dwCurY, dwY+dwCurX, color ) ;\r
+\r
+ if ( d < 0 )\r
+ {\r
+ d += (dwCurX << 2) + 6 ;\r
+ }\r
+ else\r
+ {\r
+ d += ((dwCurX - dwCurY) << 2) + 10;\r
+ dwCurY-- ;\r
+ }\r
+\r
+ dwCurX++ ;\r
+ }\r
+\r
+ return 0 ;\r
+}\r
+/**\r
+ * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks\r
+ * will be honored.\r
+ *\r
+ * \param x X-coordinate of string top-left corner.\r
+ * \param y Y-coordinate of string top-left corner.\r
+ * \param pString String to display.\r
+ * \param color String color.\r
+ */\r
+extern void LCDD_DrawString( uint32_t x, uint32_t y, const uint8_t *pString, uint32_t color )\r
+{\r
+ uint32_t xorg = x ;\r
+\r
+ while ( *pString != 0 )\r
+ {\r
+ if ( *pString == '\n' )\r
+ {\r
+ y += gFont.height + 2 ;\r
+ x = xorg ;\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawChar( x, y, *pString, color ) ;\r
+ x += gFont.width + 2 ;\r
+ }\r
+\r
+ pString++ ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws a string inside a LCD buffer, at the given coordinates\r
+ * with given background color. Line breaks will be honored.\r
+ *\r
+ * \param x X-coordinate of string top-left corner.\r
+ * \param y Y-coordinate of string top-left corner.\r
+ * \param pString String to display.\r
+ * \param fontColor String color.\r
+ * \param bgColor Background color.\r
+ */\r
+extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor )\r
+{\r
+ unsigned xorg = x;\r
+\r
+ while ( *pString != 0 )\r
+ {\r
+ if ( *pString == '\n' )\r
+ {\r
+ y += gFont.height + 2 ;\r
+ x = xorg ;\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawCharWithBGColor( x, y, *pString, fontColor, bgColor ) ;\r
+ x += gFont.width + 2;\r
+ }\r
+\r
+ pString++;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Returns the width & height in pixels that a string will occupy on the screen\r
+ * if drawn using LCDD_DrawString.\r
+ *\r
+ * \param pString String.\r
+ * \param pWidth Pointer for storing the string width (optional).\r
+ * \param pHeight Pointer for storing the string height (optional).\r
+ *\r
+ * \return String width in pixels.\r
+ */\r
+extern void LCDD_GetStringSize( const uint8_t *pString, uint32_t *pWidth, uint32_t *pHeight )\r
+{\r
+ uint32_t width = 0;\r
+ uint32_t height = gFont.height;\r
+\r
+ while ( *pString != 0 )\r
+ {\r
+ if ( *pString == '\n' )\r
+ {\r
+ height += gFont.height + 2 ;\r
+ }\r
+ else\r
+ {\r
+ width += gFont.width + 2 ;\r
+ }\r
+\r
+ pString++ ;\r
+ }\r
+\r
+ if ( width > 0 )\r
+ {\r
+ width -= 2;\r
+ }\r
+\r
+ if ( pWidth != NULL )\r
+ {\r
+ *pWidth = width;\r
+ }\r
+\r
+ if ( pHeight != NULL )\r
+ {\r
+ *pHeight = height ;\r
+ }\r
+}\r
+\r
+/*\r
+ * \brief Draw a raw image at given position on LCD.\r
+ *\r
+ * \param x X-coordinate of image start.\r
+ * \param y Y-coordinate of image start.\r
+ * \param pImage Image buffer.\r
+ * \param width Image width.\r
+ * \param height Image height.\r
+ */\r
+extern void LCDD_DrawImage( uint32_t dwX, uint32_t dwY, const LcdColor_t *pImage, uint32_t dwWidth, uint32_t dwHeight )\r
+{\r
+ uint32_t size;\r
+\r
+\r
+ /* Determine the refresh window area */\r
+ /* Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) */\r
+ CheckBoxCoordinates(&dwX, &dwY, &dwWidth, &dwHeight);\r
+ ILI9488_SetWindow(dwX, dwY, dwWidth, dwHeight);\r
+\r
+ /* Prepare to write in GRAM */\r
+ ILI9488_WriteRAM_Prepare();\r
+\r
+ size = (dwWidth - dwX + 1) * (dwHeight - dwY + 1);\r
+\r
+ ILI9488_WriteRAMBuffer(pImage, size);\r
+\r
+ ILI9488_SetWindow( 0, 0, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT ) ;\r
+}\r
+\r
+/*\r
+ * \brief Draw a raw image at given position on LCD.\r
+ *\r
+ * \param dwX X-coordinate of image start.\r
+ * \param dwY Y-coordinate of image start.\r
+ * \param pGIMPImage Image data.\r
+ */\r
+void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage )\r
+{\r
+ uint32_t dw ;\r
+ register uint32_t dwLength ;\r
+ uint8_t* pucData ;\r
+ LcdColor_t *pData;\r
+\r
+ // Draw raw RGB bitmap\r
+ // CheckBoxCoordinates(&dwX, &dwY, &dwWidth, &dwHeight);\r
+ ILI9488_SetWindow( dwX, dwY, pGIMPImage->dwWidth, pGIMPImage->dwHeight ) ;\r
+ // LCD_SetCursor( dwX, dwY ) ;\r
+\r
+ ILI9488_WriteRAM_Prepare() ;\r
+\r
+ dwLength = pGIMPImage->dwWidth*pGIMPImage->dwHeight ;\r
+ pucData = pGIMPImage->pucPixel_data ;\r
+ for ( dw=0; dw < dwLength; dw++ )\r
+ {\r
+ *pData = ((*pucData++)<<16) ;\r
+ *pData |= ((*pucData++)<<8) ;\r
+ *pData |= (*pucData++) ;\r
+ ILI9488_WriteRAM(*pData);\r
+ }\r
+\r
+ ILI9488_SetWindow( 0, 0, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT ) ;\r
+}\r
+\r
+/*\r
+ * \brief Clear a window with an color.\r
+ *\r
+ * \param dwX X-coordinate of the window.\r
+ * \param dwY Y-coordinate of the window.\r
+ * \param dwWidth window width.\r
+ * \param dwHeight window height.\r
+ * \param dwColor background color\r
+ */\r
+extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor )\r
+{\r
+ uint32_t dw ;\r
+\r
+\r
+ ILI9488_SetWindow( dwX, dwY, dwWidth, dwHeight ) ;\r
+ ILI9488_WriteRAM_Prepare() ;\r
+\r
+ for ( dw = dwWidth * dwHeight; dw > 0; dw-- )\r
+ {\r
+ ILI9488_WriteRAM( dwColor ) ;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of draw font on LCD.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Global variable describing the font being instancied. */\r
+const Font gFont = {10, 14};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Draws an ASCII character on LCD.\r
+ *\r
+ * \param x X-coordinate of character upper-left corner.\r
+ * \param y Y-coordinate of character upper-left corner.\r
+ * \param c Character to output.\r
+ * \param color Character color.\r
+ */\r
+extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color )\r
+{\r
+ uint32_t row, col ;\r
+\r
+ assert( (c >= 0x20) && (c <= 0x7F) ) ;\r
+\r
+ for ( col = 0 ; col < 10 ; col++ )\r
+ {\r
+ for ( row = 0 ; row < 8 ; row++ )\r
+ {\r
+ if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row, color ) ;\r
+ }\r
+ }\r
+\r
+ for (row = 0; row < 6; row++ )\r
+ {\r
+ if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1)\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row+8, color ) ;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws a string inside a LCD buffer, at the given coordinates.\r
+ * Line breaks will be honored.\r
+ *\r
+ * \param dwX X-coordinate of string top-left corner.\r
+ * \param dwY Y-coordinate of string top-left corner.\r
+ * \param pString String to display.\r
+ */\r
+extern void LCD_DrawString( uint32_t dwX, uint32_t dwY, const uint8_t *pString, uint32_t color )\r
+{\r
+ uint32_t dwXorg = dwX ;\r
+\r
+ while ( *pString != 0 )\r
+ {\r
+ if ( *pString == '\n' )\r
+ {\r
+ dwY += gFont.height + 2 ;\r
+ dwX = dwXorg ;\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawChar( dwX, dwY, *pString, color ) ;\r
+ dwX += gFont.width + 2 ;\r
+ }\r
+\r
+ pString++ ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws an ASCII character on LCD with given background color.\r
+ *\r
+ * \param x X-coordinate of character upper-left corner.\r
+ * \param y Y-coordinate of character upper-left corner.\r
+ * \param c Character to output.\r
+ * \param fontColor Character color.\r
+ * \param bgColor Background color.\r
+ */\r
+extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor )\r
+{\r
+ uint32_t row, col ;\r
+\r
+ assert( (c >= 0x20) && (c <= 0x7F) ) ;\r
+\r
+ for (col = 0; col < 10; col++)\r
+ {\r
+ for (row = 0 ; row < 8 ; row++)\r
+ {\r
+ if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row, fontColor ) ;\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row, bgColor ) ;\r
+ }\r
+ }\r
+\r
+ for ( row = 0 ; row < 6 ; row++ )\r
+ {\r
+ if ( (pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1 )\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row+8, fontColor ) ;\r
+ }\r
+ else\r
+ {\r
+ LCDD_DrawPixel( x+col, y+row+8, bgColor ) ;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /**\r
+ * \file\r
+ *\r
+ * Font 10x14 table definition.\r
+ *\r
+ */\r
+\r
+#include "board.h"\r
+\r
+/** Char set of font 10x14 */\r
+const uint8_t pCharset10x14[] = {\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,\r
+ 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,\r
+ 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,\r
+ 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,\r
+ 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,\r
+ 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,\r
+ 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,\r
+ 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,\r
+ 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,\r
+ 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,\r
+ 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,\r
+ 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,\r
+ 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,\r
+ 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,\r
+ 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,\r
+ 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,\r
+ 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,\r
+ 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,\r
+ 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,\r
+ 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,\r
+ 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,\r
+ 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,\r
+ 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,\r
+ 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,\r
+ 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,\r
+ 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,\r
+ 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,\r
+ 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,\r
+ 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,\r
+ 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,\r
+ 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,\r
+ 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,\r
+ 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,\r
+ 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,\r
+ 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,\r
+ 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,\r
+ 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,\r
+ 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,\r
+ 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,\r
+ 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,\r
+ 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,\r
+ 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,\r
+ 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,\r
+ 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,\r
+ 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,\r
+ 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,\r
+ 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,\r
+ 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,\r
+ 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,\r
+ 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,\r
+ 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,\r
+ 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,\r
+ 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC\r
+} ;\r
+\r
+const unsigned char FONT6x8[97][8] = {\r
+ {0x06,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00}, // !\r
+ {0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00}, // #\r
+ {0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00}, // $\r
+ {0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00}, // %\r
+ {0x40,0xA0,0xA0,0x40,0xA8,0x90,0x68,0x00}, // &\r
+ {0x30,0x30,0x20,0x40,0x00,0x00,0x00,0x00}, // '\r
+ {0x10,0x20,0x40,0x40,0x40,0x20,0x10,0x00}, // (\r
+ {0x40,0x20,0x10,0x10,0x10,0x20,0x40,0x00}, // )\r
+ {0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00}, // *\r
+ {0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x30,0x30,0x20,0x40}, // ,\r
+ {0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00}, // .\r
+ {0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00}, // / (forward slash)\r
+ {0x70,0x88,0x88,0xA8,0x88,0x88,0x70,0x00}, // 0 0x30\r
+ {0x20,0x60,0x20,0x20,0x20,0x20,0x70,0x00}, // 1\r
+ {0x70,0x88,0x08,0x70,0x80,0x80,0xF8,0x00}, // 2\r
+ {0xF8,0x08,0x10,0x30,0x08,0x88,0x70,0x00}, // 3\r
+ {0x10,0x30,0x50,0x90,0xF8,0x10,0x10,0x00}, // 4\r
+ {0xF8,0x80,0xF0,0x08,0x08,0x88,0x70,0x00}, // 5\r
+ {0x38,0x40,0x80,0xF0,0x88,0x88,0x70,0x00}, // 6\r
+ {0xF8,0x08,0x08,0x10,0x20,0x40,0x80,0x00}, // 7\r
+ {0x70,0x88,0x88,0x70,0x88,0x88,0x70,0x00}, // 8\r
+ {0x70,0x88,0x88,0x78,0x08,0x10,0xE0,0x00}, // 9\r
+ {0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00}, // :\r
+ {0x00,0x00,0x20,0x00,0x20,0x20,0x40,0x00}, // ;\r
+ {0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x00}, // <\r
+ {0x00,0x00,0xF8,0x00,0xF8,0x00,0x00,0x00}, // =\r
+ {0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00}, // >\r
+ {0x70,0x88,0x08,0x30,0x20,0x00,0x20,0x00}, // ?\r
+ {0x70,0x88,0xA8,0xB8,0xB0,0x80,0x78,0x00}, // @ 0x40\r
+ {0x20,0x50,0x88,0x88,0xF8,0x88,0x88,0x00}, // A\r
+ {0xF0,0x88,0x88,0xF0,0x88,0x88,0xF0,0x00}, // B\r
+ {0x70,0x88,0x80,0x80,0x80,0x88,0x70,0x00}, // C\r
+ {0xF0,0x88,0x88,0x88,0x88,0x88,0xF0,0x00}, // D\r
+ {0xF8,0x80,0x80,0xF0,0x80,0x80,0xF8,0x00}, // E\r
+ {0xF8,0x80,0x80,0xF0,0x80,0x80,0x80,0x00}, // F\r
+ {0x78,0x88,0x80,0x80,0x98,0x88,0x78,0x00}, // G\r
+ {0x88,0x88,0x88,0xF8,0x88,0x88,0x88,0x00}, // H\r
+ {0x70,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // I\r
+ {0x38,0x10,0x10,0x10,0x10,0x90,0x60,0x00}, // J\r
+ {0x88,0x90,0xA0,0xC0,0xA0,0x90,0x88,0x00}, // K\r
+ {0x80,0x80,0x80,0x80,0x80,0x80,0xF8,0x00}, // L\r
+ {0x88,0xD8,0xA8,0xA8,0xA8,0x88,0x88,0x00}, // M\r
+ {0x88,0x88,0xC8,0xA8,0x98,0x88,0x88,0x00}, // N\r
+ {0x70,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // O\r
+ {0xF0,0x88,0x88,0xF0,0x80,0x80,0x80,0x00}, // P 0x50\r
+ {0x70,0x88,0x88,0x88,0xA8,0x90,0x68,0x00}, // Q\r
+ {0xF0,0x88,0x88,0xF0,0xA0,0x90,0x88,0x00}, // R\r
+ {0x70,0x88,0x80,0x70,0x08,0x88,0x70,0x00}, // S\r
+ {0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x00}, // T\r
+ {0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // U\r
+ {0x88,0x88,0x88,0x88,0x88,0x50,0x20,0x00}, // V\r
+ {0x88,0x88,0x88,0xA8,0xA8,0xA8,0x50,0x00}, // W\r
+ {0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00}, // X\r
+ {0x88,0x88,0x50,0x20,0x20,0x20,0x20,0x00}, // Y\r
+ {0xF8,0x08,0x10,0x70,0x40,0x80,0xF8,0x00}, // Z\r
+ {0x78,0x40,0x40,0x40,0x40,0x40,0x78,0x00}, // [\r
+ {0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00}, // \ (back slash)\r
+ {0x78,0x08,0x08,0x08,0x08,0x08,0x78,0x00}, // ]\r
+ {0x20,0x50,0x88,0x00,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00}, // _\r
+ {0x60,0x60,0x20,0x10,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x60,0x10,0x70,0x90,0x78,0x00}, // a\r
+ {0x80,0x80,0xB0,0xC8,0x88,0xC8,0xB0,0x00}, // b\r
+ {0x00,0x00,0x70,0x88,0x80,0x88,0x70,0x00}, // c\r
+ {0x08,0x08,0x68,0x98,0x88,0x98,0x68,0x00}, // d\r
+ {0x00,0x00,0x70,0x88,0xF8,0x80,0x70,0x00}, // e\r
+ {0x10,0x28,0x20,0x70,0x20,0x20,0x20,0x00}, // f\r
+ {0x00,0x00,0x70,0x98,0x98,0x68,0x08,0x70}, // g\r
+ {0x80,0x80,0xB0,0xC8,0x88,0x88,0x88,0x00}, // h\r
+ {0x20,0x00,0x60,0x20,0x20,0x20,0x70,0x00}, // i\r
+ {0x10,0x00,0x10,0x10,0x10,0x90,0x60,0x00}, // j\r
+ {0x80,0x80,0x90,0xA0,0xC0,0xA0,0x90,0x00}, // k\r
+ {0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // l\r
+ {0x00,0x00,0xD0,0xA8,0xA8,0xA8,0xA8,0x00}, // m\r
+ {0x00,0x00,0xB0,0xC8,0x88,0x88,0x88,0x00}, // n\r
+ {0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00}, // o\r
+ {0x00,0x00,0xB0,0xC8,0xC8,0xB0,0x80,0x80}, // p 0x70\r
+ {0x00,0x00,0x68,0x98,0x98,0x68,0x08,0x08}, // q\r
+ {0x00,0x00,0xB0,0xC8,0x80,0x80,0x80,0x00}, // r\r
+ {0x00,0x00,0x78,0x80,0x70,0x08,0xF0,0x00}, // s\r
+ {0x20,0x20,0xF8,0x20,0x20,0x28,0x10,0x00}, // t\r
+ {0x00,0x00,0x88,0x88,0x88,0x98,0x68,0x00}, // u\r
+ {0x00,0x00,0x88,0x88,0x88,0x50,0x20,0x00}, // v\r
+ {0x00,0x00,0x88,0x88,0xA8,0xA8,0x50,0x00}, // w\r
+ {0x00,0x00,0x88,0x50,0x20,0x50,0x88,0x00}, // x\r
+ {0x00,0x00,0x88,0x88,0x78,0x08,0x88,0x70}, // y\r
+ {0x00,0x00,0xF8,0x10,0x20,0x40,0xF8,0x00}, // z\r
+ {0x10,0x20,0x20,0x40,0x20,0x20,0x10,0x00}, // {\r
+ {0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00}, // |\r
+ {0x40,0x20,0x20,0x10,0x20,0x20,0x40,0x00}, // }\r
+ {0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00} // DEL\r
+};\r
+\r
+const unsigned char FONT8x8[97][8] = {\r
+ {0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00}, // !\r
+ {0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00}, // #\r
+ {0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00}, // $\r
+ {0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00}, // %\r
+ {0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00}, // &\r
+ {0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00}, // '\r
+ {0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00}, // (\r
+ {0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00}, // )\r
+ {0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00}, // *\r
+ {0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30}, // ,\r
+ {0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00}, // .\r
+ {0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00}, // / (forward slash)\r
+ {0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00}, // 0 0x30\r
+ {0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00}, // 1\r
+ {0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00}, // 2\r
+ {0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00}, // 3\r
+ {0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00}, // 4\r
+ {0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00}, // 5\r
+ {0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00}, // 6\r
+ {0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00}, // 7\r
+ {0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00}, // 8\r
+ {0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00}, // 9\r
+ {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00}, // :\r
+ {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30}, // ;\r
+ {0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00}, // <\r
+ {0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00}, // =\r
+ {0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00}, // >\r
+ {0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00}, // ?\r
+ {0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00}, // @ 0x40\r
+ {0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, // A\r
+ {0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00}, // B\r
+ {0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00}, // C\r
+ {0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00}, // D\r
+ {0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00}, // E\r
+ {0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00}, // F\r
+ {0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00}, // G\r
+ {0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00}, // H\r
+ {0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // I\r
+ {0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00}, // J\r
+ {0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00}, // K\r
+ {0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00}, // L\r
+ {0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00}, // M\r
+ {0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00}, // N\r
+ {0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00}, // O\r
+ {0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00}, // P 0x50\r
+ {0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00}, // Q\r
+ {0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00}, // R\r
+ {0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00}, // S\r
+ {0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00}, // T\r
+ {0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00}, // U\r
+ {0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00}, // V\r
+ {0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00}, // W\r
+ {0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00}, // X\r
+ {0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00}, // Y\r
+ {0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00}, // Z\r
+ {0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00}, // [\r
+ {0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00}, // \ (back slash)\r
+ {0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00}, // ]\r
+ {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF}, // _\r
+ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00}, // a\r
+ {0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00}, // b\r
+ {0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00}, // c\r
+ {0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00}, // d\r
+ {0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00}, // e\r
+ {0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00}, // f\r
+ {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C}, // g\r
+ {0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00}, // h\r
+ {0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00}, // i\r
+ {0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C}, // j\r
+ {0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00}, // k\r
+ {0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // l\r
+ {0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00}, // m\r
+ {0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00}, // n\r
+ {0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00}, // o\r
+ {0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78}, // p 0x70\r
+ {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F}, // q\r
+ {0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00}, // r\r
+ {0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00}, // s\r
+ {0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00}, // t\r
+ {0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00}, // u\r
+ {0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00}, // v\r
+ {0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00}, // w\r
+ {0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00}, // x\r
+ {0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C}, // y\r
+ {0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00}, // z\r
+ {0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00}, // {\r
+ {0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00}, // |\r
+ {0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00}, // }\r
+ {0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00}// DEL\r
+};\r
+const unsigned char FONT8x16[97][16] = {\r
+ {0x08,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // !\r
+ {0x00,0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x00,0x00,0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // #\r
+ {0x0C,0x0C,0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E,0x0C,0x0C,0x00,0x00}, // $\r
+ {0x00,0x00,0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63,0x00,0x00,0x00,0x00}, // %\r
+ {0x00,0x00,0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // &\r
+ {0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // '\r
+ {0x00,0x00,0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C,0x00,0x00,0x00,0x00}, // (\r
+ {0x00,0x00,0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18,0x00,0x00,0x00,0x00}, // )\r
+ {0x00,0x00,0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00,0x00,0x00,0x00,0x00}, // *\r
+ {0x00,0x00,0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ,\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // .\r
+ {0x00,0x00,0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00}, // / (forward slash)\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 0 0x30\r
+ {0x00,0x00,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F,0x00,0x00,0x00,0x00}, // 1\r
+ {0x00,0x00,0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // 2\r
+ {0x00,0x00,0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // 3\r
+ {0x00,0x00,0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F,0x00,0x00,0x00,0x00}, // 4\r
+ {0x00,0x00,0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E,0x00,0x00,0x00,0x00}, // 5\r
+ {0x00,0x00,0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 6\r
+ {0x00,0x00,0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18,0x00,0x00,0x00,0x00}, // 7\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 8\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C,0x00,0x00,0x00,0x00}, // 9\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // :\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ;\r
+ {0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00}, // <\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00}, // =\r
+ {0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00}, // >\r
+ {0x00,0x00,0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x00,0x00,0x00,0x00}, // ?\r
+ {0x00,0x00,0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E,0x00,0x00,0x00,0x00}, // @ 0x40\r
+ {0x00,0x00,0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // A\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E,0x00,0x00,0x00,0x00}, // B\r
+ {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E,0x00,0x00,0x00,0x00}, // C\r
+ {0x00,0x00,0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C,0x00,0x00,0x00,0x00}, // D\r
+ {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // E\r
+ {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // F\r
+ {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D,0x00,0x00,0x00,0x00}, // G\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // H\r
+ {0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // I\r
+ {0x00,0x00,0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00,0x00,0x00}, // J\r
+ {0x00,0x00,0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // K\r
+ {0x00,0x00,0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // L\r
+ {0x00,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // M\r
+ {0x00,0x00,0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // N\r
+ {0x00,0x00,0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x00,0x00,0x00,0x00}, // O\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // P 0x50\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07,0x00,0x00}, // Q\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // R\r
+ {0x00,0x00,0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // S\r
+ {0x00,0x00,0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // T\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // U\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08,0x00,0x00,0x00,0x00}, // V\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // W\r
+ {0x00,0x00,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3,0x00,0x00,0x00,0x00}, // X\r
+ {0x00,0x00,0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // Y\r
+ {0x00,0x00,0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // Z\r
+ {0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00}, // [\r
+ {0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01,0x00,0x00,0x00,0x00}, // \ (back slash)\r
+ {0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00}, // ]\r
+ {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00}, // _\r
+ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // a\r
+ {0x00,0x00,0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E,0x00,0x00,0x00,0x00}, // b\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // c\r
+ {0x00,0x00,0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // d\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // e\r
+ {0x00,0x00,0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // f\r
+ {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00,0x00}, // g\r
+ {0x00,0x00,0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // h\r
+ {0x00,0x00,0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // i\r
+ {0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00}, // j\r
+ {0x00,0x00,0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73,0x00,0x00,0x00,0x00}, // k\r
+ {0x00,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // l\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B,0x00,0x00,0x00,0x00}, // m\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33,0x00,0x00,0x00,0x00}, // n\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // o\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x3E,0x30,0x30,0x78,0x00,0x00}, // p 0x70\r
+ {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x06,0x0F,0x00,0x00}, // q\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // r\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // s\r
+ {0x00,0x00,0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E,0x00,0x00,0x00,0x00}, // t\r
+ {0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // u\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08,0x00,0x00,0x00,0x00}, // v\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x00,0x00,0x00,0x00}, // w\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // x\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C,0x00,0x00}, // y\r
+ {0x00,0x00,0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F,0x00,0x00,0x00,0x00}, // z\r
+ {0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00}, // {\r
+ {0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00}, // |\r
+ {0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00}, // }\r
+ {0x00,0x00,0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x00,0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
+}; // DEL\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Font 10x14 table definition.\r
+ *\r
+ */\r
+\r
+#include "board.h"\r
+\r
+/** Char set of font 10x14 */\r
+const uint8_t pCharset10x14[] = {\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,\r
+ 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,\r
+ 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,\r
+ 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,\r
+ 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,\r
+ 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,\r
+ 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,\r
+ 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,\r
+ 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,\r
+ 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,\r
+ 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,\r
+ 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,\r
+ 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,\r
+ 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,\r
+ 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,\r
+ 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,\r
+ 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,\r
+ 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,\r
+ 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,\r
+ 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,\r
+ 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,\r
+ 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,\r
+ 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,\r
+ 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,\r
+ 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,\r
+ 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,\r
+ 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,\r
+ 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,\r
+ 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,\r
+ 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,\r
+ 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,\r
+ 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,\r
+ 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,\r
+ 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,\r
+ 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,\r
+ 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,\r
+ 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,\r
+ 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,\r
+ 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,\r
+ 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,\r
+ 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,\r
+ 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,\r
+ 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,\r
+ 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,\r
+ 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,\r
+ 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,\r
+ 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,\r
+ 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,\r
+ 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,\r
+ 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,\r
+ 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,\r
+ 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,\r
+ 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC\r
+} ;\r
+\r
+const unsigned char FONT6x8[97][8] = {\r
+ {0x06,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00}, // !\r
+ {0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00}, // #\r
+ {0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00}, // $\r
+ {0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00}, // %\r
+ {0x40,0xA0,0xA0,0x40,0xA8,0x90,0x68,0x00}, // &\r
+ {0x30,0x30,0x20,0x40,0x00,0x00,0x00,0x00}, // '\r
+ {0x10,0x20,0x40,0x40,0x40,0x20,0x10,0x00}, // (\r
+ {0x40,0x20,0x10,0x10,0x10,0x20,0x40,0x00}, // )\r
+ {0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00}, // *\r
+ {0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x30,0x30,0x20,0x40}, // ,\r
+ {0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00}, // .\r
+ {0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00}, // / (forward slash)\r
+ {0x70,0x88,0x88,0xA8,0x88,0x88,0x70,0x00}, // 0 0x30\r
+ {0x20,0x60,0x20,0x20,0x20,0x20,0x70,0x00}, // 1\r
+ {0x70,0x88,0x08,0x70,0x80,0x80,0xF8,0x00}, // 2\r
+ {0xF8,0x08,0x10,0x30,0x08,0x88,0x70,0x00}, // 3\r
+ {0x10,0x30,0x50,0x90,0xF8,0x10,0x10,0x00}, // 4\r
+ {0xF8,0x80,0xF0,0x08,0x08,0x88,0x70,0x00}, // 5\r
+ {0x38,0x40,0x80,0xF0,0x88,0x88,0x70,0x00}, // 6\r
+ {0xF8,0x08,0x08,0x10,0x20,0x40,0x80,0x00}, // 7\r
+ {0x70,0x88,0x88,0x70,0x88,0x88,0x70,0x00}, // 8\r
+ {0x70,0x88,0x88,0x78,0x08,0x10,0xE0,0x00}, // 9\r
+ {0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00}, // :\r
+ {0x00,0x00,0x20,0x00,0x20,0x20,0x40,0x00}, // ;\r
+ {0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x00}, // <\r
+ {0x00,0x00,0xF8,0x00,0xF8,0x00,0x00,0x00}, // =\r
+ {0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00}, // >\r
+ {0x70,0x88,0x08,0x30,0x20,0x00,0x20,0x00}, // ?\r
+ {0x70,0x88,0xA8,0xB8,0xB0,0x80,0x78,0x00}, // @ 0x40\r
+ {0x20,0x50,0x88,0x88,0xF8,0x88,0x88,0x00}, // A\r
+ {0xF0,0x88,0x88,0xF0,0x88,0x88,0xF0,0x00}, // B\r
+ {0x70,0x88,0x80,0x80,0x80,0x88,0x70,0x00}, // C\r
+ {0xF0,0x88,0x88,0x88,0x88,0x88,0xF0,0x00}, // D\r
+ {0xF8,0x80,0x80,0xF0,0x80,0x80,0xF8,0x00}, // E\r
+ {0xF8,0x80,0x80,0xF0,0x80,0x80,0x80,0x00}, // F\r
+ {0x78,0x88,0x80,0x80,0x98,0x88,0x78,0x00}, // G\r
+ {0x88,0x88,0x88,0xF8,0x88,0x88,0x88,0x00}, // H\r
+ {0x70,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // I\r
+ {0x38,0x10,0x10,0x10,0x10,0x90,0x60,0x00}, // J\r
+ {0x88,0x90,0xA0,0xC0,0xA0,0x90,0x88,0x00}, // K\r
+ {0x80,0x80,0x80,0x80,0x80,0x80,0xF8,0x00}, // L\r
+ {0x88,0xD8,0xA8,0xA8,0xA8,0x88,0x88,0x00}, // M\r
+ {0x88,0x88,0xC8,0xA8,0x98,0x88,0x88,0x00}, // N\r
+ {0x70,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // O\r
+ {0xF0,0x88,0x88,0xF0,0x80,0x80,0x80,0x00}, // P 0x50\r
+ {0x70,0x88,0x88,0x88,0xA8,0x90,0x68,0x00}, // Q\r
+ {0xF0,0x88,0x88,0xF0,0xA0,0x90,0x88,0x00}, // R\r
+ {0x70,0x88,0x80,0x70,0x08,0x88,0x70,0x00}, // S\r
+ {0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x00}, // T\r
+ {0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // U\r
+ {0x88,0x88,0x88,0x88,0x88,0x50,0x20,0x00}, // V\r
+ {0x88,0x88,0x88,0xA8,0xA8,0xA8,0x50,0x00}, // W\r
+ {0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00}, // X\r
+ {0x88,0x88,0x50,0x20,0x20,0x20,0x20,0x00}, // Y\r
+ {0xF8,0x08,0x10,0x70,0x40,0x80,0xF8,0x00}, // Z\r
+ {0x78,0x40,0x40,0x40,0x40,0x40,0x78,0x00}, // [\r
+ {0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00}, // \ (back slash)\r
+ {0x78,0x08,0x08,0x08,0x08,0x08,0x78,0x00}, // ]\r
+ {0x20,0x50,0x88,0x00,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00}, // _\r
+ {0x60,0x60,0x20,0x10,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x60,0x10,0x70,0x90,0x78,0x00}, // a\r
+ {0x80,0x80,0xB0,0xC8,0x88,0xC8,0xB0,0x00}, // b\r
+ {0x00,0x00,0x70,0x88,0x80,0x88,0x70,0x00}, // c\r
+ {0x08,0x08,0x68,0x98,0x88,0x98,0x68,0x00}, // d\r
+ {0x00,0x00,0x70,0x88,0xF8,0x80,0x70,0x00}, // e\r
+ {0x10,0x28,0x20,0x70,0x20,0x20,0x20,0x00}, // f\r
+ {0x00,0x00,0x70,0x98,0x98,0x68,0x08,0x70}, // g\r
+ {0x80,0x80,0xB0,0xC8,0x88,0x88,0x88,0x00}, // h\r
+ {0x20,0x00,0x60,0x20,0x20,0x20,0x70,0x00}, // i\r
+ {0x10,0x00,0x10,0x10,0x10,0x90,0x60,0x00}, // j\r
+ {0x80,0x80,0x90,0xA0,0xC0,0xA0,0x90,0x00}, // k\r
+ {0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // l\r
+ {0x00,0x00,0xD0,0xA8,0xA8,0xA8,0xA8,0x00}, // m\r
+ {0x00,0x00,0xB0,0xC8,0x88,0x88,0x88,0x00}, // n\r
+ {0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00}, // o\r
+ {0x00,0x00,0xB0,0xC8,0xC8,0xB0,0x80,0x80}, // p 0x70\r
+ {0x00,0x00,0x68,0x98,0x98,0x68,0x08,0x08}, // q\r
+ {0x00,0x00,0xB0,0xC8,0x80,0x80,0x80,0x00}, // r\r
+ {0x00,0x00,0x78,0x80,0x70,0x08,0xF0,0x00}, // s\r
+ {0x20,0x20,0xF8,0x20,0x20,0x28,0x10,0x00}, // t\r
+ {0x00,0x00,0x88,0x88,0x88,0x98,0x68,0x00}, // u\r
+ {0x00,0x00,0x88,0x88,0x88,0x50,0x20,0x00}, // v\r
+ {0x00,0x00,0x88,0x88,0xA8,0xA8,0x50,0x00}, // w\r
+ {0x00,0x00,0x88,0x50,0x20,0x50,0x88,0x00}, // x\r
+ {0x00,0x00,0x88,0x88,0x78,0x08,0x88,0x70}, // y\r
+ {0x00,0x00,0xF8,0x10,0x20,0x40,0xF8,0x00}, // z\r
+ {0x10,0x20,0x20,0x40,0x20,0x20,0x10,0x00}, // {\r
+ {0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00}, // |\r
+ {0x40,0x20,0x20,0x10,0x20,0x20,0x40,0x00}, // }\r
+ {0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00} // DEL\r
+};\r
+\r
+const unsigned char FONT8x8[97][8] = {\r
+ {0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00}, // !\r
+ {0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00}, // #\r
+ {0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00}, // $\r
+ {0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00}, // %\r
+ {0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00}, // &\r
+ {0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00}, // '\r
+ {0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00}, // (\r
+ {0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00}, // )\r
+ {0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00}, // *\r
+ {0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30}, // ,\r
+ {0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00}, // .\r
+ {0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00}, // / (forward slash)\r
+ {0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00}, // 0 0x30\r
+ {0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00}, // 1\r
+ {0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00}, // 2\r
+ {0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00}, // 3\r
+ {0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00}, // 4\r
+ {0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00}, // 5\r
+ {0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00}, // 6\r
+ {0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00}, // 7\r
+ {0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00}, // 8\r
+ {0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00}, // 9\r
+ {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00}, // :\r
+ {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30}, // ;\r
+ {0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00}, // <\r
+ {0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00}, // =\r
+ {0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00}, // >\r
+ {0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00}, // ?\r
+ {0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00}, // @ 0x40\r
+ {0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, // A\r
+ {0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00}, // B\r
+ {0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00}, // C\r
+ {0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00}, // D\r
+ {0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00}, // E\r
+ {0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00}, // F\r
+ {0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00}, // G\r
+ {0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00}, // H\r
+ {0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // I\r
+ {0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00}, // J\r
+ {0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00}, // K\r
+ {0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00}, // L\r
+ {0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00}, // M\r
+ {0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00}, // N\r
+ {0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00}, // O\r
+ {0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00}, // P 0x50\r
+ {0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00}, // Q\r
+ {0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00}, // R\r
+ {0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00}, // S\r
+ {0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00}, // T\r
+ {0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00}, // U\r
+ {0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00}, // V\r
+ {0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00}, // W\r
+ {0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00}, // X\r
+ {0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00}, // Y\r
+ {0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00}, // Z\r
+ {0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00}, // [\r
+ {0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00}, // \ (back slash)\r
+ {0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00}, // ]\r
+ {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF}, // _\r
+ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00}, // a\r
+ {0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00}, // b\r
+ {0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00}, // c\r
+ {0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00}, // d\r
+ {0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00}, // e\r
+ {0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00}, // f\r
+ {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C}, // g\r
+ {0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00}, // h\r
+ {0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00}, // i\r
+ {0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C}, // j\r
+ {0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00}, // k\r
+ {0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // l\r
+ {0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00}, // m\r
+ {0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00}, // n\r
+ {0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00}, // o\r
+ {0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78}, // p 0x70\r
+ {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F}, // q\r
+ {0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00}, // r\r
+ {0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00}, // s\r
+ {0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00}, // t\r
+ {0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00}, // u\r
+ {0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00}, // v\r
+ {0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00}, // w\r
+ {0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00}, // x\r
+ {0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C}, // y\r
+ {0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00}, // z\r
+ {0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00}, // {\r
+ {0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00}, // |\r
+ {0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00}, // }\r
+ {0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00}// DEL\r
+};\r
+const unsigned char FONT8x16[97][16] = {\r
+ {0x08,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20\r
+ {0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // !\r
+ {0x00,0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // "\r
+ {0x00,0x00,0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // #\r
+ {0x0C,0x0C,0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E,0x0C,0x0C,0x00,0x00}, // $\r
+ {0x00,0x00,0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63,0x00,0x00,0x00,0x00}, // %\r
+ {0x00,0x00,0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // &\r
+ {0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // '\r
+ {0x00,0x00,0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C,0x00,0x00,0x00,0x00}, // (\r
+ {0x00,0x00,0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18,0x00,0x00,0x00,0x00}, // )\r
+ {0x00,0x00,0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00,0x00,0x00,0x00,0x00}, // *\r
+ {0x00,0x00,0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00}, // +\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ,\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // -\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // .\r
+ {0x00,0x00,0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00}, // / (forward slash)\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 0 0x30\r
+ {0x00,0x00,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F,0x00,0x00,0x00,0x00}, // 1\r
+ {0x00,0x00,0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // 2\r
+ {0x00,0x00,0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // 3\r
+ {0x00,0x00,0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F,0x00,0x00,0x00,0x00}, // 4\r
+ {0x00,0x00,0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E,0x00,0x00,0x00,0x00}, // 5\r
+ {0x00,0x00,0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 6\r
+ {0x00,0x00,0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18,0x00,0x00,0x00,0x00}, // 7\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 8\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C,0x00,0x00,0x00,0x00}, // 9\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // :\r
+ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ;\r
+ {0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00}, // <\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00}, // =\r
+ {0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00}, // >\r
+ {0x00,0x00,0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x00,0x00,0x00,0x00}, // ?\r
+ {0x00,0x00,0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E,0x00,0x00,0x00,0x00}, // @ 0x40\r
+ {0x00,0x00,0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // A\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E,0x00,0x00,0x00,0x00}, // B\r
+ {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E,0x00,0x00,0x00,0x00}, // C\r
+ {0x00,0x00,0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C,0x00,0x00,0x00,0x00}, // D\r
+ {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // E\r
+ {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // F\r
+ {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D,0x00,0x00,0x00,0x00}, // G\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // H\r
+ {0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // I\r
+ {0x00,0x00,0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00,0x00,0x00}, // J\r
+ {0x00,0x00,0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // K\r
+ {0x00,0x00,0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // L\r
+ {0x00,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // M\r
+ {0x00,0x00,0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // N\r
+ {0x00,0x00,0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x00,0x00,0x00,0x00}, // O\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // P 0x50\r
+ {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07,0x00,0x00}, // Q\r
+ {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // R\r
+ {0x00,0x00,0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // S\r
+ {0x00,0x00,0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // T\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // U\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08,0x00,0x00,0x00,0x00}, // V\r
+ {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // W\r
+ {0x00,0x00,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3,0x00,0x00,0x00,0x00}, // X\r
+ {0x00,0x00,0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // Y\r
+ {0x00,0x00,0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // Z\r
+ {0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00}, // [\r
+ {0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01,0x00,0x00,0x00,0x00}, // \ (back slash)\r
+ {0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00}, // ]\r
+ {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ^\r
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00}, // _\r
+ {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ` 0x60\r
+ {0x00,0x00,0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // a\r
+ {0x00,0x00,0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E,0x00,0x00,0x00,0x00}, // b\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // c\r
+ {0x00,0x00,0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // d\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // e\r
+ {0x00,0x00,0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // f\r
+ {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00,0x00}, // g\r
+ {0x00,0x00,0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // h\r
+ {0x00,0x00,0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // i\r
+ {0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00}, // j\r
+ {0x00,0x00,0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73,0x00,0x00,0x00,0x00}, // k\r
+ {0x00,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // l\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B,0x00,0x00,0x00,0x00}, // m\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33,0x00,0x00,0x00,0x00}, // n\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // o\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x3E,0x30,0x30,0x78,0x00,0x00}, // p 0x70\r
+ {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x06,0x0F,0x00,0x00}, // q\r
+ {0x00,0x00,0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // r\r
+ {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // s\r
+ {0x00,0x00,0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E,0x00,0x00,0x00,0x00}, // t\r
+ {0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // u\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08,0x00,0x00,0x00,0x00}, // v\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x00,0x00,0x00,0x00}, // w\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // x\r
+ {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C,0x00,0x00}, // y\r
+ {0x00,0x00,0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F,0x00,0x00,0x00,0x00}, // z\r
+ {0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00}, // {\r
+ {0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00}, // |\r
+ {0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00}, // }\r
+ {0x00,0x00,0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ~\r
+ {0x00,0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
+}; // DEL\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of LCD driver, Include LCD initialization,\r
+ * LCD on/off and LCD backlight control.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "board.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initializes the LCD controller.\r
+ * Configure SMC to access LCD controller at 64MHz MCK.\r
+ */\r
+extern void LCDD_Initialize( void )\r
+{\r
+ \r
+ /* Initialize LCD controller */\r
+ ILI9488_Initialize() ;\r
+\r
+ /* Initialize LCD controller */\r
+ ILI9488_SetDisplayPortrait( 0 ) ;\r
+\r
+ /* Set LCD backlight */\r
+ LCDD_SetBacklight( 16 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Turn on the LCD.\r
+ */\r
+void LCDD_On(void)\r
+{\r
+ ILI9488_On();\r
+}\r
+\r
+/**\r
+ * \brief Turn off the LCD.\r
+ */\r
+void LCDD_Off(void)\r
+{\r
+ ILI9488_Off();\r
+}\r
+\r
+/**\r
+ * \brief Set the backlight of the LCD.\r
+ *\r
+ * \param level Backlight brightness level [1..16], 1 means maximum brightness.\r
+ */\r
+void LCDD_SetBacklight (uint32_t level)\r
+{\r
+ \r
+ /* Ensure valid level */\r
+ level = (level < 1) ? 1 : level;\r
+ level = (level > 16) ? 16 : level;\r
+\r
+ PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, level);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef PINS_LEDS\r
+static const Pin pinsLeds[] = {PIN_LED_0, PIN_LED_1} ;\r
+static const uint32_t numLeds = PIO_LISTSIZE( pinsLeds ) ;\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global Functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Configures the pin associated with the given LED number. If the LED does\r
+ * not exist on the board, the function does nothing.\r
+ * \param led Number of the LED to configure.\r
+ * \return 1 if the LED exists and has been configured; otherwise 0.\r
+ */\r
+extern uint32_t LED_Configure( uint32_t dwLed )\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check that LED exists\r
+ if ( dwLed >= numLeds)\r
+ {\r
+\r
+ return 0;\r
+ }\r
+\r
+ // Configure LED\r
+ return ( PIO_Configure( &pinsLeds[dwLed], 1 ) ) ;\r
+#else\r
+ return 0 ;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Turns the given LED on if it exists; otherwise does nothing.\r
+ * \param led Number of the LED to turn on.\r
+ * \return 1 if the LED has been turned on; 0 otherwise.\r
+ */\r
+extern uint32_t LED_Set( uint32_t dwLed )\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if ( dwLed >= numLeds )\r
+ {\r
+ return 0 ;\r
+ }\r
+\r
+ /* Turn LED on */\r
+ if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )\r
+ {\r
+\r
+ PIO_Set( &pinsLeds[dwLed] ) ;\r
+ }\r
+ else\r
+ {\r
+ PIO_Clear( &pinsLeds[dwLed] ) ;\r
+ }\r
+\r
+ return 1 ;\r
+#else\r
+ return 0 ;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Turns a LED off.\r
+ *\r
+ * \param led Number of the LED to turn off.\r
+ * \return 1 if the LED has been turned off; 0 otherwise.\r
+ */\r
+extern uint32_t LED_Clear( uint32_t dwLed )\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if ( dwLed >= numLeds )\r
+ {\r
+ return 0 ;\r
+ }\r
+\r
+ /* Turn LED off */\r
+ if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )\r
+ {\r
+ PIO_Clear( &pinsLeds[dwLed] ) ;\r
+ }\r
+ else\r
+ {\r
+ PIO_Set( &pinsLeds[dwLed] ) ;\r
+ }\r
+\r
+ return 1 ;\r
+#else\r
+ return 0 ;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Toggles the current state of a LED.\r
+ *\r
+ * \param led Number of the LED to toggle.\r
+ * \return 1 if the LED has been toggled; otherwise 0.\r
+ */\r
+extern uint32_t LED_Toggle( uint32_t dwLed )\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if ( dwLed >= numLeds )\r
+ {\r
+ return 0 ;\r
+ }\r
+\r
+ /* Toggle LED */\r
+ if ( PIO_GetOutputDataStatus( &pinsLeds[dwLed] ) )\r
+ {\r
+ PIO_Clear( &pinsLeds[dwLed] ) ;\r
+ }\r
+ else\r
+ {\r
+ PIO_Set( &pinsLeds[dwLed] ) ;\r
+ }\r
+\r
+ return 1 ;\r
+#else\r
+ return 0 ;\r
+#endif\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Returns the minimum value between two integers.\r
+ *\r
+ * \param a First integer to compare.\r
+ * \param b Second integer to compare.\r
+ */\r
+extern uint32_t min( uint32_t dwA, uint32_t dwB )\r
+{\r
+ if ( dwA < dwB )\r
+ {\r
+ return dwA ;\r
+ }\r
+ else\r
+ {\r
+ return dwB ;\r
+ }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Returns the absolute value of an integer.\r
+ *\r
+ * \param value Integer value.\r
+ *\r
+ * \note Do not call this function "abs", problem with gcc !\r
+ */\r
+extern uint32_t absv( int32_t lValue )\r
+{\r
+ if ( lValue < 0 )\r
+ {\r
+ return -lValue ;\r
+ }\r
+ else\r
+ {\r
+ return lValue ;\r
+ }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Computes and returns x power of y.\r
+ *\r
+ * \param x Value.\r
+ * \param y Power.\r
+ */\r
+extern uint32_t power( uint32_t dwX, uint32_t dwY )\r
+{\r
+ uint32_t dwResult = 1 ;\r
+\r
+ while ( dwY > 0 )\r
+ {\r
+ dwResult *= dwX ;\r
+ dwY-- ;\r
+ }\r
+\r
+ return dwResult ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "board.h"\r
+\r
+/** Slave address of OMNIVISION chips. */\r
+#define OV_CAPTOR_ADDRESS_1 0x30 \r
+#define OV_CAPTOR_ADDRESS_2 0x21\r
+#define OV_CAPTOR_ADDRESS_3 0x3c \r
+#define OV_CAPTOR_ADDRESS_4 0x10\r
+\r
+/** terminating list entry for register in configuration file */\r
+#define OV_REG_TERM 0xFF\r
+#define OV_REG_DELAY 0xFFFF\r
+/** terminating list entry for value in configuration file */\r
+#define OV_VAL_TERM 0xFF \r
+\r
+//static const Pin pin_ISI_RST= PIN_ISI_RST;\r
+static uint8_t twiSlaveAddr = OV_CAPTOR_ADDRESS_1;\r
+/*----------------------------------------------------------------------------\r
+ * Local Functions\r
+ *----------------------------------------------------------------------------*/\r
+static void ov_reset(void)\r
+{\r
+ volatile uint32_t i;\r
+ //PIO_Configure(&pin_ISI_RST, 1);\r
+ //PIO_Clear(&pin_ISI_RST);\r
+ for(i = 0; i < 6000; i++ );\r
+ //PIO_Set(&pin_ISI_RST);\r
+ for(i = 0; i<6000; i++ );\r
+}\r
+\r
+\r
+/**\r
+ * \brief Read PID and VER\r
+ * \param pTwid TWI interface\r
+ * \return VER | (PID<<8)\r
+ */\r
+static uint16_t ov_id8(Twid *pTwid)\r
+{\r
+ uint8_t id, ver;\r
+ uint8_t status;\r
+ // OV_PID\r
+ status = ov_read_reg8(pTwid, 0x0A, &id);\r
+ if( status != 0 ) return 0;\r
+ TRACE_INFO("PID = 0x%X\n\r", id);\r
+\r
+ // OV_VER\r
+ status = ov_read_reg8(pTwid, 0x0B, &ver);\r
+ if( status != 0 ) return 0;\r
+ TRACE_INFO("VER = 0x%X\n\r", ver);\r
+\r
+ return((uint16_t)(id <<8) | ver);\r
+}\r
+\r
+/**\r
+ * \brief Read PID and VER\r
+ * \param pTwid TWI interface\r
+ * \return VER | (PID<<8)\r
+ */\r
+static uint16_t ov_id16(Twid *pTwid)\r
+{\r
+ uint8_t id, ver;\r
+ // OV_PID\r
+ ov_read_reg16(pTwid, 0x300A, &id);\r
+ TRACE_INFO("PID = 0x%X\n\r", id);\r
+\r
+ // OV_VER\r
+ ov_read_reg16(pTwid, 0x300B, &ver);\r
+ TRACE_INFO("VER = 0x%X\n\r", ver);\r
+\r
+ return((uint16_t)(id <<8) | ver);\r
+}\r
+\r
+/**\r
+ * \brief Read PID and VER\r
+ * \param pTwid TWI interface\r
+ * \return VER | (PID<<8)\r
+ */\r
+static uint16_t ov_id(Twid *pTwid)\r
+{\r
+ uint16_t id;\r
+ printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);\r
+ twiSlaveAddr = OV_CAPTOR_ADDRESS_1;\r
+ id = ov_id8(pTwid);\r
+ if (id == 0) {\r
+ twiSlaveAddr = OV_CAPTOR_ADDRESS_2;\r
+ printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);\r
+ id = ov_id8(pTwid);\r
+ if (id == 0) {\r
+ twiSlaveAddr = OV_CAPTOR_ADDRESS_3;\r
+ printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);\r
+ id = ov_id16(pTwid);\r
+ if (id == 0) {\r
+ twiSlaveAddr = OV_CAPTOR_ADDRESS_4;\r
+ printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);\r
+ id = ov_id16(pTwid);\r
+ }\r
+ }\r
+ }\r
+ return id;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global Functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Read a value from a register in an OV sensor device.\r
+ * \param pTwid TWI interface\r
+ * \param reg Register to be read\r
+ * \param isize Internal address size in bytes.\r
+ * \param pData Data read\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData)\r
+{\r
+ uint8_t status;\r
+\r
+ status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, ®, 1, 0);\r
+ status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);\r
+ if( status != 0 ) {\r
+ TRACE_ERROR("ov_read_reg pb\n\r");\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Read a value from a register in an OV sensor device.\r
+ * \param pTwid TWI interface\r
+ * \param reg Register to be read\r
+ * \param pData Data read\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData)\r
+{\r
+ uint8_t status;\r
+ uint8_t reg8[2];\r
+ reg8[0] = reg>>8;\r
+ reg8[1] = reg & 0xff;\r
+\r
+ status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, reg8, 2, 0);\r
+ status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);\r
+ if( status != 0 ) {\r
+\r
+ TRACE_ERROR("ov_read_reg pb\n\r");\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Write a value to a register in an OV sensor device.\r
+ * \param pTwid TWI interface\r
+ * \param reg Register to be writen\r
+ * \param pData Data written\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val)\r
+{\r
+ uint8_t status;\r
+\r
+ status = TWID_Write(pTwid, twiSlaveAddr, reg, 1, &val, 1, 0);\r
+ if( status != 0 ) {\r
+ TRACE_ERROR("ov_write_reg pb\n\r");\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Write a value to a register in an OV sensor device.\r
+ * \param pTwid TWI interface\r
+ * \param reg Register to be writen\r
+ * \param pData Data written\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val)\r
+{\r
+ uint8_t status;\r
+ status = TWID_Write(pTwid, twiSlaveAddr, reg, 2, &val, 1, 0);\r
+ if( status != 0 ) {\r
+ TRACE_ERROR("ov_write_reg pb\n\r");\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Initialize a list of OV registers.\r
+ * The list of registers is terminated by the pair of values\r
+ * \param pTwid TWI interface\r
+ * \param pReglist Register list to be written\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist)\r
+{\r
+ uint32_t err;\r
+ uint32_t size=0;\r
+ const struct ov_reg *pNext = pReglist;\r
+ volatile uint32_t delay;\r
+\r
+ TRACE_DEBUG("ov_write_regs:");\r
+ while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {\r
+ err = ov_write_reg8(pTwid, pNext->reg, pNext->val);\r
+\r
+ size++;\r
+ for(delay=0;delay<=10000;delay++); \r
+ if (err == TWID_ERROR_BUSY){\r
+ TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");\r
+ return err;\r
+ }\r
+ //printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);\r
+ pNext++;\r
+ }\r
+ TRACE_DEBUG_WP("\n\r");\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Initialize a list of OV registers.\r
+ * The list of registers is terminated by the pair of values\r
+ * \param pTwid TWI interface\r
+ * \param pReglist Register list to be written\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist)\r
+{\r
+ uint32_t err = 0;\r
+ uint32_t size = 0;\r
+ const struct ov_reg *pNext = pReglist;\r
+ volatile uint32_t delay;\r
+\r
+ TRACE_DEBUG("ov_write_regs:");\r
+ while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {\r
+ err = ov_write_reg16(pTwid, pNext->reg, pNext->val);\r
+ size++;\r
+ for(delay = 0;delay <= 10000; delay++); \r
+ if (err == TWID_ERROR_BUSY){\r
+ TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");\r
+ return err;\r
+ }\r
+ //printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);\r
+ pNext++;\r
+ }\r
+ TRACE_DEBUG_WP("\n\r");\r
+ return 0;\r
+}\r
+\r
+void isOV5640_AF_InitDone(Twid *pTwid)\r
+{\r
+ uint8_t value = 0;\r
+ while(1){\r
+ ov_read_reg16(pTwid, 0x3029, &value);\r
+ if (value == 0x70) break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief AF for OV 5640\r
+ * \param pTwid TWI interface\r
+ * \return 0 if no error; otherwize TWID_ERROR_BUSY\r
+ */\r
+uint32_t ov_5640_AF_single(Twid *pTwid)\r
+{\r
+ uint8_t value;\r
+ ov_write_reg16(pTwid, 0x3023, 1);\r
+ ov_write_reg16(pTwid, 0x3022, 3);\r
+ value =1;\r
+ while(1){\r
+ ov_read_reg16(pTwid, 0x3023, &value);\r
+ if (value == 0) break;\r
+ }\r
+ return 0;\r
+}\r
+\r
+uint32_t ov_5640_AF_continue(Twid *pTwid)\r
+{\r
+ uint8_t value;\r
+ ov_write_reg16(pTwid, 0x3024, 1);\r
+ ov_write_reg16(pTwid, 0x3022, 4);\r
+ value =1;\r
+ while(1){\r
+ ov_read_reg16(pTwid, 0x3023, &value);\r
+ if (value == 0) break;\r
+ }\r
+ return 0;\r
+}\r
+\r
+uint32_t ov_5640_AFPause(Twid *pTwid)\r
+{\r
+ uint8_t value;\r
+ ov_write_reg16(pTwid, 0x3023, 1);\r
+ ov_write_reg16(pTwid, 0x3022, 6);\r
+ value =1;\r
+ while(1){\r
+ ov_read_reg16(pTwid, 0x3023, &value);\r
+ if (value == 0) break;\r
+ }\r
+ return 0;\r
+}\r
+\r
+uint32_t ov_5640_AFrelease(Twid *pTwid)\r
+{\r
+ uint8_t value;\r
+ ov_write_reg16(pTwid, 0x3023, 1);\r
+ ov_write_reg16(pTwid, 0x3022, 8);\r
+ value =1;\r
+ while(1){\r
+ ov_read_reg16(pTwid, 0x3023, &value);\r
+ if (value == 0) break;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Dump all register\r
+ * \param pTwid TWI interface\r
+ */\r
+void ov_DumpRegisters8(Twid *pTwid)\r
+{\r
+ uint32_t i;\r
+ uint8_t value;\r
+\r
+ TRACE_INFO_WP("Dump all camera register\n\r");\r
+ for(i = 0; i <= 0x5C; i++) {\r
+ value = 0;\r
+ ov_read_reg8(pTwid, i, &value);\r
+ TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);\r
+ if( ((i+1)%5) == 0 ) {\r
+ TRACE_INFO_WP("\n\r");\r
+ } \r
+ }\r
+ TRACE_INFO_WP("\n\r");\r
+}\r
+\r
+/**\r
+ * \brief Dump all register\r
+ * \param pTwid TWI interface\r
+ */\r
+void ov_DumpRegisters16(Twid *pTwid)\r
+{\r
+ uint32_t i;\r
+ uint8_t value;\r
+\r
+ TRACE_INFO_WP("Dump all camera register\n\r");\r
+ for(i = 3000; i <= 0x305C; i++) {\r
+ value = 0;\r
+ ov_read_reg16(pTwid, i, &value);\r
+ TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);\r
+ if( ((i+1)%5) == 0 ) {\r
+ TRACE_INFO_WP("\n\r");\r
+ } \r
+ }\r
+ TRACE_INFO_WP("\n\r");\r
+}\r
+\r
+/**\r
+ * \brief Sequence For correct operation of the sensor\r
+ * \param pTwid TWI interface\r
+ * \return OV type\r
+ */\r
+uint8_t ov_init(Twid *pTwid)\r
+{\r
+ uint16_t id = 0;\r
+ uint8_t ovType;\r
+ ov_reset();\r
+ id = ov_id(pTwid);\r
+ switch (id) {\r
+ case 0x7740: case 0x7742:\r
+ ovType = OV_7740;\r
+ break;\r
+ case 0x9740: case 0x9742:\r
+ ovType = OV_9740;\r
+ break;\r
+ case 0x2642: case 0x2640:\r
+ ovType = OV_2640;\r
+ break;\r
+ case 0x2643: \r
+ ovType = OV_2643;\r
+ break;\r
+ case 0x5640:\r
+ ovType = OV_5640;\r
+ break;\r
+ default:\r
+ ovType = OV_UNKNOWN;\r
+ TRACE_ERROR("Can not support product ID %x \n\r", id);\r
+ break;\r
+ }\r
+ return ovType;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "board.h"\r
+\r
+const static struct capture_size ov_sizes[] = {\r
+// {width, height}\r
+ /// VGA\r
+ { 320, 240 },\r
+ { 640, 360 },\r
+ { 640, 480 },\r
+ // SWVGA\r
+ { 800, 600 },\r
+ /// SXGA\r
+ {1280, 960 },\r
+ {1280, 720 },\r
+ /// UXGA\r
+ {1600, 1200 },\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global Functions\r
+ *----------------------------------------------------------------------------*/\r
+ \r
+/**\r
+ * \brief Configure the OV for a specified image size, pixel format, \r
+ * and frame period.\r
+ */\r
+void ov_configure(Twid *pTwid, uint8_t ovType, uint32_t width, uint32_t heigth)\r
+{\r
+ const struct ov_reg *reg_conf;\r
+ uint8_t goodCaptureSize = 0;\r
+ uint8_t i;\r
+ \r
+ reg_conf = ov5640_yuv_vga;\r
+ TRACE_DEBUG("ovxxx_configure\n\r");\r
+ for( i = 0; i< sizeof(ov_sizes); i++ ) {\r
+ if( ov_sizes[i].width == width ) {\r
+ if( ov_sizes[i].height != heigth ) {\r
+ TRACE_INFO("ov configure vsize not define\n\r");\r
+ }\r
+ else {\r
+ goodCaptureSize = 1;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ if( goodCaptureSize == 0 ) {\r
+ TRACE_ERROR("Problem size\n\r");\r
+ while(1);\r
+ }\r
+ switch (ovType){\r
+ case OV_2640: {\r
+ // Default value\r
+ reg_conf = ov2640_yuv_qvga;\r
+ // common register initialization\r
+ switch(width) {\r
+ case 320: //VGA\r
+ printf("-I- QVGA 640 x 480\n\r");\r
+ reg_conf = ov2640_yuv_qvga;\r
+ break;\r
+ case 640: //VGA\r
+ printf("-I- VGA 640 x 480\n\r");\r
+ reg_conf = ov2640_yuv_vga;\r
+ break;\r
+ default:\r
+ TRACE_DEBUG("ov2640_configure problem\n\r");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+ case OV_7740: {\r
+ // Default value\r
+ reg_conf = ov7740_yuv_vga;\r
+ // common register initialization\r
+ switch(width) {\r
+ case 640: //VGA\r
+ printf("-I- VGA 640 x 480\n\r");\r
+ reg_conf = ov7740_yuv_vga;\r
+ break;\r
+ default:\r
+ TRACE_DEBUG("ov7740_configure problem\n\r");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+ case OV_9740: {\r
+ // Default value\r
+ reg_conf = ov9740_yuv_vga;\r
+ // common register initialization\r
+ switch(width) {\r
+ case 640: //VGA\r
+ printf("-I- VGA 640 x 360\n\r");\r
+ reg_conf = ov9740_yuv_vga;\r
+ break;\r
+ case 1280: //VGA\r
+ printf("-I- VGA 1280 x 720\n\r");\r
+ reg_conf = ov9740_yuv_sxga;\r
+ break;\r
+ default:\r
+ TRACE_DEBUG("ov9740_configure problem\n\r");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+ case OV_2643: {\r
+ // Default value\r
+ reg_conf = ov2643_yuv_vga;\r
+ // common register initialization\r
+ switch(width) {\r
+ case 1600: //UXGA\r
+ printf("-I- UXGA 1600 x 1200 \n\r");\r
+ reg_conf = ov2643_yuv_uxga;\r
+ break;\r
+ case 800: //SWVGA\r
+ printf("-I- SWVGA 800 x 600\n\r");\r
+ reg_conf = ov2643_yuv_swvga;\r
+ break;\r
+ case 640: //VGA\r
+ printf("-I- VGA 640 x 480\n\r");\r
+ reg_conf = ov2643_yuv_vga;\r
+ break;\r
+ default: \r
+ TRACE_DEBUG("ov2643_configure problem\n\r");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+ case OV_5640: {\r
+ // Default value\r
+ reg_conf = ov5640_yuv_vga;\r
+ // common register initialization\r
+ switch(width) {\r
+ case 640: //VGA\r
+ printf("-I- VGA 640 x 480\n\r");\r
+ reg_conf = ov5640_yuv_vga;\r
+ break;\r
+ case 1280: //SXGA\r
+ printf("-I- SXGA 1280 x 720\n\r");\r
+ reg_conf = ov5640_yuv_sxga;\r
+ break;\r
+ default: \r
+ TRACE_DEBUG("ov5640_configure problem\n\r");\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+ if ((ovType == OV_5640) || (ovType == OV_9740))\r
+ ov_write_regs16(pTwid, reg_conf);\r
+ else \r
+ ov_write_regs8(pTwid, reg_conf);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the OV 5640 afc fireware. \r
+ */\r
+void ov_5640Afc_Firmware(Twid *pTwid)\r
+{\r
+ const struct ov_reg *reg_conf;\r
+ reg_conf = ov5640_afc;\r
+ ov_write_regs16(pTwid, reg_conf);\r
+}
\ No newline at end of file
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*\r
+ * ID\r
+ */\r
+\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/* 320*240 */\r
+const struct ov_reg ov2640_yuv_qvga[]= {\r
+{0xff, 0x01},{0x12, 0x80},\r
+{0xff, 0x00},{0x2c, 0xff},{0x2e, 0xdf},\r
+{0xff, 0x01},{0x3c, 0x32},{0x11, 0x00},{0x09, 0x02},\r
+{0x04, 0x28},{0x13, 0xe5},{0x14, 0x48},{0x2c, 0x0c},{0x33, 0x78},{0x3a, 0x33},{0x3b, 0xfb},{0x3e, 0x00},{0x43, 0x11},\r
+{0x16, 0x10},{0x39, 0x02},{0x35, 0x88},{0x22, 0x0a},{0x37, 0x40},{0x23, 0x00},{0x34, 0xa0},{0x36, 0x1a},{0x06, 0x02},\r
+{0x07, 0xc0},{0x0d, 0xb7},{0x0e, 0x01},{0x4c, 0x00},{0x4a, 0x81},{0x21, 0x99},{0x24, 0x3a},{0x25, 0x32},{0x26, 0x82},\r
+{0x5c, 0x00},{0x63, 0x00},{0x5d, 0x55},{0x5e, 0x7d},{0x5f, 0x7d},{0x60, 0x55},{0x61, 0x70},{0x62, 0x80},{0x7c, 0x05},\r
+{0x20, 0x80},{0x28, 0x30},{0x6c, 0x00},{0x6d, 0x80},{0x6e, 0x00},{0x70, 0x02},{0x71, 0x94},{0x73, 0xc1},{0x3d, 0x34},\r
+{0x5a, 0x57},{0x4f, 0xbb},{0x50, 0x9c},\r
+{0xff, 0x00},{0xe5, 0x7f},{0xf9, 0xc0},{0x41, 0x24},{0xe0, 0x14},{0x76, 0xff},\r
+{0x33, 0xa0},{0x42, 0x20},{0x43, 0x18},{0x4c, 0x00},{0x87, 0xd0},{0x88, 0x3f},{0xd7, 0x03},{0xd9, 0x10},{0xd3, 0x82},\r
+{0xc8, 0x08},{0xc9, 0x80},{0x7c, 0x00},{0x7d, 0x02},{0x7c, 0x03},{0x7d, 0x48},{0x7d, 0x48},{0x7c, 0x08},{0x7d, 0x20},\r
+{0x7d, 0x10},{0x7d, 0x0e},{0x90, 0x00},{0x91, 0x0e},{0x91, 0x1a},{0x91, 0x31},{0x91, 0x5a},{0x91, 0x69},{0x91, 0x75},\r
+{0x91, 0x7e},{0x91, 0x88},{0x91, 0x8f},{0x91, 0x96},{0x91, 0xa3},{0x91, 0xaf},{0x91, 0xc4},{0x91, 0xd7},{0x91, 0xe8},\r
+{0x91, 0x20},{0x92, 0x00},{0x93, 0x06},{0x93, 0xe3},{0x93, 0x05},{0x93, 0x05},{0x93, 0x00},{0x93, 0x02},{0x93, 0x00},\r
+{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x96, 0x00},{0x97, 0x08},{0x97, 0x19},\r
+{0x97, 0x02},{0x97, 0x0c},{0x97, 0x24},{0x97, 0x30},{0x97, 0x28},{0x97, 0x26},{0x97, 0x02},{0x97, 0x98},{0x97, 0x80},\r
+{0x97, 0x00},{0x97, 0x00},{0xc3, 0xed},{0xa4, 0x00},{0xa8, 0x00},{0xc5, 0x11},{0xc6, 0x51},{0xbf, 0x80},{0xc7, 0x10},\r
+{0xb6, 0x66},{0xb8, 0xa5},{0xb7, 0x64},{0xb9, 0x7c},{0xb3, 0xaf},{0xb4, 0x97},{0xb5, 0xff},{0xb0, 0xc5},{0xb1, 0x94},\r
+{0xb2, 0x0f},{0xc4, 0x5c},{0xc0, 0xc8},{0xc1, 0x96},{0x86, 0x1d},{0x50, 0x00},{0x51, 0x90},{0x52, 0x18},{0x53, 0x00},\r
+{0x54, 0x00},{0x55, 0x88},{0x57, 0x00},{0x5a, 0x90},{0x5b, 0x18},{0x5c, 0x05},{0xc3, 0xed},{0x7f, 0x00},{0xda, 0x04},\r
+{0xe5, 0x1f},{0xe1, 0x67},{0xe0, 0x00},{0xdd, 0xff},{0x05, 0x00},\r
+{0xff, 0x01},{0x11, 0x01},\r
+{0xff, 0x01},{0x12, 0x40},\r
+{0x17, 0x11},{0x18, 0x43},{0x19, 0x00},{0x1a, 0x4b},{0x32, 0x09},{0x4f, 0xca},{0x50, 0xa8},{0x5a, 0x23},{0x6d, 0x00},\r
+{0x3d, 0x38},{0x39, 0x12},{0x35, 0xda},{0x22, 0x1a},{0x37, 0xc3},{0x23, 0x00},{0x34, 0xc0},{0x36, 0x1a},{0x06, 0x88},\r
+{0x07, 0xc0},{0x0d, 0x87},{0x0e, 0x41},{0x4c, 0x00},{0x48, 0x00},{0x5B, 0x00},{0x42, 0x03},\r
+{0xff, 0x00},{0xe0, 0x04},\r
+{0xc0, 0x64},{0xc1, 0x4B},{0x8c, 0x00},{0x86, 0x1D},{0xd3, 0x82},{0xe0, 0x00},\r
+{0xff, 0x00},\r
+{0xc0, 0x64},{0xc1, 0x4B},{0x8c, 0x00}, // Xiao: HSIZE 0x64*8 = 800, VSIZE 0x4b*8 = 600\r
+{0x86, 0x3D},\r
+{0x50, 0x89}, // LP_DP, V_DIV 1, H_DIV 1\r
+{0x51, 0xC8},{0x52, 0x96},{0x53, 0x00},{0x54, 0x00},{0x55, 0x00}, // Xiao: HSIZE 0xC8(200)*4 = 800, VSIZE 0x96(150)*4 = 600\r
+{0x5a, 0x50},{0x5b, 0x3C},{0x5c, 0x00}, // Xiao: ZMOW 0x50(80)*4 = 320, ZMOH 0x3C(60)*4 = 240\r
+{0xd3, 0x04},\r
+{0xFF, 0x00},{0xE0, 0x04},{0xE1, 0x67},{0xD7, 0x01},{0xDA, 0x00},{0xD3, 0x82},{0xE0, 0x00},\r
+{0xFF, 0xFF}\r
+};\r
+\r
+const struct ov_reg ov2640_yuv_vga[]= {\r
+ {0xff, 0x01}, //dsp\r
+ {0x12, 0x80}, //reset\r
+ {0xff, 0x00}, //sensor\r
+ {0x2c, 0xff}, //?\r
+ {0x2e, 0xdf}, //ADDVSH, VSYNC msb=223\r
+ {0xff, 0x01}, //dsp\r
+ {0x3c, 0x32}, //?\r
+ {0x11, 0x00}, //clock rate off\r
+ {0x09, 0x02}, //2 capablity + standby mode \r
+ {0x04, 0x28}, //? ??????????????????????????????????\r
+ {0x13, 0xe5}, //\r
+ {0x14, 0x48}, //Auto agc\r
+ {0x2c, 0x0c}, //?\r
+ {0x33, 0x78}, //? \r
+ {0x3a, 0x33}, //?\r
+ {0x3b, 0xfb}, //?\r
+ {0x3e, 0x00}, //? \r
+ {0x43, 0x11}, //?\r
+ {0x16, 0x10}, //?\r
+ {0x39, 0x02}, //?\r
+ {0x35, 0x88}, //?\r
+ {0x22, 0x0a}, //?\r
+ {0x37, 0x40}, //?\r
+ {0x23, 0x00}, //?\r
+ {0x34, 0xa0}, //startpoint 0\r
+ {0x36, 0x1a}, //? XXXXXXXXXXXXXXXX\r
+ {0x06, 0x02}, //?\r
+ {0x07, 0xc0}, //?\r
+ {0x0d, 0xb7}, //?\r
+ {0x0e, 0x01}, //?\r
+ {0x4c, 0x00}, //?\r
+ {0x4a, 0x81}, //?\r
+ {0x21, 0x99}, //?\r
+ {0x24, 0x3a}, // Luminance high\r
+ {0x25, 0x32}, // Luminance low\r
+ //{0x24, 0x10}, // Luminance high\r
+ //{0x25, 0x03}, // Luminance low\r
+\r
+ {0x26, 0xF3}, // Fast mode large Step Range Threshold \r
+ {0x5c, 0x00}, //?\r
+ {0x63, 0x00}, //?\r
+ {0x5d, 0x55}, //zone\r
+ {0x5e, 0x7d}, //zone\r
+ {0x5f, 0x7d}, //zone\r
+ {0x60, 0x55}, //zone\r
+ {0x61, 0x70}, //Histogram low\r
+ {0x62, 0x80}, //Histogram high\r
+ {0x7c, 0x05}, //?\r
+ {0x20, 0x80}, //?\r
+ {0x28, 0x30}, //?\r
+ {0x6c, 0x00}, //?\r
+ {0x6d, 0x80}, //?\r
+ {0x6e, 0x00}, //?\r
+ {0x70, 0x02}, //?\r
+ {0x71, 0x94}, //?\r
+ {0x73, 0xc1}, //?\r
+ {0x3d, 0x34}, //?\r
+ {0x5a, 0x57}, //?\r
+ {0x4f, 0xbb}, //50Hz\r
+ {0x50, 0x9c}, //60Hz\r
+\r
+ {0xff, 0x00}, //dsp\r
+ {0xe5, 0x7f}, //?\r
+ {0xf9, 0xc0}, //MicroC reset,Boot\r
+ {0x41, 0x24}, //?\r
+ {0xe0, 0x14}, //JPEG,DVP reset\r
+ {0x76, 0xff}, //?\r
+ {0x33, 0xa0}, //?\r
+ {0x42, 0x20}, //?\r
+ {0x43, 0x18}, //?\r
+ {0x4c, 0x00}, //?\r
+ {0x87, 0xd0}, //Module Enable BPC+WPC 11010000\r
+ {0x88, 0x3f}, //?\r
+ {0xd7, 0x03}, //?\r
+ {0xd9, 0x10}, //?\r
+ {0xd3, 0x82}, //Auto mode \r
+ {0xc8, 0x08}, //?\r
+ {0xc9, 0x80}, //?\r
+ {0x7c, 0x00}, //SDE indirect register access: address \r
+ {0x7d, 0x02}, //SDE indirect register data \r
+ {0x7c, 0x03}, //\r
+ {0x7d, 0x48}, //\r
+ {0x7d, 0x48}, //\r
+ {0x7c, 0x08}, //\r
+ {0x7d, 0x20}, //\r
+ {0x7d, 0x10}, // \r
+ {0x7d, 0x0e}, //\r
+ {0x90, 0x00}, //?\r
+ {0x91, 0x0e}, //?\r
+ {0x91, 0x1a}, //?\r
+ {0x91, 0x31}, //?\r
+ {0x91, 0x5a}, //?\r
+ {0x91, 0x69}, //?\r
+ {0x91, 0x75}, //?\r
+ {0x91, 0x7e}, //?\r
+ {0x91, 0x88}, //?\r
+ {0x91, 0x8f}, //?\r
+ {0x91, 0x96}, //?\r
+ {0x91, 0xa3}, //?\r
+ {0x91, 0xaf}, //?\r
+ {0x91, 0xc4}, //?\r
+ {0x91, 0xd7}, //?\r
+ {0x91, 0xe8}, //?\r
+ {0x91, 0x20}, //?\r
+ {0x92, 0x00}, //?\r
+ {0x93, 0x06}, //?\r
+ {0x93, 0xe3}, //?\r
+ {0x93, 0x05}, //?\r
+ {0x93, 0x05}, //?\r
+ {0x93, 0x00}, //?\r
+ {0x93, 0x02}, //?\r
+ {0x93, 0x00}, //? \r
+ {0x93, 0x00}, //? \r
+ {0x93, 0x00}, //?\r
+ {0x93, 0x00}, //?\r
+ {0x93, 0x00}, //?\r
+ {0x93, 0x00}, //?\r
+ {0x93, 0x00}, //?\r
+ {0x96, 0x00}, //?\r
+ {0x97, 0x08}, //?\r
+ {0x97, 0x19}, //?\r
+ {0x97, 0x02}, //?\r
+ {0x97, 0x0c}, //?\r
+ {0x97, 0x24}, //?\r
+ {0x97, 0x30}, //?\r
+ {0x97, 0x28}, //?\r
+ {0x97, 0x26}, //?\r
+ {0x97, 0x02}, //?\r
+ {0x97, 0x98}, //?\r
+ {0x97, 0x80}, //?\r
+ {0x97, 0x00}, //?\r
+ {0x97, 0x00}, //?\r
+ {0xc3, 0xed}, //Module enable \r
+ {0xa4, 0x00}, //?\r
+ {0xa8, 0x00}, //?\r
+ {0xc5, 0x11}, //?\r
+ {0xc6, 0x51}, //?\r
+ {0xbf, 0x80}, //?\r
+ {0xc7, 0x10}, //?\r
+ {0xb6, 0x66}, //?\r
+ {0xb8, 0xa5}, //?\r
+ {0xb7, 0x64}, //?\r
+ {0xb9, 0x7c}, //?\r
+ {0xb3, 0xaf}, //?\r
+ {0xb4, 0x97}, //?\r
+ {0xb5, 0xff}, //?\r
+ {0xb0, 0xc5}, //?\r
+ {0xb1, 0x94}, //?\r
+ {0xb2, 0x0f}, //?\r
+ {0xc4, 0x5c}, //?\r
+ {0xc0, 0xc8}, // HSIZE8[7:0] 1600\r
+ {0xc1, 0x96}, // VSIZE8[7:0] 1200\r
+ {0x86, 0x1d}, //Module enable \r
+ {0x50, 0x00}, //?\r
+ {0x51, 0x90}, //H_SIZE[7:0] (real/4) 1600\r
+ {0x52, 0x18}, //V_SIZE[7:0] (real/4) 1120\r
+ {0x53, 0x00}, //OFFSET_X[7:0]\r
+ {0x54, 0x00}, //OFFSET_Y[7:0]\r
+ {0x55, 0x88}, //V_SIZE[8]=1 H_SIZE[8]\r
+ {0x57, 0x00}, //?\r
+ {0x5a, 0x90}, //OUTW\r
+ {0x5b, 0x18}, //OUTH\r
+ {0x5c, 0x05}, //OUTW8 ,OUTH8\r
+ {0xc3, 0xed}, //\r
+ {0x7f, 0x00}, //?\r
+ {0xda, 0x04}, //Image output format select ------ RAW \r
+ {0xe5, 0x1f}, //? \r
+ {0xe1, 0x67}, //?\r
+ {0xe0, 0x00}, //Reset\r
+ {0xdd, 0xff}, //?\r
+ {0x05, 0x00}, //Bypass DSP no\r
+ {0xC2, 0x08 | 0x04 | 0x02 },\r
+\r
+ {0xff, 0x01}, //Sensor\r
+ {0x11, 0x01}, //?\r
+ {0xff, 0x01}, //Sensor\r
+ {0x12, 0x40}, //Preview mode \r
+ {0x17, 0x11}, //?\r
+ {0x18, 0x43}, //?\r
+ {0x19, 0x00}, //?\r
+ {0x1a, 0x4b}, //?\r
+ {0x32, 0x09}, //?\r
+ {0x4f, 0xca}, //?\r
+ {0x50, 0xa8}, //10 101 000 V_DIVDER = 5\r
+ {0x5a, 0x23}, // OUTW 23\r
+ {0x6d, 0x00}, //?\r
+ {0x3d, 0x38}, //?\r
+ {0x39, 0x12}, //?\r
+ {0x35, 0xda}, //?\r
+ {0x22, 0x1a}, //?\r
+ {0x37, 0xc3}, //?\r
+ {0x23, 0x00}, //?\r
+ {0x34, 0xc0}, //?\r
+ {0x36, 0x1a}, //?\r
+ {0x06, 0x88}, //?\r
+ {0x07, 0xc0}, //?\r
+ {0x0d, 0x87}, //?\r
+ {0x0e, 0x41}, //?\r
+ {0x4c, 0x00}, //?\r
+ {0x48, 0x00}, //?\r
+ {0x5B, 0x00}, //OUTH\r
+ {0x42, 0x03}, //?\r
+ {0xff, 0x00}, //DSP\r
+\r
+ {0xe0, 0x04}, //Reset DVP\r
+ {0xc0, 0x64}, // HSIZE8[7:0] 400\r
+ {0xc1, 0x4B}, // VSIZE8[7:0] 300\r
+ {0x8c, 0x00}, //?\r
+ {0x86, 0x1D}, //Modle enable\r
+ {0xd3, 0x82}, //Auto mode DVP PCLK=2\r
+ {0xe0, 0x00}, //Reset\r
+\r
+ {0xff, 0x00}, //DSP\r
+ {0xc0, 0x64}, // HSIZE8[7:0] 400\r
+ {0xc1, 0x4B}, // VSIZE8[7:0] 300\r
+ {0x8c, 0x00}, //?\r
+ {0x86, 0x3D}, //?\r
+ {0x50, 0x00}, //?\r
+ {0x51, 0xC8}, //H_SIZE[7:0] (real/4) 800\r
+ {0x52, 0x96}, //V_SIZE[7:0] (real/4) 600\r
+ {0x53, 0x00}, //OFFSET\r
+ {0x54, 0x00}, //OFFSET\r
+ {0x55, 0x00}, //H_SIZE[8],V_SIZE[8]\r
+ {0x5a, 0xA0}, //OUTW[0-7] 160?\r
+ {0x5b, 0x78}, //OUTH[0-7] 120?\r
+ {0x5c, 0x00}, //OUTW8,OUTH8\r
+ {0xd3, 0x04}, //?\r
+ {0xFF, 0x00},\r
+ {0xE0, 0x04},\r
+ {0xE1, 0x67},\r
+ {0xD7, 0x01},\r
+ {0xDA, 0x00}, //Image output format select ------ YUV422\r
+ {0xD3, 0x82},\r
+ {0xE0, 0x00},\r
+ {0xFF, 0xFF}\r
+ };\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*\r
+ * ID\r
+ */\r
+#define MANUFACTURER_ID 0x7FA2\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+const struct ov_reg ov2643_yuv_uxga[]= {\r
+ {0x12, 0x80},\r
+ {0xc3, 0x1f},\r
+ {0xc4, 0xff},\r
+ {0x3d, 0x48},\r
+ {0xdd, 0xa5},\r
+ {0x0e, 0xb7},\r
+ {0x10, 0x0a},\r
+ {0x11, 0x00},\r
+ {0x0f, 0x14},\r
+ {0x21, 0x25},\r
+ {0x23, 0x0c},\r
+ {0x12, 0x08},\r
+ {0x39, 0x10},\r
+ {0xcd, 0x12},\r
+ {0x13, 0xff},\r
+ {0x14, 0xa7},\r
+ {0x15, 0x42},\r
+ {0x3c, 0xa4},\r
+ {0x18, 0x60},\r
+ {0x19, 0x50},\r
+ {0x1a, 0xe2},\r
+ {0x37, 0xe8},\r
+ {0x16, 0x90},\r
+ {0x43, 0x00},\r
+ {0x40, 0xfb},\r
+ {0xa9, 0x44},\r
+ {0x2f, 0xec},\r
+ {0x35, 0x10},\r
+ {0x36, 0x10},\r
+ {0x0c, 0x00},\r
+ {0x0d, 0x00},\r
+ {0xd0, 0x93},\r
+ {0xdc, 0x2b},\r
+ {0xd9, 0x41},\r
+ {0xd3, 0x02},\r
+ {0x3d, 0x08},\r
+ {0x0c, 0x00},\r
+ {0x18, 0x2c},\r
+ {0x19, 0x24},\r
+ {0x1a, 0x71},\r
+ {0x9b, 0x69},\r
+ {0x9c, 0x7d},\r
+ {0x9d, 0x7d},\r
+ {0x9e, 0x69},\r
+ {0x35, 0x04},\r
+ {0x36, 0x04},\r
+ {0x65, 0x12},\r
+ {0x66, 0x20},\r
+ {0x67, 0x39},\r
+ {0x68, 0x4e},\r
+ {0x69, 0x62},\r
+ {0x6a, 0x74},\r
+ {0x6b, 0x85},\r
+ {0x6c, 0x92},\r
+ {0x6d, 0x9e},\r
+ {0x6e, 0xb2},\r
+ {0x6f, 0xc0},\r
+ {0x70, 0xcc},\r
+ {0x71, 0xe0},\r
+ {0x72, 0xee},\r
+ {0x73, 0xf6},\r
+ {0x74, 0x11},\r
+ {0xab, 0x20},\r
+ {0xac, 0x5b},\r
+ {0xad, 0x05},\r
+ {0xae, 0x1b},\r
+ {0xaf, 0x76},\r
+ {0xb0, 0x90},\r
+ {0xb1, 0x90},\r
+ {0xb2, 0x8c},\r
+ {0xb3, 0x04},\r
+ {0xb4, 0x98},\r
+ {0x4c, 0x03},\r
+ {0x4d, 0x30},\r
+ {0x4e, 0x02},\r
+ {0x4f, 0x5c},\r
+ {0x50, 0x56},\r
+ {0x51, 0x00},\r
+ {0x52, 0x66},\r
+ {0x53, 0x03},\r
+ {0x54, 0x30},\r
+ {0x55, 0x02},\r
+ {0x56, 0x5c},\r
+ {0x57, 0x40},\r
+ {0x58, 0x00},\r
+ {0x59, 0x66},\r
+ {0x5a, 0x03},\r
+ {0x5b, 0x20},\r
+ {0x5c, 0x02},\r
+ {0x5d, 0x5c},\r
+ {0x5e, 0x3a},\r
+ {0x5f, 0x00},\r
+ {0x60, 0x66},\r
+ {0x41, 0x1f},\r
+ {0xb5, 0x01},\r
+ {0xb6, 0x02},\r
+ {0xb9, 0x40},\r
+ {0xba, 0x28},\r
+ {0xbf, 0x0c},\r
+ {0xc0, 0x3e},\r
+ {0xa3, 0x0a},\r
+ {0xa4, 0x0f},\r
+ {0xa5, 0x09},\r
+ {0xa6, 0x16},\r
+ {0x9f, 0x0a},\r
+ {0xa0, 0x0f},\r
+ {0xa7, 0x0a},\r
+ {0xa8, 0x0f},\r
+ {0xa1, 0x10},\r
+ {0xa2, 0x04},\r
+ {0xa9, 0x04},\r
+ {0xaa, 0xa6},\r
+ {0x75, 0x6a},\r
+ {0x76, 0x11},\r
+ {0x77, 0x92},\r
+ {0x78, 0x21},\r
+ {0x79, 0xe1},\r
+ {0x7a, 0x02},\r
+ {0x7c, 0x05},\r
+ {0x7d, 0x08},\r
+ {0x7e, 0x08},\r
+ {0x7f, 0x7c},\r
+ {0x80, 0x58},\r
+ {0x81, 0x2a},\r
+ {0x82, 0xc5},\r
+ {0x83, 0x46},\r
+ {0x84, 0x3a},\r
+ {0x85, 0x54},\r
+ {0x86, 0x44},\r
+ {0x87, 0xf8},\r
+ {0x88, 0x08},\r
+ {0x89, 0x70},\r
+ {0x8a, 0xf0},\r
+ {0x8b, 0xf0},\r
+ {0x90, 0xe3},\r
+ {0x93, 0x10},\r
+ {0x94, 0x20},\r
+ {0x95, 0x10},\r
+ {0x96, 0x18},\r
+ {0x0f, 0x34},\r
+\r
+ {0x12, 0x80},\r
+ {0xc3, 0x1f},\r
+ {0xc4, 0xff},\r
+ {0x3d, 0x48},\r
+ {0xdd, 0xa5},\r
+ {0x0e, 0xb4},\r
+ {0x10, 0x0a},\r
+ {0x11, 0x00},\r
+ {0x0f, 0x14},\r
+ {0x21, 0x25},\r
+ {0x23, 0x0c},\r
+ {0x12, 0x08},\r
+ {0x39, 0x10},\r
+ {0xcd, 0x12},\r
+ {0x13, 0xff},\r
+ {0x14, 0xa7},\r
+ {0x15, 0x42},\r
+ {0x3c, 0xa4},\r
+ {0x18, 0x60},\r
+ {0x19, 0x50},\r
+ {0x1a, 0xe2},\r
+ {0x37, 0xe8},\r
+ {0x16, 0x90},\r
+ {0x43, 0x00},\r
+ {0x40, 0xfb},\r
+ {0xa9, 0x44},\r
+ {0x2f, 0xec},\r
+ {0x35, 0x10},\r
+ {0x36, 0x10},\r
+ {0x0c, 0x00},\r
+ {0x0d, 0x00},\r
+ {0xd0, 0x93},\r
+ {0xdc, 0x2b},\r
+ {0xd9, 0x41},\r
+ {0xd3, 0x02},\r
+ {0x3d, 0x08},\r
+ {0x0c, 0x00},\r
+ {0x18, 0x2c},\r
+ {0x19, 0x24},\r
+ {0x1a, 0x71},\r
+ {0x9b, 0x69},\r
+ {0x9c, 0x7d},\r
+ {0x9d, 0x7d},\r
+ {0x9e, 0x69},\r
+ {0x35, 0x04},\r
+ {0x36, 0x04},\r
+ {0x65, 0x12},\r
+ {0x66, 0x20},\r
+ {0x67, 0x39},\r
+ {0x68, 0x4e},\r
+ {0x69, 0x62},\r
+ {0x6a, 0x74},\r
+ {0x6b, 0x85},\r
+ {0x6c, 0x92},\r
+ {0x6d, 0x9e},\r
+ {0x6e, 0xb2},\r
+ {0x6f, 0xc0},\r
+ {0x70, 0xcc},\r
+ {0x71, 0xe0},\r
+ {0x72, 0xee},\r
+ {0x73, 0xf6},\r
+ {0x74, 0x11},\r
+ {0xab, 0x20},\r
+ {0xac, 0x5b},\r
+ {0xad, 0x05},\r
+ {0xae, 0x1b},\r
+ {0xaf, 0x76},\r
+ {0xb0, 0x90},\r
+ {0xb1, 0x90},\r
+ {0xb2, 0x8c},\r
+ {0xb3, 0x04},\r
+ {0xb4, 0x98},\r
+ {0x4c, 0x03},\r
+ {0x4d, 0x30},\r
+ {0x4e, 0x02},\r
+ {0x4f, 0x5c},\r
+ {0x50, 0x56},\r
+ {0x51, 0x00},\r
+ {0x52, 0x66},\r
+ {0x53, 0x03},\r
+ {0x54, 0x30},\r
+ {0x55, 0x02},\r
+ {0x56, 0x5c},\r
+ {0x57, 0x40},\r
+ {0x58, 0x00},\r
+ {0x59, 0x66},\r
+ {0x5a, 0x03},\r
+ {0x5b, 0x20},\r
+ {0x5c, 0x02},\r
+ {0x5d, 0x5c},\r
+ {0x5e, 0x3a},\r
+ {0x5f, 0x00},\r
+ {0x60, 0x66},\r
+ {0x41, 0x1f},\r
+ {0xb5, 0x01},\r
+ {0xb6, 0x02},\r
+ {0xb9, 0x40},\r
+ {0xba, 0x28},\r
+ {0xbf, 0x0c},\r
+ {0xc0, 0x3e},\r
+ {0xa3, 0x0a},\r
+ {0xa4, 0x0f},\r
+ {0xa5, 0x09},\r
+ {0xa6, 0x16},\r
+ {0x9f, 0x0a},\r
+ {0xa0, 0x0f},\r
+ {0xa7, 0x0a},\r
+ {0xa8, 0x0f},\r
+ {0xa1, 0x10},\r
+ {0xa2, 0x04},\r
+ {0xa9, 0x04},\r
+ {0xaa, 0xa6},\r
+ {0x75, 0x6a},\r
+ {0x76, 0x11},\r
+ {0x77, 0x92},\r
+ {0x78, 0x21},\r
+ {0x79, 0xe1},\r
+ {0x7a, 0x02},\r
+ {0x7c, 0x05},\r
+ {0x7d, 0x08},\r
+ {0x7e, 0x08},\r
+ {0x7f, 0x7c},\r
+ {0x80, 0x58},\r
+ {0x81, 0x2a},\r
+ {0x82, 0xc5},\r
+ {0x83, 0x46},\r
+ {0x84, 0x3a},\r
+ {0x85, 0x54},\r
+ {0x86, 0x44},\r
+ {0x87, 0xf8},\r
+ {0x88, 0x08},\r
+ {0x89, 0x70},\r
+ {0x8a, 0xf0},\r
+ {0x8b, 0xf0},\r
+ {0x90, 0xe3},\r
+ {0x93, 0x10},\r
+ {0x94, 0x20},\r
+ {0x95, 0x10},\r
+ {0x96, 0x18},\r
+ {0x0f, 0x34},\r
+ {0xFF, 0xFF}\r
+};\r
+\r
+const struct ov_reg ov2643_yuv_swvga[]= {\r
+{0x12, 0x80},\r
+ {0xc3, 0x1f},\r
+ {0xc4, 0xff},\r
+ {0x3d, 0x48},\r
+ {0xdd, 0xa5},\r
+ {0x0e, 0xb4},\r
+ {0x10, 0x0a},\r
+ {0x11, 0x00},\r
+ {0x0f, 0x14},\r
+ {0x21, 0x25},\r
+ {0x23, 0x0c},\r
+ {0x12, 0x08},\r
+ {0x39, 0x10},\r
+ {0xcd, 0x12},\r
+ {0x13, 0xff},\r
+ {0x14, 0xa7},\r
+ {0x15, 0x42},\r
+ {0x3c, 0xa4},\r
+ {0x18, 0x60},\r
+ {0x19, 0x50},\r
+ {0x1a, 0xe2},\r
+ {0x37, 0xe8},\r
+ {0x16, 0x90},\r
+ {0x43, 0x00},\r
+ {0x40, 0xfb},\r
+ {0xa9, 0x44},\r
+ {0x2f, 0xec},\r
+ {0x35, 0x10},\r
+ {0x36, 0x10},\r
+ {0x0c, 0x00},\r
+ {0x0d, 0x00},\r
+ {0xd0, 0x93},\r
+ {0xdc, 0x2b},\r
+ {0xd9, 0x41},\r
+ {0xd3, 0x02},\r
+ {0x3d, 0x08},\r
+ {0x0c, 0x00},\r
+ {0x18, 0x2c},\r
+ {0x19, 0x24},\r
+ {0x1a, 0x71},\r
+ {0x9b, 0x69},\r
+ {0x9c, 0x7d},\r
+ {0x9d, 0x7d},\r
+ {0x9e, 0x69},\r
+ {0x35, 0x04},\r
+ {0x36, 0x04},\r
+ {0x65, 0x12},\r
+ {0x66, 0x20},\r
+ {0x67, 0x39},\r
+ {0x68, 0x4e},\r
+ {0x69, 0x62},\r
+ {0x6a, 0x74},\r
+ {0x6b, 0x85},\r
+ {0x6c, 0x92},\r
+ {0x6d, 0x9e},\r
+ {0x6e, 0xb2},\r
+ {0x6f, 0xc0},\r
+ {0x70, 0xcc},\r
+ {0x71, 0xe0},\r
+ {0x72, 0xee},\r
+ {0x73, 0xf6},\r
+ {0x74, 0x11},\r
+ {0xab, 0x20},\r
+ {0xac, 0x5b},\r
+ {0xad, 0x05},\r
+ {0xae, 0x1b},\r
+ {0xaf, 0x76},\r
+ {0xb0, 0x90},\r
+ {0xb1, 0x90},\r
+ {0xb2, 0x8c},\r
+ {0xb3, 0x04},\r
+ {0xb4, 0x98},\r
+ {0x4c, 0x03},\r
+ {0x4d, 0x30},\r
+ {0x4e, 0x02},\r
+ {0x4f, 0x5c},\r
+ {0x50, 0x56},\r
+ {0x51, 0x00},\r
+ {0x52, 0x66},\r
+ {0x53, 0x03},\r
+ {0x54, 0x30},\r
+ {0x55, 0x02},\r
+ {0x56, 0x5c},\r
+ {0x57, 0x40},\r
+ {0x58, 0x00},\r
+ {0x59, 0x66},\r
+ {0x5a, 0x03},\r
+ {0x5b, 0x20},\r
+ {0x5c, 0x02},\r
+ {0x5d, 0x5c},\r
+ {0x5e, 0x3a},\r
+ {0x5f, 0x00},\r
+ {0x60, 0x66},\r
+ {0x41, 0x1f},\r
+ {0xb5, 0x01},\r
+ {0xb6, 0x02},\r
+ {0xb9, 0x40},\r
+ {0xba, 0x28},\r
+ {0xbf, 0x0c},\r
+ {0xc0, 0x3e},\r
+ {0xa3, 0x0a},\r
+ {0xa4, 0x0f},\r
+ {0xa5, 0x09},\r
+ {0xa6, 0x16},\r
+ {0x9f, 0x0a},\r
+ {0xa0, 0x0f},\r
+ {0xa7, 0x0a},\r
+ {0xa8, 0x0f},\r
+ {0xa1, 0x10},\r
+ {0xa2, 0x04},\r
+ {0xa9, 0x04},\r
+ {0xaa, 0xa6},\r
+ {0x75, 0x6a},\r
+ {0x76, 0x11},\r
+ {0x77, 0x92},\r
+ {0x78, 0x21},\r
+ {0x79, 0xe1},\r
+ {0x7a, 0x02},\r
+ {0x7c, 0x05},\r
+ {0x7d, 0x08},\r
+ {0x7e, 0x08},\r
+ {0x7f, 0x7c},\r
+ {0x80, 0x58},\r
+ {0x81, 0x2a},\r
+ {0x82, 0xc5},\r
+ {0x83, 0x46},\r
+ {0x84, 0x3a},\r
+ {0x85, 0x54},\r
+ {0x86, 0x44},\r
+ {0x87, 0xf8},\r
+ {0x88, 0x08},\r
+ {0x89, 0x70},\r
+ {0x8a, 0xf0},\r
+ {0x8b, 0xf0},\r
+ {0x90, 0xe3},\r
+ {0x93, 0x10},\r
+ {0x94, 0x20},\r
+ {0x95, 0x10},\r
+ {0x96, 0x18},\r
+ {0x0f, 0x34},\r
+\r
+ {0x3d, 0x48},\r
+ {0x0e, 0xb8},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x20, 0x01},\r
+ {0x21, 0x98},\r
+ {0x22, 0x00},\r
+ {0x23, 0x06},\r
+ {0x24, 0x32},\r
+ {0x25, 0x04},\r
+ {0x26, 0x25},\r
+ {0x27, 0x84},\r
+ {0x28, 0x40},\r
+ {0x29, 0x04},\r
+ {0x2a, 0xce},\r
+ {0x2b, 0x02},\r
+ {0x2c, 0x8a},\r
+ {0x12, 0x09},\r
+ {0x39, 0xd0},\r
+ {0xcd, 0x13},\r
+ {0xde, 0x7c},\r
+ {0x3d, 0x08},\r
+ {0x15, 0x42},\r
+ {0xde, 0x7c},\r
+ {0x0f, 0x24},\r
+ {0xFF, 0xFF}\r
+};\r
+\r
+const struct ov_reg ov2643_yuv_vga[]= {\r
+ {0x12, 0x80},\r
+ {0xc3, 0x1f},\r
+ {0xc4, 0xff},\r
+ {0x3d, 0x48},\r
+ {0xdd, 0xa5},\r
+ {0x0e, 0xb7},\r
+ {0x10, 0x0a},\r
+ {0x11, 0x00},\r
+ {0x0f, 0x14},\r
+ {0x21, 0x25},\r
+ {0x23, 0x0c},\r
+ {0x12, 0x08},\r
+ {0x39, 0x10},\r
+ {0xcd, 0x12},\r
+ {0x13, 0xff},\r
+ {0x14, 0xa7},\r
+ {0x15, 0x42},\r
+ {0x3c, 0xa4},\r
+ {0x18, 0x60},\r
+ {0x19, 0x50},\r
+ {0x1a, 0xe2},\r
+ {0x37, 0xe8},\r
+ {0x16, 0x90},\r
+ //{0x43, 0xC0},\r
+ {0x43, 0x00},\r
+ {0x40, 0xfb},\r
+ {0xa9, 0x44},\r
+ {0x2f, 0xec},\r
+ {0x35, 0x10},\r
+ {0x36, 0x10},\r
+ {0x0c, 0x00},\r
+ {0x0d, 0x00},\r
+ {0xd0, 0x93},\r
+ {0xdc, 0x2b},\r
+ {0xd9, 0x41},\r
+ {0xd3, 0x02},\r
+ {0x3d, 0x08},\r
+ {0x0c, 0x00},\r
+ {0x18, 0x2c},\r
+ {0x19, 0x24},\r
+ {0x1a, 0x71},\r
+ {0x9b, 0x69},\r
+ {0x9c, 0x7d},\r
+ {0x9d, 0x7d},\r
+ {0x9e, 0x69},\r
+ {0x35, 0x04},\r
+ {0x36, 0x04},\r
+ {0x65, 0x12},\r
+ {0x66, 0x20},\r
+ {0x67, 0x39},\r
+ {0x68, 0x4e},\r
+ {0x69, 0x62},\r
+ {0x6a, 0x74},\r
+ {0x6b, 0x85},\r
+ {0x6c, 0x92},\r
+ {0x6d, 0x9e},\r
+ {0x6e, 0xb2},\r
+ {0x6f, 0xc0},\r
+ {0x70, 0xcc},\r
+ {0x71, 0xe0},\r
+ {0x72, 0xee},\r
+ {0x73, 0xf6},\r
+ {0x74, 0x11},\r
+ {0xab, 0x20},\r
+ {0xac, 0x5b},\r
+ {0xad, 0x05},\r
+ {0xae, 0x1b},\r
+ {0xaf, 0x76},\r
+ {0xb0, 0x90},\r
+ {0xb1, 0x90},\r
+ {0xb2, 0x8c},\r
+ {0xb3, 0x04},\r
+ {0xb4, 0x98},\r
+ {0x4c, 0x03},\r
+ {0x4d, 0x30},\r
+ {0x4e, 0x02},\r
+ {0x4f, 0x5c},\r
+ {0x50, 0x56},\r
+ {0x51, 0x00},\r
+ {0x52, 0x66},\r
+ {0x53, 0x03},\r
+ {0x54, 0x30},\r
+ {0x55, 0x02},\r
+ {0x56, 0x5c},\r
+ {0x57, 0x40},\r
+ {0x58, 0x00},\r
+ {0x59, 0x66},\r
+ {0x5a, 0x03},\r
+ {0x5b, 0x20},\r
+ {0x5c, 0x02},\r
+ {0x5d, 0x5c},\r
+ {0x5e, 0x3a},\r
+ {0x5f, 0x00},\r
+ {0x60, 0x66},\r
+ {0x41, 0x1f},\r
+ {0xb5, 0x01},\r
+ {0xb6, 0x02},\r
+ {0xb9, 0x40},\r
+ {0xba, 0x28},\r
+ {0xbf, 0x0c},\r
+ {0xc0, 0x3e},\r
+ {0xa3, 0x0a},\r
+ {0xa4, 0x0f},\r
+ {0xa5, 0x09},\r
+ {0xa6, 0x16},\r
+ {0x9f, 0x0a},\r
+ {0xa0, 0x0f},\r
+ {0xa7, 0x0a},\r
+ {0xa8, 0x0f},\r
+ {0xa1, 0x10},\r
+ {0xa2, 0x04},\r
+ {0xa9, 0x04},\r
+ {0xaa, 0xa6},\r
+ {0x75, 0x6a},\r
+ {0x76, 0x11},\r
+ {0x77, 0x92},\r
+ {0x78, 0x21},\r
+ {0x79, 0xe1},\r
+ {0x7a, 0x02},\r
+ {0x7c, 0x05},\r
+ {0x7d, 0x08},\r
+ {0x7e, 0x08},\r
+ {0x7f, 0x7c},\r
+ {0x80, 0x58},\r
+ {0x81, 0x2a},\r
+ {0x82, 0xc5},\r
+ {0x83, 0x46},\r
+ {0x84, 0x3a},\r
+ {0x85, 0x54},\r
+ {0x86, 0x44},\r
+ {0x87, 0xf8},\r
+ {0x88, 0x08},\r
+ {0x89, 0x70},\r
+ {0x8a, 0xf0},\r
+ {0x8b, 0xf0}, \r
+ {0x90, 0xe3},\r
+ {0x93, 0x10},\r
+ {0x94, 0x20},\r
+ {0x95, 0x10},\r
+ {0x96, 0x18},\r
+ {0x0f, 0x34},\r
+\r
+ {0x13, 0x00},\r
+ {0x3d, 0x48}, \r
+ {0x0e, 0xb8}, \r
+ {0x20, 0x02}, \r
+ {0x21, 0x18}, \r
+ {0x22, 0x00}, \r
+ {0x23, 0x42},\r
+ {0x24, 0x28}, \r
+ {0x25, 0x04},\r
+ {0x26, 0x1e}, \r
+ {0x27, 0x04},\r
+ {0x28, 0x40},\r
+ {0x29, 0x04},\r
+ {0x2a, 0xce},\r
+ {0x2b, 0x02},\r
+ {0x2c, 0x8a},\r
+ //YUV\r
+ {0x12, 0x09},\r
+ //RGB\r
+ //{0x12, 0x05},\r
+ \r
+ \r
+ {0x39, 0xd0},\r
+ {0xcd, 0x13},\r
+ {0xde, 0x7c},\r
+ {0x3d, 0x08},\r
+ {0x13, 0xff},\r
+ {0x15, 0x42},\r
+ {0xFF, 0xFF}\r
+};\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+const struct ov_reg ov5640_yuv_vga[]= {\r
+ {0x3103, 0x11},\r
+ {0x3008, 0x82},\r
+ {0xFFFF, 0x05},\r
+ {0x3008, 0x42},\r
+ {0x3103, 0x03}, \r
+ {0x3017, 0xff},\r
+ {0x3018, 0xff},\r
+\r
+ {0x3034, 0x1a},\r
+ {0x3035, 0x11},\r
+ {0x3036, 0x6a},\r
+ {0x3037, 0x14},\r
+ {0x3108, 0x01},\r
+ {0x303b, 0x1c},\r
+ {0x303d, 0x30},\r
+\r
+ {0x3630, 0x36},\r
+ {0x3631, 0x0e},\r
+ {0x3632, 0xe2},\r
+ {0x3633, 0x12},\r
+ {0x3621, 0xe0},\r
+ {0x3704, 0xa0},\r
+ {0x3703, 0x5a},\r
+ {0x3715, 0x78},\r
+ {0x3717, 0x01},\r
+ {0x370b, 0x60},\r
+ {0x3705, 0x1a},\r
+ {0x3905, 0x02},\r
+ {0x3906, 0x10},\r
+ {0x3901, 0x0a},\r
+ {0x3731, 0x12},\r
+ {0x3600, 0x08},\r
+ {0x3601, 0x33},\r
+ {0x302d, 0x60},\r
+ {0x3620, 0x52},\r
+ {0x371b, 0x20},\r
+ {0x471c, 0x50},\r
+ {0x3a13, 0x43},\r
+ {0x3a18, 0x00},\r
+ {0x3a19, 0xf8},\r
+ {0x3635, 0x13},\r
+ {0x3636, 0x03},\r
+ {0x3634, 0x40},\r
+ {0x3622, 0x01},\r
+ {0x3c01, 0x34},\r
+ {0x3c04, 0x28},\r
+ {0x3c05, 0x98},\r
+ {0x3c06, 0x00},\r
+ {0x3c07, 0x08},\r
+ {0x3c08, 0x00},\r
+ {0x3c09, 0x1c},\r
+ {0x3c0a, 0x9c},\r
+ {0x3c0b, 0x40},\r
+ {0x3820, 0x41},\r
+ {0x3821, 0x07},\r
+ {0x3814, 0x31},\r
+ {0x3815, 0x31},\r
+ {0x3800, 0x00},\r
+ {0x3801, 0x00},\r
+ {0x3802, 0x00},\r
+ {0x3803, 0x04},\r
+ {0x3804, 0x0a},\r
+ {0x3805, 0x3f},\r
+ {0x3806, 0x07},\r
+ {0x3807, 0x9b},\r
+ {0x3808, 0x02},\r
+ {0x3809, 0x80},\r
+ {0x380a, 0x01},\r
+ {0x380b, 0xe0},\r
+ {0x380c, 0x07},\r
+ {0x380d, 0x68},\r
+ {0x380e, 0x03},\r
+ {0x380f, 0xd8},\r
+ {0x3810, 0x00},\r
+ {0x3811, 0x10},\r
+ {0x3812, 0x00},\r
+ {0x3813, 0x06},\r
+ {0x3618, 0x00},\r
+ {0x3612, 0x29},\r
+ {0x3708, 0x64},\r
+ {0x3709, 0x52},\r
+ {0x370c, 0x03},\r
+ {0x3a02, 0x03},\r
+ {0x3a03, 0xd8},\r
+ {0x3a08, 0x01},\r
+ {0x3a09, 0x27},\r
+ {0x3a0a, 0x00},\r
+ {0x3a0b, 0xf6},\r
+ {0x3a0e, 0x03},\r
+ {0x3a0d, 0x04},\r
+ {0x3a14, 0x03},\r
+ {0x3a15, 0xd8},\r
+ {0x4001, 0x02},\r
+ {0x4004, 0x02},\r
+ {0x3000, 0x00},\r
+ {0x3002, 0x1c},\r
+ {0x3004, 0xff},\r
+ {0x3006, 0xc3},\r
+ {0x300e, 0x58},\r
+ {0x302e, 0x00},\r
+ {0x4300, 0x30},\r
+ {0x501f, 0x00},\r
+ {0x4713, 0x03},\r
+ {0x4407, 0x04},\r
+ {0x440e, 0x00},\r
+ {0x460b, 0x35},\r
+ {0x460c, 0x22},\r
+ {0x4837, 0x22},\r
+ {0x3824, 0x02},\r
+ {0x5000, 0xa7},\r
+ {0x5001, 0xa3},\r
+ {0x5180, 0xff},\r
+ {0x5181, 0xf2},\r
+ {0x5182, 0x00},\r
+ {0x5183, 0x14},\r
+ {0x5184, 0x25},\r
+ {0x5185, 0x24},\r
+ {0x5186, 0x09},\r
+ {0x5187, 0x09},\r
+ {0x5188, 0x09},\r
+ {0x5189, 0x75},\r
+ {0x518a, 0x54},\r
+ {0x518b, 0xe0},\r
+ {0x518c, 0xb2},\r
+ {0x518d, 0x42},\r
+ {0x518e, 0x3d},\r
+ {0x518f, 0x56},\r
+ {0x5190, 0x46},\r
+ {0x5191, 0xf8},\r
+ {0x5192, 0x04},\r
+ {0x5193, 0x70},\r
+ {0x5194, 0xf0},\r
+ {0x5195, 0xf0},\r
+ {0x5196, 0x03},\r
+ {0x5197, 0x01},\r
+ {0x5198, 0x04},\r
+ {0x5199, 0x12},\r
+ {0x519a, 0x04},\r
+ {0x519b, 0x00},\r
+ {0x519c, 0x06},\r
+ {0x519d, 0x82},\r
+ {0x519e, 0x38},\r
+ {0x5381, 0x1e},\r
+ {0x5382, 0x5b},\r
+ {0x5383, 0x08},\r
+ {0x5384, 0x0a},\r
+ {0x5385, 0x7e},\r
+ {0x5386, 0x88},\r
+ {0x5387, 0x7c},\r
+ {0x5388, 0x6c},\r
+ {0x5389, 0x10},\r
+ {0x538a, 0x01},\r
+ {0x538b, 0x98},\r
+ {0x5300, 0x08},\r
+ {0x5301, 0x30},\r
+ {0x5302, 0x10},\r
+ {0x5303, 0x00},\r
+ {0x5304, 0x08},\r
+ {0x5305, 0x30},\r
+ {0x5306, 0x08},\r
+ {0x5307, 0x16},\r
+ {0x5309, 0x08},\r
+ {0x530a, 0x30},\r
+ {0x530b, 0x04},\r
+ {0x530c, 0x06},\r
+ {0x5480, 0x01},\r
+ {0x5481, 0x08},\r
+ {0x5482, 0x14},\r
+ {0x5483, 0x28},\r
+ {0x5484, 0x51},\r
+ {0x5485, 0x65},\r
+ {0x5486, 0x71},\r
+ {0x5487, 0x7d},\r
+ {0x5488, 0x87},\r
+ {0x5489, 0x91},\r
+ {0x548a, 0x9a},\r
+ {0x548b, 0xaa},\r
+ {0x548c, 0xb8},\r
+ {0x548d, 0xcd},\r
+ {0x548e, 0xdd},\r
+ {0x548f, 0xea},\r
+ {0x5490, 0x1d},\r
+ {0x5580, 0x02},\r
+ {0x5583, 0x40},\r
+ {0x5584, 0x10},\r
+ {0x5589, 0x10},\r
+ {0x558a, 0x00},\r
+ {0x558b, 0xf8},\r
+ {0x5800, 0x23},\r
+ {0x5801, 0x14},\r
+ {0x5802, 0x0f},\r
+ {0x5803, 0x0f},\r
+ {0x5804, 0x12},\r
+ {0x5805, 0x26},\r
+ {0x5806, 0x0c},\r
+ {0x5807, 0x08},\r
+ {0x5808, 0x05},\r
+ {0x5809, 0x05},\r
+ {0x580a, 0x08},\r
+ {0x580b, 0x0d},\r
+ {0x580c, 0x08},\r
+ {0x580d, 0x03},\r
+ {0x580e, 0x00},\r
+ {0x580f, 0x00},\r
+ {0x5810, 0x03},\r
+ {0x5811, 0x09},\r
+ {0x5812, 0x07},\r
+ {0x5813, 0x03},\r
+ {0x5814, 0x00},\r
+ {0x5815, 0x01},\r
+ {0x5816, 0x03},\r
+ {0x5817, 0x08},\r
+ {0x5818, 0x0d},\r
+ {0x5819, 0x08},\r
+ {0x581a, 0x05},\r
+ {0x581b, 0x06},\r
+ {0x581c, 0x08},\r
+ {0x581d, 0x0e},\r
+ {0x581e, 0x29},\r
+ {0x581f, 0x17},\r
+ {0x5820, 0x11},\r
+ {0x5821, 0x11},\r
+ {0x5822, 0x15},\r
+ {0x5823, 0x28},\r
+ {0x5824, 0x46},\r
+ {0x5825, 0x26},\r
+ {0x5826, 0x08},\r
+ {0x5827, 0x26},\r
+ {0x5828, 0x64},\r
+ {0x5829, 0x26},\r
+ {0x582a, 0x24},\r
+ {0x582b, 0x22},\r
+ {0x582c, 0x24},\r
+ {0x582d, 0x24},\r
+ {0x582e, 0x06},\r
+ {0x582f, 0x22},\r
+ {0x5830, 0x40},\r
+ {0x5831, 0x42},\r
+ {0x5832, 0x24},\r
+ {0x5833, 0x26},\r
+ {0x5834, 0x24},\r
+ {0x5835, 0x22},\r
+ {0x5836, 0x22},\r
+ {0x5837, 0x26},\r
+ {0x5838, 0x44},\r
+ {0x5839, 0x24},\r
+ {0x583a, 0x26},\r
+ {0x583b, 0x28},\r
+ {0x583c, 0x42},\r
+ {0x583d, 0xce},\r
+ {0x5025, 0x00},\r
+ {0x3a0f, 0x30},\r
+ {0x3a10, 0x28},\r
+ {0x3a1b, 0x30},\r
+ {0x3a1e, 0x26},\r
+ {0x3a11, 0x60},\r
+ {0x3a1f, 0x14},\r
+ {0x3008, 0x02},\r
+#if 1\r
+ {0x3503, 0x00},\r
+ {0x3c07, 0x08},\r
+ {0x3820, 0x41},\r
+ {0x3821, 0x07},\r
+ {0x3814, 0x31},\r
+ {0x3815, 0x31},\r
+ {0x3803, 0x04},\r
+ {0x3807, 0x9b},\r
+ {0x3808, 0x02},\r
+ {0x3809, 0x80},\r
+ {0x380a, 0x01},\r
+ {0x380b, 0xe0},\r
+ {0x380c, 0x07},\r
+ {0x380d, 0x68},\r
+ {0x380e, 0x03},\r
+ {0x380f, 0xd8},\r
+ {0x3813, 0x06},\r
+ {0x3618, 0x00},\r
+ {0x3612, 0x29},\r
+ {0x3708, 0x62},\r
+ {0x3709, 0x52},\r
+ {0x370c, 0x03},\r
+ {0x3a02, 0x03},\r
+ {0x3a03, 0xd8},\r
+ {0x3a0e, 0x03},\r
+ {0x3a0d, 0x04},\r
+ {0x3a14, 0x03},\r
+ {0x3a15, 0xd8},\r
+ {0x4004, 0x02},\r
+ {0x4713, 0x03},\r
+ {0x4407, 0x04},\r
+ {0x460b, 0x35},\r
+ {0x460c, 0x22},\r
+ {0x3824, 0x02},\r
+ {0x5001, 0xa3},\r
+\r
+#endif\r
+ {0xFF, 0xFF}\r
+};\r
+\r
+const struct ov_reg ov5640_yuv_sxga[]= {\r
+ {0x3103, 0x11},\r
+ {0x3008, 0x82},\r
+ {0xFFFF, 0x05},\r
+ {0x3008, 0x42},\r
+ {0x3103, 0x03}, \r
+ {0x3017, 0xff},\r
+ {0x3018, 0xff},\r
+\r
+\r
+ {0x3034, 0x1a},\r
+ {0x3035, 0x11},\r
+ {0x3036, 0x6a},\r
+ {0x3037, 0x14},\r
+ {0x3108, 0x01},\r
+ {0x303b, 0x1c},\r
+ {0x303d, 0x30},\r
+\r
+ {0x3630, 0x36},\r
+ {0x3631, 0x0e},\r
+ {0x3632, 0xe2},\r
+ {0x3633, 0x12},\r
+ {0x3621, 0xe0},\r
+ {0x3704, 0xa0},\r
+ {0x3703, 0x5a},\r
+ {0x3715, 0x78},\r
+ {0x3717, 0x01},\r
+ {0x370b, 0x60},\r
+ {0x3705, 0x1a},\r
+ {0x3905, 0x02},\r
+ {0x3906, 0x10},\r
+ {0x3901, 0x0a},\r
+ {0x3731, 0x12},\r
+ {0x3600, 0x08},\r
+ {0x3601, 0x33},\r
+ {0x302d, 0x60},\r
+ {0x3620, 0x52},\r
+ {0x371b, 0x20},\r
+ {0x471c, 0x50},\r
+ {0x3a13, 0x43},\r
+ {0x3a18, 0x00},\r
+ {0x3a19, 0xf8},\r
+ {0x3635, 0x13},\r
+ {0x3636, 0x03},\r
+ {0x3634, 0x40},\r
+ {0x3622, 0x01},\r
+ {0x3c01, 0x34},\r
+ {0x3c04, 0x28},\r
+ {0x3c05, 0x98},\r
+ {0x3c06, 0x00},\r
+ {0x3c07, 0x08},\r
+ {0x3c08, 0x00},\r
+ {0x3c09, 0x1c},\r
+ {0x3c0a, 0x9c},\r
+ {0x3c0b, 0x40},\r
+ {0x3820, 0x41},\r
+ {0x3821, 0x07},\r
+ {0x3814, 0x31},\r
+ {0x3815, 0x31},\r
+ {0x3800, 0x00},\r
+ {0x3801, 0x00},\r
+ {0x3802, 0x00},\r
+ {0x3803, 0x04},\r
+ {0x3804, 0x0a},\r
+ {0x3805, 0x3f},\r
+ {0x3806, 0x07},\r
+ {0x3807, 0x9b},\r
+ {0x3808, 0x02},\r
+ {0x3809, 0x80},\r
+ {0x380a, 0x01},\r
+ {0x380b, 0xe0},\r
+ {0x380c, 0x07},\r
+ {0x380d, 0x68},\r
+ {0x380e, 0x03},\r
+ {0x380f, 0xd8},\r
+ {0x3810, 0x00},\r
+ {0x3811, 0x10},\r
+ {0x3812, 0x00},\r
+ {0x3813, 0x06},\r
+ {0x3618, 0x00},\r
+ {0x3612, 0x29},\r
+ {0x3708, 0x64},\r
+ {0x3709, 0x52},\r
+ {0x370c, 0x03},\r
+ {0x3a02, 0x03},\r
+ {0x3a03, 0xd8},\r
+ {0x3a08, 0x01},\r
+ {0x3a09, 0x27},\r
+ {0x3a0a, 0x00},\r
+ {0x3a0b, 0xf6},\r
+ {0x3a0e, 0x03},\r
+ {0x3a0d, 0x04},\r
+ {0x3a14, 0x03},\r
+ {0x3a15, 0xd8},\r
+ {0x4001, 0x02},\r
+ {0x4004, 0x02},\r
+ {0x3000, 0x00},\r
+ {0x3002, 0x1c},\r
+ {0x3004, 0xff},\r
+ {0x3006, 0xc3},\r
+ {0x300e, 0x58},\r
+ {0x302e, 0x00},\r
+ {0x4300, 0x30},\r
+ {0x501f, 0x00},\r
+ {0x4713, 0x03},\r
+ {0x4407, 0x04},\r
+ {0x440e, 0x00},\r
+ {0x460b, 0x35},\r
+ {0x460c, 0x22},\r
+ {0x4837, 0x22},\r
+ {0x3824, 0x02},\r
+ {0x5000, 0xa7},\r
+ {0x5001, 0xa3},\r
+ {0x5180, 0xff},\r
+ {0x5181, 0xf2},\r
+ {0x5182, 0x00},\r
+ {0x5183, 0x14},\r
+ {0x5184, 0x25},\r
+ {0x5185, 0x24},\r
+ {0x5186, 0x09},\r
+ {0x5187, 0x09},\r
+ {0x5188, 0x09},\r
+ {0x5189, 0x75},\r
+ {0x518a, 0x54},\r
+ {0x518b, 0xe0},\r
+ {0x518c, 0xb2},\r
+ {0x518d, 0x42},\r
+ {0x518e, 0x3d},\r
+ {0x518f, 0x56},\r
+ {0x5190, 0x46},\r
+ {0x5191, 0xf8},\r
+ {0x5192, 0x04},\r
+ {0x5193, 0x70},\r
+ {0x5194, 0xf0},\r
+ {0x5195, 0xf0},\r
+ {0x5196, 0x03},\r
+ {0x5197, 0x01},\r
+ {0x5198, 0x04},\r
+ {0x5199, 0x12},\r
+ {0x519a, 0x04},\r
+ {0x519b, 0x00},\r
+ {0x519c, 0x06},\r
+ {0x519d, 0x82},\r
+ {0x519e, 0x38},\r
+ {0x5381, 0x1e},\r
+ {0x5382, 0x5b},\r
+ {0x5383, 0x08},\r
+ {0x5384, 0x0a},\r
+ {0x5385, 0x7e},\r
+ {0x5386, 0x88},\r
+ {0x5387, 0x7c},\r
+ {0x5388, 0x6c},\r
+ {0x5389, 0x10},\r
+ {0x538a, 0x01},\r
+ {0x538b, 0x98},\r
+ {0x5300, 0x08},\r
+ {0x5301, 0x30},\r
+ {0x5302, 0x10},\r
+ {0x5303, 0x00},\r
+ {0x5304, 0x08},\r
+ {0x5305, 0x30},\r
+ {0x5306, 0x08},\r
+ {0x5307, 0x16},\r
+ {0x5309, 0x08},\r
+ {0x530a, 0x30},\r
+ {0x530b, 0x04},\r
+ {0x530c, 0x06},\r
+ {0x5480, 0x01},\r
+ {0x5481, 0x08},\r
+ {0x5482, 0x14},\r
+ {0x5483, 0x28},\r
+ {0x5484, 0x51},\r
+ {0x5485, 0x65},\r
+ {0x5486, 0x71},\r
+ {0x5487, 0x7d},\r
+ {0x5488, 0x87},\r
+ {0x5489, 0x91},\r
+ {0x548a, 0x9a},\r
+ {0x548b, 0xaa},\r
+ {0x548c, 0xb8},\r
+ {0x548d, 0xcd},\r
+ {0x548e, 0xdd},\r
+ {0x548f, 0xea},\r
+ {0x5490, 0x1d},\r
+ {0x5580, 0x02},\r
+ {0x5583, 0x40},\r
+ {0x5584, 0x10},\r
+ {0x5589, 0x10},\r
+ {0x558a, 0x00},\r
+ {0x558b, 0xf8},\r
+ {0x5800, 0x23},\r
+ {0x5801, 0x14},\r
+ {0x5802, 0x0f},\r
+ {0x5803, 0x0f},\r
+ {0x5804, 0x12},\r
+ {0x5805, 0x26},\r
+ {0x5806, 0x0c},\r
+ {0x5807, 0x08},\r
+ {0x5808, 0x05},\r
+ {0x5809, 0x05},\r
+ {0x580a, 0x08},\r
+ {0x580b, 0x0d},\r
+ {0x580c, 0x08},\r
+ {0x580d, 0x03},\r
+ {0x580e, 0x00},\r
+ {0x580f, 0x00},\r
+ {0x5810, 0x03},\r
+ {0x5811, 0x09},\r
+ {0x5812, 0x07},\r
+ {0x5813, 0x03},\r
+ {0x5814, 0x00},\r
+ {0x5815, 0x01},\r
+ {0x5816, 0x03},\r
+ {0x5817, 0x08},\r
+ {0x5818, 0x0d},\r
+ {0x5819, 0x08},\r
+ {0x581a, 0x05},\r
+ {0x581b, 0x06},\r
+ {0x581c, 0x08},\r
+ {0x581d, 0x0e},\r
+ {0x581e, 0x29},\r
+ {0x581f, 0x17},\r
+ {0x5820, 0x11},\r
+ {0x5821, 0x11},\r
+ {0x5822, 0x15},\r
+ {0x5823, 0x28},\r
+ {0x5824, 0x46},\r
+ {0x5825, 0x26},\r
+ {0x5826, 0x08},\r
+ {0x5827, 0x26},\r
+ {0x5828, 0x64},\r
+ {0x5829, 0x26},\r
+ {0x582a, 0x24},\r
+ {0x582b, 0x22},\r
+ {0x582c, 0x24},\r
+ {0x582d, 0x24},\r
+ {0x582e, 0x06},\r
+ {0x582f, 0x22},\r
+ {0x5830, 0x40},\r
+ {0x5831, 0x42},\r
+ {0x5832, 0x24},\r
+ {0x5833, 0x26},\r
+ {0x5834, 0x24},\r
+ {0x5835, 0x22},\r
+ {0x5836, 0x22},\r
+ {0x5837, 0x26},\r
+ {0x5838, 0x44},\r
+ {0x5839, 0x24},\r
+ {0x583a, 0x26},\r
+ {0x583b, 0x28},\r
+ {0x583c, 0x42},\r
+ {0x583d, 0xce},\r
+ {0x5025, 0x00},\r
+ {0x3a0f, 0x30},\r
+ {0x3a10, 0x28},\r
+ {0x3a1b, 0x30},\r
+ {0x3a1e, 0x26},\r
+ {0x3a11, 0x60},\r
+ {0x3a1f, 0x14},\r
+ {0x3008, 0x02},\r
+ \r
+#if 1\r
+ {0x3503, 0x00},\r
+ {0x3c07, 0x08},\r
+ {0x3820, 0x41},\r
+ {0x3821, 0x07},\r
+ {0x3814, 0x31},\r
+ {0x3815, 0x31},\r
+ {0x3803, 0x04},\r
+ {0x3807, 0x9b},\r
+ {0x3808, 0x02},\r
+ {0x3809, 0x80},\r
+ {0x380a, 0x01},\r
+ {0x380b, 0xe0},\r
+ {0x380c, 0x07},\r
+ {0x380d, 0x68},\r
+ {0x380e, 0x03},\r
+ {0x380f, 0xd8},\r
+ {0x3813, 0x06},\r
+ {0x3618, 0x00},\r
+ {0x3612, 0x29},\r
+ {0x3708, 0x62},\r
+ {0x3709, 0x52},\r
+ {0x370c, 0x03},\r
+ {0x3a02, 0x03},\r
+ {0x3a03, 0xd8},\r
+ {0x3a0e, 0x03},\r
+ {0x3a0d, 0x04},\r
+ {0x3a14, 0x03},\r
+ {0x3a15, 0xd8},\r
+ {0x4004, 0x02},\r
+ {0x4713, 0x03},\r
+ {0x4407, 0x04},\r
+ {0x460b, 0x35},\r
+ {0x460c, 0x22},\r
+ {0x3824, 0x02},\r
+ {0x5001, 0xa3},\r
+#endif\r
+ {0x3c07,0x08},\r
+ {0x3820,0x41},\r
+ {0x3821,0x07},\r
+ {0x3800,0x00},\r
+ {0x3801,0x00},\r
+ {0x3802,0x00},\r
+ {0x3803,0x04},\r
+ {0x3804,0x0a},\r
+ {0x3805,0x3f},\r
+ {0x3806,0x07},\r
+ {0x3807,0x9b},\r
+ {0x3808,0x05},\r
+ {0x3809,0x00},\r
+ {0x380a,0x02},\r
+ {0x380b,0xd0},\r
+ {0x380c,0x07},\r
+ {0x380d,0x68},\r
+ {0x380e,0x03},\r
+ {0x380f,0xd8},\r
+ {0x3810,0x00},\r
+ {0x3811,0x10},\r
+ {0x3812,0x00},\r
+ {0x3813,0x7e},\r
+ {0x3814,0x31},\r
+ {0x3815,0x31},\r
+ {0x3618,0x00},\r
+ {0x3612,0x29},\r
+ {0x3709,0x52},\r
+ {0x370c,0x03},\r
+ {0x3a02,0x0b},\r
+ {0x3a03,0x88},\r
+ {0x3a14,0x0b},\r
+ {0x3a15,0x88},\r
+ {0x4004,0x02},\r
+ {0x3002,0x1c},\r
+ {0x3006,0xc3},\r
+ {0x4713,0x03},\r
+ {0x4407,0x04},\r
+ {0x460b,0x35},\r
+ {0x460c,0x20},\r
+ {0x4837,0x22},\r
+ {0x3824,0x02},\r
+ {0x5001,0xa3},\r
+ {0x3034,0x1a},\r
+ {0x3035,0x11},\r
+ {0x3036,0x46},\r
+ {0x3037,0x13},\r
+ {0x3503,0x03},\r
+ {0xFF, 0xFF}\r
+};\r
+\r
+const struct ov_reg ov5640_afc[]= {\r
+{0x3000 ,0x20 },\r
+{0x8000 ,0x02 },\r
+{0x8001 ,0x0f },\r
+{0x8002 ,0xe0 },\r
+{0x8003 ,0x02 },\r
+{0x8004 ,0x09 },\r
+{0x8005 ,0x28 },\r
+{0x8006 ,0xc2 },\r
+{0x8007 ,0x01 },\r
+{0x8008 ,0x22 },\r
+{0x8009 ,0x22 },\r
+{0x800a ,0x00 },\r
+{0x800b ,0x02 },\r
+{0x800c ,0x0d },\r
+{0x800d ,0xea },\r
+{0x800e ,0x30 },\r
+{0x800f ,0x01 },\r
+{0x8010 ,0x03 },\r
+{0x8011 ,0x02 },\r
+{0x8012 ,0x02 },\r
+{0x8013 ,0xa6 },\r
+{0x8014 ,0x30 },\r
+{0x8015 ,0x02 },\r
+{0x8016 ,0x03 },\r
+{0x8017 ,0x02 },\r
+{0x8018 ,0x02 },\r
+{0x8019 ,0xa6 },\r
+{0x801a ,0x90 },\r
+{0x801b ,0x51 },\r
+{0x801c ,0xa5 },\r
+{0x801d ,0xe0 },\r
+{0x801e ,0x78 },\r
+{0x801f ,0x93 },\r
+{0x8020 ,0xf6 },\r
+{0x8021 ,0xa3 },\r
+{0x8022 ,0xe0 },\r
+{0x8023 ,0x08 },\r
+{0x8024 ,0xf6 },\r
+{0x8025 ,0xa3 },\r
+{0x8026 ,0xe0 },\r
+{0x8027 ,0x08 },\r
+{0x8028 ,0xf6 },\r
+{0x8029 ,0xe5 },\r
+{0x802a ,0x1f },\r
+{0x802b ,0x70 },\r
+{0x802c ,0x4f },\r
+{0x802d ,0x75 },\r
+{0x802e ,0x1e },\r
+{0x802f ,0x20 },\r
+{0x8030 ,0xd2 },\r
+{0x8031 ,0x35 },\r
+{0x8032 ,0xd3 },\r
+{0x8033 ,0x78 },\r
+{0x8034 ,0x4f },\r
+{0x8035 ,0xe6 },\r
+{0x8036 ,0x94 },\r
+{0x8037 ,0x00 },\r
+{0x8038 ,0x18 },\r
+{0x8039 ,0xe6 },\r
+{0x803a ,0x94 },\r
+{0x803b ,0x00 },\r
+{0x803c ,0x40 },\r
+{0x803d ,0x07 },\r
+{0x803e ,0xe6 },\r
+{0x803f ,0xfe },\r
+{0x8040 ,0x08 },\r
+{0x8041 ,0xe6 },\r
+{0x8042 ,0xff },\r
+{0x8043 ,0x80 },\r
+{0x8044 ,0x03 },\r
+{0x8045 ,0x12 },\r
+{0x8046 ,0x0c },\r
+{0x8047 ,0x67 },\r
+{0x8048 ,0x78 },\r
+{0x8049 ,0x7e },\r
+{0x804a ,0xa6 },\r
+{0x804b ,0x06 },\r
+{0x804c ,0x08 },\r
+{0x804d ,0xa6 },\r
+{0x804e ,0x07 },\r
+{0x804f ,0x78 },\r
+{0x8050 ,0x8b },\r
+{0x8051 ,0xa6 },\r
+{0x8052 ,0x09 },\r
+{0x8053 ,0x18 },\r
+{0x8054 ,0x76 },\r
+{0x8055 ,0x01 },\r
+{0x8056 ,0x12 },\r
+{0x8057 ,0x0c },\r
+{0x8058 ,0x67 },\r
+{0x8059 ,0x78 },\r
+{0x805a ,0x4e },\r
+{0x805b ,0xa6 },\r
+{0x805c ,0x06 },\r
+{0x805d ,0x08 },\r
+{0x805e ,0xa6 },\r
+{0x805f ,0x07 },\r
+{0x8060 ,0x78 },\r
+{0x8061 ,0x8b },\r
+{0x8062 ,0xe6 },\r
+{0x8063 ,0x78 },\r
+{0x8064 ,0x6e },\r
+{0x8065 ,0xf6 },\r
+{0x8066 ,0x75 },\r
+{0x8067 ,0x1f },\r
+{0x8068 ,0x01 },\r
+{0x8069 ,0x78 },\r
+{0x806a ,0x93 },\r
+{0x806b ,0xe6 },\r
+{0x806c ,0x78 },\r
+{0x806d ,0x90 },\r
+{0x806e ,0xf6 },\r
+{0x806f ,0x78 },\r
+{0x8070 ,0x94 },\r
+{0x8071 ,0xe6 },\r
+{0x8072 ,0x78 },\r
+{0x8073 ,0x91 },\r
+{0x8074 ,0xf6 },\r
+{0x8075 ,0x78 },\r
+{0x8076 ,0x95 },\r
+{0x8077 ,0xe6 },\r
+{0x8078 ,0x78 },\r
+{0x8079 ,0x92 },\r
+{0x807a ,0xf6 },\r
+{0x807b ,0x22 },\r
+{0x807c ,0x79 },\r
+{0x807d ,0x90 },\r
+{0x807e ,0xe7 },\r
+{0x807f ,0xd3 },\r
+{0x8080 ,0x78 },\r
+{0x8081 ,0x93 },\r
+{0x8082 ,0x96 },\r
+{0x8083 ,0x40 },\r
+{0x8084 ,0x05 },\r
+{0x8085 ,0xe7 },\r
+{0x8086 ,0x96 },\r
+{0x8087 ,0xff },\r
+{0x8088 ,0x80 },\r
+{0x8089 ,0x08 },\r
+{0x808a ,0xc3 },\r
+{0x808b ,0x79 },\r
+{0x808c ,0x93 },\r
+{0x808d ,0xe7 },\r
+{0x808e ,0x78 },\r
+{0x808f ,0x90 },\r
+{0x8090 ,0x96 },\r
+{0x8091 ,0xff },\r
+{0x8092 ,0x78 },\r
+{0x8093 ,0x88 },\r
+{0x8094 ,0x76 },\r
+{0x8095 ,0x00 },\r
+{0x8096 ,0x08 },\r
+{0x8097 ,0xa6 },\r
+{0x8098 ,0x07 },\r
+{0x8099 ,0x79 },\r
+{0x809a ,0x91 },\r
+{0x809b ,0xe7 },\r
+{0x809c ,0xd3 },\r
+{0x809d ,0x78 },\r
+{0x809e ,0x94 },\r
+{0x809f ,0x96 },\r
+{0x80a0 ,0x40 },\r
+{0x80a1 ,0x05 },\r
+{0x80a2 ,0xe7 },\r
+{0x80a3 ,0x96 },\r
+{0x80a4 ,0xff },\r
+{0x80a5 ,0x80 },\r
+{0x80a6 ,0x08 },\r
+{0x80a7 ,0xc3 },\r
+{0x80a8 ,0x79 },\r
+{0x80a9 ,0x94 },\r
+{0x80aa ,0xe7 },\r
+{0x80ab ,0x78 },\r
+{0x80ac ,0x91 },\r
+{0x80ad ,0x96 },\r
+{0x80ae ,0xff },\r
+{0x80af ,0x12 },\r
+{0x80b0 ,0x0c },\r
+{0x80b1 ,0xb0 },\r
+{0x80b2 ,0x79 },\r
+{0x80b3 ,0x92 },\r
+{0x80b4 ,0xe7 },\r
+{0x80b5 ,0xd3 },\r
+{0x80b6 ,0x78 },\r
+{0x80b7 ,0x95 },\r
+{0x80b8 ,0x96 },\r
+{0x80b9 ,0x40 },\r
+{0x80ba ,0x05 },\r
+{0x80bb ,0xe7 },\r
+{0x80bc ,0x96 },\r
+{0x80bd ,0xff },\r
+{0x80be ,0x80 },\r
+{0x80bf ,0x08 },\r
+{0x80c0 ,0xc3 },\r
+{0x80c1 ,0x79 },\r
+{0x80c2 ,0x95 },\r
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+{0x8ee8 ,0x22 },\r
+{0x8ee9 ,0x78 },\r
+{0x8eea ,0xbf },\r
+{0x8eeb ,0xa6 },\r
+{0x8eec ,0x07 },\r
+{0x8eed ,0xc3 },\r
+{0x8eee ,0x08 },\r
+{0x8eef ,0xe6 },\r
+{0x8ef0 ,0x64 },\r
+{0x8ef1 ,0x80 },\r
+{0x8ef2 ,0x94 },\r
+{0x8ef3 ,0xb3 },\r
+{0x8ef4 ,0x22 },\r
+{0x8ef5 ,0x25 },\r
+{0x8ef6 ,0xe0 },\r
+{0x8ef7 ,0x24 },\r
+{0x8ef8 ,0x0a },\r
+{0x8ef9 ,0xf8 },\r
+{0x8efa ,0xe6 },\r
+{0x8efb ,0xfe },\r
+{0x8efc ,0x08 },\r
+{0x8efd ,0xe6 },\r
+{0x8efe ,0xff },\r
+{0x8eff ,0x22 },\r
+{0x8f00 ,0xe5 },\r
+{0x8f01 ,0x40 },\r
+{0x8f02 ,0x24 },\r
+{0x8f03 ,0xf2 },\r
+{0x8f04 ,0xf5 },\r
+{0x8f05 ,0x37 },\r
+{0x8f06 ,0xe5 },\r
+{0x8f07 ,0x3f },\r
+{0x8f08 ,0x34 },\r
+{0x8f09 ,0x43 },\r
+{0x8f0a ,0xf5 },\r
+{0x8f0b ,0x36 },\r
+{0x8f0c ,0xe5 },\r
+{0x8f0d ,0x3e },\r
+{0x8f0e ,0x34 },\r
+{0x8f0f ,0xa2 },\r
+{0x8f10 ,0xf5 },\r
+{0x8f11 ,0x35 },\r
+{0x8f12 ,0xe5 },\r
+{0x8f13 ,0x3d },\r
+{0x8f14 ,0x34 },\r
+{0x8f15 ,0x28 },\r
+{0x8f16 ,0xf5 },\r
+{0x8f17 ,0x34 },\r
+{0x8f18 ,0xe5 },\r
+{0x8f19 ,0x37 },\r
+{0x8f1a ,0xff },\r
+{0x8f1b ,0xe4 },\r
+{0x8f1c ,0xfe },\r
+{0x8f1d ,0xfd },\r
+{0x8f1e ,0xfc },\r
+{0x8f1f ,0x78 },\r
+{0x8f20 ,0x18 },\r
+{0x8f21 ,0x12 },\r
+{0x8f22 ,0x06 },\r
+{0x8f23 ,0xca },\r
+{0x8f24 ,0x8f },\r
+{0x8f25 ,0x40 },\r
+{0x8f26 ,0x8e },\r
+{0x8f27 ,0x3f },\r
+{0x8f28 ,0x8d },\r
+{0x8f29 ,0x3e },\r
+{0x8f2a ,0x8c },\r
+{0x8f2b ,0x3d },\r
+{0x8f2c ,0xe5 },\r
+{0x8f2d ,0x37 },\r
+{0x8f2e ,0x54 },\r
+{0x8f2f ,0xa0 },\r
+{0x8f30 ,0xff },\r
+{0x8f31 ,0xe5 },\r
+{0x8f32 ,0x36 },\r
+{0x8f33 ,0xfe },\r
+{0x8f34 ,0xe4 },\r
+{0x8f35 ,0xfd },\r
+{0x8f36 ,0xfc },\r
+{0x8f37 ,0x78 },\r
+{0x8f38 ,0x07 },\r
+{0x8f39 ,0x12 },\r
+{0x8f3a ,0x06 },\r
+{0x8f3b ,0xb7 },\r
+{0x8f3c ,0x78 },\r
+{0x8f3d ,0x10 },\r
+{0x8f3e ,0x12 },\r
+{0x8f3f ,0x0f },\r
+{0x8f40 ,0xac },\r
+{0x8f41 ,0xe4 },\r
+{0x8f42 ,0xff },\r
+{0x8f43 ,0xfe },\r
+{0x8f44 ,0xe5 },\r
+{0x8f45 ,0x35 },\r
+{0x8f46 ,0xfd },\r
+{0x8f47 ,0xe4 },\r
+{0x8f48 ,0xfc },\r
+{0x8f49 ,0x78 },\r
+{0x8f4a ,0x0e },\r
+{0x8f4b ,0x12 },\r
+{0x8f4c ,0x06 },\r
+{0x8f4d ,0xb7 },\r
+{0x8f4e ,0x12 },\r
+{0x8f4f ,0x0f },\r
+{0x8f50 ,0xaf },\r
+{0x8f51 ,0xe4 },\r
+{0x8f52 ,0xff },\r
+{0x8f53 ,0xfe },\r
+{0x8f54 ,0xfd },\r
+{0x8f55 ,0xe5 },\r
+{0x8f56 ,0x34 },\r
+{0x8f57 ,0xfc },\r
+{0x8f58 ,0x78 },\r
+{0x8f59 ,0x18 },\r
+{0x8f5a ,0x12 },\r
+{0x8f5b ,0x06 },\r
+{0x8f5c ,0xb7 },\r
+{0x8f5d ,0x78 },\r
+{0x8f5e ,0x08 },\r
+{0x8f5f ,0x12 },\r
+{0x8f60 ,0x0f },\r
+{0x8f61 ,0xac },\r
+{0x8f62 ,0x22 },\r
+{0x8f63 ,0xa2 },\r
+{0x8f64 ,0xaf },\r
+{0x8f65 ,0x92 },\r
+{0x8f66 ,0x32 },\r
+{0x8f67 ,0xc2 },\r
+{0x8f68 ,0xaf },\r
+{0x8f69 ,0xe5 },\r
+{0x8f6a ,0x23 },\r
+{0x8f6b ,0x45 },\r
+{0x8f6c ,0x22 },\r
+{0x8f6d ,0x90 },\r
+{0x8f6e ,0x0e },\r
+{0x8f6f ,0x5d },\r
+{0x8f70 ,0x60 },\r
+{0x8f71 ,0x0e },\r
+{0x8f72 ,0x12 },\r
+{0x8f73 ,0x0f },\r
+{0x8f74 ,0xc7 },\r
+{0x8f75 ,0xe0 },\r
+{0x8f76 ,0xf5 },\r
+{0x8f77 ,0x2c },\r
+{0x8f78 ,0x12 },\r
+{0x8f79 ,0x0f },\r
+{0x8f7a ,0xc4 },\r
+{0x8f7b ,0xe0 },\r
+{0x8f7c ,0xf5 },\r
+{0x8f7d ,0x2d },\r
+{0x8f7e ,0x80 },\r
+{0x8f7f ,0x0c },\r
+{0x8f80 ,0x12 },\r
+{0x8f81 ,0x0f },\r
+{0x8f82 ,0xc7 },\r
+{0x8f83 ,0xe5 },\r
+{0x8f84 ,0x30 },\r
+{0x8f85 ,0xf0 },\r
+{0x8f86 ,0x12 },\r
+{0x8f87 ,0x0f },\r
+{0x8f88 ,0xc4 },\r
+{0x8f89 ,0xe5 },\r
+{0x8f8a ,0x31 },\r
+{0x8f8b ,0xf0 },\r
+{0x8f8c ,0xa2 },\r
+{0x8f8d ,0x32 },\r
+{0x8f8e ,0x92 },\r
+{0x8f8f ,0xaf },\r
+{0x8f90 ,0x22 },\r
+{0x8f91 ,0x8f },\r
+{0x8f92 ,0x3b },\r
+{0x8f93 ,0x8e },\r
+{0x8f94 ,0x3a },\r
+{0x8f95 ,0x8d },\r
+{0x8f96 ,0x39 },\r
+{0x8f97 ,0x8c },\r
+{0x8f98 ,0x38 },\r
+{0x8f99 ,0x22 },\r
+{0x8f9a ,0x12 },\r
+{0x8f9b ,0x06 },\r
+{0x8f9c ,0xdd },\r
+{0x8f9d ,0x8f },\r
+{0x8f9e ,0x31 },\r
+{0x8f9f ,0x8e },\r
+{0x8fa0 ,0x30 },\r
+{0x8fa1 ,0x8d },\r
+{0x8fa2 ,0x2f },\r
+{0x8fa3 ,0x8c },\r
+{0x8fa4 ,0x2e },\r
+{0x8fa5 ,0x22 },\r
+{0x8fa6 ,0x93 },\r
+{0x8fa7 ,0xf9 },\r
+{0x8fa8 ,0xf8 },\r
+{0x8fa9 ,0x02 },\r
+{0x8faa ,0x06 },\r
+{0x8fab ,0xca },\r
+{0x8fac ,0x12 },\r
+{0x8fad ,0x06 },\r
+{0x8fae ,0xca },\r
+{0x8faf ,0xe5 },\r
+{0x8fb0 ,0x40 },\r
+{0x8fb1 ,0x2f },\r
+{0x8fb2 ,0xf5 },\r
+{0x8fb3 ,0x40 },\r
+{0x8fb4 ,0xe5 },\r
+{0x8fb5 ,0x3f },\r
+{0x8fb6 ,0x3e },\r
+{0x8fb7 ,0xf5 },\r
+{0x8fb8 ,0x3f },\r
+{0x8fb9 ,0xe5 },\r
+{0x8fba ,0x3e },\r
+{0x8fbb ,0x3d },\r
+{0x8fbc ,0xf5 },\r
+{0x8fbd ,0x3e },\r
+{0x8fbe ,0xe5 },\r
+{0x8fbf ,0x3d },\r
+{0x8fc0 ,0x3c },\r
+{0x8fc1 ,0xf5 },\r
+{0x8fc2 ,0x3d },\r
+{0x8fc3 ,0x22 },\r
+{0x8fc4 ,0x90 },\r
+{0x8fc5 ,0x0e },\r
+{0x8fc6 ,0x5f },\r
+{0x8fc7 ,0xe4 },\r
+{0x8fc8 ,0x93 },\r
+{0x8fc9 ,0xfe },\r
+{0x8fca ,0x74 },\r
+{0x8fcb ,0x01 },\r
+{0x8fcc ,0x93 },\r
+{0x8fcd ,0xf5 },\r
+{0x8fce ,0x82 },\r
+{0x8fcf ,0x8e },\r
+{0x8fd0 ,0x83 },\r
+{0x8fd1 ,0x22 },\r
+{0x8fd2 ,0xd2 },\r
+{0x8fd3 ,0x01 },\r
+{0x8fd4 ,0xc2 },\r
+{0x8fd5 ,0x02 },\r
+{0x8fd6 ,0xe4 },\r
+{0x8fd7 ,0xf5 },\r
+{0x8fd8 ,0x1f },\r
+{0x8fd9 ,0xf5 },\r
+{0x8fda ,0x1e },\r
+{0x8fdb ,0xd2 },\r
+{0x8fdc ,0x35 },\r
+{0x8fdd ,0xd2 },\r
+{0x8fde ,0x33 },\r
+{0x8fdf ,0x22 },\r
+{0x8fe0 ,0x78 },\r
+{0x8fe1 ,0x7f },\r
+{0x8fe2 ,0xe4 },\r
+{0x8fe3 ,0xf6 },\r
+{0x8fe4 ,0xd8 },\r
+{0x8fe5 ,0xfd },\r
+{0x8fe6 ,0x75 },\r
+{0x8fe7 ,0x81 },\r
+{0x8fe8 ,0xcd },\r
+{0x8fe9 ,0x02 },\r
+{0x8fea ,0x0c },\r
+{0x8feb ,0xc4 },\r
+{0x8fec ,0x8f },\r
+{0x8fed ,0x82 },\r
+{0x8fee ,0x8e },\r
+{0x8fef ,0x83 },\r
+{0x8ff0 ,0x75 },\r
+{0x8ff1 ,0xf0 },\r
+{0x8ff2 ,0x04 },\r
+{0x8ff3 ,0xed },\r
+{0x8ff4 ,0x02 },\r
+{0x8ff5 ,0x07 },\r
+{0x8ff6 ,0x06 },\r
+{0x3022 ,0x00 },\r
+{0x3023 ,0x00 },\r
+{0x3024 ,0x00 },\r
+{0x3025 ,0x00 },\r
+{0x3026 ,0x00 },\r
+{0x3027 ,0x00 },\r
+{0x3028 ,0x00 },\r
+{0x3029 ,0x7F },\r
+{0x3000 ,0x00 },\r
+{0x3004, 0xff },\r
+{0x3005, 0xF7 },\r
+\r
+{0xFF, 0xFF}\r
+};\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*\r
+ * ID\r
+ */\r
+\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+const struct ov_reg ov7740_yuv_vga[]= {\r
+{0x12 ,0x80},\r
+//{0x11 ,0x07},\r
+\r
+{0x55 ,0x40},\r
+{0x11 ,0x02},\r
+\r
+{0x12 ,0x00},\r
+{0xd5 ,0x10},\r
+{0x0c ,0x12},\r
+{0x0d ,0x34},\r
+{0x17 ,0x25},\r
+{0x18 ,0xa0},\r
+{0x19 ,0x03},\r
+{0x1a ,0xf0},\r
+{0x1b ,0x89}, //;was 81\r
+{0x22 ,0x03}, //;new\r
+{0x29 ,0x18}, //;was 17\r
+{0x2b ,0xf8},\r
+{0x2c ,0x01},\r
+{0x31 ,0xa0},\r
+{0x32 ,0xf0},\r
+{0x33 ,0xc4}, //;was44\r
+{0x35 ,0x05}, //;new\r
+{0x36 ,0x3f},\r
+{0x04 ,0x60},\r
+{0x27 ,0x80}, //;delete "42 3a b4"\r
+{0x3d ,0x0f},\r
+{0x3e ,0x80},\r
+{0x3f ,0x40},\r
+{0x40 ,0x7f},\r
+{0x41 ,0x6a},\r
+{0x42 ,0x29},\r
+{0x44 ,0x22}, //;was 11\r
+{0x45 ,0x41},\r
+{0x47 ,0x02},\r
+{0x49 ,0x64},\r
+{0x4a ,0xa1},\r
+{0x4b ,0x40},\r
+{0x4c ,0x1a},\r
+{0x4d ,0x50},\r
+{0x4e ,0x13},\r
+{0x64 ,0x00},\r
+{0x67 ,0x88},\r
+{0x68 ,0x1a},\r
+\r
+{0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling\r
+{0x24 ,0x3c},\r
+{0x25 ,0x30},\r
+{0x26 ,0x72},\r
+{0x50 ,0x97},\r
+{0x51 ,0x1f}, //;0fc/7e/3f/1f for 60/30/15/7.5fps, 60Hz\r
+{0x52 ,0x00}, //;[7:6]/[5:4] 2 msb for 60/50Hz\r
+{0x53 ,0x00},\r
+{0x20 ,0x00},\r
+{0x21 ,0xcf}, //;01/23/57/cf for 60/30/15/7.5fps\r
+{0x50, 0x4b}, // ;12e/97/4b/25 for 60/30/15/7.5fps, 50Hz\r
+{0x38 ,0x14},\r
+{0xe9 ,0x00},\r
+{0x56 ,0x55},\r
+{0x57 ,0xff},\r
+{0x58 ,0xff},\r
+{0x59 ,0xff},\r
+{0x5f ,0x04},\r
+{0xec ,0x00},\r
+{0x13 ,0xff},\r
+\r
+{0x80 ,0x7f}, //;[6]/[5] for BPC/WPC\r
+{0x81 ,0x3f},\r
+{0x82 ,0x32},\r
+{0x83 ,0x01},\r
+{0x38 ,0x11},\r
+{0x84 ,0x70},\r
+{0x85 ,0x00},\r
+{0x86 ,0x03},\r
+{0x87 ,0x01},\r
+{0x88 ,0x05},\r
+{0x89 ,0x30},\r
+{0x8d ,0x30},\r
+{0x8f ,0x85},\r
+{0x93 ,0x30},\r
+{0x95 ,0x85},\r
+{0x99 ,0x30},\r
+{0x9b ,0x85},\r
+\r
+{0x9c ,0x08},\r
+{0x9d ,0x12},\r
+{0x9e ,0x23},\r
+{0x9f ,0x45},\r
+{0xa0 ,0x55},\r
+{0xa1 ,0x64},\r
+{0xa2 ,0x72},\r
+{0xa3 ,0x7f},\r
+{0xa4 ,0x8b},\r
+{0xa5 ,0x95},\r
+{0xa6 ,0xa7},\r
+{0xa7 ,0xb5},\r
+{0xa8 ,0xcb},\r
+{0xa9 ,0xdd},\r
+{0xaa ,0xec},\r
+{0xab ,0x1a},\r
+\r
+{0xce ,0x78},\r
+{0xcf ,0x6e},\r
+{0xd0 ,0x0a},\r
+{0xd1 ,0x0c},\r
+{0xd2 ,0x84},\r
+{0xd3 ,0x90},\r
+{0xd4 ,0x1e},\r
+\r
+{0x5a ,0x24},\r
+{0x5b ,0x1f},\r
+{0x5c ,0x88},\r
+{0x5d ,0x60},\r
+\r
+{0xac ,0x6e},\r
+{0xbe ,0xff},\r
+{0xbf ,0x00},\r
+\r
+{0x0f ,0x1d},\r
+{0x0f ,0x1f},\r
+{0xFF, 0xFF}\r
+};\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+const struct ov_reg ov9740_yuv_vga[]= {\r
+//@@ VGA 640x360 bin YUV DVP 60FPS (Full speed)\r
+{0x0103,0x01},\r
+{0x3026,0x00},\r
+{0x3027,0x00},\r
+{0x3002,0xe8},\r
+{0x3004,0x03},\r
+{0x3005,0xff},\r
+{0x3703,0x42},\r
+{0x3704,0x10},\r
+{0x3705,0x45},\r
+{0x3603,0xaa},\r
+{0x3632,0x27},\r
+{0x3620,0x66},\r
+{0x3621,0xc0},\r
+{0x0202,0x03},\r
+{0x0203,0x43},\r
+{0x3833,0x04},\r
+{0x3835,0x02},\r
+{0x4702,0x04},\r
+{0x4704,0x00},\r
+{0x4706,0x08},\r
+{0x3819,0x6e},\r
+{0x3817,0x94},\r
+{0x3a18,0x00},\r
+{0x3a19,0x7f},\r
+{0x5003,0xa7},\r
+{0x3631,0x5e},\r
+{0x3633,0x50},\r
+{0x3630,0xd2},\r
+{0x3604,0x0c},\r
+{0x3601,0x40},\r
+{0x3602,0x16},\r
+{0x3610,0xa1},\r
+{0x3612,0x24},\r
+{0x034a,0x02},\r
+{0x034b,0xd3},\r
+{0x034c,0x02},\r
+{0x034d,0x80},\r
+{0x034e,0x01},\r
+{0x034f,0x68},\r
+{0x0202,0x01},\r
+{0x0203,0x9e},\r
+{0x381a,0x44},\r
+{0x3707,0x14},\r
+{0x3622,0x9f},\r
+{0x5841,0x04},\r
+{0x4002,0x45},\r
+{0x5000,0x01},\r
+{0x5001,0x00},\r
+{0x3406,0x00},\r
+{0x5000,0xff},\r
+{0x5001,0xef},\r
+{0x5003,0xff},\r
+{0x4005,0x18},\r
+{0x3503,0x10},\r
+{0x3a11,0xa0},\r
+{0x3a1b,0x50},\r
+{0x3a0f,0x50},\r
+{0x3a10,0x4c},\r
+{0x3a1e,0x4c},\r
+{0x3a1f,0x26},\r
+{0x3104,0x20},\r
+{0x0305,0x03},\r
+{0x0307,0x5f},\r
+{0x0303,0x01},\r
+{0x0301,0x0a},\r
+{0x3010,0x01},\r
+{0x300c,0x02},\r
+{0x0340,0x02},\r
+{0x0341,0x08},\r
+{0x0342,0x04},\r
+{0x0343,0xc0},\r
+{0x0101,0x01},\r
+{0x3a08,0x01},\r
+{0x3a09,0x38},\r
+{0x3a0e,0x01},\r
+{0x3a14,0x09},\r
+{0x3a15,0xc0},\r
+{0x3a0a,0x01},\r
+{0x3a0b,0x02},\r
+{0x3a0d,0x02},\r
+{0x3a02,0x10},\r
+{0x3a03,0x30},\r
+{0x3c0a,0x9c},\r
+{0x3c0b,0x3f},\r
+{0x529a,0x1 }, \r
+{0x529b,0x2 }, \r
+{0x529c,0x3 }, \r
+{0x529d,0x5 }, \r
+{0x529e,0x5 }, \r
+{0x529f,0x28}, \r
+{0x52a0,0x32}, \r
+{0x52a2,0x0 },\r
+{0x52a3,0x2 },\r
+{0x52a4,0x0 },\r
+{0x52a5,0x4 }, \r
+{0x52a6,0x0 }, \r
+{0x52a7,0x8 }, \r
+{0x52a8,0x0 }, \r
+{0x52a9,0x10}, \r
+{0x52aa,0x0 }, \r
+{0x52ab,0x38}, \r
+{0x52ac,0x0 }, \r
+{0x52ad,0x3c}, \r
+{0x52ae,0x0 }, \r
+{0x52af,0x4c}, \r
+{0x5842,0x02},\r
+{0x5843,0x5e},\r
+{0x5844,0x04},\r
+{0x5845,0x32},\r
+{0x5846,0x03},\r
+{0x5847,0x29},\r
+{0x5848,0x02},\r
+{0x5849,0xcc},\r
+{0x5800,0x22},\r
+{0x5801,0x1e},\r
+{0x5802,0x1a},\r
+{0x5803,0x1a},\r
+{0x5804,0x1f},\r
+{0x5805,0x26},\r
+{0x5806,0xe },\r
+{0x5807,0x9 },\r
+{0x5808,0x7 },\r
+{0x5809,0x8 },\r
+{0x580a,0xb },\r
+{0x580b,0x11},\r
+{0x580c,0x5 },\r
+{0x580d,0x2 },\r
+{0x580e,0x0 },\r
+{0x580f,0x0 },\r
+{0x5810,0x3 },\r
+{0x5811,0x7 },\r
+{0x5812,0x4 },\r
+{0x5813,0x1 },\r
+{0x5814,0x0 },\r
+{0x5815,0x0 },\r
+{0x5816,0x3 },\r
+{0x5817,0x7 },\r
+{0x5818,0xc },\r
+{0x5819,0x8 },\r
+{0x581a,0x6 },\r
+{0x581b,0x6 },\r
+{0x581c,0x9 },\r
+{0x581d,0x10},\r
+{0x581e,0x20},\r
+{0x581f,0x1b},\r
+{0x5820,0x17},\r
+{0x5821,0x18},\r
+{0x5822,0x1d},\r
+{0x5823,0x23},\r
+{0x5824,0x5b},\r
+{0x5825,0x6e},\r
+{0x5826,0x6e},\r
+{0x5827,0x7e},\r
+{0x5828,0xab},\r
+{0x5829,0x5e},\r
+{0x582a,0x8a},\r
+{0x582b,0x8a},\r
+{0x582c,0x8a},\r
+{0x582d,0x9d},\r
+{0x582e,0x5b},\r
+{0x582f,0x88},\r
+{0x5830,0x88},\r
+{0x5831,0x98},\r
+{0x5832,0x9a},\r
+{0x5833,0x4e},\r
+{0x5834,0x8a},\r
+{0x5835,0x79},\r
+{0x5836,0x7a},\r
+{0x5837,0xad},\r
+{0x5838,0x9b},\r
+{0x5839,0x9d},\r
+{0x583a,0xad},\r
+{0x583b,0x8e},\r
+{0x583c,0x5c},\r
+{0x583e,0x08},\r
+{0x583f,0x04},\r
+{0x5840,0x10},\r
+{0x5480,0x07}, \r
+{0x5481,0x16}, \r
+{0x5482,0x2c}, \r
+{0x5483,0x4d}, \r
+{0x5484,0x59}, \r
+{0x5485,0x64}, \r
+{0x5486,0x6e}, \r
+{0x5487,0x76}, \r
+{0x5488,0x7f}, \r
+{0x5489,0x86}, \r
+{0x548a,0x94}, \r
+{0x548b,0xa3}, \r
+{0x548c,0xba}, \r
+{0x548d,0xd2}, \r
+{0x548e,0xe9}, \r
+{0x548f,0x1e},\r
+{0x5490,0x0f},\r
+{0x5491,0xff},\r
+{0x5492,0x0e},\r
+{0x5493,0x34},\r
+{0x5494,0x07},\r
+{0x5495,0x1a},\r
+{0x5496,0x04},\r
+{0x5497,0x0e},\r
+{0x5498,0x03},\r
+{0x5499,0x82},\r
+{0x549a,0x03},\r
+{0x549b,0x20},\r
+{0x549c,0x02}, \r
+{0x549d,0xd7},\r
+{0x549e,0x02},\r
+{0x549f,0xa5},\r
+{0x54a0,0x02},\r
+{0x54a1,0x75},\r
+{0x54a2,0x02},\r
+{0x54a3,0x55},\r
+{0x54a4,0x02},\r
+{0x54a5,0x1c},\r
+{0x54a6,0x01},\r
+{0x54a7,0xea},\r
+{0x54a8,0x01},\r
+{0x54a9,0xae},\r
+{0x54aa,0x01},\r
+{0x54ab,0x7c},\r
+{0x54ac,0x01},\r
+{0x54ad,0x57},\r
+{0x5180,0xf0},\r
+{0x5181,0x00},\r
+{0x5182,0x41},\r
+{0x5183,0x42},\r
+{0x5184,0x8f},\r
+{0x5185,0x63},\r
+{0x5186,0xce},\r
+{0x5187,0xa8},\r
+{0x5188,0x17},\r
+{0x5189,0x1f},\r
+{0x518a,0x27},\r
+{0x518b,0x41},\r
+{0x518c,0x34},\r
+{0x518d,0xf0},\r
+{0x518e,0x10},\r
+{0x518f,0xff},\r
+{0x5190,0x00},\r
+{0x5191,0xff},\r
+{0x5192,0x00},\r
+{0x5193,0xff},\r
+{0x5194,0x00},\r
+{0x5380,0x1 },\r
+{0x5381,0x0 },\r
+{0x5382,0x0 },\r
+{0x5383,0x17},\r
+{0x5384,0x0 },\r
+{0x5385,0x1 },\r
+{0x5386,0x0 }, \r
+{0x5387,0x0 }, \r
+{0x5388,0x0 }, \r
+{0x5389,0xad}, \r
+{0x538a,0x0 },\r
+{0x538b,0x11}, \r
+{0x538c,0x0 },\r
+{0x538d,0x0 },\r
+{0x538e,0x0 },\r
+{0x538f,0x7 },\r
+{0x5390,0x0 }, \r
+{0x5391,0x80}, \r
+{0x5392,0x0 },\r
+{0x5393,0xa0}, \r
+{0x5394,0x18}, \r
+{0x3c0a,0x9c},\r
+{0x3c0b,0x3f},\r
+{0x5501,0x14},\r
+{0x5502,0x00}, \r
+{0x5503,0x40},\r
+{0x5504,0x00},\r
+{0x5505,0x80},\r
+{0x0100,0x01},\r
+{0xFF, 0xFF}\r
+};\r
+\r
+\r
+\r
+const struct ov_reg ov9740_yuv_sxga[]= {\r
+//@@ WXGA 1280x720 YUV DVP 15FPS for card reader\r
+{0x0103, 0x01},\r
+{0x3026, 0x00},\r
+{0x3027, 0x00},\r
+{0x3002, 0xe8},\r
+{0x3004, 0x03},\r
+{0x3005, 0xff},\r
+{0x3406, 0x00},\r
+{0x3603, 0xaa},\r
+{0x3632, 0x27},\r
+{0x3620, 0x66},\r
+{0x3621, 0xc0},\r
+{0x3631, 0x5e},\r
+{0x3633, 0x50},\r
+{0x3630, 0xd2},\r
+{0x3604, 0x0c},\r
+{0x3601, 0x40},\r
+{0x3602, 0x16},\r
+{0x3610, 0xa1},\r
+{0x3612, 0x24},\r
+{0x3622, 0x9f},\r
+{0x3703, 0x42},\r
+{0x3704, 0x10},\r
+{0x3705, 0x45},\r
+{0x3707, 0x14},\r
+{0x3833, 0x04},\r
+{0x3835, 0x03},\r
+{0x3819, 0x6e},\r
+{0x3817, 0x94},\r
+{0x3503, 0x10},\r
+{0x3a18, 0x00},\r
+{0x3a19, 0x7f},\r
+{0x3a11, 0xa0},\r
+{0x3a1a, 0x05},\r
+{0x3a1b, 0x50},\r
+{0x3a0f, 0x50},\r
+{0x3a10, 0x4c},\r
+{0x3a1e, 0x4c},\r
+{0x3a1f, 0x26},\r
+{0x4002, 0x45},\r
+{0x4005, 0x18},\r
+{0x4702, 0x04},\r
+{0x4704, 0x00},\r
+{0x4706, 0x08},\r
+{0x5000, 0xff},\r
+{0x5001, 0xef},\r
+{0x5003, 0xff},\r
+\r
+{0x3104,0x20},\r
+{0x0305,0x03},\r
+{0x0307,0x4c},\r
+{0x0303,0x01},\r
+{0x0301,0x08},\r
+{0x3010,0x01},\r
+{0x300c,0x03},\r
+\r
+{0x0340, 0x03},\r
+{0x0341, 0x07},\r
+{0x0342, 0x06},\r
+{0x0343, 0x62},\r
+{0x034b, 0xd1},\r
+{0x034c, 0x05},\r
+{0x034d, 0x00},\r
+{0x034e, 0x02},\r
+{0x034f, 0xd0},\r
+{0x0101, 0x01},\r
+{0x3a08, 0x00},\r
+{0x3a09, 0xe8},\r
+{0x3a0e, 0x03},\r
+{0x3a14, 0x15},\r
+{0x3a15, 0xc6},\r
+{0x3a0a, 0x00},\r
+{0x3a0b, 0xc0},\r
+{0x3a0d, 0x04},\r
+{0x3a02, 0x18},\r
+{0x3a03, 0x20},\r
+{0x3c0a, 0x9c},\r
+{0x3c0b, 0x3f},\r
+{0x529a, 0x1 },\r
+{0x529b, 0x2 },\r
+{0x529c, 0x3 },\r
+{0x529d, 0x5 },\r
+{0x529e, 0x5 },\r
+{0x529f, 0x28},\r
+{0x52a0, 0x32},\r
+{0x52a2, 0x0 },\r
+{0x52a3, 0x2 },\r
+{0x52a4, 0x0 },\r
+{0x52a5, 0x4 },\r
+{0x52a6, 0x0 },\r
+{0x52a7, 0x8 },\r
+{0x52a8, 0x0 },\r
+{0x52a9, 0x10},\r
+{0x52aa, 0x0 },\r
+{0x52ab, 0x38},\r
+{0x52ac, 0x0 },\r
+{0x52ad, 0x3c},\r
+{0x52ae, 0x0 },\r
+{0x52af, 0x4c},\r
+{0x5842, 0x02},\r
+{0x5843, 0x5e},\r
+{0x5844, 0x04},\r
+{0x5845, 0x32},\r
+{0x5846, 0x03},\r
+{0x5847, 0x29},\r
+{0x5848, 0x02},\r
+{0x5849, 0xcc},\r
+{0x5800, 0x22},\r
+{0x5801, 0x1e},\r
+{0x5802, 0x1a},\r
+{0x5803, 0x1a},\r
+{0x5804, 0x1f},\r
+{0x5805, 0x26},\r
+{0x5806, 0xe },\r
+{0x5807, 0x9 },\r
+{0x5808, 0x7 },\r
+{0x5809, 0x8 },\r
+{0x580a, 0xb },\r
+{0x580b, 0x11},\r
+{0x580c, 0x5 },\r
+{0x580d, 0x2 },\r
+{0x580e, 0x0 },\r
+{0x580f, 0x0 },\r
+{0x5810, 0x3 },\r
+{0x5811, 0x7 },\r
+{0x5812, 0x4 },\r
+{0x5813, 0x1 },\r
+{0x5814, 0x0 },\r
+{0x5815, 0x0 },\r
+{0x5816, 0x3 },\r
+{0x5817, 0x7 },\r
+{0x5818, 0xc },\r
+{0x5819, 0x8 },\r
+{0x581a, 0x6 },\r
+{0x581b, 0x6 },\r
+{0x581c, 0x9 },\r
+{0x581d, 0x10},\r
+{0x581e, 0x20},\r
+{0x581f, 0x1b},\r
+{0x5820, 0x17},\r
+{0x5821, 0x18},\r
+{0x5822, 0x1d},\r
+{0x5823, 0x23},\r
+{0x5824, 0x5b},\r
+{0x5825, 0x6e},\r
+{0x5826, 0x6e},\r
+{0x5827, 0x7e},\r
+{0x5828, 0xab},\r
+{0x5829, 0x5e},\r
+{0x582a, 0x8a},\r
+{0x582b, 0x8a},\r
+{0x582c, 0x8a},\r
+{0x582d, 0x9d},\r
+{0x582e, 0x5b},\r
+{0x582f, 0x88},\r
+{0x5830, 0x88},\r
+{0x5831, 0x98},\r
+{0x5832, 0x9a},\r
+{0x5833, 0x4e},\r
+{0x5834, 0x8a},\r
+{0x5835, 0x79},\r
+{0x5836, 0x7a},\r
+{0x5837, 0xad},\r
+{0x5838, 0x9b},\r
+{0x5839, 0x9d},\r
+{0x583a, 0xad},\r
+{0x583b, 0x8e},\r
+{0x583c, 0x5c},\r
+{0x583e, 0x08},\r
+{0x583f, 0x04},\r
+{0x5840, 0x10},\r
+{0x5480, 0x07},\r
+{0x5481, 0x16},\r
+{0x5482, 0x2c},\r
+{0x5483, 0x4d},\r
+{0x5484, 0x59},\r
+{0x5485, 0x64},\r
+{0x5486, 0x6e},\r
+{0x5487, 0x76},\r
+{0x5488, 0x7f},\r
+{0x5489, 0x86},\r
+{0x548a, 0x94},\r
+{0x548b, 0xa3},\r
+{0x548c, 0xba},\r
+{0x548d, 0xd2},\r
+{0x548e, 0xe9},\r
+{0x548f, 0x1e},\r
+{0x5490, 0x0f},\r
+{0x5491, 0xff},\r
+{0x5492, 0x0e},\r
+{0x5493, 0x34},\r
+{0x5494, 0x07},\r
+{0x5495, 0x1a},\r
+{0x5496, 0x04},\r
+{0x5497, 0x0e},\r
+{0x5498, 0x03},\r
+{0x5499, 0x82},\r
+{0x549a, 0x03},\r
+{0x549b, 0x20},\r
+{0x549c, 0x02},\r
+{0x549d, 0xd7},\r
+{0x549e, 0x02},\r
+{0x549f, 0xa5},\r
+{0x54a0, 0x02},\r
+{0x54a1, 0x75},\r
+{0x54a2, 0x02},\r
+{0x54a3, 0x55},\r
+{0x54a4, 0x02},\r
+{0x54a5, 0x1c},\r
+{0x54a6, 0x01},\r
+{0x54a7, 0xea},\r
+{0x54a8, 0x01},\r
+{0x54a9, 0xae},\r
+{0x54aa, 0x01},\r
+{0x54ab, 0x7c},\r
+{0x54ac, 0x01},\r
+{0x54ad, 0x57},\r
+{0x5180, 0xf0},\r
+{0x5181, 0x00},\r
+{0x5182, 0x41},\r
+{0x5183, 0x42},\r
+{0x5184, 0x8f},\r
+{0x5185, 0x63},\r
+{0x5186, 0xce},\r
+{0x5187, 0xa8},\r
+{0x5188, 0x17},\r
+{0x5189, 0x1f},\r
+{0x518a, 0x27},\r
+{0x518b, 0x41},\r
+{0x518c, 0x34},\r
+{0x518d, 0xf0},\r
+{0x518e, 0x10},\r
+{0x518f, 0xff},\r
+{0x5190, 0x00},\r
+{0x5191, 0xff},\r
+{0x5192, 0x00},\r
+{0x5193, 0xff},\r
+{0x5194, 0x00},\r
+{0x5380, 0x1 },\r
+{0x5381, 0x0 },\r
+{0x5382, 0x0 },\r
+{0x5383, 0x17},\r
+{0x5384, 0x0 },\r
+{0x5385, 0x1 },\r
+{0x5386, 0x0 },\r
+{0x5387, 0x0 },\r
+{0x5388, 0x0 },\r
+{0x5389, 0xad},\r
+{0x538a, 0x0 },\r
+{0x538b, 0x11},\r
+{0x538c, 0x0 },\r
+{0x538d, 0x0 },\r
+{0x538e, 0x0 },\r
+{0x538f, 0x7 },\r
+{0x5390, 0x0 },\r
+{0x5391, 0x80},\r
+{0x5392, 0x0 },\r
+{0x5393, 0xa0},\r
+{0x5394, 0x18},\r
+{0x3c0a, 0x9c},\r
+{0x3c0b, 0x3f},\r
+{0x5501, 0x14},\r
+{0x5502, 0x00},\r
+{0x5503, 0x40},\r
+{0x5504, 0x00},\r
+{0x5505, 0x80},\r
+{0x5308, 0x40},\r
+{0x5309, 0x60},\r
+{0x3a11, 0xd0},\r
+{0x3a1b, 0x78},\r
+{0x3a0f, 0x78},\r
+{0x3a10, 0x68},\r
+{0x3a1e, 0x68},\r
+{0x3a1f, 0x40},\r
+{0x0100, 0x01},\r
+{0xFF, 0xFF}\r
+};\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \addtogroup at25d_module S25FL1 driver\r
+ * \ingroup lib_spiflash\r
+ * The S25FL1 serial dataflash driver is based on the corresponding S25FL1 SPI driver.\r
+ * A S25FL1 instance has to be initialized using the Dataflash levle function\r
+ * S25FL1D_Configure(). S25FL1 Dataflash can be automatically detected using\r
+ * the S25FL1D_FindDevice() function. Then S25FL1 dataflash operations such as\r
+ * read, write and erase DF can be launched using S25FL1D_SendCommand function\r
+ * with corresponding S25FL1 command set.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Reads a serial flash device ID using S25FL1D_ReadJedecId().</li>\r
+ * <li> Reads data from the S25fl1 at the specified address using S25FL1D_Read().</li>\r
+ * <li> Writes data on the S25fl1 at the specified address using S25FL1D_Write().</li>\r
+ * <li> Erases all chip using S25FL1D_EraseBlock().</li>\r
+ * <li> Erases a specified block using S25FL1D_EraseBlock().</li>\r
+ * <li> Poll until the S25fl1 has completed of corresponding operations using\r
+ * S25FL1D_IsBusy().</li>\r
+ * <li> Retrieves and returns the S25fl1 current using S25FL1D_ReadStatus().</li>\r
+ * </ul>\r
+ *\r
+ * Related files :\n\r
+ * \ref at25d.c\n\r
+ * \ref at25d.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the S25FL1 Serialflash driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <board.h>\r
+//#include <libspiflash.h>\r
+#include <assert.h>\r
+#include "stdlib.h"\r
+#include "string.h"\r
+\r
+\r
+static qspiFrame *pDev, *pMem;\r
+#define READ_DEV 0\r
+#define WRITE_DEV 1 \r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+static void S25FL1D_DefaultParams(void)\r
+{ \r
+ pDev->spiMode = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;\r
+ pDev->ContinuousRead = 0;\r
+ pDev->DataSize = 0;\r
+ pDev->DummyCycles = 0;\r
+ pDev->InstAddr = 0;\r
+ pDev->InstAddrFlag = 0;\r
+ pDev->OptionEn = 0;\r
+\r
+}\r
+\r
+\r
+static uint8_t S25FL1D_SendCommand(uint8_t Instr, AccesType ReadWrite)\r
+\r
+{ \r
+ pDev->Instruction = Instr;\r
+ QSPI_SendFrame(QSPI, pDev, ReadWrite);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reads and returns the status register of the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+static uint8_t S25FL1D_ReadStatus(void)\r
+{\r
+ uint8_t status;\r
+\r
+ pDev->DataSize = 1; \r
+ S25FL1D_SendCommand(0x05, READ_DEV);\r
+ status = *(pDev->pData);\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the status register of the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+static uint8_t S25FL1D_ReadStatus2(void)\r
+{\r
+ uint8_t status;\r
+\r
+ pDev->DataSize = 1;\r
+ S25FL1D_SendCommand(0x35, READ_DEV);\r
+ status = *(pDev->pData);\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the status register of the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+static uint8_t S25FL1D_ReadStatus3(void)\r
+{\r
+ uint8_t status;\r
+\r
+ pDev->DataSize = 1;\r
+ S25FL1D_SendCommand(0x33, READ_DEV);\r
+ status = *(pDev->pData);\r
+ return status;\r
+}\r
+/**\r
+ * \brief Wait for transfer to finish calling the SPI driver ISR. (interrupts are disabled)\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+static void S25FL1D_IsBusy(void)\r
+{\r
+ while(S25FL1D_ReadStatus() & STATUS_RDYBSY);\r
+}\r
+\r
+\r
+\r
+\r
+\r
+static void S25FL1D_EnableWrite(void)\r
+{\r
+ uint8_t status;\r
+\r
+ status = S25FL1D_ReadStatus();\r
+\r
+\r
+ while(status != STATUS_WEL)\r
+ { \r
+ pDev->DataSize = 0;\r
+ S25FL1D_SendCommand(WRITE_ENABLE, READ_DEV);\r
+ status = S25FL1D_ReadStatus();\r
+ }\r
+}\r
+\r
+\r
+static void S25FL1D_DisableWrite(void)\r
+{\r
+ uint8_t status;\r
+\r
+ status = S25FL1D_ReadStatus();\r
+\r
+ while( (status & STATUS_WEL) != 0)\r
+ { \r
+ pDev->DataSize = 0;\r
+ S25FL1D_SendCommand(WRITE_DISABLE, READ_DEV);\r
+ status = S25FL1D_ReadStatus();\r
+ }\r
+}\r
+/**\r
+ * \brief Writes the given value in the status register of the serial flash device.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param status Status to write.\r
+ */\r
+static void S25FL1D_WriteStatus( uint8_t *pStatus)\r
+{\r
+ S25FL1D_EnableWrite();\r
+\r
+ pDev->DataSize = 3;\r
+ pDev->Instruction = WRITE_STATUS; \r
+ pDev->pData = pStatus;\r
+ QSPI_SendFrame(QSPI, pDev, Device_Write);\r
+ S25FL1D_DisableWrite();\r
+}\r
+\r
+/**\r
+ * \brief Writes the given value in the status register of the serial flash device.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param status Status to write.\r
+ */\r
+static void S25FL1D_WriteVolatileStatus( uint8_t *pStatus)\r
+{\r
+\r
+\r
+ pDev->DataSize = 0;\r
+ S25FL1D_SendCommand(0x50, READ_DEV);\r
+\r
+ pDev->DataSize = 3;\r
+ pDev->Instruction = WRITE_STATUS; \r
+ pDev->pData = pStatus;\r
+ QSPI_SendFrame(QSPI, pDev, Device_Write);\r
+ S25FL1D_DisableWrite();\r
+}\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+void S25FL1D_InitFlashInterface(void)\r
+{\r
+ pDev = (qspiFrame *)malloc (sizeof(qspiFrame)); \r
+ memset(pDev, 0, sizeof(qspiFrame));\r
+ pDev->spiMode = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;\r
+ pDev->pData = (uint8_t *)malloc (sizeof(uint32_t));\r
+\r
+\r
+ pMem = (qspiFrame *)malloc (sizeof(qspiFrame));\r
+ memset(pMem, 0, sizeof(qspiFrame));\r
+ pMem->spiMode = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;\r
+ pMem->pData = (uint8_t *)malloc (sizeof(uint8_t));\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the serial flash device ID.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+unsigned int S25FL1D_ReadJedecId(void)\r
+{\r
+ unsigned int id = 0;\r
+\r
+ pDev->DataSize = 3;\r
+ S25FL1D_SendCommand(READ_JEDEC_ID, READ_DEV);\r
+\r
+ id = ( (pDev->pData[0] << 16) || (pDev->pData[1] << 8) || (pDev->pData[2]));\r
+\r
+ return id;\r
+}\r
+\r
+/**\r
+ * \brief Enables critical writes operation on a serial flash device, such as sector\r
+ * protection, status register, etc.\r
+ *\r
+ * \para pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+void S25FL1D_EnableQuadMode(void)\r
+{\r
+\r
+ uint8_t status[3];\r
+\r
+ status[0] = S25FL1D_ReadStatus();\r
+ status[1] = S25FL1D_ReadStatus2();\r
+ status[2] = S25FL1D_ReadStatus3();\r
+\r
+ while(!(status[1] & STATUS_QUAD_ENABLE))\r
+ {\r
+ status[1] |= STATUS_QUAD_ENABLE;\r
+ S25FL1D_WriteStatus(status);\r
+ status[1] = S25FL1D_ReadStatus2();\r
+ Wait(50);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enables critical writes operation on a serial flash device, such as sector\r
+ * protection, status register, etc.\r
+ *\r
+ * \para pS25fl1 Pointer to an S25FL1 driver instance.\r
+ */\r
+void S25FL1D_EnableWrap(uint8_t ByetAlign)\r
+{\r
+\r
+ uint8_t status[3];\r
+\r
+ status[0] = S25FL1D_ReadStatus();\r
+ status[1] = S25FL1D_ReadStatus2();\r
+ status[2] = S25FL1D_ReadStatus3();\r
+\r
+ status[2] = (ByetAlign << 5);\r
+\r
+ pDev->DataSize = 1;\r
+ *(pDev->pData) = status[2];\r
+ pDev->DummyCycles = 24;\r
+ S25FL1D_SendCommand(WRAP_ENABLE, WRITE_DEV);\r
+ pDev->DummyCycles = 0;\r
+\r
+ S25FL1D_WriteVolatileStatus(status);\r
+ status[2] = S25FL1D_ReadStatus3();\r
+ Wait(50);\r
+}\r
+\r
+void S25FL1D_SoftReset(void)\r
+{\r
+\r
+ pDev->DataSize = 0;\r
+ S25FL1D_SendCommand(SOFT_RESET_ENABLE, READ_DEV);\r
+ S25FL1D_SendCommand(SOFT_RESET, READ_DEV);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Unprotects the contents of the serial flash device.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ *\r
+ * \return 0 if the device has been unprotected; otherwise returns\r
+ * S25FL1D_ERROR_PROTECTED.\r
+ */\r
+unsigned char S25FL1D_Unprotect(void)\r
+{\r
+ unsigned char status[3];\r
+\r
+\r
+\r
+ /* Get the status register value to check the current protection */\r
+ status[0]= S25FL1D_ReadStatus();\r
+ status[1]= S25FL1D_ReadStatus2();\r
+ status[2]= S25FL1D_ReadStatus3();\r
+ if ((status[0] & STATUS_SWP) == STATUS_SWP_PROTNONE) {\r
+\r
+ /* Protection already disabled */\r
+ return 0;\r
+ }\r
+\r
+ status[0] &= (!STATUS_SWP);\r
+ /* Check if sector protection registers are locked */\r
+ if ((status[0] & STATUS_SPRL) == STATUS_SPRL_LOCKED) {\r
+ status[0] &= (!STATUS_SPRL);\r
+ /* Unprotect sector protection registers by writing the status reg. */\r
+ S25FL1D_WriteStatus(status);\r
+ }\r
+\r
+ S25FL1D_WriteStatus(status);\r
+\r
+ /* Check the new status */\r
+ status[0] = S25FL1D_ReadStatus();\r
+ if ((status[0] & (STATUS_SPRL | STATUS_SWP)) != 0) {\r
+\r
+ return ERROR_PROTECTED;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Unprotects the contents of the serial flash device.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ *\r
+ * \return 0 if the device has been unprotected; otherwise returns\r
+ * S25FL1D_ERROR_PROTECTED.\r
+ */\r
+unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size)\r
+{\r
+ unsigned char status[3];\r
+\r
+\r
+\r
+ /* Get the status register value to check the current protection */\r
+ status[0]= S25FL1D_ReadStatus();\r
+ status[1]= S25FL1D_ReadStatus2();\r
+ status[2]= S25FL1D_ReadStatus3();\r
+\r
+ status[0] &= (!STATUS_SWP);\r
+ /* Check if sector protection registers are locked */\r
+ if ((status[0] & STATUS_SPRL) == STATUS_SPRL_LOCKED) {\r
+ status[0] &= (!STATUS_SPRL);\r
+ /* Unprotect sector protection registers by writing the status reg. */\r
+ S25FL1D_WriteStatus(status);\r
+ }\r
+\r
+ S25FL1D_WriteStatus(status);\r
+\r
+ /* Check the new status */\r
+ status[0] = S25FL1D_ReadStatus();\r
+ if ((status[0] & (STATUS_SPRL | STATUS_SWP)) != 0) {\r
+\r
+ return ERROR_PROTECTED;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Erases all the content of the memory chip.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ *\r
+ * \return 0 if the device has been unprotected; otherwise returns\r
+ * ERROR_PROTECTED.\r
+ */\r
+unsigned char S25FL1D_EraseChip(void)\r
+{\r
+ char wait_ch[4] = {'\\','|','/','-' };\r
+ uint8_t i=0;\r
+\r
+ S25FL1D_EnableWrite(); \r
+ pDev->DataSize=0;\r
+ S25FL1D_SendCommand(CHIP_ERASE_2, READ_DEV);\r
+ S25FL1D_ReadStatus();\r
+\r
+ while(*(pDev->pData) & STATUS_RDYBSY)\r
+ {\r
+ S25FL1D_ReadStatus(); \r
+ Wait(500);\r
+ printf("Erasing flash memory %c\r", wait_ch[i]);\r
+ i++;\r
+ if(i==4)\r
+ i=0;\r
+ }\r
+ printf("\rErasing flash memory done..... 100%\n\r");\r
+ return 0;\r
+}\r
+\r
+/**\r
+ *\brief Erases the specified block of the serial firmware dataflash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param address Address of the block to erase.\r
+ *\r
+ * \return 0 if successful; otherwise returns ERROR_PROTECTED if the\r
+ * device is protected or ERROR_BUSY if it is busy executing a command.\r
+ */\r
+unsigned char S25FL1D_EraseSector(unsigned int address)\r
+{\r
+ uint8_t status;\r
+ uint32_t EraseAddr;\r
+\r
+ EraseAddr = address;\r
+\r
+ /* Check that the flash is ready and unprotected */\r
+ status = S25FL1D_ReadStatus();\r
+ if ((status & STATUS_RDYBSY) != STATUS_RDYBSY_READY) {\r
+ TRACE_ERROR("EraseBlock : Flash busy\n\r");\r
+ return ERROR_BUSY;\r
+ }\r
+ else if ((status & STATUS_SWP) != STATUS_SWP_PROTNONE) {\r
+ TRACE_ERROR("S25FL1D_EraseBlock : Flash protected\n\r");\r
+ return ERROR_PROTECTED;\r
+ }\r
+\r
+\r
+ /* Enable critical write operation */\r
+ S25FL1D_EnableWrite();\r
+\r
+ pDev->InstAddrFlag = 1;\r
+ pDev->InstAddr = address;\r
+ /* Start the block erase command */\r
+ S25FL1D_SendCommand(BLOCK_ERASE_4K, WRITE_DEV);\r
+ S25FL1D_DefaultParams();\r
+\r
+ /* Wait for transfer to finish */\r
+ S25FL1D_IsBusy();\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ *\brief Erases the specified 64KB block of the serial firmware dataflash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param address Address of the block to erase.\r
+ *\r
+ * \return 0 if successful; otherwise returns ERROR_PROTECTED if the\r
+ * device is protected or ERROR_BUSY if it is busy executing a command.\r
+ */\r
+unsigned char S25FL1D_Erase64KBlock( unsigned int address)\r
+{\r
+ unsigned char status;\r
+\r
+ /* Check that the flash is ready and unprotected */\r
+ status = S25FL1D_ReadStatus();\r
+ if ((status & STATUS_RDYBSY) != STATUS_RDYBSY_READY) {\r
+ TRACE_ERROR("S25FL1D_EraseBlock : Flash busy\n\r");\r
+ return ERROR_BUSY;\r
+ }\r
+ else if ((status & STATUS_SWP) != STATUS_SWP_PROTNONE) {\r
+ TRACE_ERROR("EraseBlock : Flash protected\n\r");\r
+ return ERROR_PROTECTED;\r
+ }\r
+\r
+ /* Enable critical write operation */\r
+ S25FL1D_EnableWrite();\r
+\r
+ pDev->DataSize = 0;\r
+ pDev->InstAddrFlag = 1;\r
+ pDev->InstAddr = address;\r
+\r
+ /* Start the block erase command */\r
+ S25FL1D_SendCommand(BLOCK_ERASE_64K, WRITE_DEV);\r
+ S25FL1D_DefaultParams();\r
+\r
+ /* Wait for transfer to finish */\r
+ S25FL1D_IsBusy();\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Writes data at the specified address on the serial firmware dataflash. The\r
+ * page(s) to program must have been erased prior to writing. This function\r
+ * handles page boundary crossing automatically.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes in buffer.\r
+ * \param address Write address.\r
+ *\r
+ * \return 0 if successful; otherwise, returns ERROR_PROGRAM is there has\r
+ * been an error during the data programming.\r
+ */\r
+unsigned char S25FL1D_Write(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address)\r
+{\r
+ unsigned int pageSize = 256;\r
+ unsigned int writeSize;\r
+ unsigned int i = 0;\r
+\r
+\r
+ writeSize = size >> 8;\r
+ S25FL1D_EnableWrite();\r
+ pMem->Instruction = 0x02; \r
+ pMem->InstAddrFlag=1; pMem->InstAddr=address; \r
+ if(writeSize ==0) // if less than page size\r
+ {\r
+ pMem->pData = (pData);\r
+ pMem->DataSize = size;\r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Write);\r
+ }\r
+ else // mulptiple pagesize\r
+ { \r
+ pMem->DataSize = pageSize;\r
+ for(i=0; i< writeSize; i++)\r
+ {\r
+ S25FL1D_EnableWrite();\r
+ pMem->pData = pData; \r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Write);\r
+ S25FL1D_IsBusy();\r
+ pData += pageSize;\r
+ pMem->InstAddr += pageSize;\r
+ memory_barrier();\r
+ }\r
+ if((writeSize * pageSize) < size)\r
+ {\r
+ S25FL1D_EnableWrite();\r
+ pMem->DataSize = (size - (writeSize * pageSize)) ;\r
+ pMem->pData = pData; \r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Write);\r
+ S25FL1D_IsBusy();\r
+ }\r
+ }\r
+\r
+ S25FL1D_DisableWrite();\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Reads data from the specified address on the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes to read.\r
+ * \param address Read address.\r
+ *\r
+ * \return 0 if successful; otherwise, fail.\r
+ */\r
+unsigned char S25FL1D_Read(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address)\r
+{ \r
+ pMem->Instruction = READ_ARRAY_LF;\r
+ pMem->InstAddrFlag=1; pMem->InstAddr=address;\r
+ pMem->pData = pData;\r
+ pMem->DataSize = size;\r
+ pMem->DummyCycles = 0;\r
+ pMem->spiMode = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;\r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Read);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reads data from the specified address on the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes to read.\r
+ * \param address Read address.\r
+ *\r
+ * \return 0 if successful; otherwise, fail.\r
+ */\r
+unsigned char S25FL1D_ReadDual(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address)\r
+{\r
+ pMem->Instruction = READ_ARRAY_DUAL;\r
+ pMem->InstAddrFlag=1; pMem->InstAddr=address;\r
+ pMem->pData = pData;\r
+ pMem->DataSize = size;\r
+ pMem->DummyCycles = 8;\r
+ pMem->spiMode = QSPI_IFR_WIDTH_DUAL_OUTPUT;\r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Read);\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reads data from the specified address on the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes to read.\r
+ * \param address Read address.\r
+ *\r
+ * \return 0 if successful; otherwise, fail.\r
+ */\r
+unsigned char S25FL1D_ReadQuad(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address)\r
+{\r
+\r
+ pMem->Instruction = READ_ARRAY_QUAD;\r
+ pMem->InstAddrFlag=1; pMem->InstAddr=address;\r
+ pMem->pData = pData;\r
+ pMem->DataSize = size;\r
+ pMem->DummyCycles = 8;\r
+ pMem->spiMode = QSPI_IFR_WIDTH_QUAD_OUTPUT;\r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Read);\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Reads data from the specified address on the serial flash.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pData Data buffer.\r
+ * \param size Number of bytes to read.\r
+ * \param address Read address.\r
+ *\r
+ * \return 0 if successful; otherwise, fail.\r
+ */\r
+unsigned char S25FL1D_ReadQuadIO(\r
+ uint8_t *pData,\r
+ uint32_t size,\r
+ uint32_t address,\r
+ uint8_t ContMode)\r
+{\r
+\r
+ pMem->Instruction = READ_ARRAY_QUAD_IO;\r
+ pMem->InstAddrFlag=1; \r
+ pMem->InstAddr=address;\r
+ pMem->pData = pData;\r
+ pMem->DataSize = size; \r
+ pMem->DummyCycles = 6;\r
+ if(ContMode)\r
+ {\r
+ pMem->OptionLen = QSPI_IFR_OPTL_OPTION_4BIT;\r
+ pMem->Option = 0x2;\r
+ pMem->ContinuousRead = ContMode;\r
+ pMem->DummyCycles = 5;\r
+ pMem->OptionEn = ContMode;\r
+ }\r
+\r
+ pMem->spiMode = QSPI_IFR_WIDTH_QUAD_IO;\r
+ QSPI_SendFrameToMem(QSPI, pMem, Device_Read);\r
+ pMem->OptionEn = 0;\r
+ pMem->ContinuousRead = 0;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/** \r
+ * \addtogroup at25_spi_module S25FL1 SPI driver\r
+ * \ingroup lib_spiflash\r
+ *\r
+ * The S25FL1 serial firmware dataflash driver is based on top of the\r
+ * corresponding Spi driver. A Dataflash structure instance has to be\r
+ * initialized using the S25FL1_Configure() function. Then a command can be send \r
+ * to the serial flash using the SPI_SendCommand() function. \r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li>Initializes an S25FL1 instance and configures SPI chip select pin\r
+ * using S25FL1_Configure(). </li>\r
+ * <li>Detect DF and returns DF description corresponding to the device\r
+ * connected using S25FL1D_ReadJedecId() and S25FL1_FindDevice().\r
+ * This function shall be called by the application before S25FL1_SendCommand().</li>\r
+ * <li> Sends a command to the DF through the SPI using S25FL1_SendCommand().\r
+ * The command is identified by its command code and the number of\r
+ * bytes to transfer.</li>\r
+ * <li> Example code for sending command to write a page to DF.</li>\r
+ * \code\r
+ * // Program page\r
+ * error = S25FL1_SendCommand(pS25fl1, S25FL1_BYTE_PAGE_PROGRAM, 4,\r
+ * pData, writeSize, address, 0, 0);\r
+ * \endcode\r
+ * <li> Example code for sending command to read a page from DF.\r
+ * If data needs to be received, then a data buffer must be\r
+ * provided.</li>\r
+ * \code\r
+ * // Start a read operation\r
+ * error = S25FL1_SendCommand(pS25fl1, S25FL1_READ_ARRAY_LF,\r
+ * 4, pData, size, address, 0, 0);\r
+ * \endcode\r
+ * <li> This function does not block; its optional callback will\r
+ * be invoked when the transfer completes.</li>\r
+ * <li> Check the S25FL1 driver is ready or not by polling S25FL1_IsBusy().</li>\r
+ * </ul>\r
+ *\r
+ * Related files :\n\r
+ * \ref at25_spi.c\n\r
+ * \ref at25_spi.h.\n\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the S25FL1 SPI driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <board.h>\r
+//#include <libspiflash.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initializes an S25FL1 driver instance with the given SPI driver and chip\r
+ * select value.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param pSpid Pointer to an SPI driver instance.\r
+ * \param cs Chip select value to communicate with the serial flash.\r
+ * \param polling Uses polling mode instead of IRQ trigger.\r
+ */\r
+void S25FL1_Configure(S25fl1 *pS25fl1, Qspid *pQspid, uint8_t polling)\r
+{\r
+ SpidCmd *pCommand;\r
+\r
+ assert(pS25fl1);\r
+ assert(pQSpid);\r
+\r
+\r
+ /* Initialize the S25FL1 fields */\r
+ pS25fl1->pQspid = pSpid;\r
+ pS25fl1->pDesc = 0;\r
+ pS25fl1->pollingMode = polling;\r
+\r
+ /* Initialize the command structure */\r
+ pCommand = &(pS25fl1->command);\r
+ pCommand->pCmd = (uint8_t *) pS25fl1->CmdBuffer;\r
+ pCommand->callback = 0;\r
+ pCommand->pArgument = 0;\r
+}\r
+\r
+/**\r
+ * \brief Is serial flash driver busy.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25fl1 driver instance.\r
+ *\r
+ * \return 1 if the serial flash driver is currently busy executing a command;\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t S25FL1_IsBusy(S25fl1 *pS25fl1)\r
+{\r
+ if (pS25fl1->pollingMode)\r
+ {\r
+ SPID_Handler(pS25fl1->pSpid);\r
+ SPID_DmaHandler(pS25fl1->pSpid);\r
+ }\r
+ return SPID_IsBusy(pS25fl1->pSpid);\r
+}\r
+\r
+/**\r
+ * \brief Sends a command to the serial flash through the SPI. The command is made up\r
+ * of two parts: the first is used to transmit the command byte and optionally,\r
+ * address and dummy bytes. The second part is the data to send or receive.\r
+ * This function does not block: it returns as soon as the transfer has been\r
+ * started. An optional callback can be invoked to notify the end of transfer.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25fl1 driver instance.\r
+ * \param cmd Command byte.\r
+ * \param cmdSize Size of command (command byte + address bytes + dummy bytes).\r
+ * \param pData Data buffer.\r
+ * \param dataSize Number of bytes to send/receive.\r
+ * \param address Address to transmit.\r
+ * \param callback Optional user-provided callback to invoke at end of transfer.\r
+ * \param pArgument Optional argument to the callback function.\r
+ *\r
+ * \return 0 if successful; otherwise, returns S25FL1_ERROR_BUSY if the S25FL1\r
+ * driver is currently executing a command, or S25FL1_ERROR_SPI if the command\r
+ * cannot be sent because of a SPI error.\r
+ */\r
+uint8_t S25FL1_SendCommand(uint8_t Instr, uint8_t ReadWrite)\r
+\r
+{ \r
+ pDev->Instruction = Instr; \r
+ QSPI_SendFrame(QSPI, pDev, ReadWrite);\r
+}\r
+\r
+/**\r
+ * \brief Tries to detect a serial firmware flash device given its JEDEC identifier.\r
+ * The JEDEC id can be retrieved by sending the correct command to the device.\r
+ *\r
+ * \param pS25fl1 Pointer to an S25FL1 driver instance.\r
+ * \param jedecId JEDEC identifier of device.\r
+ *\r
+ * \return the corresponding S25FL1 descriptor if found; otherwise returns 0.\r
+ */\r
+const S25fl1Desc * S25FL1_FindDevice(S25fl1 *pS25fl1, uint32_t jedecId)\r
+{\r
+ uint32_t i = 0;\r
+\r
+ assert(pS25fl1);\r
+\r
+ /* Search if device is recognized */\r
+ pS25fl1->pDesc = 0;\r
+ while ((i < NUMDATAFLASH) && !(pS25fl1->pDesc)) {\r
+\r
+ if ((jedecId & 0xFF00FFFF) == (at25Devices[i].jedecId & 0xFF00FFFF)) {\r
+\r
+ pS25fl1->pDesc = &(at25Devices[i]);\r
+ }\r
+\r
+ i++;\r
+ }\r
+\r
+ return pS25fl1->pDesc;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+/**\r
+ * \file syscalls.c\r
+ *\r
+ * Implementation of newlib syscall.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+#include "board.h"\r
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+#include <errno.h>\r
+#include <intrinsics.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#undef errno\r
+extern int errno ;\r
+extern int _heap ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void _exit( int status ) ;\r
+extern void _kill( int pid, int sig ) ;\r
+extern int _getpid ( void ) ;\r
+\r
+extern caddr_t _sbrk ( int incr )\r
+{\r
+ static unsigned char *heap = NULL ;\r
+ unsigned char *prev_heap ;\r
+\r
+ if ( heap == NULL )\r
+ {\r
+ heap = (unsigned char *)&_heap ;\r
+ }\r
+ prev_heap = heap;\r
+\r
+ heap += incr ;\r
+\r
+ return (caddr_t) prev_heap ;\r
+}\r
+\r
+extern int link( char *old, char *new )\r
+{\r
+ return -1 ;\r
+}\r
+\r
+extern int _close( int file )\r
+{\r
+ return -1 ;\r
+}\r
+\r
+extern int _fstat( int file, struct stat *st )\r
+{\r
+ st->st_mode = S_IFCHR ;\r
+\r
+ return 0 ;\r
+}\r
+\r
+extern int _isatty( int file )\r
+{\r
+ return 1 ;\r
+}\r
+\r
+extern int _lseek( int file, int ptr, int dir )\r
+{\r
+ return 0 ;\r
+}\r
+\r
+extern int _read(int file, char *ptr, int len)\r
+{\r
+ return 0 ;\r
+}\r
+\r
+extern int _write( int file, char *ptr, int len )\r
+{\r
+ int iIndex ;\r
+ \r
+ \r
+// for ( ; *ptr != 0 ; ptr++ )\r
+ for ( iIndex=0 ; iIndex < len ; iIndex++, ptr++ )\r
+ {\r
+ DBG_PutChar( *ptr ) ;\r
+ }\r
+\r
+ return iIndex ;\r
+}\r
+\r
+extern void _exit( int status )\r
+{\r
+ printf( "Exiting with status %d.\n", status ) ;\r
+\r
+ for ( ; ; ) ;\r
+}\r
+\r
+extern void _kill( int pid, int sig )\r
+{\r
+ return ; \r
+}\r
+\r
+extern int _getpid ( void )\r
+{\r
+ return -1 ;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Internal variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** Trace level can be set at applet initialization */\r
+#if !defined(NOTRACE) && (DYN_TRACES == 1)\r
+uint32_t dwTraceLevel = TRACE_LEVEL ;\r
+#endif\r
+\r
+/**\r
+ * Initializes the U(S)ART Console\r
+ *\r
+ * \param dwBaudRate U(S)ART baudrate.\r
+ * \param dwMCk Master clock frequency.\r
+ */\r
+extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk )\r
+{\r
+ const Pin pinsUART0[] = { PINS_UART0 } ;\r
+\r
+ PIO_Configure( pinsUART0, PIO_LISTSIZE( pinsUART0 ) ) ;\r
+\r
+ DBG_Configure( dwBaudRate, dwMCk ) ;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definiation\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* WAV letters "RIFF" */\r
+#define WAV_CHUNKID 0x46464952\r
+/* WAV letters "WAVE"*/\r
+#define WAV_FORMAT 0x45564157\r
+/* WAV letters "fmt "*/\r
+#define WAV_SUBCHUNKID 0x20746D66\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Check if the header of a Wav file is valid ot not.\r
+ *\r
+ * \param file Buffer holding the file to examinate.\r
+ * \return 1 if the header of a Wav file is valid; otherwise returns 0.\r
+ */\r
+unsigned char WAV_IsValid(const WavHeader *header)\r
+{\r
+ return ((header->chunkID == WAV_CHUNKID)\r
+ && (header->format == WAV_FORMAT)\r
+ && (header->subchunk1Size == 0x10));\r
+}\r
+\r
+/**\r
+ * \brief Display the information of the WAV file (sample rate, stereo/mono\r
+ * and frame size).\r
+ *\r
+ * \param header Wav head information.\r
+ */\r
+\r
+void WAV_DisplayInfo(const WavHeader *header)\r
+{\r
+ printf( "Wave file header information\n\r");\r
+ printf( "--------------------------------\n\r");\r
+ printf( " - Chunk ID = 0x%08X\n\r", header->chunkID);\r
+ printf( " - Chunk Size = %u\n\r", header->chunkSize);\r
+ printf( " - Format = 0x%08X\n\r", header->format);\r
+ printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID);\r
+ printf( " - Subchunk1 Size = %u\n\r", header->subchunk1Size);\r
+ printf( " - Audio Format = 0x%04X\n\r", header->audioFormat);\r
+ printf( " - Num. Channels = %d\n\r", header->numChannels);\r
+ printf( " - Sample Rate = %u\n\r", header->sampleRate);\r
+ printf( " - Byte Rate = %u\n\r", header->byteRate);\r
+ printf( " - Block Align = %d\n\r", header->blockAlign);\r
+ printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample);\r
+ printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID);\r
+ printf( " - Subchunk2 Size = %u\n\r", header->subchunk2Size);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation WM8904 driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ uint16_t value;\r
+ uint8_t address;\r
+}WM8904_PARA;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Read data from WM8904 Register.\r
+ *\r
+ * \param pTwid Pointer to twi driver structure\r
+ * \param device Twi slave address.\r
+ * \param regAddr Register address to read.\r
+ * \return value in the given register.\r
+ */\r
+uint16_t WM8904_Read(Twid *pTwid,\r
+ uint32_t device,\r
+ uint32_t regAddr)\r
+{\r
+ uint16_t bitsDataRegister;\r
+ uint8_t Tdata[2]={0,0};\r
+\r
+ TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0);\r
+ bitsDataRegister = (Tdata[0] << 8) | Tdata[1];\r
+ return bitsDataRegister;\r
+}\r
+\r
+/**\r
+ * \brief Write data to WM8904 Register.\r
+ *\r
+ * \param pTwid Pointer to twi driver structure\r
+ * \param device Twi slave address.\r
+ * \param regAddr Register address to read.\r
+ * \param data Data to write\r
+ */\r
+void WM8904_Write(Twid *pTwid,\r
+ uint32_t device,\r
+ uint32_t regAddr,\r
+ uint16_t data)\r
+{\r
+ uint8_t tmpData[2];\r
+\r
+ tmpData[0] = (data & 0xff00) >> 8;\r
+ tmpData[1] = data & 0xff;\r
+ TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0);\r
+}\r
+\r
+static WM8904_PARA wm8904_access_slow[]=\r
+{ \r
+ { 0x0000, 0}, /** R0 - SW Reset and ID */ \r
+ { 0x001A, 4}, /** R4 - Bias Control 0 */ \r
+ { 0x0047, 5}, /** R5 - VMID Control 0 */ /*insert_delay_ms 5*/\r
+\r
+ { 0x0043, 5}, /** R5 - VMID Control 0 */ \r
+ { 0x000B, 4}, /** R4 - Bias Control 0 */ \r
+\r
+ { 0x0003, 0x0C}, /** R12 - Power Management 0 CC */ \r
+\r
+ { 0x0003, 0x0E}, /** R14 - Power Management 2 */ \r
+ { 0x000C, 0x12}, /** R18 - Power Management 6 */\r
+ { 0x0000, 0x21}, /** R33 - DAC Digital 1 */ \r
+ { 0x0000, 0x3D}, /** R61 - Analogue OUT12 ZC */ \r
+ { 0x0001, 0x62}, /** R98 - Charge Pump 0 */ \r
+ { 0x0005, 0x68}, /** R104 - Class W 0 */ \r
+\r
+ //FLL setting,32.768KHZ MCLK input,12.288M output.\r
+ { 0x0000, 0x74}, /** R116 - FLL Control 1 */ \r
+ { 0x0704, 0x75}, /** R117 - FLL Control 2 */ \r
+ { 0x8000, 0x76}, /** R118 - FLL Control 3 */ \r
+ { 0x1760, 0x77}, /** R119 - FLL Control 4 */ \r
+ { 0x0005, 0x74}, /** R116 - FLL Control 1 */ /*insert_delay_ms 5*/\r
+\r
+ { 0x0C05, 0x15}, /** R21 - Clock Rates 1 */ \r
+ { 0x845E, 0x14}, /** R20 - Clock Rates 0 */ \r
+ { 0x4006, 0x16}, /** R22 - Clock Rates 2 */\r
+\r
+ ////////////////WM8904 IIS master\r
+ //BCLK=12.288MHz/8=1.536MHz\r
+ //LRCK=1.536MHz/32=48KHz\r
+ //{ 0x0042, 0x18}, /** R24 - Audio Interface 0 */ \r
+ { 0x0042, 0x19}, /** R25 - Audio Interface 1 */ \r
+ { 0x00E8, 0x1A}, /** R26 - Audio Interface 2 */ \r
+ { 0x0820, 0x1B}, /** R27 - Audio Interface 3 */ \r
+ ////////////////ADC\r
+\r
+ { 0x0003, 0x0C}, /** R12 - Power Management 0 */ \r
+ { 0x000F, 0x12}, /** R18 - Power Management 6 */ /*insert_delay_ms 5*/\r
+\r
+ { 0x0010, 0x2C}, /** R44 - Analogue Left Input 0 */ \r
+ { 0x0010, 0x2D}, /** R45 - Analogue Right Input 0 */ \r
+ { 0x0044, 0x2E}, /** R46 - Analogue Left Input 1 */ \r
+ { 0x0044, 0x2F}, /** R47 - Analogue Right Input 1 */\r
+\r
+ { 0x0011, 0x5A}, /** R90 - Analogue HP 0 */ \r
+ { 0x0033, 0x5A}, /** R90 - Analogue HP 0 */ \r
+\r
+ { 0x000F, 0x43}, /** R67 - DC Servo 0 */ \r
+ { 0x00F0, 0x44}, /** R68 - DC Servo 1 */ /*insert_delay_ms 100*/\r
+\r
+ //{ 0x0000, 0xFF}, /** end */ \r
+ { 0x0077, 0x5A}, /** R90 - Analogue HP 0 */ \r
+ { 0x00FF, 0x5A}, /** R90 - Analogue HP 0 */ \r
+ { 0x00B9, 0x39}, /** R57 - Analogue OUT1 Left */ \r
+ { 0x00B9, 0x3A}, /** R58 - Analogue OUT1 Right */ \r
+\r
+ //{ 0x0150, 0x18} ;Loopback\r
+};\r
+\r
+static WM8904_PARA wm8904_access_main[] = \r
+{ \r
+ //{ 0x8904, 0}, /** R0 - SW Reset and ID */ \r
+ //{ 0x0000, 1}, /** R1 - Revision */ \r
+ //{ 0x0000, 2}, /** R2 */ \r
+ //{ 0x0000, 3}, /** R3 */ \r
+ { 0x0019, 4}, /** R4 - Bias Control 0 */ \r
+ { 0x0043, 5}, /** R5 - VMID Control 0 */ \r
+ //{ 0x0003, 6}, /** R6 - Mic Bias Control 0 */ \r
+ //{ 0xC000, 7}, /** R7 - Mic Bias Control 1 */ \r
+ //{ 0x001E, 8}, /** R8 - Analogue DAC 0 */ \r
+ //{ 0xFFFF, 9}, /** R9 - mic Filter Control */ \r
+ //{ 0x0001, 10}, /** R10 - Analogue ADC 0 */ \r
+ //{ 0x0000, 11}, /** R11 */ \r
+ { 0x0003, 12}, /** R12 - Power Management 0 */ \r
+ //{ 0x0000, 13}, /** R13 */ \r
+ { 0x0003, 14}, /** R14 - Power Management 2 */ \r
+ //{ 0x0003, 15}, /** R15 - Power Management 3 */ \r
+ //{ 0x0000, 16}, /** R16 */ \r
+ //{ 0x0000, 17}, /** R17 */ \r
+ { 0x000F, 18}, /** R18 - Power Management 6 */ \r
+ //{ 0x0000, 19}, /** R19 */ \r
+ { 0x845E, 20}, /** R20 - Clock Rates 0 */ \r
+ //{ 0x3C07, 21}, /** R21 - Clock Rates 1 */ \r
+ { 0x0006, 22}, /** R22 - Clock Rates 2 */ \r
+ //{ 0x0000, 23}, /** R23 */ \r
+ //{ 0x1FFF, 24}, /** R24 - Audio Interface 0 */ \r
+ { 0x404A, 25}, /** R25 - Audio Interface 1 */ \r
+ //{ 0x0004, 26}, /** R26 - Audio Interface 2 */ \r
+ { 0x0840, 27}, /** R27 - Audio Interface 3 */ \r
+ //{ 0x0000, 28}, /** R28 */ \r
+ //{ 0x0000, 29}, /** R29 */ \r
+ //{ 0x00FF, 30}, /** R30 - DAC Digital Volume Left */ \r
+ //{ 0x00FF, 31}, /** R31 - DAC Digital Volume Right */ \r
+ //{ 0x0FFF, 32}, /** R32 - DAC Digital 0 */ \r
+ { 0x0000, 33}, /** R33 - DAC Digital 1 */ \r
+ //{ 0x0000, 34}, /** R34 */ \r
+ //{ 0x0000, 35}, /** R35 */ \r
+ //{ 0x00FF, 36}, /** R36 - ADC Digital Volume Left */ \r
+ //{ 0x00FF, 37}, /** R37 - ADC Digital Volume Right */ \r
+ //{ 0x0073, 38}, /** R38 - ADC Digital 0 */ \r
+ //{ 0x1800, 39}, /** R39 - Digital Microphone 0 */ \r
+ //{ 0xDFEF, 40}, /** R40 - DRC 0 */ \r
+ //{ 0xFFFF, 41}, /** R41 - DRC 1 */ \r
+ //{ 0x003F, 42}, /** R42 - DRC 2 */ \r
+ //{ 0x07FF, 43}, /** R43 - DRC 3 */ \r
+ { 0x0005, 44}, /** R44 - Analogue Left Input 0 */ \r
+ { 0x0005, 45}, /** R45 - Analogue Right Input 0 */ \r
+ { 0x0000, 46}, /** R46 - Analogue Left Input 1 */ \r
+ { 0x0000, 47}, /** R47 - Analogue Right Input 1 */ \r
+ //{ 0x0000, 48}, /** R48 */ \r
+ //{ 0x0000, 49}, /** R49 */ \r
+ //{ 0x0000, 50}, /** R50 */ \r
+ //{ 0x0000, 51}, /** R51 */ \r
+ //{ 0x0000, 52}, /** R52 */ \r
+ //{ 0x0000, 53}, /** R53 */ \r
+ //{ 0x0000, 54}, /** R54 */ \r
+ //{ 0x0000, 55}, /** R55 */ \r
+ //{ 0x0000, 56}, /** R56 */ \r
+ //{ 0x017F, 57}, /** R57 - Analogue OUT1 Left */ \r
+ { 0x00AD, 58}, /** R58 - Analogue OUT1 Right */ \r
+ //{ 0x017F, 59}, /** R59 - Analogue OUT2 Left */ \r
+ //{ 0x017F, 60}, /** R60 - Analogue OUT2 Right */ \r
+ //{ 0x000F, 61}, /** R61 - Analogue OUT12 ZC */ \r
+ //{ 0x0000, 62}, /** R62 */ \r
+ //{ 0x0000, 63}, /** R63 */ \r
+ //{ 0x0000, 64}, /** R64 */ \r
+ //{ 0x0000, 65}, /** R65 */ \r
+ //{ 0x0000, 66}, /** R66 */ \r
+ { 0x0003, 67}, /** R67 - DC Servo 0 */ \r
+ //{ 0xFFFF, 68}, /** R68 - DC Servo 1 */ \r
+ //{ 0x0F0F, 69}, /** R69 - DC Servo 2 */ \r
+ //{ 0x0000, 70}, /** R70 */ \r
+ //{ 0x007F, 71}, /** R71 - DC Servo 4 */ \r
+ //{ 0x007F, 72}, /** R72 - DC Servo 5 */ \r
+ //{ 0x00FF, 73}, /** R73 - DC Servo 6 */ \r
+ //{ 0x00FF, 74}, /** R74 - DC Servo 7 */ \r
+ //{ 0x00FF, 75}, /** R75 - DC Servo 8 */ \r
+ //{ 0x00FF, 76}, /** R76 - DC Servo 9 */ \r
+ //{ 0x0FFF, 77}, /** R77 - DC Servo Readback 0 */ \r
+ //{ 0x0000, 78}, /** R78 */ \r
+ //{ 0x0000, 79}, /** R79 */ \r
+ //{ 0x0000, 80}, /** R80 */ \r
+ //{ 0x0000, 81}, /** R81 */ \r
+ //{ 0x0000, 82}, /** R82 */ \r
+ //{ 0x0000, 83}, /** R83 */ \r
+ //{ 0x0000, 84}, /** R84 */ \r
+ //{ 0x0000, 85}, /** R85 */ \r
+ //{ 0x0000, 86}, /** R86 */ \r
+ //{ 0x0000, 87}, /** R87 */ \r
+ //{ 0x0000, 88}, /** R88 */ \r
+ //{ 0x0000, 89}, /** R89 */ \r
+ { 0x00FF, 90}, /** R90 - Analogue HP 0 */ \r
+ //{ 0x0000, 91}, /** R91 */ \r
+ //{ 0x0000, 92}, /** R92 */ \r
+ //{ 0x0000, 93}, /** R93 */ \r
+ //{ 0x00FF, 94}, /** R94 - Analogue Lineout 0 */ \r
+ //{ 0x0000, 95}, /** R95 */ \r
+ //{ 0x0000, 96}, /** R96 */ \r
+ //{ 0x0000, 97}, /** R97 */ \r
+ { 0x0001, 98}, /** R98 - Charge Pump 0 */ \r
+ //{ 0x0000, 99}, /** R99 */ \r
+ //{ 0x0000, 100}, /** R100 */\r
+ //{ 0x0000, 101}, /** R101 */ \r
+ //{ 0x0000, 102}, /** R102 */ \r
+ //{ 0x0000, 103}, /** R103 */ \r
+ { 0x0005, 104}, /** R104 - Class W 0 */ \r
+ //{ 0x0000, 105}, /** R105 */ \r
+ //{ 0x0000, 106}, /** R106 */ \r
+ //{ 0x0000, 107}, /** R107 */ \r
+ //{ 0x011F, 108}, /** R108 - Write Sequencer 0 */ \r
+ //{ 0x7FFF, 109}, /** R109 - Write Sequencer 1 */ \r
+ //{ 0x4FFF, 110}, /** R110 - Write Sequencer 2 */ \r
+ //{ 0x003F, 111}, /** R111 - Write Sequencer 3 */ \r
+ //{ 0x03F1, 112}, /** R112 - Write Sequencer 4 */ \r
+ //{ 0x0000, 113}, /** R113 */ \r
+ //{ 0x0000, 114}, /** R114 */ \r
+ //{ 0x0000, 115}, /** R115 */ \r
+ { 0x0004, 116}, /** R116 - FLL Control 1 */ \r
+ { 0x0704, 117}, /** R117 - FLL Control 2 */ \r
+ { 0x8000, 118}, /** R118 - FLL Control 3 */ \r
+ { 0x1760, 119}, /** R119 - FLL Control 4 */ \r
+ //{ 0x001B, 120}, /** R120 - FLL Control 5 */ \r
+ //{ 0x0014, 121}, /** R121 - GPIO Control 1 */ \r
+ //{ 0x0010, 122}, /** R122 - GPIO Control 2 */ \r
+ //{ 0x0010, 123}, /** R123 - GPIO Control 3 */ \r
+ //{ 0x0000, 124}, /** R124 - GPIO Control 4 */ \r
+ //{ 0x0000, 125}, /** R125 */ \r
+ //{ 0x000A, 126}, /** R126 - Digital Pulls */ \r
+ //{ 0x07FF, 127}, /** R127 - Interrupt Status */ \r
+ //{ 0x03FF, 128}, /** R128 - Interrupt Status Mask */ \r
+ //{ 0x03FF, 129}, /** R129 - Interrupt Polarity */ \r
+ //{ 0x03FF, 130}, /** R130 - Interrupt Debounce */\r
+ //{ 0x0000, 131}, /** R131 */ \r
+ //{ 0x0000, 132}, /** R132 */ \r
+ //{ 0x0000, 133}, /** R133 */ \r
+ //{ 0x0001, 134}, /** R134 - EQ1 */ \r
+ //{ 0x001F, 135}, /** R135 - EQ2 */ \r
+ //{ 0x001F, 136}, /** R136 - EQ3 */ \r
+ //{ 0x001F, 137}, /** R137 - EQ4 */ \r
+ //{ 0x001F, 138}, /** R138 - EQ5 */ \r
+ //{ 0x001F, 139}, /** R139 - EQ6 */ \r
+ //{ 0xFFFF, 140}, /** R140 - EQ7 */ \r
+ //{ 0xFFFF, 141}, /** R141 - EQ8 */ \r
+ //{ 0xFFFF, 142}, /** R142 - EQ9 */ \r
+ //{ 0xFFFF, 143}, /** R143 - EQ10 */ \r
+ //{ 0xFFFF, 144}, /** R144 - EQ11 */ \r
+ //{ 0xFFFF, 145}, /** R145 - EQ12 */ \r
+ //{ 0xFFFF, 146}, /** R146 - EQ13 */ \r
+ //{ 0xFFFF, 147}, /** R147 - EQ14 */ \r
+ //{ 0xFFFF, 148}, /** R148 - EQ15 */ \r
+ //{ 0xFFFF, 149}, /** R149 - EQ16 */ \r
+ //{ 0xFFFF, 150}, /** R150 - EQ17 */ \r
+ //{ 0xFFFF, 151}, /** R151wm8523_dai - EQ18 */ \r
+ //{ 0xFFFF, 152}, /** R152 - EQ19 */ \r
+ //{ 0xFFFF, 153}, /** R153 - EQ20 */ \r
+ //{ 0xFFFF, 154}, /** R154 - EQ21 */ \r
+ //{ 0xFFFF, 155}, /** R155 - EQ22 */ \r
+ //{ 0xFFFF, 156}, /** R156 - EQ23 */ \r
+ //{ 0xFFFF, 157}, /** R157 - EQ24 */ \r
+ //{ 0x0000, 158}, /** R158 */ \r
+ //{ 0x0000, 159}, /** R159 */ \r
+ //{ 0x0000, 160}, /** R160 */ \r
+ //{ 0x0002, 161}, /** R161 - Control Interface Test 1 */ \r
+ //{ 0x0000, 162}, /** R162 */ \r
+ //{ 0x0000, 163}, /** R163 */ \r
+ //{ 0x0000, 164}, /** R164 */ \r
+ //{ 0x0000, 165}, /** R165 */ \r
+ //{ 0x0000, 166}, /** R166 */ \r
+ //{ 0x0000, 167}, /** R167 */ \r
+ //{ 0x0000, 168}, /** R168 */ \r
+ //{ 0x0000, 169}, /** R169 */ \r
+ //{ 0x0000, 170}, /** R170 */ \r
+ //{ 0x0000, 171}, /** R171 */ \r
+ //{ 0x0000, 172}, /** R172 */ \r
+ //{ 0x0000, 173}, /** R173 */ \r
+ //{ 0x0000, 174}, /** R174 */ \r
+ //{ 0x0000, 175}, /** R175 */ \r
+ //{ 0x0000, 176}, /** R176 */ \r
+ //{ 0x0000, 177}, /** R177 */ \r
+ //{ 0x0000, 178}, /** R178 */ \r
+ //{ 0x0000, 179}, /** R179 */ \r
+ //{ 0x0000, 180}, /** R180 */ \r
+ //{ 0x0000, 181}, /** R181 */ \r
+ //{ 0x0000, 182}, /** R182 */ \r
+ //{ 0x0000, 183}, /** R183 */ \r
+ //{ 0x0000, 184}, /** R184 */ \r
+ //{ 0x0000, 185}, /** R185 */ \r
+ //{ 0x0000, 186}, /** R186 */ \r
+ //{ 0x0000, 187}, /** R187 */ \r
+ //{ 0x0000, 188}, /** R188 */ \r
+ //{ 0x0000, 189}, /** R189 */ \r
+ //{ 0x0000, 190}, /** R190 */ \r
+ //{ 0x0000, 191}, /** R191 */ \r
+ //{ 0x0000, 192}, /** R192 */ \r
+ //{ 0x0000, 193}, /** R193 */ \r
+ //{ 0x0000, 194}, /** R194 */ \r
+ //{ 0x0000, 195}, /** R195 */ \r
+ //{ 0x0000, 196}, /** R196 */ \r
+ //{ 0x0000, 197}, /** R197 */ \r
+ //{ 0x0000, 198}, /** R198 */ \r
+ //{ 0x0000, 199}, /** R199 */ \r
+ //{ 0x0000, 200}, /** R200 */ \r
+ //{ 0x0000, 201}, /** R201 */ \r
+ //{ 0x0000, 202}, /** R202 */ \r
+ //{ 0x0000, 203}, /** R203 */ \r
+ //{ 0x0070, 204}, /** R204 - Analogue Output Bias 0 */ \r
+ //{ 0x0000, 205}, /** R205 */ \r
+ //{ 0x0000, 206}, /** R206 */ \r
+ //{ 0x0000, 207}, /** R207 */ \r
+ //{ 0x0000, 208}, /** R208 */ \r
+ //{ 0x0000, 209}, /** R209 */ \r
+ //{ 0x0000, 210}, /** R210 */ \r
+ //{ 0x0000, 211}, /** R211 */ \r
+ //{ 0x0000, 212}, /** R212 */ \r
+ //{ 0x0000, 213}, /** R213 */ \r
+ //{ 0x0000, 214}, /** R214 */ \r
+ //{ 0x0000, 215}, /** R215 */ \r
+ //{ 0x0000, 216}, /** R216 */ \r
+ //{ 0x0000, 217}, /** R217 */ \r
+ //{ 0x0000, 218}, /** R218 */ \r
+ //{ 0x0000, 219}, /** R219 */ \r
+ //{ 0x0000, 220}, /** R220 */ \r
+ //{ 0x0000, 221}, /** R221 */ \r
+ //{ 0x0000, 222}, /** R222 */ \r
+ //{ 0x0000, 223}, /** R223 */ \r
+ //{ 0x0000, 224}, /** R224 */ \r
+ //{ 0x0000, 225}, /** R225 */ \r
+ //{ 0x0000, 226}, /** R226 */ \r
+ //{ 0x0000, 227}, /** R227 */ \r
+ //{ 0x0000, 228}, /** R228 */ \r
+ //{ 0x0000, 229}, /** R229 */ \r
+ //{ 0x0000, 230}, /** R230 */ \r
+ //{ 0x0000, 231}, /** R231 */ \r
+ //{ 0x0000, 232}, /** R232 */ \r
+ //{ 0x0000, 233}, /** R233 */ \r
+ //{ 0x0000, 234}, /** R234 */ \r
+ //{ 0x0000, 235}, /** R235 */ \r
+ //{ 0x0000, 236}, /** R236 */ \r
+ //{ 0x0000, 237}, /** R237 */ \r
+ //{ 0x0000, 238}, /** R238 */ \r
+ //{ 0x0000, 239}, /** R239 */ \r
+ //{ 0x0000, 240}, /** R240 */ \r
+ //{ 0x0000, 241}, /** R241 */ \r
+ //{ 0x0000, 242}, /** R242 */ \r
+ //{ 0x0000, 243}, /** R243 */ \r
+ //{ 0x0000, 244}, /** R244 */ \r
+ //{ 0x0000, 245}, /** R245 */ \r
+ //{ 0x0000, 246}, /** R246 */ \r
+ //{ 0x0000, 247}, /** R247 - FLL NCO Test 0 */ \r
+ //{ 0x0019, 248}, /** R248 - FLL NCO Test 1 */ \r
+ { 0x55AA, 255} /** end */ \r
+};\r
+\r
+uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK)\r
+{\r
+ uint8_t count, size;\r
+ uint16_t data = 0;\r
+\r
+ // Reset (write Reg@0x0 to reset)\r
+ WM8904_Write(pTwid, device, 0, 0xFFFF);\r
+\r
+ for(data=0;data<1000;data++);\r
+ //wait ready \r
+ while(data!=0x8904)\r
+ data=WM8904_Read(pTwid, device, 0);\r
+\r
+ if (PMC_MCKR_CSS_SLOW_CLK == PCK)\r
+ {\r
+ {\r
+ size = sizeof(wm8904_access_slow)/4+1;\r
+ for(count=0; count<size; count++)\r
+ {\r
+ WM8904_Write(pTwid, device, wm8904_access_slow[count].address, wm8904_access_slow[count].value);\r
+ if(((wm8904_access_slow[count].address==0x05)&&(wm8904_access_slow[count].value==0x0047))\r
+ ||((wm8904_access_slow[count].address==0x74)&&(wm8904_access_slow[count].value==0x0005))\r
+ ||((wm8904_access_slow[count].address==0x12)&&(wm8904_access_slow[count].value==0x000F)))\r
+ {\r
+ Wait(5);\r
+ }\r
+ if (((wm8904_access_slow[count].address==0x44)&&(wm8904_access_slow[count].value==0x00F0))\r
+ ||((wm8904_access_slow[count].address==0x3A)&&(wm8904_access_slow[count].value==0x00B9)))\r
+ { \r
+ Wait(100);\r
+ }\r
+ } \r
+ } \r
+ }\r
+ else if (PMC_MCKR_CSS_MAIN_CLK == PCK)\r
+ {\r
+ for(count=0;count<255;count++)\r
+ {\r
+ if(wm8904_access_main[count].address<255)\r
+ {\r
+ WM8904_Write(pTwid, device, wm8904_access_main[count].address, wm8904_access_main[count].value);\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ printf("W: PCK not supported! \n\r");\r
+ while(1);\r
+ }\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device)\r
+{\r
+ //{ 0x0005, 44}, /** R44 - Analogue Left Input 0 */ \r
+ //{ 0x0005, 45}, /** R45 - Analogue Right Input 0 */ \r
+ //{ 0x0000, 46}, /** R46 - Analogue Left Input 1 */ \r
+ //{ 0x0010, 47}, /** R47 - Analogue Right Input 1 */\r
+ WM8904_Write(pTwid, device, 0x2C, 0x0008);\r
+ WM8904_Write(pTwid, device, 0x2D, 0x0005);\r
+ WM8904_Write(pTwid, device, 0x2E, 0x0000);\r
+ WM8904_Write(pTwid, device, 0x2F, 0x0010);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef SAMS7_CHIP_H\r
+#define SAMS7_CHIP_H\r
+\r
+\r
+/* Define WEAK attribute */\r
+#if defined ( __CC_ARM )\r
+ #define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ )\r
+ #define WEAK __weak\r
+#elif defined ( __GNUC__ )\r
+ #define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+ #define NO_INIT\r
+#elif defined ( __ICCARM__ )\r
+ #define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+ #define NO_INIT\r
+#endif\r
+\r
+/* Define RAMFUNC attribute */\r
+#ifdef __ICCARM__\r
+#define RAMFUNC __ramfunc\r
+#else\r
+#define RAMFUNC __attribute__ ((section (".ramfunc")))\r
+#endif\r
+\r
+/*\r
+ * Peripherals registers definitions\r
+ */\r
+#include "include/samv7/sam.h"\r
+\r
+/*\r
+ * Core\r
+ */\r
+//#include "include/exceptions.h"\r
+\r
+#define memory_barrier() __DSB();\r
+/*\r
+ * Peripherals\r
+ */\r
+\r
+#include "include/acc.h"\r
+#include "include/aes.h"\r
+#include "include/afec.h"\r
+#include "include/efc.h"\r
+#include "include/pio.h"\r
+#include "include/pio_it.h"\r
+#include "include/efc.h"\r
+#include "include/mpu.h"\r
+#include "include/gmac.h"\r
+#include "include/gmacd.h"\r
+#include "include/video.h"\r
+#include "include/icm.h"\r
+#include "include/isi.h"\r
+#include "include/exceptions.h"\r
+#include "include/pio_capture.h"\r
+#include "include/rtc.h"\r
+#include "include/rtt.h"\r
+#include "include/tc.h"\r
+#include "include/timetick.h"\r
+#include "include/twi.h"\r
+#include "include/twid.h"\r
+#include "include/flashd.h"\r
+#include "include/pmc.h"\r
+#include "include/pwmc.h"\r
+#include "include/supc.h"\r
+#include "include/usart.h"\r
+#include "include/uart.h"\r
+#include "include/isi.h"\r
+#include "include/hsmci.h"\r
+#include "include/ssc.h"\r
+#include "include/twi.h"\r
+#include "include/twid.h"\r
+#include "include/trng.h"\r
+#include "include/wdt.h"\r
+#include "include/spi.h"\r
+#include "include/qspi.h"\r
+#include "include/trace.h"\r
+#include "include/xdmac.h"\r
+#include "include/xdma_hardware_interface.h"\r
+#include "include/xdmad.h"\r
+#include "include/mcid.h"\r
+#include "include/spi_dma.h"\r
+#include "include/qspi_dma.h"\r
+#include "include/uart_dma.h"\r
+#include "include/usart_dma.h"\r
+#include "include/afe_dma.h"\r
+#include "include/dac_dma.h"\r
+\r
+#define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral( dwId )\r
+#define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral( dwId )\r
+ \r
+ \r
+/* SCB Interrupt Control State Register Definitions */\r
+#ifndef SCB_VTOR_TBLBASE_Pos\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+#endif\r
+\r
+#define RESET_CYCLE_COUNTER() { DWT->CTRL = 0;__ISB(); \\r
+ while(DWT->CYCCNT != 0)DWT->CYCCNT = 0;\\r
+ DWT->CTRL = DWT_CTRL_CYCCNTENA_Msk; }\r
+\r
+#define GET_CYCLE_COUNTER(x) x=DWT->CYCCNT;\r
+\r
+#endif /* SAMS7_CHIP_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for ACC\r
+ * -# Initialize the ACC with ACC_Initialize().\r
+ * -# Select the active channel using ACC_EnableChannel()\r
+ * -# Start the conversion with ACC_StartConversion()\r
+ * -# Wait the end of the conversion by polling status with ACC_GetStatus()\r
+ * -# Finally, get the converted data using ACC_GetConvertedData()\r
+ *\r
+ */\r
+#ifndef _ACC_\r
+#define _ACC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+#define ACC_SELPLUS_AD12B0 0\r
+#define ACC_SELPLUS_AD12B1 1\r
+#define ACC_SELPLUS_AD12B2 2\r
+#define ACC_SELPLUS_AD12B3 3\r
+#define ACC_SELPLUS_AD12B4 4\r
+#define ACC_SELPLUS_AD12B5 5\r
+#define ACC_SELPLUS_AD12B6 6\r
+#define ACC_SELPLUS_AD12B7 7\r
+#define ACC_SELMINUS_TS 0\r
+#define ACC_SELMINUS_ADVREF 1\r
+#define ACC_SELMINUS_DAC0 2\r
+#define ACC_SELMINUS_DAC1 3\r
+#define ACC_SELMINUS_AD12B0 4\r
+#define ACC_SELMINUS_AD12B1 5\r
+#define ACC_SELMINUS_AD12B2 6\r
+#define ACC_SELMINUS_AD12B3 7\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+#define ACC_CfgModeReg(pAcc, mode) { \\r
+ (pAcc)->ACC_MR = (mode);\\r
+ }\r
+\r
+#define ACC_GetModeReg( pAcc ) ((pAcc)->ACC_MR)\r
+\r
+#define ACC_StartConversion( pAcc ) ((pAcc)->ACC_CR = ACC_CR_START)\r
+\r
+#define ACC_SoftReset( pAcc ) ((pAcc)->ACC_CR = ACC_CR_SWRST)\r
+\r
+#define ACC_EnableChannel( pAcc, dwChannel ) {\\r
+ assert( dwChannel < 16 ) ;\\r
+ (pAcc)->ACC_CHER = (1 << (dwChannel));\\r
+ }\r
+\r
+#define ACC_DisableChannel( pAcc, dwChannel ) {\\r
+ assert( dwChannel < 16 ) ;\\r
+ (pAcc)->ACC_CHDR = (1 << (dwChannel));\\r
+ }\r
+\r
+#define ACC_EnableIt( pAcc, dwMode ) {\\r
+ assert( ((dwMode)&0xFFF00000)== 0 ) ;\\r
+ (pAcc)->ACC_IER = (dwMode);\\r
+ }\r
+\r
+#define ACC_DisableIt( pAcc, dwMode ) {\\r
+ assert( ((dwMode)&0xFFF00000)== 0 ) ;\\r
+ (pAcc)->ACC_IDR = (dwMode);\\r
+ }\r
+\r
+#define ACC_EnableDataReadyIt( pAcc ) ((pAcc)->ACC_IER = AT91C_ACC_DRDY)\r
+\r
+#define ACC_GetStatus( pAcc ) ((pAcc)->ACC_ISR)\r
+\r
+#define ACC_GetChannelStatus( pAcc ) ((pAcc)->ACC_CHSR)\r
+\r
+#define ACC_GetInterruptMaskStatus( pAcc ) ((pAcc)->ACC_IMR)\r
+\r
+#define ACC_GetLastConvertedData( pAcc ) ((pAcc)->ACC_LCDR)\r
+\r
+#define ACC_CfgAnalogCtrlReg( pAcc, dwMode ) {\\r
+ assert( ((dwMode) & 0xFFFCFF3C) == 0 ) ;\\r
+ (pAcc)->ACC_ACR = (dwMode);\\r
+ }\r
+\r
+#define ACC_CfgExtModeReg( pAcc, extmode ) {\\r
+ assert( ((extmode) & 0xFF00FFFE) == 0 ) ;\\r
+ (pAcc)->ACC_EMR = (extmode);\\r
+ }\r
+\r
+#define ACC_GetAnalogCtrlReg( pAcc ) ((pAcc)->ACC_ACR)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, uint8_t ucSelminus,\r
+ uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert ) ;\r
+\r
+extern void ACC_SetComparisonPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus ) ;\r
+\r
+extern uint32_t ACC_GetComparisonResult( Acc* pAcc, uint32_t dwStatus ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _ACC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for ADC.\r
+ * -# Initialize the ADC with ADC_Initialize().\r
+ * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming().\r
+ * -# Select the active channel using ADC_EnableChannel().\r
+ * -# Start the conversion with ADC_StartConversion().\r
+ * -# Wait the end of the conversion by polling status with ADC_GetStatus().\r
+ * -# Finally, get the converted data using ADC_GetConvertedData() or ADC_GetLastConvertedData().\r
+ *\r
+*/\r
+#ifndef _ADC_\r
+#define _ADC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <assert.h>\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/* Max. ADC Clock Frequency (Hz) */\r
+#define ADC_CLOCK_MAX 20000000\r
+\r
+/* Max. normal ADC startup time (us) */\r
+#define ADC_STARTUP_NORMAL_MAX 40\r
+/* Max. fast ADC startup time (us) */\r
+#define ADC_STARTUP_FAST_MAX 12\r
+\r
+/* Definitions for ADC channels */\r
+#define ADC_CHANNEL_0 0\r
+#define ADC_CHANNEL_1 1\r
+#define ADC_CHANNEL_2 2\r
+#define ADC_CHANNEL_3 3\r
+#define ADC_CHANNEL_4 4\r
+#define ADC_CHANNEL_5 5\r
+#define ADC_CHANNEL_6 6\r
+#define ADC_CHANNEL_7 7\r
+#define ADC_CHANNEL_8 8\r
+#define ADC_CHANNEL_9 9\r
+#define ADC_CHANNEL_10 10\r
+#define ADC_CHANNEL_11 11\r
+#define ADC_CHANNEL_12 12\r
+#define ADC_CHANNEL_13 13\r
+#define ADC_CHANNEL_14 14\r
+#define ADC_CHANNEL_15 15\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR)\r
+\r
+#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START)\r
+\r
+#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL)\r
+\r
+#define ADC_EnableChannel( pAdc, dwChannel ) {\\r
+ (pAdc)->ADC_CHER = (1 << (dwChannel));\\r
+ }\r
+\r
+#define ADC_DisableChannel(pAdc, dwChannel) {\\r
+ (pAdc)->ADC_CHDR = (1 << (dwChannel));\\r
+ }\r
+\r
+#define ADC_EnableIt(pAdc, dwMode) {\\r
+ (pAdc)->ADC_IER = (dwMode);\\r
+ }\r
+\r
+#define ADC_DisableIt(pAdc, dwMode) {\\r
+ (pAdc)->ADC_IDR = (dwMode);\\r
+ }\r
+\r
+#define ADC_SetChannelGain(pAdc,dwMode) {\\r
+ (pAdc)->ADC_CGR = dwMode;\\r
+ }\r
+\r
+#define ADC_SetChannelOffset(pAdc,dwMode) {\\r
+ (pAdc)->ADC_COR = dwMode;\\r
+ }\r
+\r
+#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY)\r
+\r
+#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR)\r
+\r
+#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk))\r
+\r
+#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR)\r
+\r
+#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR)\r
+\r
+#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern void ADC_Initialize( Adc* pAdc, uint32_t dwId );\r
+extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck );\r
+extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling );\r
+extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel );\r
+extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode);\r
+extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis );\r
+extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis );\r
+extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis );\r
+extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis );\r
+extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 );\r
+extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh );\r
+extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis );\r
+extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis );\r
+extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ;\r
+extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ;\r
+extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ;\r
+extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ;\r
+extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ;\r
+extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv);\r
+extern uint32_t ADC_GetTsXPosition(Adc *pADC);\r
+extern uint32_t ADC_GetTsYPosition(Adc *pADC);\r
+extern uint32_t ADC_GetTsPressure(Adc *pADC);\r
+extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime);\r
+extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis);\r
+extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs );\r
+extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs );\r
+extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod);\r
+extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode);\r
+extern void ADC_TsCalibration( Adc *pAdc );\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _ADC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _AES_\r
+#define _AES_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Definition */\r
+/*------------------------------------------------------------------------------*/\r
+#define AES_MR_CIPHER_ENCRYPT 1\r
+#define AES_MR_CIPHER_DECRYPT 0\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void AES_Start(void);\r
+extern void AES_SoftReset(void);\r
+extern void AES_Recount(void);\r
+extern void AES_Configure(uint32_t mode);\r
+extern void AES_EnableIt(uint32_t sources);\r
+extern void AES_DisableIt(uint32_t sources);\r
+extern uint32_t AES_GetStatus(void);\r
+extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength);\r
+extern void AES_SetInput(uint32_t *data);\r
+extern void AES_GetOutput(uint32_t *data);\r
+extern void AES_SetVector(const uint32_t *pVector);\r
+extern void AES_SetAadLen(uint32_t len);\r
+extern void AES_SetDataLen(uint32_t len);\r
+extern void AES_SetGcmHash(uint32_t * hash);\r
+extern void AES_GetGcmTag(uint32_t * tag);\r
+extern void AES_GetGcmCounter(uint32_t * counter);\r
+extern void AES_GetGcmH(uint32_t *h);\r
+\r
+\r
+#endif /* #ifndef _AES_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for AFEC.\r
+ * -# Initialize the AFEC with AFEC_Initialize().\r
+ * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming().\r
+ * -# Select the active channel using AFEC_EnableChannel().\r
+ * -# Start the conversion with AFEC_StartConversion().\r
+ * -# Wait the end of the conversion by polling status with AFEC_GetStatus().\r
+ * -# Finally, get the converted data using AFEC_GetConvertedData() or AFEC_GetLastConvertedData().\r
+ *\r
+*/\r
+#ifndef _AFE_DMA_\r
+#define _AFE_DMA_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** AFE transfer complete callback. */\r
+typedef void (*AfeCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief Spi Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the AFE_SendCommand function to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct\r
+{\r
+ /** Pointer to the Rx data. */\r
+ uint32_t *pRxBuff;\r
+ /** Rx size in bytes. */\r
+ uint16_t RxSize;\r
+ /** Callback function invoked at the end of transfer. */\r
+ AfeCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+} AfeCmd ;\r
+\r
+\r
+/** Constant structure associated with AFE port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct \r
+{\r
+ /** Pointer to AFE Hardware registers */\r
+ Afec* pAfeHw ;\r
+ /** Current SpiCommand being processed */\r
+ AfeCmd *pCurrentCommand ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad;\r
+ /** AFEC Id as defined in the product datasheet */\r
+ uint8_t afeId ;\r
+ /** Mutual exclusion semaphore. */\r
+ volatile int8_t semaphore ;\r
+} AfeDma;\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+#define AFE_OK 0\r
+#define AFE_ERROR 1\r
+#define AFE_ERROR_LOCK 2\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern uint32_t Afe_ConfigureDma( AfeDma *pAfed ,\r
+ Afec *pAfeHw ,\r
+ uint8_t AfeId,\r
+ sXdmad *pXdmad );\r
+extern uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand);\r
+\r
+\r
+#endif /* #ifndef _AFE_DMA_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for AFEC.\r
+ * -# Initialize the AFEC with AFEC_Initialize().\r
+ * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming().\r
+ * -# Select the active channel using AFEC_EnableChannel().\r
+ * -# Start the conversion with AFEC_StartConversion().\r
+ * -# Wait the end of the conversion by polling status with AFEC_GetStatus().\r
+ * -# Finally, get the converted data using AFEC_GetConvertedData() or AFEC_GetLastConvertedData().\r
+ *\r
+*/\r
+#ifndef _AFEC_\r
+#define _AFEC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <assert.h>\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */\r
+#define AFEC_MR_SETTLING_Pos 20\r
+#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) /**< \brief (AFEC_MR) Trigger Selection */\r
+#define AFEC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */\r
+#define AFEC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/\r
+#define AFEC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/\r
+\r
+/***************************** Single Trigger Mode ****************************/\r
+#define AFEC_EMR_STM_Pos 25\r
+#define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) /**< \brief (AFEC_EMR) Single Trigger Mode */\r
+#define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to get an averaged result. */\r
+#define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required to get an averaged value. */\r
+\r
+/***************************** TAG of the AFEC_LDCR Register ******************/\r
+#define AFEC_EMR_TAG_Pos 24\r
+#define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */\r
+#define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero in AFEC_LDCR. */\r
+#define AFEC_EMR_TAG_APPENDS (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel number to the conversion result in AFEC_LDCR register. */\r
+\r
+/***************************** Compare All Channels ******************/\r
+#define AFEC_EMR_CMPALL_Pos 9\r
+#define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) /**< \brief (AFEC_EMR) Compare All Channels */\r
+#define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) /**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in CMPSEL field is compared. */\r
+#define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */\r
+\r
+#define AFEC_ACR_PGA0_ON (0x1u << 2)\r
+#define AFEC_ACR_PGA1_ON (0x1u << 3)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#define AFEC_GetModeReg( pAFEC ) ((pAFEC)->AFEC_MR)\r
+#define AFEC_SetModeReg( pAFEC, mode ) ((pAFEC)->AFEC_MR = mode)\r
+\r
+#define AFEC_GetExtModeReg( pAFEC ) ((pAFEC)->AFEC_EMR)\r
+#define AFEC_SetExtModeReg( pAFEC, mode ) ((pAFEC)->AFEC_EMR = mode)\r
+\r
+#define AFEC_StartConversion( pAFEC ) ((pAFEC)->AFEC_CR = AFEC_CR_START)\r
+\r
+#define AFEC_EnableChannel( pAFEC, dwChannel ) {\\r
+ (pAFEC)->AFEC_CHER = (1 << (dwChannel));\\r
+ }\r
+\r
+#define AFEC_DisableChannel(pAFEC, dwChannel) {\\r
+ (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\\r
+ }\r
+\r
+#define AFEC_EnableIt(pAFEC, dwMode) {\\r
+ (pAFEC)->AFEC_IER = (dwMode);\\r
+ }\r
+\r
+#define AFEC_DisableIt(pAFEC, dwMode) {\\r
+ (pAFEC)->AFEC_IDR = (dwMode);\\r
+ }\r
+\r
+#define AFEC_SetChannelGain(pAFEC,dwMode) {\\r
+ (pAFEC)->AFEC_CG1R = dwMode;\\r
+ }\r
+\r
+#define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY)\r
+\r
+#define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR)\r
+\r
+#define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk))\r
+\r
+#define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR)\r
+\r
+#define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR)\r
+\r
+#define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern void AFEC_Initialize( Afec* pAFEC, uint32_t dwId );\r
+extern uint32_t AFEC_SetClock( Afec* pAFEC, uint32_t dwPres, uint32_t dwMck );\r
+extern void AFEC_SetTiming( Afec* pAFEC, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling );\r
+extern void AFEC_SetTrigger( Afec* pAFEC, uint32_t dwTrgSel );\r
+extern void AFEC_SetAnalogChange( Afec* pAFE, uint8_t bEnDis );\r
+extern void AFEC_SetSleepMode( Afec* pAFEC, uint8_t bEnDis );\r
+extern void AFEC_SetFastWakeup( Afec* pAFEC, uint8_t bEnDis );\r
+extern void AFEC_SetSequenceMode( Afec* pAFEC, uint8_t bEnDis );\r
+extern void AFEC_SetSequence( Afec* pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2 );\r
+extern void AFEC_SetSequenceByList( Afec* pAFEC, uint8_t ucChList[], uint8_t ucNumCh );\r
+extern void AFEC_SetTagEnable( Afec* pAFEC, uint8_t bEnDis );\r
+extern void AFEC_SetCompareChannel( Afec* pAFEC, uint32_t dwChannel ) ;\r
+extern void AFEC_SetCompareMode( Afec* pAFEC, uint32_t dwMode ) ;\r
+extern void AFEC_SetComparisonWindow( Afec* pAFEC, uint32_t dwHi_Lo ) ;\r
+extern uint8_t AFEC_CheckConfiguration( Afec* pAFEC, uint32_t dwMcK ) ;\r
+extern uint32_t AFEC_GetConvertedData( Afec* pAFEC, uint32_t dwChannel ) ;\r
+extern void AFEC_SetStartupTime( Afec* pAFEC, uint32_t dwUs );\r
+extern void AFEC_SetTrackingTime( Afec* pAFEC, uint32_t dwNs );\r
+extern void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset );\r
+extern void AFEC_SetAnalogControl( Afec *pAFE, uint32_t control);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _AFEC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ * Definitions and prototypes for Controller Area Network (CAN)\r
+ * peripheral operations.\r
+ */\r
+\r
+/** \ingroup lib_chip\r
+ * \ingroup cand_module\r
+ * \addtogroup can_module Working with CAN\r
+ *\r
+ * \section Purpose\r
+ * Interface for Controller Area Network (CAN).\r
+ *\r
+ * \section Usage\r
+ *\r
+ * Before CAN operation, its peripheral clock should be enabled, see\r
+ * PMC_EnablePeripheral().\r
+ *\r
+ * Modify CAN registers or register fields with API functions:\r
+ * - Modify CAN Mode register with CAN_ConfigureMode().\r
+ * - Enable/Disable CAN with CAN_Enable().\r
+ * - Change CAN interrupt settings with CAN_EnableIt(), CAN_DisableIt(),\r
+ * get interrupt mask by CAN_GetItMask().\r
+ * - Get CAN status with CAN_GetStatus().\r
+ * - Setup CAN baudrate via CAN_CalcBaudrate().\r
+ * - Start several mailbox transmition through CAN_Command().\r
+ * - The following functions setup mailboxes for message transfer:\r
+ * - CAN_ConfigureMessageMode() : setup _MMRx.\r
+ * - CAN_ConfigureMessageAcceptanceMask() : setup _MARx.\r
+ * - CAN_ConfigureMessageID() : setup _MIDx.\r
+ * - CAN_SetMessage() : setup _MDLx and _MDHx.\r
+ * - CAN_MessageControl() : setup _MCRx.\r
+ * - The following get status and data from mailbox:\r
+ * - CAN_GetMessage() : \r
+ * - CAN_GetMessageStatus() : \r
+ */\r
+\r
+#ifndef _CAN_H_\r
+#define _CAN_H_\r
+/**@{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Number of mailboxes in a CAN controller */\r
+#define CAN_NUM_MAILBOX 8\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void CAN_ConfigureMode(Can * pCan,uint32_t dwMr);\r
+void CAN_Enable(Can * pCan,uint8_t bEnDis);\r
+void CAN_EnableLowPower(Can * pCan,uint8_t bEnDis);\r
+void CAN_EnableAutobaud(Can * pCan,uint8_t bEnDis);\r
+void CAN_EnableOverloadFrame(Can * pCan,uint8_t bEnDis);\r
+void CAN_EnableTimeStampEof(Can * pCan,uint8_t bEofSof);\r
+void CAN_EnableTimeTriggerMode(Can * pCan,uint8_t bEnDis);\r
+void CAN_EnableTimerFreeze(Can * pCan,uint8_t bEnDis);\r
+void CAN_DisableRepeat(Can * pCan,uint8_t bDisEn);\r
+\r
+void CAN_EnableIt(Can * pCan,uint32_t dwSources);\r
+void CAN_DisableIt(Can * pCan,uint32_t dwSources);\r
+uint32_t CAN_GetItMask(Can * pCan);\r
+uint32_t CAN_GetStatus(Can * pCan);\r
+\r
+uint8_t CAN_CalcBaudrate(Can * pCan, uint32_t dwBaud, uint32_t dwMck);\r
+void CAN_ConfigureBaudrate(Can * pCan,uint32_t dwBr);\r
+void CAN_SetSamplingMode(Can * pCan,uint8_t bAvg3);\r
+\r
+uint32_t CAN_GetTimer(Can * pCan);\r
+uint32_t CAN_GetTimestamp(Can * pCan);\r
+\r
+uint32_t CAN_GetErrorCount(Can * pCan);\r
+uint32_t CAN_GetRxErrorCount(Can * pCan);\r
+uint32_t CAN_GetTxErrorCount(Can * pCan);\r
+\r
+void CAN_Command(Can * pCan,uint32_t dwRequests);\r
+void CAN_ResetTimer(Can * pCan);\r
+void CAN_Tx(Can * pCan,uint8_t bMb);\r
+\r
+void CAN_Abort(Can * pCan,uint32_t dwAborts);\r
+void CAN_AbortMailbox(Can * pCan,uint8_t bMb);\r
+\r
+void CAN_ConfigureMessageMode(Can * pCan,uint8_t bMb,uint32_t dwMr);\r
+uint32_t CAN_GetMessageMode(Can * pCan,uint8_t bMb);\r
+void CAN_SetTimemark(Can * pCan,uint8_t bMb,uint8_t bTimemarks);\r
+void CAN_SetPriority(Can * pCan,uint8_t bMb,uint8_t bPriority);\r
+void CAN_SetObjectType(Can * pCan,uint8_t bMb,uint8_t bType);\r
+\r
+void CAN_ConfigureMessageAcceptanceMask(Can * pCan,uint8_t bMb,uint32_t dwMAM);\r
+uint32_t CAN_GetMessageAcceptanceMask(Can * pCan,uint8_t bMb);\r
+void CAN_ConfigureIdentifierMask(Can * pCan,uint8_t bMb,uint8_t bIdCfg);\r
+void CAN_SetMIDvAMask(Can * pCan,uint8_t bMb,uint32_t dwIDvA);\r
+void CAN_SetMIDvBMask(Can * pCan,uint8_t bMb,uint32_t dwIDvA);\r
+\r
+void CAN_ConfigureMessageID(Can * pCan,uint8_t bMb,uint32_t dwMID);\r
+uint32_t CAN_GetMessageID(Can * pCan,uint8_t bMb);\r
+void CAN_ConfigureIdVer(Can * pCan,uint8_t bMb,uint8_t bIdVer);\r
+void CAN_SetMIDvA(Can * pCan,uint8_t bMb,uint32_t dwIDvA);\r
+void CAN_SetMIDvB(Can * pCan,uint8_t bMb,uint32_t dwIDvA);\r
+\r
+uint32_t CAN_GetFamilyID(Can * pCan,uint8_t bMb);\r
+\r
+uint32_t CAN_GetMessageStatus(Can * pCan,uint8_t bMb);\r
+\r
+void CAN_SetMessageDataL(Can * pCan,uint8_t bMb,uint32_t dwL);\r
+uint32_t CAN_GetMessageDataL(Can * pCan,uint8_t bMb);\r
+void CAN_SetMessageDataH(Can * pCan,uint8_t bMb,uint32_t dwH);\r
+uint32_t CAN_GetMessageDataH(Can * pCan,uint8_t bMb);\r
+void CAN_SetMessage(Can * pCan,uint8_t bMb,uint32_t * pDwData);\r
+void CAN_GetMessage(Can * pCan,uint8_t bMb,uint32_t * pDwData);\r
+void CAN_SetMessageData64(Can * pCan,uint8_t bMb,uint64_t u64);\r
+uint64_t CAN_GetMessageData64(Can * pCan,uint8_t bMb);\r
+\r
+void CAN_MessageControl(Can * pCan,uint8_t bMb,uint32_t dwCtrl);\r
+void CAN_MessageRemote(Can * pCan,uint8_t bMb);\r
+void CAN_MessageAbort(Can * pCan,uint8_t bMb);\r
+void CAN_MessageTx(Can * pCan,uint8_t bMb,uint8_t bLen);\r
+void CAN_MessageRx(Can * pCan,uint8_t bMb);\r
+\r
+/**@}*/\r
+#endif /* #ifndef _CAN_H_ */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+\r
+<package schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">\r
+ <name>CMSIS</name>\r
+ <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>\r
+ <vendor>ARM</vendor>\r
+ <!-- <license>CMSIS\CMSIS_END_USER_LICENCE_AGREEMENT.rtf</license> -->\r
+ <url>http://www.keil.com/pack/</url>\r
+\r
+ <taxonomy>\r
+ <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>\r
+ <description Cclass="CMSIS" doc="CMSIS\Documentation\General\html\index.html">Cortex Microcontroller Software Interface Components</description>\r
+ <description Cclass="Device" doc="CMSIS\Documentation\Core\html\index.html">Startup, System Setup</description>\r
+ <description Cclass="CMSIS Driver" doc="CMSIS\Documentation\Driver\html\index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>\r
+ <description Cclass="File System">File Drive Support and File System</description>\r
+ <description Cclass="Graphics">Graphical User Interface</description>\r
+ <description Cclass="Network">Network Stack using Internet Protocols</description>\r
+ <description Cclass="USB">Universal Serial Bus Stack</description>\r
+ </taxonomy>\r
+\r
+ <releases>\r
+ <release version="4.1.0" date="2014-06-12">\r
+ - CMSIS-Driver 2.02 (incompatible update)\r
+ - CMSIS-Pack 1.3 (see revision history for details)\r
+ - CMSIS-DSP 1.4.2 (unchanged)\r
+ - CMSIS-Core 3.30 (unchanged)\r
+ - CMSIS-RTOS RTX 4.74 (unchanged)\r
+ - CMSIS-RTOS API 1.02 (unchanged)\r
+ - CMSIS-SVD 1.10 (unchanged)\r
+ PACK:\r
+ - removed G++ specific files from PACK\r
+ - added Component Startup variant "C Startup"\r
+ - added Pack Checking Utility \r
+ - updated conditions to reflect tool-chain dependency\r
+ - added Taxonomy for Graphics\r
+ - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"\r
+ </release>\r
+ <release version="4.0.0">\r
+ - CMSIS-Driver 2.00 Preliminary (incompatible update)\r
+ - CMSIS-Pack 1.1 Preliminary\r
+ - CMSIS-DSP 1.4.2 (see revision history for details)\r
+ - CMSIS-Core 3.30 (see revision history for details)\r
+ - CMSIS-RTOS RTX 4.74 (see revision history for details)\r
+ - CMSIS-RTOS API 1.02 (unchanged)\r
+ - CMSIS-SVD 1.10 (unchanged)\r
+ </release>\r
+ <release version="3.20.4">\r
+ - CMSIS-RTOS 4.74 (see revision history for details)\r
+ - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.\r
+ </release>\r
+ <release version="3.20.3">\r
+ - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)\r
+ - CMSIS-RTOS 4.73 (see revision history for details)\r
+ </release>\r
+ <release version="3.20.2">\r
+ - CMSIS-Pack documentation has been added\r
+ - CMSIS-Drivers header and documentation have been added to PACK\r
+ - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged\r
+ </release>\r
+ <release version="3.20.1">\r
+ - CMSIS-RTOS Keil RTX V4.72 has been added to PACK\r
+ - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged\r
+ </release>\r
+ <release version="3.20.0">\r
+ The software portions that are deployed in the application program are now under a BSD license which allows usage\r
+ of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases\r
+ The individual components have been update as listed below:\r
+ - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.\r
+ - CMSIS-DSP library is optimized for more performance and contains several bug fixes.\r
+ - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.\r
+ - CMSIS-SVD is unchanged.\r
+ </release>\r
+ </releases>\r
+\r
+ <devices>\r
+ <!-- ****************************** Cortex-M0 ****************************** -->\r
+ <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">\r
+ <device Dname="ARMCM0">\r
+ <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMCM0\Include\ARMCM0.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMCM0.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+ <book name="Device\ARM\Documents\cortex_m0_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>\r
+\r
+ <description>\r
+ The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ • upward compatibility with the rest of the Cortex-M processor family.\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+ <!-- ****************************** Cortex-M0P ****************************** -->\r
+ <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">\r
+ <device Dname="ARMCM0P">\r
+ <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMCM0P.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+ <book name="Device\ARM\Documents\cortex_m0p_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>\r
+ <description>\r
+ The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ • upward compatibility with the rest of the Cortex-M processor family.\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+ <!-- ****************************** Cortex-M3 ****************************** -->\r
+ <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">\r
+ <device Dname="ARMCM3">\r
+ <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMCM3\Include\ARMCM3.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMCM3.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+ <book name="Device\ARM\Documents\cortex_m3_dgug.pdf" title="Cortex-M3 Device Generic Users Guide"/>\r
+ <description>\r
+ The Cortex-M3 processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ • upward compatibility with the rest of the Cortex-M processor family.\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+ <!-- ****************************** Cortex-M4 ****************************** -->\r
+ <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">\r
+ <device Dname="ARMCM4">\r
+ <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="1" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMCM4\Include\ARMCM4.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMCM4.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+ <book name="Device\ARM\Documents\cortex_m4_dgug.pdf" title="Cortex-M4 Device Generic Users Guide"/>\r
+ <description>\r
+ The Cortex-M4 processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ • upward compatibility with the rest of the Cortex-M processor family.\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+\r
+ <!-- ****************************** ARMSC000 ****************************** -->\r
+ <family Dfamily="ARM SC000" Dvendor="ARM:82">\r
+ <device Dname="ARMSC000">\r
+ <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMSC000\Include\ARMSC000.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMSC000.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+ <description>\r
+ The ARM SC000 processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of secure embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+\r
+ <!-- ****************************** ARMSC300 ****************************** -->\r
+ <family Dfamily="ARM SC300" Dvendor="ARM:82">\r
+ <device Dname="ARMSC300">\r
+ <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>\r
+ <compile header="Device\ARM\ARMSC300\Include\ARMSC300.h"/>\r
+ <debug svd="Device\ARM\SVD\ARMSC300.svd"/>\r
+ <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/>\r
+\r
+ <description>\r
+ The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed\r
+ for a broad range of secure embedded applications. It offers significant benefits to developers,\r
+ including:\r
+ • simple, easy-to-use programmers model\r
+ • highly efficient ultra-low power operation\r
+ • excellent code density\r
+ • deterministic, high-performance interrupt handling\r
+ </description>\r
+ </device>\r
+ </family>\r
+\r
+ </devices>\r
+\r
+\r
+ <apis>\r
+ <!-- CMSIS-RTOS API -->\r
+ <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0" exclusive="1">\r
+ <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\RTOS\html\index.html"/>\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.01" exclusive="0">\r
+ <description>USART Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__usart__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_USART.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.01" exclusive="0">\r
+ <description>SPI Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__spi__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_SPI.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.02" exclusive="0">\r
+ <description>I2C Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__i2c__interface__gr.html"/>\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_I2C.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.00" exclusive="0">\r
+ <description>Flash Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__flash__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_Flash.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.02" exclusive="0">\r
+ <description>MCI Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__mci__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_MCI.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.01" exclusive="0">\r
+ <description>NAND Flash Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__nand__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_NAND.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.01" exclusive="0">\r
+ <description>Ethernet MAC and PHY Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.01" exclusive="0">\r
+ <description>Ethernet MAC Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__mac__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.00" exclusive="0">\r
+ <description>Ethernet PHY Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__phy__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.01" exclusive="0">\r
+ <description>USB Device Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbd__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_USBD.h" />\r
+ </files>\r
+ </api>\r
+ <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.00" exclusive="0">\r
+ <description>USB Host Driver API for Cortex-M</description>\r
+ <files>\r
+ <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbh__interface__gr.html" />\r
+ <file category="header" name="CMSIS\Driver\Include\Driver_USBH.h" />\r
+ </files>\r
+ </api>\r
+ </apis>\r
+\r
+ <!-- conditions are dependency rules that can apply to a component or an individual file -->\r
+ <conditions>\r
+ <condition id="ARMCC">\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="GCC">\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="IAR">\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="Cortex-M Device">\r
+ <description>Cortex-M processor based device: one of CM0, CM0+, CM3, CM4, SC000, SC3000</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="Cortex-M4"/>\r
+ <accept Dcore="SC000"/>\r
+ <accept Dcore="SC300"/>\r
+ </condition>\r
+\r
+ <condition id="Cortex-M CMSIS Device">\r
+ <description>ARM Cortex-M device</description>\r
+ <require condition="Cortex-M Device"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="CMSIS Core">\r
+ <description>CMSIS CORE processor and device specific Startup files</description>\r
+ <require condition="Cortex-M Device"/>\r
+ <require Cclass="Device" Cgroup="Startup"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM0 CMSIS">\r
+ <!-- conditions selecting Devices -->\r
+ <description>Generic ARM Cortex-M0 device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMCM0"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM0 CMSIS GCC">\r
+ <!-- conditions selecting Devices -->\r
+ <description>Generic ARM Cortex-M0 device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMCM0 CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM0+ CMSIS">\r
+ <description>Generic ARM Cortex-M0+ device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMCM0P"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM0+ CMSIS GCC">\r
+ <description>Generic ARM Cortex-M0+ device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMCM0+ CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM3 CMSIS">\r
+ <description>Generic ARM Cortex-M3 device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMCM3"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM3 CMSIS GCC">\r
+ <description>Generic ARM Cortex-M3 device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMCM3 CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM4 CMSIS">\r
+ <description>Generic ARM Cortex-M4 device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMCM4"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMCM4 CMSIS GCC">\r
+ <description>Generic ARM Cortex-M4 device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMCM4 CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="ARMSC000 CMSIS">\r
+ <description>Generic ARM SC000 device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMSC000"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMSC000 CMSIS GCC">\r
+ <description>Generic ARM SC000 device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMSC000 CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="ARMSC300 CMSIS">\r
+ <description>Generic ARM SC300 device and CMSIS Core</description>\r
+ <require Dvendor="ARM:82" Dname="ARMSC300"/>\r
+ <require Cclass="CMSIS" Cgroup="CORE"/>\r
+ </condition>\r
+\r
+ <condition id="ARMSC300 CMSIS GCC">\r
+ <description>Generic ARM SC300 device and CMSIS Core requiring GCC</description>\r
+ <require condition="ARMSC300 CMSIS"/>\r
+ <require condition="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CMSIS DSP">\r
+ <description>CMSIS DSP Library is for ARM Cortex-M Devices only and is prebuild for one of the compilers ARMCC, GCC or IAR</description>\r
+ <require condition="Cortex-M CMSIS Device"/>\r
+ <accept Tcompiler="GCC"/>\r
+ <accept Tcompiler="ARMCC"/>\r
+ <accept Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM0_LE_ARMCC">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the ARM Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM0_BE_ARMCC">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the ARM Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_LE_ARMCC">\r
+ <description>Cortex-M3 or SC300 processor based device in little endian mode for the ARM Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_BE_ARMCC">\r
+ <description>Cortex-M3 or SC300 processor based device in big endian mode for the ARM Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_LE_ARMCC">\r
+ <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>\r
+ <deny Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_BE_ARMCC">\r
+ <description>Cortex-M4 processor based device in big endian mode for the ARM Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_LE_ARMCC">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>\r
+ <deny Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+ \r
+ <!-- XMC 4000 Series devices from Infineon require a special library -->\r
+ <condition id="CM4_LE_ARMCC_IFX">\r
+ <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler and Infineon devices</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+ <condition id="CM4F_LE_ARMCC_IFX">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler and Infineon devices</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_BE_ARMCC">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="ARMCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM0_LE_GCC">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM0_BE_GCC">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_LE_GCC">\r
+ <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_BE_GCC">\r
+ <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_LE_GCC">\r
+ <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>\r
+ <deny Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_BE_GCC">\r
+ <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_LE_GCC">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>\r
+ <deny Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <!-- XMC 4000 Series devices from Infineon require a special library -->\r
+ <condition id="CM4_LE_GCC_IFX">\r
+ <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler and Infineon devices</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+ <condition id="CM4F_LE_GCC_IFX">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler and Infineon devices</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_BE_GCC">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="GCC"/>\r
+ </condition>\r
+\r
+ <!-- IAR compiler -->\r
+ <condition id="CM0_LE_IAR">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM0_BE_IAR">\r
+ <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>\r
+ <accept Dcore="Cortex-M0"/>\r
+ <accept Dcore="Cortex-M0+"/>\r
+ <accept Dcore="SC000"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_LE_IAR">\r
+ <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Little-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM3_BE_IAR">\r
+ <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>\r
+ <accept Dcore="Cortex-M3"/>\r
+ <accept Dcore="SC300"/>\r
+ <require Dendian="Big-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_LE_IAR">\r
+ <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM4_BE_IAR">\r
+ <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_LE_IAR">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+\r
+ <condition id="CM4F_BE_IAR">\r
+ <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>\r
+ <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>\r
+ <require Tcompiler="IAR"/>\r
+ </condition>\r
+ </conditions>\r
+ \r
+ <components>\r
+ <!-- CMSIS-Core component -->\r
+ <component Cclass="CMSIS" Cgroup="CORE" Cversion="3.30.0" condition="CMSIS Core">\r
+ <description>CMSIS-CORE for Cortex-M, SC000, and SC300</description>\r
+ <files>\r
+ <!-- templates -->\r
+ <file category="source" attr="template" name="CMSIS\UserCodeTemplates\ARM\ITM_Retarget.c" select="CMSIS-CORE 'ITM Printf Debug'" condition="ARMCC"/>\r
+ <!-- CPU independent -->\r
+ <file category="doc" name="CMSIS\Documentation\Core\html\index.html"/>\r
+ <file category="include" name="CMSIS\Include\"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- CMSIS-Startup components -->\r
+ <!-- Cortex-M0 -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS">\r
+ <description>System and Startup for Generic ARM Cortex-M0 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM0\Include\ARMCM0.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM0\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">\r
+ <description>System and Startup for Generic ARM Cortex-M0 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM0\Include\ARMCM0.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM0\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- Cortex-M0+ -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS">\r
+ <description>System and Startup for Generic ARM Cortex-M0+ device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">\r
+ <description>System and Startup for Generic ARM Cortex-M0+ device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- Cortex-M3 -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS">\r
+ <description>System and Startup for Generic ARM Cortex-M3 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM3\Include\ARMCM3.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">\r
+ <description>System and Startup for Generic ARM Cortex-M3 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM3\Include\ARMCM3.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- Cortex-M4 -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS">\r
+ <description>System and Startup for Generic ARM Cortex-M4 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM4\Include\ARMCM4.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">\r
+ <description>System and Startup for Generic ARM Cortex-M4 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMCM4\Include\ARMCM4.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- Cortex-SC000 -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS">\r
+ <description>System and Startup for Generic ARM SC000 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMSC000\Include\ARMSC000.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMSC000\Source\ARM\startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMSC000\Source\GCC\startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMSC000\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMSC000\Source\system_ARMSC000.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">\r
+ <description>System and Startup for Generic ARM SC000 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMSC000\Include\ARMSC000.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMSC000\Source\GCC\startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMSC000\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMSC000\Source\system_ARMSC000.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- Cortex-SC300 -->\r
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS">\r
+ <description>System and Startup for Generic ARM SC300 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMSC300\Include\ARMSC300.h"/>\r
+ <!-- startup file -->\r
+ <!-- for ARMCC -->\r
+ <file category="source" name="Device\ARM\ARMSC300\Source\ARM\startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMSC300\Source\GCC\startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMSC300\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMSC300\Source\system_ARMSC300.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+ <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">\r
+ <description>System and Startup for Generic ARM SC300 device</description>\r
+ <files>\r
+ <!-- device header file -->\r
+ <file category="header" name="Device\ARM\ARMSC300\Include\ARMSC300.h"/>\r
+ <!-- startup file -->\r
+ <!-- for GCC -->\r
+ <file category="source" name="Device\ARM\ARMSC300\Source\GCC\startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>\r
+ <file category="doc" name="Device\ARM\ARMSC300\Source\GCC\gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>\r
+ <!-- system file (system header not specified, as the path is already set by device header) -->\r
+ <file category="source" name="Device\ARM\ARMSC300\Source\system_ARMSC300.c" version="1.0.0" attr="config"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- CMSIS-DSP component -->\r
+ <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.4.2" condition="CMSIS DSP">\r
+ <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>\r
+ <files>\r
+ <!-- CPU independent -->\r
+ <file category="doc" name="CMSIS\Documentation\DSP\html\index.html"/>\r
+ <!-- <file category="header" name="CMSIS\Include\arm_common_tables.h"/> -->\r
+ <file category="header" name="CMSIS\Include\arm_math.h"/>\r
+ <!-- CPU and Compiler dependent -->\r
+ <!-- ARMCC -->\r
+ <file category="library" condition="CM0_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM0l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM0_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM0b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM3_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM3l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM3_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM3b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM4_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4l_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM4_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4b_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM4F_LE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4lf_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <file category="library" condition="CM4F_BE_ARMCC" name="CMSIS\Lib\ARM\arm_cortexM4bf_math.lib" src="CMSIS\DSP_Lib\Source\ARM"/>\r
+ <!-- GCC -->\r
+ <file category="library" condition="CM0_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM0l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>\r
+ <file category="library" condition="CM3_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM3l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>\r
+ <file category="library" condition="CM4_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM4l_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>\r
+ <file category="library" condition="CM4F_LE_GCC" name="CMSIS\Lib\GCC\libarm_cortexM4lf_math.a" src="CMSIS\DSP_Lib\Source\GCC"/>\r
+ </files>\r
+ </component>\r
+\r
+ <!-- CMSIS-RTOS Keil RTX component -->\r
+ <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.74.0" condition="CMSIS Core">\r
+ <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>\r
+ <RTE_Components_h>\r
+ <!-- the following content goes into file 'RTE_Components.h' -->\r
+ #define RTE_CMSIS_RTOS /* CMSIS-RTOS */\r
+ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */\r
+ </RTE_Components_h>\r
+ <files>\r
+ <!-- CPU independent -->\r
+ <file category="doc" name="CMSIS_RTX\Doc\index.html"/>\r
+ <file category="header" name="CMSIS_RTX\INC\cmsis_os.h"/>\r
+ <file category="source" attr="config" name="CMSIS_RTX\Templates\RTX_Conf_CM.c" version="4.70"/>\r
+ \r
+ <!-- RTX templates -->\r
+ <file category="header" attr="template" name="CMSIS_RTX\UserCodeTemplates\osObjects.h" select="CMSIS-RTOS 'main' function"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\main.c" select="CMSIS-RTOS 'main' function"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MailQueue.c" select="CMSIS-RTOS Mail Queue"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MemPool.c" select="CMSIS-RTOS Memory Pool"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MsgQueue.c" select="CMSIS-RTOS Message Queue"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Mutex.c" select="CMSIS-RTOS Mutex"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Semaphore.c" select="CMSIS-RTOS Semaphore"/>\r
+ <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Thread.c" select="CMSIS-RTOS Thread"/>\r
+ <!-- tool-chain specific template file -->\r
+ <file category="source" attr="template" condition="ARMCC" name="CMSIS_RTX\SRC\ARM\SVC_Table.s" select="CMSIS-RTOS User SVC"/>\r
+ <file category="source" attr="template" condition="GCC" name="CMSIS_RTX\SRC\GCC\SVC_Table.s" select="CMSIS-RTOS User SVC"/>\r
+ <file category="source" attr="template" condition="IAR" name="CMSIS_RTX\SRC\IAR\SVC_Table.s" select="CMSIS-RTOS User SVC"/>\r
+\r
+ <!-- CPU and Compiler dependent -->\r
+ <!-- ARMCC -->\r
+ <file category="library" condition="CM0_LE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM0.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM0_BE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM0_B.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM3_LE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM3.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM3_BE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM3_B.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4_LE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM3.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4_BE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM3_B.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4_LE_ARMCC_IFX" name="CMSIS_RTX\LIB\ARM\RTX_CM3_IFX.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4F_LE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM4.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4F_BE_ARMCC" name="CMSIS_RTX\LIB\ARM\RTX_CM4_B.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <file category="library" condition="CM4F_LE_ARMCC_IFX" name="CMSIS_RTX\LIB\ARM\RTX_CM4_IFX.lib" src="CMSIS_RTX\SRC\ARM"/>\r
+ <!-- GCC -->\r
+ <file category="library" condition="CM0_LE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM0.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM0_BE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM0_B.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM3_LE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM3.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM3_BE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM3_B.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4_LE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM3.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4_BE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM3_B.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4_LE_GCC_IFX" name="CMSIS_RTX\LIB\GCC\libRTX_CM3_IFX.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4F_LE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM4.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4F_BE_GCC" name="CMSIS_RTX\LIB\GCC\libRTX_CM4_B.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <file category="library" condition="CM4F_LE_GCC_IFX" name="CMSIS_RTX\LIB\GCC\libRTX_CM4_IFX.a" src="CMSIS_RTX\SRC\GCC"/>\r
+ <!-- IAR -->\r
+ <file category="library" condition="CM0_LE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM0.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM0_BE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM0_B.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM3_LE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM3.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM3_BE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM3_B.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM4_LE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM3.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM4_BE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM3_B.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM4F_LE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM4.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ <file category="library" condition="CM4F_BE_IAR" name="CMSIS_RTX\LIB\IAR\RTX_CM4_B.a" src="CMSIS_RTX\SRC\IAR"/>\r
+ </files>\r
+ </component>\r
+ </components>\r
+ \r
+ <boards>\r
+ <board name="uVision Simulator" vendor="Keil">\r
+ <description>uVision Simulator</description>\r
+ <mountedDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>\r
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>\r
+ <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>\r
+ </board>\r
+ </boards>\r
+\r
+ <examples>\r
+ <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_class_marks_example\ARM">\r
+ <description>DSP_Lib Class Marks example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_class_marks_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_convolution_example\ARM">\r
+ <description>DSP_Lib Convolution example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_convolution_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_dotproduct_example\ARM">\r
+ <description>DSP_Lib Dotproduct example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_dotproduct_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_fft_bin_example\ARM">\r
+ <description>DSP_Lib FFT Bin example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_fft_bin_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_fir_example\ARM">\r
+ <description>DSP_Lib FIR example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_fir_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_graphic_equalizer_example\ARM">\r
+ <description>DSP_Lib Graphic Equalizer example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_linear_interp_example\ARM">\r
+ <description>DSP_Lib Linear Interpolation example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_linear_interp_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_matrix_example\ARM">\r
+ <description>DSP_Lib Matrix example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_matrix_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_signal_converge_example\ARM">\r
+ <description>DSP_Lib Signal Convergence example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_signal_converge_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+ <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_sin_cos_example\ARM">\r
+ <description>DSP_Lib Sinus/Cosinus example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_sin_cos_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+\r
+\r
+ <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_variance_example\ARM">\r
+ <description>DSP_Lib Variance example</description>\r
+ <board name="uVision Simulator" vendor="Keil"/>\r
+ <project>\r
+ <environment name="uv" load="arm_variance_example.uvprojx"/>\r
+ </project>\r
+ <attributes>\r
+ <component Cclass="CMSIS" Cgroup="CORE"/>\r
+ <component Cclass="CMSIS" Cgroup="DSP"/>\r
+ <component Cclass="Device" Cgroup="Startup"/>\r
+ <category>Getting Started</category>\r
+ </attributes>\r
+ </example>\r
+ </examples>\r
+\r
+</package>\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 12. March 2014\r
+* $Revision: V1.4.3\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_common_tables.h\r
+*\r
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\r
+*\r
+* Target Processor: Cortex-M4/Cortex-M3\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+* -------------------------------------------------------------------- */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+extern const q31_t realCoefAQ31[1024];\r
+extern const q31_t realCoefBQ31[1024];\r
+extern const float32_t twiddleCoef_16[32];\r
+extern const float32_t twiddleCoef_32[64];\r
+extern const float32_t twiddleCoef_64[128];\r
+extern const float32_t twiddleCoef_128[256];\r
+extern const float32_t twiddleCoef_256[512];\r
+extern const float32_t twiddleCoef_512[1024];\r
+extern const float32_t twiddleCoef_1024[2048];\r
+extern const float32_t twiddleCoef_2048[4096];\r
+extern const float32_t twiddleCoef_4096[8192];\r
+#define twiddleCoef twiddleCoef_4096\r
+extern const q31_t twiddleCoefQ31[6144];\r
+extern const q15_t twiddleCoefQ15[6144];\r
+extern const float32_t twiddleCoef_rfft_32[32];\r
+extern const float32_t twiddleCoef_rfft_64[64];\r
+extern const float32_t twiddleCoef_rfft_128[128];\r
+extern const float32_t twiddleCoef_rfft_256[256];\r
+extern const float32_t twiddleCoef_rfft_512[512];\r
+extern const float32_t twiddleCoef_rfft_1024[1024];\r
+extern const float32_t twiddleCoef_rfft_2048[2048];\r
+extern const float32_t twiddleCoef_rfft_4096[4096];\r
+\r
+\r
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )\r
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )\r
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )\r
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\r
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\r
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\r
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\r
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\r
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\r
+\r
+/* Tables for Fast Math Sine and Cosine */\r
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-20134 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 12. March 2014\r
+* $Revision: V1.4.3\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_const_structs.h\r
+*\r
+* Description: This file has constant structs that are initialized for\r
+* user convenience. For example, some can be given as\r
+* arguments to the arm_cfft_f32() function.\r
+*\r
+* Target Processor: Cortex-M4/Cortex-M3\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+* -------------------------------------------------------------------- */\r
+\r
+#ifndef _ARM_CONST_STRUCTS_H\r
+#define _ARM_CONST_STRUCTS_H\r
+\r
+#include "arm_math.h"\r
+#include "arm_common_tables.h"\r
+\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 12. March 2014\r
+* $Revision: V1.4.3\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_math.h\r
+*\r
+* Description: Public header file for CMSIS DSP Library\r
+*\r
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * Introduction\r
+ * ------------\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of functions each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * Using the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
+ *\r
+ * Examples\r
+ * --------\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * Toolchain Support\r
+ * ------------\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.60.\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * Building the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM_math.uvproj\r
+ *\r
+ *\r
+ * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * Pre-processor Macros\r
+ * ------------\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * - UNALIGNED_SUPPORT_DISABLE:\r
+ *\r
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
+ *\r
+ * - ARM_MATH_BIG_ENDIAN:\r
+ *\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * - ARM_MATH_MATRIX_CHECK:\r
+ *\r
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
+ *\r
+ * - ARM_MATH_ROUNDING:\r
+ *\r
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
+ *\r
+ * - ARM_MATH_CMx:\r
+ *\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.\r
+ *\r
+ * - __FPU_PRESENT:\r
+ *\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
+ *\r
+ * <hr>\r
+ * CMSIS-DSP in ARM::CMSIS Pack\r
+ * -----------------------------\r
+ * \r
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
+ * |File/Folder |Content |\r
+ * |------------------------------|------------------------------------------------------------------------|\r
+ * |\b CMSIS\\Documentation\\DSP | This documentation |\r
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
+ * \r
+ * <hr>\r
+ * Revision History of CMSIS-DSP\r
+ * ------------\r
+ * Please refer to \ref ChangeLog_pg.\r
+ *\r
+ * Copyright Notice\r
+ * ------------\r
+ *\r
+ * Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined (ARM_MATH_CM4)\r
+#include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+#include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+#include "core_cm0.h"\r
+#define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_CM0PLUS)\r
+#include "core_cm0plus.h"\r
+#define ARM_MATH_CM0_FAMILY\r
+#else\r
+#include "ARMCM4.h"\r
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+#include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#ifndef PI\r
+#define PI 3.14159265358979f\r
+#endif\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define FAST_MATH_TABLE_SIZE 512\r
+#define FAST_MATH_Q31_SHIFT (32 - 10)\r
+#define FAST_MATH_Q15_SHIFT (16 - 10)\r
+#define CONTROLLER_Q31_SHIFT (32 - 9)\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x400000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+ /**\r
+ * @brief Macro for Unaligned Support\r
+ */\r
+#ifndef UNALIGNED_SUPPORT_DISABLE\r
+ #define ALIGN4\r
+#else\r
+ #if defined (__GNUC__)\r
+ #define ALIGN4 __attribute__((aligned(4)))\r
+ #else\r
+ #define ALIGN4 __align(4)\r
+ #endif\r
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#if defined __CC_ARM\r
+#define __SIMD32_TYPE int32_t __packed\r
+#define CMSIS_UNUSED __attribute__((unused))\r
+#elif defined __ICCARM__\r
+#define CMSIS_UNUSED\r
+#define __SIMD32_TYPE int32_t __packed\r
+#elif defined __GNUC__\r
+#define __SIMD32_TYPE int32_t\r
+#define CMSIS_UNUSED __attribute__((unused))\r
+#elif defined __CSMC__ /* Cosmic */\r
+#define CMSIS_UNUSED\r
+#define __SIMD32_TYPE int32_t\r
+#else\r
+#error Unknown compiler\r
+#endif\r
+\r
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
+\r
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
+\r
+#define __SIMD64(addr) (*(int64_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ static __INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ static __INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ static __INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
+\r
+ static __INLINE uint32_t __CLZ(\r
+ q31_t data);\r
+\r
+\r
+ static __INLINE uint32_t __CLZ(\r
+ q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return (count);\r
+\r
+ }\r
+\r
+#endif\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ static __INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
+ */\r
+ static __INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0_FAMILY)\r
+\r
+ static __INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0_FAMILY */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (q7_t) x;\r
+ s = (q7_t) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum =\r
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (q7_t) x;\r
+ s = (q7_t) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &\r
+ 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum =\r
+ ((sum +\r
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum =\r
+ ((sum +\r
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -\r
+ ((q15_t) (x >> 16) * (q15_t) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +\r
+ ((q15_t) (x >> 16) * (q15_t) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
+ ((q15_t) x * (q15_t) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
+ ((q15_t) x * (q15_t) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SXTB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SXTB16(\r
+ q31_t x)\r
+ {\r
+\r
+ return ((((x << 24) >> 24) & 0x0000FFFF) |\r
+ (((x << 8) >> 8) & 0xFFFF0000));\r
+ }\r
+\r
+\r
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pScratch);\r
+\r
+ /**\r
+ * @brief Q31, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t * pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t * pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t * pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+#ifdef ARM_MATH_CM0_FAMILY\r
+ q15_t A1;\r
+ q15_t A2;\r
+#else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+#endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q15;\r
+\r
+ arm_status arm_cfft_radix2_init_q15(\r
+ arm_cfft_radix2_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ void arm_cfft_radix2_q15(\r
+ const arm_cfft_radix2_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q31;\r
+\r
+ arm_status arm_cfft_radix2_init_q31(\r
+ arm_cfft_radix2_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ void arm_cfft_radix2_q31(\r
+ const arm_cfft_radix2_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix2_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_f32(\r
+ arm_cfft_radix2_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_f32(\r
+ const arm_cfft_radix2_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_f32;\r
+\r
+ void arm_cfft_f32(\r
+ const arm_cfft_instance_f32 * S,\r
+ float32_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+typedef struct\r
+ {\r
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
+ uint16_t fftLenRFFT; /**< length of the real sequence */\r
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
+ } arm_rfft_fast_instance_f32 ;\r
+\r
+arm_status arm_rfft_fast_init_f32 (\r
+ arm_rfft_fast_instance_f32 * S,\r
+ uint16_t fftLen);\r
+\r
+void arm_rfft_fast_f32(\r
+ arm_rfft_fast_instance_f32 * S,\r
+ float32_t * p, float32_t * pOut,\r
+ uint8_t ifftFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+\r
+ void arm_conv_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pkCoeffs,\r
+ float32_t * pvCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pkCoeffs,\r
+ q31_t * pvCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pkCoeffs,\r
+ q15_t * pvCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @return none.\r
+ */\r
+ void arm_correlate_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cos output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t * pSinVal,\r
+ float32_t * pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cosine output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t * pSinVal,\r
+ q31_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+\r
+ static __INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ static __INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+#ifndef ARM_MATH_CM0_FAMILY\r
+ __SIMD32_TYPE *vstate;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ vstate = __SIMD32_CONST(S->state);\r
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);\r
+\r
+#else\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0) * in;\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0];\r
+ acc += (q31_t) S->A2 * S->state[1];\r
+\r
+#endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta =\r
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ static __INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ static __INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (int32_t) ((x - S->x1) / xSpacing);\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if((uint32_t)i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues - 1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i + 1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q31_t arm_linear_interp_q31(\r
+ q31_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q15_t arm_linear_interp_q15(\r
+ q15_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+ if(index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ static __INLINE q7_t arm_linear_interp_q7(\r
+ q7_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ uint32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ if (x < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ index = (x >> 20) & 0xfff;\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate, and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ static __INLINE arm_status arm_sqrt_f32(\r
+ float32_t in,\r
+ float32_t * pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+#else\r
+ *pOut = sqrtf(in);\r
+#endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in,\r
+ q31_t * pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in,\r
+ q15_t * pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none.\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0\r
+ || yIndex > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex - 1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+#if defined ( __CC_ARM ) //Keil\r
+//SMMLAR\r
+ #define multAcc_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+//SMMLSR\r
+ #define multSub_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+//SMMULR\r
+ #define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("push") \\r
+ _Pragma ("O1")\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define LOW_OPTIMIZATION_EXIT \\r
+ _Pragma ("pop")\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__ICCARM__) //IAR\r
+ //SMMLA\r
+ #define multAcc_32x32_keep32_R(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+ //SMMLS\r
+ #define multSub_32x32_keep32_R(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+//SMMUL\r
+ #define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__GNUC__)\r
+ //SMMLA\r
+ #define multAcc_32x32_keep32_R(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+ //SMMLS\r
+ #define multSub_32x32_keep32_R(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+//SMMUL\r
+ #define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))\r
+\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__CSMC__) // Cosmic\r
+//SMMLA\r
+ #define multAcc_32x32_keep32_R(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+ //SMMLS\r
+ #define multSub_32x32_keep32_R(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+//SMMUL\r
+ #define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+#define LOW_OPTIMIZATION_ENTER\r
+#define LOW_OPTIMIZATION_EXIT\r
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0P definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if (__VTOR_PRESENT == 1)\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if (__VTOR_PRESENT == 1)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0+ Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4_simd.h\r
+ * @brief CMSIS Cortex-M4 SIMD Header File\r
+ * @version V3.30\r
+ * @date 17. February 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_SIMD_H\r
+#define __CORE_CM4_SIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32) ) >> 32))\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+/* not yet supported */\r
+\r
+\r
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/\r
+/* Cosmic specific functions */\r
+#include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_SIMD_H */\r
--- /dev/null
+\r
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 07. April 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x07) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler (use -pc99 on compile line ) */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x07)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x07)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93];\r
+ __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15];\r
+ __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
+ uint32_t RESERVED5[1];\r
+ __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1];\r
+ __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6];\r
+ __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1];\r
+ __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* Cache Level ID register */\r
+#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* Cache Type register */\r
+#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* Cache Size ID Register */\r
+#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* Cache Size Selection Register */\r
+#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register */\r
+#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register*/\r
+#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */\r
+\r
+\r
+/* Data Tightly-Coupled Memory Control Registers */\r
+#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register */\r
+#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register */\r
+#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBSCR control register */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )\r
+\r
+\r
+/** \brief Enable I-Cache\r
+\r
+ The function turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0; // invalidate I-Cache\r
+ SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Disable I-Cache\r
+\r
+ The function turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache\r
+ SCB->ICIALLU = 0; // invalidate I-Cache\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Invalidate I-Cache\r
+\r
+ The function invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Enable D-Cache\r
+\r
+ The function turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+ __DSB();\r
+\r
+ SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Disable D-Cache\r
+\r
+ The function turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache\r
+\r
+ do { // clean & invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Invalidate D-Cache\r
+\r
+ The function invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Clean D-Cache\r
+\r
+ The function cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // clean D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCSW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Clean & Invalidate D-Cache\r
+\r
+ The function cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // clean & invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.21\r
+ * @date 29. November 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) // CM7Pelican\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) // CM7Pelican\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.01\r
+ * @date 06. March 2013\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2014 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+\r
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );\r
+ return(op1);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V3.21\r
+ * @date 29. November 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/*------ CM SIMD Intrinsics ------------------------------------------------------*/\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32) ) >> 32))\r
+\r
+/*-- End CM SIMD Intrinsics ------------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+/*------ CM SIMD Intrinsics ------------------------------------------------------*/\r
+#include <cmsis_iar.h>\r
+\r
+/*-- End CM SIMD Intrinsics ------------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+/*------ CM SIMD Intrinsics ------------------------------------------------------*/\r
+#include <cmsis_ccs.h>\r
+\r
+/*-- End CM SIMD Intrinsics ------------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/*------ CM SIMD Intrinsics ------------------------------------------------------*/\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+/*-- End CM SIMD Intrinsics ------------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+\r
+/*------ CM SIMD Intrinsics ------------------------------------------------------*/\r
+/* not yet supported */\r
+\r
+/*-- End CM SIMD Intrinsics ------------------------------------------------------*/\r
+\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CORE_CM7Pelican_SIMD_H */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (000) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154];\r
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/* SCB Security Features Register Definitions */\r
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */\r
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */\r
+\r
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */\r
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of SC000 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V3.30\r
+ * @date 06. May 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for DACC\r
+ * -# Initialize the DACC with DACC_Initialize().\r
+ * -# Select the active channel using DACC_EnableChannel()\r
+ * -# Start the conversion with DACC_StartConversion()\r
+ * -# Wait the end of the conversion by polling status with DACC_GetStatus()\r
+ * -# Finally, get the converted data using DACC_GetConvertedData()\r
+ *\r
+*/\r
+#ifndef _DAC_DMA_\r
+#define _DAC_DMA_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** DAC transfer complete callback. */\r
+typedef void (*DacCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief Dac Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the DAC_SendCommand function to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct\r
+{\r
+ /** Pointer to the Tx data. */\r
+ uint8_t *pTxBuff;\r
+ /** Tx size in bytes. */\r
+ uint16_t TxSize;\r
+ /** Tx loop back. */\r
+ uint16_t loopback;\r
+ /** DACC channel*/\r
+ uint8_t dacChannel; \r
+ /** Callback function invoked at the end of transfer. */\r
+ DacCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+} DacCmd ;\r
+\r
+\r
+/** Constant structure associated with DAC port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct \r
+{\r
+ /** Pointer to DAC Hardware registers */\r
+ Dacc* pDacHw ;\r
+ /** Current SpiCommand being processed */\r
+ DacCmd *pCurrentCommand ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad ;\r
+ /** DACC Id as defined in the product datasheet */\r
+ uint8_t dacId ;\r
+ /** Mutual exclusion semaphore. */\r
+ volatile int8_t semaphore ;\r
+} DacDma;\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+#define DAC_OK 0\r
+#define DAC_ERROR 1\r
+#define DAC_ERROR_LOCK 2\r
+\r
+#define DACC_CHANNEL_0 0\r
+#define DACC_CHANNEL_1 1\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern uint32_t Dac_ConfigureDma( DacDma *pDacd ,\r
+ Dacc *pDacHw ,\r
+ uint8_t DacId,\r
+ sXdmad *pXdmad );\r
+extern uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand);\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST)\r
+#define DACC_CfgModeReg(pDACC, mode) { (pDACC)->DACC_MR = (mode); }\r
+#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR)\r
+#define DACC_CfgTrigger(pDACC, mode) { (pDACC)->DACC_TRIGR = (mode); }\r
+\r
+#define DACC_EnableChannel(pDACC, channel) {(pDACC)->DACC_CHER = (1 << (channel));}\r
+#define DACC_DisableChannel(pDACC, channel) {(pDACC)->DACC_CHDR = (1 << (channel));}\r
+\r
+#define DACC_EnableIt(pDACC, mode) {(pDACC)->DACC_IER = (mode);}\r
+#define DACC_DisableIt(pDACC, mode) {(pDACC)->DACC_IDR = (mode);}\r
+#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR)\r
+#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR)\r
+#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR)\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _DAC_DMA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for DACC\r
+ * -# Initialize the DACC with DACC_Initialize().\r
+ * -# Select the active channel using DACC_EnableChannel()\r
+ * -# Start the conversion with DACC_StartConversion()\r
+ * -# Wait the end of the conversion by polling status with DACC_GetStatus()\r
+ * -# Finally, get the converted data using DACC_GetConvertedData()\r
+ *\r
+*/\r
+#ifndef _DACC_\r
+#define _DACC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+#define DACC_CHANNEL_0 0\r
+#define DACC_CHANNEL_1 1\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+#define DACC_CfgModeReg(pDACC, mode) { \\r
+ (pDACC)->DACC_MR = (mode);\\r
+ }\r
+\r
+#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR)\r
+\r
+#define DACC_StartConversion(pDACC) ((pDACC)->DACC_CR = DACC_CR_START)\r
+\r
+#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST)\r
+\r
+#define DACC_EnableChannel(pDACC, channel) {\\r
+ (pDACC)->DACC_CHER = (1 << (channel));\\r
+ }\r
+\r
+#define DACC_DisableChannel(pDACC, channel) {\\r
+ (pDACC)->DACC_CHDR = (1 << (channel));\\r
+ }\r
+\r
+#define DACC_EnableIt(pDACC, mode) {\\r
+ assert( ((mode)&0xFFF00000)== 0 ) ;\\r
+ (pDACC)->DACC_IER = (mode);\\r
+ }\r
+\r
+#define DACC_DisableIt(pDACC, mode) {\\r
+ assert( ((mode)&0xFFF00000)== 0 ) ;\\r
+ (pDACC)->DACC_IDR = (mode);\\r
+ }\r
+\r
+#define DACC_EnableDataReadyIt(pDACC) ((pDACC)->DACC_IER = AT91C_DACC_DRDY)\r
+\r
+#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR)\r
+\r
+#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR)\r
+\r
+#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR)\r
+\r
+#define DACC_GetLastConvertedData(pDACC) ((pDACC)->DACC_LCDR)\r
+\r
+#define DACC_CfgAnalogCtrlReg(pDACC,mode) {\\r
+ assert( ((mode) & 0xFFFCFF3C)==0 ) ;\\r
+ (pDACC)->DACC_ACR = (mode);\\r
+ }\r
+\r
+#define DACC_CfgExtModeReg(pDACC, extmode) {\\r
+ assert( ((extmode) & 0xFF00FFFE)==0 ) ;\\r
+ (pDACC)->DACC_EMR = (extmode);\\r
+ }\r
+\r
+#define DACC_GetAnalogCtrlReg(pDACC) ((pDACC)->DACC_ACR)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+extern void DACC_Initialize( Dacc* pDACC,\r
+ uint8_t idDACC,\r
+ uint8_t trgEn,\r
+ uint8_t trgSel,\r
+ uint8_t word,\r
+ uint8_t sleepMode,\r
+ uint32_t mck,\r
+ uint8_t refresh,/*refresh period*/\r
+ uint8_t user_sel,/*user channel selection*/\r
+ uint32_t tag_mode,/*using tag for channel number*/\r
+ uint32_t startup\r
+ );\r
+\r
+\r
+extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData ) ;\r
+\r
+extern uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t* pwBuffer, uint32_t dwSize ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _DACC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) \r
+ * peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt()\r
+ * and EFC_DisableFrdyIt().\r
+ * -# Translates the given address into which EEFC, page and offset values\r
+ * for difference density %flash memory using EFC_TranslateAddress().\r
+ * -# Computes the address of a %flash access given the EFC, page and offset\r
+ * for difference density %flash memory using EFC_ComputeAddress().\r
+ * -# Start the executing command with EFC_PerformCommand()\r
+ * -# Retrieve the current status of the EFC using EFC_GetStatus().\r
+ * -# Retrieve the result of the last executed command with EFC_GetResult().\r
+ */\r
+\r
+#ifndef _EEFC_\r
+#define _EEFC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+/* TODO: Temporary definition for missing symbol in header file */\r
+#define IFLASH_SECTOR_SIZE 65536u\r
+\r
+\r
+/* EFC command */\r
+#define EFC_FCMD_GETD 0x00 /* Get Flash Descriptor */\r
+#define EFC_FCMD_WP 0x01 /* Write page */\r
+#define EFC_FCMD_WPL 0x02 /* Write page and lock */\r
+#define EFC_FCMD_EWP 0x03 /* Erase page and write page */\r
+#define EFC_FCMD_EWPL 0x04 /* Erase page and write page then lock */\r
+#define EFC_FCMD_EA 0x05 /* Erase all */\r
+#define EFC_FCMD_EPA 0x07 /* Erase pages */\r
+#define EFC_FCMD_SLB 0x08 /* Set Lock Bit */\r
+#define EFC_FCMD_CLB 0x09 /* Clear Lock Bit */\r
+#define EFC_FCMD_GLB 0x0A /* Get Lock Bit */\r
+#define EFC_FCMD_SFB 0x0B /* Set GPNVM Bit */\r
+#define EFC_FCMD_CFB 0x0C /* Clear GPNVM Bit */\r
+#define EFC_FCMD_GFB 0x0D /* Get GPNVM Bit */\r
+#define EFC_FCMD_STUI 0x0E /* Start unique ID */\r
+#define EFC_FCMD_SPUI 0x0F /* Stop unique ID */\r
+#define EFC_FCMD_GCALB 0x10 /* Get CALIB Bit */\r
+#define EFC_FCMD_ES 0x11 /* Erase Sector */\r
+#define EFC_FCMD_WUS 0x12 /* Write User Signature */\r
+#define EFC_FCMD_EUS 0x13 /* Erase User Signature */\r
+#define EFC_FCMD_STUS 0x14 /* Start Read User Signature */\r
+#define EFC_FCMD_SPUS 0x15 /* Stop Read User Signature */\r
+\r
+/* The IAP function entry addreass */\r
+#define CHIP_FLASH_IAP_ADDRESS (0x00800008)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void EFC_EnableFrdyIt( Efc* efc ) ;\r
+\r
+extern void EFC_DisableFrdyIt( Efc* efc ) ;\r
+\r
+extern void EFC_SetWaitState( Efc* efc, uint8_t cycles ) ;\r
+\r
+extern void EFC_TranslateAddress( Efc** pEfc, uint32_t dwAddress, \r
+ uint16_t *pwPage, uint16_t *pwOffset ) ;\r
+\r
+extern void EFC_ComputeAddress( Efc* efc, uint16_t wPage, uint16_t wOffset, \r
+ uint32_t *pdwAddress ) ;\r
+\r
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, \r
+ uint32_t dwArgument, uint32_t dwUseIAP ) ;\r
+\r
+extern uint32_t EFC_GetStatus( Efc* efc ) ;\r
+\r
+extern uint32_t EFC_GetResult( Efc* efc ) ;\r
+\r
+extern void EFC_SetFlashAccessMode(Efc* efc, uint32_t dwMode) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _EEFC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Interface for default exception handlers.\r
+ */\r
+\r
+#ifndef _EXCEPTIONS_\r
+#define _EXCEPTIONS_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Function prototype for exception table items (interrupt handler). */\r
+typedef void( *IntFunc )( void ) ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Default empty handler */\r
+extern void IrqHandlerNotUsed( void ) ;\r
+\r
+/* Cortex-M3 core handlers */\r
+extern void NMI_Handler( void );\r
+extern void HardFault_Handler( void );\r
+extern void MemManage_Handler( void );\r
+extern void BusFault_Handler( void );\r
+extern void UsageFault_Handler( void );\r
+extern void SVC_Handler( void );\r
+extern void DebugMon_Handler( void );\r
+extern void PendSV_Handler( void );\r
+extern void SysTick_Handler( void );\r
+\r
+/* Peripherals handlers */\r
+extern void ACC_IrqHandler( void ) ;\r
+extern void ADC_IrqHandler( void ) ;\r
+extern void CRCCU_IrqHandler( void ) ;\r
+extern void DAC_IrqHandler( void ) ;\r
+extern void EEFC_IrqHandler( void ) ;\r
+extern void MCI_IrqHandler( void ) ;\r
+extern void PIOA_IrqHandler( void ) ;\r
+extern void PIOB_IrqHandler( void ) ;\r
+extern void PIOC_IrqHandler( void ) ;\r
+extern void PMC_IrqHandler( void ) ;\r
+extern void PWM_IrqHandler( void ) ;\r
+extern void RSTC_IrqHandler( void ) ;\r
+extern void RTC_IrqHandler( void ) ;\r
+extern void RTT_IrqHandler( void ) ;\r
+extern void SMC_IrqHandler( void ) ;\r
+extern void SPI_IrqHandler( void ) ;\r
+extern void SSC_IrqHandler( void ) ;\r
+extern void SUPC_IrqHandler( void ) ;\r
+extern void TC0_IrqHandler( void ) ;\r
+extern void TC1_IrqHandler( void ) ;\r
+extern void TC2_IrqHandler( void ) ;\r
+extern void TC3_IrqHandler( void ) ;\r
+extern void TC4_IrqHandler( void ) ;\r
+extern void TC5_IrqHandler( void ) ;\r
+extern void TWI0_IrqHandler( void ) ;\r
+extern void TWI1_IrqHandler( void ) ;\r
+extern void UART0_IrqHandler( void ) ;\r
+extern void UART1_IrqHandler( void ) ;\r
+extern void USART0_IrqHandler( void ) ;\r
+extern void USART1_IrqHandler( void ) ;\r
+extern void USART2_IrqHandler( void ) ; \r
+extern void USBD_IrqHandler(void);\r
+extern void WDT_IrqHandler( void ) ;\r
+\r
+\r
+#endif /* _EXCEPTIONS_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * The flash driver provides the unified interface for flash program operations.\r
+ *\r
+ */\r
+\r
+#ifndef _FLASHD_\r
+#define _FLASHD_\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+ \r
+#define GPNVBit_SecurityBit 0\r
+#define GPNVBit_BootMode 1\r
+#define GPNVBit_TCMBit1 6\r
+#define GPNVBit_TCMBit2 7\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) ;\r
+\r
+extern uint32_t FLASHD_Erase( uint32_t dwAddress ) ;\r
+\r
+extern uint32_t FLASHD_EraseSector( uint32_t dwAddress ) ;\r
+\r
+extern uint32_t FLASHD_ErasePages( uint32_t dwAddress, uint32_t dwPageNum ) ;\r
+\r
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, \r
+ uint32_t dwSize ) ;\r
+\r
+extern uint32_t FLASHD_Lock( uint32_t dwStart, uint32_t dwEnd, \r
+ uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;\r
+\r
+extern uint32_t FLASHD_Unlock( uint32_t dwStart, uint32_t dwEnd, \r
+ uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;\r
+\r
+extern uint32_t FLASHD_IsLocked( uint32_t dwStart, uint32_t dwEnd ) ;\r
+\r
+extern uint32_t FLASHD_SetGPNVM( uint8_t gpnvm ) ;\r
+\r
+extern uint32_t FLASHD_ClearGPNVM( uint8_t gpnvm ) ;\r
+\r
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t gpnvm ) ;\r
+\r
+#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet( 0 )\r
+\r
+#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM( 0 )\r
+\r
+extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _FLASHD_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup gmac_module\r
+ * @{\r
+ * Provides the interface to configure and use the GMAC peripheral.\r
+ *\r
+ * \section gmac_usage Usage\r
+ * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls\r
+ * are also available, such as:\r
+ * - GMAC_SetSpeed(): Setup GMAC working clock.\r
+ * - GMAC_FullDuplexEnable(): Working in full duplex or not.\r
+ * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).\r
+ * - ...\r
+ * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls\r
+ * can modify with:\r
+ * - GMAC_ReceiveEnable(): Enable/Disable Rx.\r
+ * - GMAC_TransmitEnable(): Enable/Disable Tx.\r
+ * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.\r
+ * - ...\r
+ * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),\r
+ * GMAC_GetItMask() and GMAC_GetItStatus().\r
+ * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()\r
+ * GMAC_ClearTxStatus() and GMAC_ClearRxStatus().\r
+ * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),\r
+ * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define\r
+ * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.\r
+ * - Manage PHY through GMAC is performed by\r
+ * - GMAC_ManagementEnable(): Enable/Disable PHY management.\r
+ * - GMAC_PHYMaintain(): Execute PHY management commands.\r
+ * - GMAC_PHYData(): Return PHY management data.\r
+ * - GMAC_IsIdle(): Check if PHY is idle.\r
+ * - Setup GMAC parameters with following functions:\r
+ * - GMAC_SetHash(): Set Hash value.\r
+ * - GMAC_SetAddress(): Set MAC address.\r
+ * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()\r
+ * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()\r
+ *\r
+ * For more accurate information, please look at the GMAC section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref gmacd_module\r
+ *\r
+ * Related files:\n\r
+ * gmac.c\n\r
+ * gmac.h.\n\r
+ *\r
+ * \defgroup gmac_defines GMAC Defines\r
+ * \defgroup gmac_structs GMAC Data Structs\r
+ * \defgroup gmac_functions GMAC Functions\r
+ */\r
+/**@}*/\r
+\r
+#ifndef _GMAC_H\r
+#define _GMAC_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Defines\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup gmac_defines\r
+ @{*/\r
+\r
+#define NUM_GMAC_QUEUES 3\r
+/// Board GMAC base address\r
+\r
+ \r
+/// Buffer Size\r
+#define GMAC_RX_UNITSIZE 512 /// Fixed size for RX buffer\r
+#define GMAC_TX_UNITSIZE 512 /// Size for ETH frame length\r
+#define GMAC_FRAME_LENTGH_MAX 1536\r
+ \r
+#define GMAC_DUPLEX_HALF 0\r
+#define GMAC_DUPLEX_FULL 1\r
+\r
+//\r
+#define GMAC_SPEED_10M 0\r
+#define GMAC_SPEED_100M 1\r
+#define GMAC_SPEED_1000M 2\r
+ \r
+/*------------------------------------------------------------------------------\r
+ Definitions\r
+------------------------------------------------------------------------------\r
+*/\r
+/// The buffer addresses written into the descriptors must be aligned so the\r
+/// last few bits are zero. These bits have special meaning for the GMAC\r
+/// peripheral and cannot be used as part of the address.\r
+#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)\r
+#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask\r
+\r
+// receive buffer descriptor bits\r
+#define GMAC_RX_OWNERSHIP_BIT (1u << 0)\r
+#define GMAC_RX_WRAP_BIT (1u << 1)\r
+#define GMAC_RX_SOF_BIT (1u << 14)\r
+#define GMAC_RX_EOF_BIT (1u << 15)\r
+\r
+// Transmit buffer descriptor bits\r
+#define GMAC_TX_LAST_BUFFER_BIT (1u << 15)\r
+#define GMAC_TX_WRAP_BIT (1u << 30)\r
+#define GMAC_TX_USED_BIT (1u << 31)\r
+#define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded\r
+#define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Underrun\r
+#define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame\r
+#define GMAC_TX_ERR_BITS \\r
+ (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)\r
+\r
+// Interrupt bits\r
+#define GMAC_INT_RX_BITS \\r
+ (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)\r
+#define GMAC_INT_TX_ERR_BITS \\r
+ (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)\r
+#define GMAC_INT_TX_BITS \\r
+ (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup gmac_structs\r
+ @{*/\r
+ \r
+/* This is the list of GMAC queue */\r
+typedef enum {\r
+ GMAC_QUE_0 = 0,\r
+ GMAC_QUE_1 = 1,\r
+ GMAC_QUE_2 = 2\r
+}gmacQueList_t;\r
+\r
+/** Receive buffer descriptor struct */\r
+typedef struct _GmacRxDescriptor {\r
+ union _GmacRxAddr {\r
+ uint32_t val;\r
+ struct _GmacRxAddrBM {\r
+ uint32_t bOwnership:1, /**< User clear, GMAC set this to one once\r
+ it has successfully written a frame to\r
+ memory */\r
+ bWrap:1, /**< Marks last descriptor in receive buffer */\r
+ addrDW:30; /**< Address in number of DW */\r
+ } bm;\r
+ } addr; /**< Address, Wrap & Ownership */\r
+ union _GmacRxStatus {\r
+ uint32_t val;\r
+ struct _GmacRxStatusBM {\r
+ uint32_t len:12, /** Length of frame including FCS */\r
+ offset:2, /** Receive buffer offset,\r
+ bits 13:12 of frame length for jumbo\r
+ frame */\r
+ bSof:1, /** Start of frame */\r
+ bEof:1, /** End of frame */\r
+ bCFI:1, /** Concatenation Format Indicator */\r
+ vlanPriority:3, /** VLAN priority (if VLAN detected) */\r
+ bPriorityDetected:1, /** Priority tag detected */\r
+ bVlanDetected:1, /**< VLAN tag detected */\r
+ bTypeIDMatch:1, /**< Type ID match */\r
+ bAddr4Match:1, /**< Address register 4 match */\r
+ bAddr3Match:1, /**< Address register 3 match */\r
+ bAddr2Match:1, /**< Address register 2 match */\r
+ bAddr1Match:1, /**< Address register 1 match */\r
+ reserved:1,\r
+ bExtAddrMatch:1, /**< External address match */\r
+ bUniHashMatch:1, /**< Unicast hash match */\r
+ bMultiHashMatch:1, /**< Multicast hash match */\r
+ bBroadcastDetected:1; /**< Global all ones broadcast\r
+ address detected */\r
+ } bm;\r
+ } status;\r
+} sGmacRxDescriptor ; /* GCC */\r
+\r
+/** Transmit buffer descriptor struct */\r
+typedef struct _GmacTxDescriptor {\r
+ uint32_t addr;\r
+ union _GmacTxStatus {\r
+ uint32_t val;\r
+ struct _GmacTxStatusBM {\r
+ uint32_t len:11, /**< Length of buffer */\r
+ reserved:4,\r
+ bLastBuffer:1, /**< Last buffer (in the current frame) */\r
+ bNoCRC:1, /**< No CRC */\r
+ reserved1:10,\r
+ bExhausted:1, /**< Buffer exhausted in mid frame */\r
+ bUnderrun:1, /**< Transmit underrun */\r
+ bError:1, /**< Retry limit exceeded, error detected */\r
+ bWrap:1, /**< Marks last descriptor in TD list */\r
+ bUsed:1; /**< User clear, GMAC sets this once a frame\r
+ has been successfully transmitted */\r
+ } bm;\r
+ } status;\r
+} sGmacTxDescriptor; /* GCC */\r
+\r
+/** @}*/\r
+\r
+//-----------------------------------------------------------------------------\r
+// PHY Exported functions\r
+//-----------------------------------------------------------------------------\r
+extern uint8_t GMAC_IsIdle(Gmac *pGmac);\r
+extern void GMAC_PHYMaintain(Gmac *pGmac,\r
+ uint8_t bPhyAddr,\r
+ uint8_t bRegAddr,\r
+ uint8_t bRW,\r
+ uint16_t wData);\r
+extern uint16_t GMAC_PHYData(Gmac *pGmac);\r
+extern void GMAC_ClearStatistics(Gmac *pGmac);\r
+extern void GMAC_IncreaseStatistics(Gmac *pGmac);\r
+extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);\r
+extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck );\r
+extern void GMAC_EnableMdio(Gmac *pGmac );\r
+extern void GMAC_DisableMdio(Gmac *pGmac );\r
+extern void GMAC_EnableMII(Gmac *pGmac );\r
+extern void GMAC_EnableRMII(Gmac *pGmac );\r
+extern void GMAC_EnableGMII( Gmac *pGmac );\r
+extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);\r
+extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);\r
+extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);\r
+extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);\r
+extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);\r
+extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);\r
+extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);\r
+extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);\r
+extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);\r
+extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);\r
+extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);\r
+extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis);\r
+extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);\r
+extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);\r
+extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);\r
+extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);\r
+extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);\r
+extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);\r
+extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);\r
+extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);\r
+extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);\r
+extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB);\r
+extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);\r
+extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);\r
+extern void GMAC_DmaConfigure(Gmac *pGmac, uint32_t dwCfg);\r
+extern uint32_t GMAC_GetConfigure(Gmac *pGmac);\r
+extern void GMAC_TransmissionStart(Gmac *pGmac);\r
+extern void GMAC_TransmissionHalt(Gmac *pGmac);\r
+extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);\r
+#endif // #ifndef GMAC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup gmacd_module\r
+ * @{\r
+ * Implement GMAC data transfer and PHY management functions.\r
+ *\r
+ * \section Usage\r
+ * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler()\r
+ * to handle GMAC interrupt events.\r
+ * -# Implement sGmacd instance in application.\r
+ * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(),\r
+ * so that GMAC data can be transmitted/received.\r
+ * -# Some management callbacks can be set by GMACD_SetRxCallback()\r
+ * and GMACD_SetTxWakeupCallback().\r
+ * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used\r
+ * to check the free space in TX queue.\r
+ * -# Check and obtain received ethernet packets via GMACD_Poll().\r
+ *\r
+ * \sa \ref gmacb_module, \ref gmac_module\r
+ *\r
+ * Related files:\n\r
+ * \ref gmacd.c\n\r
+ * \ref gmacd.h.\n\r
+ *\r
+ * \defgroup gmacd_defines GMAC Driver Defines\r
+ * \defgroup gmacd_types GMAC Driver Types\r
+ * \defgroup gmacd_functions GMAC Driver Functions\r
+ */\r
+/**@}*/\r
+\r
+#ifndef _GMACD_H_\r
+#define _GMACD_H_\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Definitions\r
+ *---------------------------------------------------------------------------*/\r
+/** \addtogroup gmacd_defines\r
+ @{*/\r
+\r
+\r
+/** \addtogroup gmacd_rc GMACD Return Codes\r
+ @{*/\r
+#define GMACD_OK 0 /**< Operation OK */\r
+#define GMACD_TX_BUSY 1 /**< TX in progress */\r
+#define GMACD_RX_NULL 1 /**< No data received */\r
+/** Buffer size not enough */\r
+#define GMACD_SIZE_TOO_SMALL 2\r
+/** Parameter error, TX packet invalid or RX size too small */\r
+#define GMACD_PARAM 3\r
+/** Transter is not initialized */\r
+#define GMACD_NOT_INITIALIZED 4\r
+/** @}*/\r
+\r
+/** @}*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+/** \addtogroup gmacd_types\r
+ @{*/\r
+\r
+/** RX callback */\r
+typedef void (*fGmacdTransferCallback)(uint32_t status);\r
+/** Wakeup callback */\r
+typedef void (*fGmacdWakeupCallback)(void);\r
+\r
+/**\r
+ * GMAC scatter-gather entry.\r
+ */\r
+typedef struct _GmacSG {\r
+ uint32_t size;\r
+ void *pBuffer;\r
+} sGmacSG;\r
+\r
+/**\r
+ * GMAC scatter-gather list.\r
+ */\r
+typedef struct _GmacSGList {\r
+ uint32_t len;\r
+ sGmacSG *sg;\r
+} sGmacSGList;\r
+\r
+/**\r
+ * GMAC Queue driver.\r
+ */\r
+typedef struct _GmacQueueDriver {\r
+ uint8_t *pTxBuffer;\r
+ /** Pointer to allocated RX buffer */\r
+ uint8_t *pRxBuffer;\r
+\r
+ /** Pointer to Rx TDs (must be 8-byte aligned) */\r
+ sGmacRxDescriptor *pRxD;\r
+ /** Pointer to Tx TDs (must be 8-byte aligned) */\r
+ sGmacTxDescriptor *pTxD;\r
+\r
+ /** Optional callback to be invoked once a frame has been received */\r
+ fGmacdTransferCallback fRxCb;\r
+ /** Optional callback to be invoked once several TD have been released */\r
+ fGmacdWakeupCallback fWakupCb;\r
+ /** Optional callback list to be invoked once TD has been processed */\r
+ fGmacdTransferCallback *fTxCbList;\r
+\r
+ /** RX TD list size */\r
+ uint16_t wRxListSize;\r
+ /** RX index for current processing TD */\r
+ uint16_t wRxI;\r
+\r
+ /** TX TD list size */\r
+ uint16_t wTxListSize;\r
+ /** Circular buffer head pointer by upper layer (buffer to be sent) */\r
+ uint16_t wTxHead;\r
+ /** Circular buffer tail pointer incremented by handlers (buffer sent) */\r
+ uint16_t wTxTail;\r
+\r
+ /** Number of free TD before wakeup callback is invoked */\r
+ uint8_t bWakeupThreshold;\r
+ \r
+} sGmacQd;\r
+\r
+/**\r
+ * GMAC driver struct.\r
+ */\r
+typedef struct _GmacDriver {\r
+\r
+ /** Pointer to HW register base */\r
+ Gmac *pHw;\r
+ /** HW ID */\r
+ uint8_t bId;\r
+ /** Base Queue list params **/\r
+ sGmacQd queueList[NUM_GMAC_QUEUES]; \r
+} sGmacd;\r
+\r
+/** @}*/\r
+\r
+/** \addtogroup gmacd_functions\r
+ @{*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * GMAC Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+extern void GMACD_Handler(sGmacd *pGmacd , gmacQueList_t queIdx);\r
+\r
+extern void GMACD_Init(sGmacd *pGmacd,\r
+ Gmac *pHw,\r
+ uint8_t bID, \r
+ uint8_t enableCAF, \r
+ uint8_t enableNBC );\r
+\r
+extern uint8_t GMACD_InitTransfer( sGmacd *pGmacd,\r
+ uint8_t *pRxBuffer, \r
+ sGmacRxDescriptor *pRxD,\r
+ uint16_t wRxSize,\r
+ uint8_t *pTxBuffer, \r
+ sGmacTxDescriptor *pTxD, \r
+ fGmacdTransferCallback *pTxCb,\r
+ uint16_t wTxSize,\r
+ gmacQueList_t queIdx);\r
+\r
+extern void GMACD_Reset(sGmacd *pGmacd);\r
+\r
+extern uint8_t GMACD_SendSG(sGmacd *pGmacd,\r
+ const sGmacSGList *sgl,\r
+ fGmacdTransferCallback fTxCb, \r
+ gmacQueList_t queIdx);\r
+\r
+extern uint8_t GMACD_Send(sGmacd *pGmacd,\r
+ void *pBuffer,\r
+ uint32_t size,\r
+ fGmacdTransferCallback fTxCb, \r
+ gmacQueList_t queIdx );\r
+\r
+extern uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx);\r
+\r
+extern uint8_t GMACD_Poll(sGmacd * pGmacd, \r
+ uint8_t *pFrame, \r
+ uint32_t frameSize, \r
+ uint32_t *pRcvSize, \r
+ gmacQueList_t queIdx);\r
+\r
+extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb, gmacQueList_t queIdx);\r
+\r
+extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,\r
+ fGmacdWakeupCallback fWakeup,\r
+ uint8_t bThreshold, \r
+ gmacQueList_t queIdx);\r
+\r
+/** @}*/\r
+\r
+#endif // #ifndef _GMACD_H_\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup hsmci_module Working with HSMCI\r
+ * \ingroup mcid_module\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * The HSMCI driver provides the interface to configure and use the HSMCI\r
+ * peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface.\r
+ * -# HSMCI_Reset(): Reset HSMCI interface.\r
+ * -# HSMCI_Select(): HSMCI slot and buswidth selection\r
+ * (\ref Hsmci::HSMCI_SDCR).\r
+ * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register\r
+ * (\ref Hsmci::HSMCI_MR).\r
+ * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus()\r
+ * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR,\r
+ * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR).\r
+ * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer\r
+ * (\ref Hsmci::HSMCI_BLKR).\r
+ * -# HSMCI_SendCmd(): Send SD/MMC command with argument\r
+ * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR).\r
+ * -# HSMCI_GetResponse(): Get SD/MMC response after command finished\r
+ * (\ref Hsmci::HSMCI_RSPR).\r
+ * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer\r
+ * (\ref Hsmci::HSMCI_DMA).\r
+ * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG).\r
+ * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control.\r
+ *\r
+ * For more accurate information, please look at the HSMCI section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref mcid_module\r
+ *\r
+ * Related files :\n\r
+ * \ref hsmci.h\n\r
+ * \ref hsmci.c.\n\r
+ */\r
+\r
+#ifndef HSMCID_H\r
+#define HSMCID_H\r
+/** \addtogroup hsmci_module\r
+ *@{\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup hsmci_functions HSMCI Functions\r
+ * @{\r
+ */\r
+\r
+extern void HSMCI_Enable(Hsmci* pRMci);\r
+extern void HSMCI_Disable(Hsmci* pRMci);\r
+extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup);\r
+\r
+extern void HSMCI_Select(Hsmci * pRMci,uint8_t bSlot,uint8_t bBusWidth);\r
+extern void HSMCI_SetSlot(Hsmci * pRMci,uint8_t bSlot);\r
+extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth);\r
+extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci);\r
+\r
+extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode);\r
+extern uint32_t HSMCI_GetMode(Hsmci *pRMci);\r
+extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof);\r
+extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv);\r
+extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn);\r
+extern uint8_t HSMCI_IsFByteEnabled(Hsmci * pRMci);\r
+extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv);\r
+\r
+extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources);\r
+extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources);\r
+extern uint32_t HSMCI_GetItMask(Hsmci *pRMci);\r
+\r
+extern void HSMCI_ConfigureTransfer(Hsmci * pRMci,uint16_t wBlkLen,uint16_t wCnt);\r
+extern void HSMCI_SetBlockLen(Hsmci * pRMci,uint16_t wBlkSize);\r
+extern void HSMCI_SetBlockCount(Hsmci * pRMci,uint16_t wBlkCnt);\r
+\r
+extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure);\r
+extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure);\r
+\r
+extern void HSMCI_SendCmd(Hsmci * pRMci,uint32_t dwCmd,uint32_t dwArg);\r
+extern uint32_t HSMCI_GetResponse(Hsmci *pRMci);\r
+extern uint32_t HSMCI_Read(Hsmci *pRMci);\r
+extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize);\r
+extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData);\r
+extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize);\r
+\r
+extern uint32_t HSMCI_GetStatus(Hsmci *pRMci);\r
+\r
+extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure);\r
+extern void HSMCI_EnableDma(Hsmci * pRMci,uint8_t bEnable);\r
+\r
+extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure);\r
+extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable);\r
+extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci);\r
+\r
+extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth);\r
+extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot);\r
+extern uint8_t HSMCI_GetSlot(Hsmci *pRMci);\r
+\r
+extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure);\r
+extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @}*/\r
+/**@}*/\r
+#endif //#ifndef HSMCID_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _ICM_\r
+#define _ICM_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Definition */\r
+/*------------------------------------------------------------------------------*/\r
+#define ICM_RCFG_CDWBN (0x1u << 0) /**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */\r
+#define ICM_RCFG_WRAP (0x1u << 1) /**< \brief (ICM_RCFG) Wrap Command */\r
+#define ICM_RCFG_EOM (0x1u << 2) /**< \brief (ICM_RCFG) End Of Monitoring */\r
+#define ICM_RCFG_RHIEN (0x1u << 4) /**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */\r
+#define ICM_RCFG_DMIEN (0x1u << 5) /**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */\r
+#define ICM_RCFG_BEIEN (0x1u << 6) /**< \brief (ICM_RCFG) Bus error interrupt enable */\r
+#define ICM_RCFG_WCIEN (0x1u << 7) /**< \brief (ICM_RCFG) Warp condition interrupt enable */\r
+#define ICM_RCFG_ECIEN (0x1u << 8) /**< \brief (ICM_RCFG) End bit condition interrupt enable */\r
+#define ICM_RCFG_SUIEN (0x1u << 9) /**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */\r
+#define ICM_RCFG_PROCDLY (0x1u << 10) /**< \brief (ICM_RCFG) Processing Delay*/\r
+#define ICM_RCFG_UALGO_Pos 12\r
+#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) /**< \brief (ICM_RCFG) User SHA Algorithm */\r
+#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) /**< \brief (ICM_RCFG) SHA1 algorithm processed */\r
+#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) /**< \brief (ICM_RCFG) SHA256 algorithm processed */\r
+#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) /**< \brief (ICM_RCFG) SHA224 algorithm processed */\r
+#define ICM_RCFG_MRPROT_Pos 24\r
+#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) /**< \brief (ICM_RCFG) Memory Region AHB Protection */\r
+#define ICM_RCFG_MRPROT(value) ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos)))\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Type */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/** \brief Structure ICM region descriptor area. */\r
+typedef struct _LinkedListDescriporIcmRegion\r
+{\r
+ /** the first byte address of the Region. */\r
+ uint32_t icm_raddr;\r
+ /** Configuration Structure Member. */\r
+ uint32_t icm_rcfg;\r
+ /** Control Structure Member. */\r
+ uint32_t icm_rctrl;\r
+ /** Next Address Structure Member. */\r
+ uint32_t icm_rnext;\r
+}LinkedListDescriporIcmRegion;\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+extern void ICM_Enable(void);\r
+extern void ICM_Disable(void);\r
+extern void ICM_SoftReset(void);\r
+extern void ICM_ReComputeHash(uint8_t region);\r
+extern void ICM_EnableMonitor(uint8_t region);\r
+extern void ICM_DisableMonitor(uint8_t region);\r
+extern void ICM_Configure(uint32_t mode);\r
+extern void ICM_EnableIt(uint32_t sources);\r
+extern void ICM_DisableIt(uint32_t sources);\r
+extern uint32_t ICM_GetIntStatus(void);\r
+extern uint32_t ICM_GetStatus(void);\r
+extern uint32_t ICM_GetUStatus(void);\r
+extern void ICM_SetDescStartAddress(uint32_t addr);\r
+extern void ICM_SetHashStartAddress(uint32_t addr);\r
+extern void ICM_SetInitHashValue(uint32_t val);\r
+#endif /* #ifndef _ICM_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup isi_module\r
+ * @{\r
+ * \section gmac_usage Usage\r
+ * - ISI_Init: initialize ISI with default parameters\r
+ * - ISI_EnableInterrupt: enable one or more interrupts\r
+ * - ISI_DisableInterrupt: disable one or more interrupts\r
+ * - ISI_Enable: enable isi module\r
+ * - ISI_Disable: disable isi module\r
+ * - ISI_CodecPathFull: enable codec path\r
+ * - ISI_SetFrame: set frame rate\r
+ * - ISI_BytesForOnePixel: return number of byte for one pixel\r
+ * - ISI_StatusRegister: return ISI status register\r
+ * - ISI_Reset: make a software reset\r
+ */\r
+/**@}*/\r
+\r
+#ifndef ISI_H\r
+#define ISI_H\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** ISI descriptors */\r
+typedef struct\r
+{\r
+ /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */\r
+ uint32_t CurrentLcdIndex;\r
+ /** set if Fifo Codec Empty is present */\r
+ volatile uint32_t DisplayCodec;\r
+ /** upgrade for each Fifo Codec Overflow (statistics use) */\r
+ uint32_t nb_codec_ovf;\r
+ /** upgrade for each Fifo Preview Overflow (statistics use) */\r
+ uint32_t nb_prev_ovf;\r
+}ISI_Descriptors;\r
+\r
+/** Frame Buffer Descriptors */\r
+typedef struct\r
+{\r
+ /** Address of the Current FrameBuffer */\r
+ uint32_t Current;\r
+ /** Address of the Control */\r
+ uint32_t Control;\r
+ /** Address of the Next FrameBuffer */\r
+ uint32_t Next;\r
+}ISI_FrameBufferDescriptors;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void ISI_Enable(void);\r
+extern void ISI_Disable(void);\r
+extern void ISI_EnableInterrupt(uint32_t flag);\r
+extern void ISI_DisableInterrupt(uint32_t flag);\r
+extern void ISI_CodecPathFull(void);\r
+extern void ISI_SetFrame(uint32_t frate);\r
+extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb);\r
+extern void ISI_Reset(void);\r
+extern void ISI_Init(pIsi_Video pVideo);\r
+extern uint32_t ISI_StatusRegister(void);\r
+\r
+#endif //#ifndef ISI_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/** \file */\r
+\r
+/**\r
+ * \ingroup sdmmc_hal\r
+ * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib)\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This driver implements SD(IO)/MMC command operations and MCI configuration\r
+ * routines to perform SD(IO)/MMC access. It's used for upper layer\r
+ * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# MCID_Init(): Initializes a MCI driver instance and the underlying\r
+ * peripheral.\r
+ * -# MCID_SendCmd(): Starts a MCI transfer which described by\r
+ * \ref sSdmmcCommand.\r
+ * -# MCID_CancelCmd(): Cancel a pending command.\r
+ * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished.\r
+ * -# MCID_Handler(): Interrupt handler which is called by ISR handler.\r
+ * -# MCID_IOCtrl(): IO control function to report HW attributes to upper\r
+ * layer driver and modify HW settings (such as clock\r
+ * frequency, High-speed support, etc. See\r
+ * \ref sdmmc_ioctrls).\r
+ *\r
+ * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI",\r
+ * \ref libsdmmc_module "SD/MMC Library"\r
+ *\r
+ * Related files:\n\r
+ * \ref mcid.h\n\r
+ * \ref mcid_dma.c.\n\r
+ */\r
+\r
+#ifndef MCID_H\r
+#define MCID_H\r
+/** \addtogroup mcid_module\r
+ *@{\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+\r
+/** \addtogroup mcid_defines MCI Driver Defines\r
+ * @{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** MCI States */\r
+#define MCID_IDLE 0 /**< Idle */\r
+#define MCID_LOCKED 1 /**< Locked for specific slot */\r
+#define MCID_CMD 2 /**< Processing the command */\r
+#define MCID_ERROR 3 /**< Command error */\r
+\r
+/** MCI Initialize clock 400K Hz */\r
+#define MCI_INITIAL_SPEED 400000\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup mcid_structs MCI Driver Data Structs\r
+ * @{\r
+ */\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief MCI Driver\r
+ */\r
+typedef struct _Mcid\r
+{\r
+ /** Pointer to a MCI peripheral. */\r
+ Hsmci *pMciHw;\r
+ /** Pointer to a DMA driver */\r
+ sXdmad *pXdmad;\r
+ /** Pointer to currently executing command. */\r
+ void *pCmd;\r
+ /** MCK source, Hz */\r
+ uint32_t dwMck;\r
+ /** DMA transfer channel */\r
+ uint32_t dwDmaCh;\r
+ /** DMA transferred data index (bytes) */\r
+ uint32_t dwXfrNdx;\r
+ /** DMA transfer size (bytes) */\r
+ uint32_t dwXSize;\r
+ /** MCI peripheral identifier. */\r
+ uint8_t bID;\r
+ /** Polling mode */\r
+ uint8_t bPolling;\r
+ /** Reserved */\r
+ uint8_t reserved;\r
+ /** state. */\r
+ volatile uint8_t bState;\r
+ /** Status. */\r
+ volatile uint8_t bOpStatus;\r
+} sMcid;\r
+\r
+/** @}*/\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup mcid_functions MCI Driver Functions\r
+ @{*/\r
+extern void MCID_Init(sMcid * pMcid,\r
+ Hsmci * pMci, uint8_t bID, uint32_t dwMck,\r
+ sXdmad * pXdmad,\r
+ uint8_t bPolling);\r
+\r
+extern void MCID_Reset(sMcid * pMcid);\r
+\r
+extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot);\r
+\r
+extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot);\r
+\r
+extern uint32_t MCID_Release(sMcid * pMcid);\r
+\r
+extern void MCID_Handler(sMcid * pMcid);\r
+\r
+extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd);\r
+\r
+extern uint32_t MCID_CancelCmd(sMcid * pMcid);\r
+\r
+extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid);\r
+\r
+extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/** @}*/\r
+/**@}*/\r
+#endif //#ifndef HSMCID_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _MEDILB_H_\r
+#define _MEDILB_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+ \r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ \r
+\r
+#endif /* #ifndef _MEDILB_H_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _MPU_H_\r
+#define _MPU_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+#define ARM_MODE_USR 0x10\r
+\r
+#define PRIVILEGE_MODE 0\r
+#define USER_MODE 1\r
+\r
+//#define ITCM_SIZE\r
+//#define DTCM_SIZE\r
+//#define FLASH_SIZE\r
+//#define ISRAM_SIZE\r
+\r
+#define MPU_UNPRIVILEGED_RAM_REGION ( 0 )\r
+#define MPU_PRIVILEGE_RAM_REGION ( 1 )\r
+#define MPU_UNPRIVILEGED_FLASH_REGION ( 2 )\r
+#define MPU_PRIVILEGED_FLASH_REGION ( 3 )\r
+#define MPU_PRIVILEGED_PERIPHERALS_REGION ( 4 )\r
+#define MPU_UART_REGION_REGION ( 5 )\r
+#define MPU_SDRAM_REGION ( 6 )\r
+\r
+#if 1\r
+#define MPU_DEFAULT_ITCM_REGION ( 1 )\r
+#define MPU_DEFAULT_IFLASH_REGION ( 2 )\r
+#define MPU_DEFAULT_DTCM_REGION ( 3 )\r
+#define MPU_DEFAULT_PRAM_REGION ( 4 )\r
+#define MPU_DEFAULT_UPRAM_REGION ( 5 )\r
+#define MPU_PERIPHERALS_REGION ( 6 )\r
+#define MPU_USBHSRAM_REGION ( 7 )\r
+#define MPU_QSPIMEM_REGION ( 8 )\r
+#endif\r
+\r
+#if 0\r
+#define MPU_QSPIMEM_REGION ( 0 )\r
+#define MPU_USBHSRAM_REGION ( 1 )\r
+#define MPU_PERIPHERALS_REGION ( 2 )\r
+#define MPU_DEFAULT_DTCM_REGION ( 3 )\r
+#define MPU_DEFAULT_ITCM_REGION ( 4 )\r
+#define MPU_DEFAULT_UPRAM_REGION ( 5 )\r
+#define MPU_DEFAULT_IFLASH_REGION ( 6 )\r
+#define MPU_DEFAULT_PRAM_REGION ( 7 )\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+#define MPU_REGION_VALID ( 0x10 )\r
+#define MPU_REGION_ENABLE ( 0x01 )\r
+#define MPU_REGION_DISABLE ( 0x0 )\r
+\r
+#define MPU_ENABLE ( 0x1 )\r
+#define MPU_BGENABLE ( 0x1 << 2 )\r
+\r
+#define PROTECT_PIO_SUBREGION ( 0x1 << 4 ) \r
+\r
+#define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos )\r
+#define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos )\r
+#define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos )\r
+\r
+#define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos )\r
+\r
+#define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos )\r
+#define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos )\r
+\r
+#define MPU_TEX_NON_CACHE ( 0x04 << MPU_RASR_TEX_Pos )\r
+#define MPU_TEX_WRITE_BACK_ALLOCATE ( 0x05 << MPU_RASR_TEX_Pos )\r
+#define MPU_TEX_WRITE_THROUGH ( 0x06 << MPU_RASR_TEX_Pos )\r
+#define MPU_TEX_WRITE_BACK_NOALLOCATE ( 0x07 << MPU_RASR_TEX_Pos )\r
+\r
+/* Default memory map \r
+Address range Memory region Memory type Shareability Cache policy\r
+0x00000000- 0x1FFFFFFF Code Normal Non-shareablea WTb\r
+0x20000000- 0x3FFFFFFF SRAM Normal Non-shareablea WBWAb\r
+0x40000000- 0x5FFFFFFF Peripheral Device Non-shareablea -\r
+0x60000000- 0x7FFFFFFF External RAM Normal Non-shareablea WBWAb\r
+0x80000000- 0x9FFFFFFF WTb\r
+0xA0000000- 0xBFFFFFFF External device Devicea Shareable\r
+0xC0000000- 0xDFFFFFFF Non-shareablea\r
+0xE0000000- 0xE00FFFFF Private Peripheral Bus Strongly ordered Shareablea -\r
+0xE0100000- 0xFFFFFFFF Vendor-specific device Device Non-shareablea -\r
+*/\r
+\r
+/********* IFLASH memory macros *********************/\r
+#define ITCM_START_ADDRESS 0x00000000UL\r
+#define ITCM_END_ADDRESS 0x00400000UL\r
+#define IFLASH_START_ADDRESS 0x00400000UL\r
+#define IFLASH_END_ADDRESS 0x00600000UL\r
+#define IFLASH_HALF ((IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) >> 1)\r
+\r
+#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)\r
+#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + IFLASH_HALF)\r
+\r
+#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS + IFLASH_HALF + 1)\r
+#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)\r
+\r
+/**************** DTCM *******************************/\r
+#define DTCM_START_ADDRESS 0x20000000UL\r
+#define DTCM_END_ADDRESS 0x20400000UL\r
+\r
+\r
+/******* SRAM memory macros ***************************/\r
+\r
+#define SRAM_START_ADDRESS 0x20400000UL\r
+#define SRAM_END_ADDRESS 0x2045FFFFUL\r
+#define SRAM_HALF ((SRAM_END_ADDRESS - SRAM_START_ADDRESS) >>1)\r
+\r
+\r
+#define SRAM_PRIVILEGE_START_ADDRESS (SRAM_START_ADDRESS)\r
+#define SRAM_PRIVILEGE_END_ADDRESS (SRAM_START_ADDRESS + 0x3FFFF)\r
+\r
+#define SRAM_UNPRIVILEGE_START_ADDRESS (SRAM_PRIVILEGE_END_ADDRESS + 1)\r
+#define SRAM_UNPRIVILEGE_END_ADDRESS (SRAM_END_ADDRESS)\r
+\r
+/************** Peripherials memory region macros ********/\r
+\r
+#define PERIPHERALS_START_ADDRESS 0x40000000UL\r
+#define PERIPHERALS_END_ADDRESS 0x400E2000UL\r
+\r
+#define UART_REGION_START_ADDRESS 0x400E1C00UL\r
+#define UART_REGION_END_ADDRESS 0x400E2000UL\r
+\r
+/************** Peripherials memory region macros ********/\r
+\r
+#define PERIPHERALS_START_ADDRESS 0x40000000UL\r
+#define PERIPHERALS_END_ADDRESS 0x400E2000UL\r
+\r
+/************** QSPI region macros ******************/\r
+\r
+#define QSPI_START_ADDRESS 0x80000000UL\r
+#define QSPI_END_ADDRESS 0x9FFFFFFFUL\r
+\r
+/************** USBHS_RAM region macros ******************/\r
+\r
+#define USBHSRAM_START_ADDRESS 0xA0100000UL\r
+#define USBHSRAM_END_ADDRESS 0xA0200000UL\r
+\r
+/******* Ext-SRAM memory macros ***************************/\r
+\r
+#define SDRAM_START_ADDRESS 0x70000000UL\r
+#define SDRAM_END_ADDRESS 0x7FFFFFFFUL\r
+\r
+ /** Flag to indicate whether the svc is done */\r
+extern volatile uint32_t dwRaisePriDone;\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+void MPU_Enable( uint32_t dwMPUEnable );\r
+void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr );\r
+void MPU_SetRegionNum( uint32_t dwRegionNum );\r
+void MPU_DisableRegion( void );\r
+uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes );\r
+void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,\r
+ uint32_t dwRegionAttr);\r
+\r
+#endif /* #ifndef _MMU_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file provides a basic API for PIO configuration and usage of\r
+ * user-controlled pins. Please refer to the board.h file for a list of\r
+ * available pin definitions.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Define a constant pin description array such as the following one, using\r
+ * the existing definitions provided by the board.h file if possible:\r
+ * \code\r
+ * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD};\r
+ * \endcode\r
+ * Alternatively, it is possible to add new pins by provided the full Pin\r
+ * structure:\r
+ * \code\r
+ * // Pin instance to configure PA10 & PA11 as inputs with the internal\r
+ * // pull-up enabled.\r
+ * const Pin pPins = {\r
+ * (1 << 10) | (1 << 11),\r
+ * REG_PIOA,\r
+ * ID_PIOA,\r
+ * PIO_INPUT,\r
+ * PIO_PULLUP\r
+ * };\r
+ * \endcode\r
+ * -# Configure a pin array by calling PIO_Configure() with a pointer to the\r
+ * array and its size (which is computed using the PIO_LISTSIZE macro).\r
+ * -# Change and get the value of a user-controlled pin using the PIO_Set,\r
+ * PIO_Clear and PIO_Get methods.\r
+ * -# Get the level being currently output by a user-controlled pin configured\r
+ * as an output using PIO_GetOutputDataStatus().\r
+ */\r
+\r
+#ifndef _PIO_\r
+#define _PIO_\r
+\r
+/*\r
+ * Headers\r
+ */\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Global Definitions\r
+ */\r
+\r
+/** The pin is controlled by the associated signal of peripheral A. */\r
+#define PIO_PERIPH_A 0\r
+/** The pin is controlled by the associated signal of peripheral B. */\r
+#define PIO_PERIPH_B 1\r
+/** The pin is controlled by the associated signal of peripheral C. */\r
+#define PIO_PERIPH_C 2\r
+/** The pin is controlled by the associated signal of peripheral D. */\r
+#define PIO_PERIPH_D 3\r
+/** The pin is an input. */\r
+#define PIO_INPUT 4\r
+/** The pin is an output and has a default level of 0. */\r
+#define PIO_OUTPUT_0 5\r
+/** The pin is an output and has a default level of 1. */\r
+#define PIO_OUTPUT_1 6\r
+\r
+/** Default pin configuration (no attribute). */\r
+#define PIO_DEFAULT (0 << 0)\r
+/** The internal pin pull-up is active. */\r
+#define PIO_PULLUP (1 << 0)\r
+/** The internal glitch filter is active. */\r
+#define PIO_DEGLITCH (1 << 1)\r
+/** The pin is open-drain. */\r
+#define PIO_OPENDRAIN (1 << 2)\r
+\r
+/** The internal debouncing filter is active. */\r
+#define PIO_DEBOUNCE (1 << 3)\r
+\r
+/** Enable additional interrupt modes. */\r
+#define PIO_IT_AIME (1 << 4)\r
+\r
+/** Interrupt High Level/Rising Edge detection is active. */\r
+#define PIO_IT_RE_OR_HL (1 << 5)\r
+/** Interrupt Edge detection is active. */\r
+#define PIO_IT_EDGE (1 << 6)\r
+\r
+/** Low level interrupt is active */\r
+#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)\r
+/** High level interrupt is active */\r
+#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)\r
+/** Falling edge interrupt is active */\r
+#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)\r
+/** Rising edge interrupt is active */\r
+#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)\r
+/** The WP is enable */\r
+#define PIO_WPMR_WPEN_EN ( 0x01 << 0 )\r
+/** The WP is disable */\r
+#define PIO_WPMR_WPEN_DIS ( 0x00 << 0 )\r
+/** Valid WP key */\r
+#define PIO_WPMR_WPKEY_VALID ( 0x50494F << 8 )\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*\r
+ * Global Macros\r
+ */\r
+\r
+/**\r
+ * Calculates the size of an array of Pin instances. The array must be defined\r
+ * locally (i.e. not a pointer), otherwise the computation will not be correct.\r
+ * \param pPins Local array of Pin instances.\r
+ * \return Number of elements in array.\r
+ */\r
+#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin))\r
+\r
+/*\r
+ * Global Types\r
+ */\r
+\r
+\r
+/*\r
+ * Describes the type and attribute of one PIO pin or a group of similar pins.\r
+ * The #type# field can have the following values:\r
+ * - PIO_PERIPH_A\r
+ * - PIO_PERIPH_B\r
+ * - PIO_OUTPUT_0\r
+ * - PIO_OUTPUT_1\r
+ * - PIO_INPUT\r
+ *\r
+ * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,\r
+ * or combine (using bitwise OR '|') any number of the following constants:\r
+ * - PIO_PULLUP\r
+ * - PIO_DEGLITCH\r
+ * - PIO_DEBOUNCE\r
+ * - PIO_OPENDRAIN\r
+ * - PIO_IT_LOW_LEVEL\r
+ * - PIO_IT_HIGH_LEVEL\r
+ * - PIO_IT_FALL_EDGE\r
+ * - PIO_IT_RISE_EDGE\r
+ */\r
+typedef struct _Pin\r
+{\r
+ /* Bitmask indicating which pin(s) to configure. */\r
+ uint32_t mask;\r
+ /* Pointer to the PIO controller which has the pin(s). */\r
+ Pio *pio;\r
+ /* Peripheral ID of the PIO controller which has the pin(s). */\r
+ uint8_t id;\r
+ /* Pin type. */\r
+ uint8_t type;\r
+ /* Pin attribute. */\r
+ uint8_t attribute;\r
+} Pin ;\r
+\r
+/*\r
+ * Global Access Macros\r
+ */\r
+\r
+/*\r
+ * Global Functions\r
+ */\r
+\r
+extern uint8_t PIO_Configure( const Pin *list, uint32_t size ) ;\r
+\r
+extern void PIO_Set( const Pin *pin ) ;\r
+\r
+extern void PIO_Clear( const Pin *pin ) ;\r
+\r
+extern uint8_t PIO_Get( const Pin *pin ) ;\r
+\r
+extern uint8_t PIO_GetOutputDataStatus( const Pin *pin ) ;\r
+\r
+extern void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff );\r
+\r
+extern void PIO_EnableWriteProtect( const Pin *pin );\r
+\r
+extern void PIO_DisableWriteProtect( const Pin *pin );\r
+\r
+extern void PIO_SetPinType( Pin * pin, uint8_t pinType);\r
+\r
+extern uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin );\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PIO_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef PIO_CAPTURE_H\r
+#define PIO_CAPTURE_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \brief PIO Parallel Capture structure for initialize.\r
+ *\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct _SpioCaptureInit {\r
+\r
+ /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */\r
+ uint8_t dsize;\r
+ /** PDC size, data to be received */\r
+ uint16_t dPDCsize;\r
+ /** Data to be received */\r
+ uint32_t *pData;\r
+ /** Parallel Capture Mode Always Sampling */\r
+ uint8_t alwaysSampling;\r
+ /** Parallel Capture Mode Half Sampling */\r
+ uint8_t halfSampling;\r
+ /** Parallel Capture Mode First Sample */\r
+ uint8_t modeFirstSample;\r
+ /** Callback function invoked at Mode Data Ready */\r
+ void (*CbkDataReady)( struct _SpioCaptureInit* );\r
+ /** Callback function invoked at Mode Overrun Error */\r
+ void (*CbkOverrun)( struct _SpioCaptureInit* );\r
+ /** Callback function invoked at End of Reception Transfer */\r
+ void (*CbkEndReception)( struct _SpioCaptureInit* );\r
+ /** Callback function invoked at Reception Buffer Full */\r
+ void (*CbkBuffFull)( struct _SpioCaptureInit* );\r
+ /** Callback arguments.*/\r
+ void *pParam;\r
+\r
+} SpioCaptureInit ;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global Functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void PIO_CaptureDisableIt( uint32_t itToDisable ) ;\r
+extern void PIO_CaptureEnableIt( uint32_t itToEnable ) ;\r
+extern void PIO_CaptureEnable( void ) ;\r
+extern void PIO_CaptureDisable( void ) ;\r
+extern void PIO_CaptureInit( SpioCaptureInit* pInit ) ;\r
+\r
+#endif /* #ifndef PIO_CAPTURE_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Configuration and handling of interrupts on PIO status changes. The API\r
+ * provided here have several advantages over the traditional PIO interrupt\r
+ * configuration approach:\r
+ * - It is highly portable\r
+ * - It automatically demultiplexes interrupts when multiples pins have been\r
+ * configured on a single PIO controller\r
+ * - It allows a group of pins to share the same interrupt\r
+ *\r
+ * However, it also has several minor drawbacks that may prevent from using it\r
+ * in particular applications:\r
+ * - It enables the clocks of all PIO controllers\r
+ * - PIO controllers all share the same interrupt handler, which does the\r
+ * demultiplexing and can be slower than direct configuration\r
+ * - It reserves space for a fixed number of interrupts, which can be\r
+ * increased by modifying the appropriate constant in pio_it.c.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()\r
+ * with the desired priority (0 ... 7).\r
+ * -# Configure a status change interrupt on one or more pin(s) with\r
+ * PIO_ConfigureIt().\r
+ * -# Enable & disable interrupts on pins using PIO_EnableIt() and\r
+ * PIO_DisableIt().\r
+ */\r
+\r
+#ifndef _PIO_IT_\r
+#define _PIO_IT_\r
+\r
+/*\r
+ * Headers\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*\r
+ * Global functions\r
+ */\r
+\r
+extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ;\r
+\r
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ;\r
+\r
+extern void PIO_EnableIt( const Pin *pPin ) ;\r
+\r
+extern void PIO_DisableIt( const Pin *pPin ) ;\r
+\r
+extern void PIO_IT_InterruptHandler( void ) ;\r
+\r
+extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ;\r
+\r
+extern void PIO_CaptureHandler( void ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PIO_IT_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _PMC_\r
+#define _PMC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <stdint.h>\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+/* Definition for fast RC frequency */\r
+#define FAST_RC_4MHZ CKGR_MOR_MOSCRCF_4MHz\r
+#define FAST_RC_8MHZ CKGR_MOR_MOSCRCF_8MHz\r
+#define FAST_RC_12MHZ CKGR_MOR_MOSCRCF_12MHz\r
+\r
+/* Definitions for startup count.\r
+ * Note: 1 count unit stand for: 1 / 32768 * 8 = 244 us\r
+ */\r
+/* Default startup count for 4/8/12MHz fast RC (startup time: 10us ) */\r
+#define DEFAUTL_FAST_RC_COUNT 1\r
+/* Default startup count for 3-20MHz main oscilator (startup time: 1.4ms ) */\r
+#define DEFAUTL_MAIN_OSC_COUNT 8\r
+/* Default startup count for PLLA (startup time: 200us ) */\r
+#define DEFAUTL_PLLA_COUNT 1\r
+/* Default startup count for UPLL */\r
+#define DEFAUTL_UPLL_COUNT 3\r
+/* No change for default startup count */\r
+#define DEFAUTL_COUNT_NO_CHANGE 0xFFFF\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern void PMC_EnablePeripheral( uint32_t dwId ) ;\r
+extern void PMC_DisablePeripheral( uint32_t dwId ) ;\r
+\r
+extern void PMC_EnableAllPeripherals( void ) ;\r
+extern void PMC_DisableAllPeripherals( void ) ;\r
+\r
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ;\r
+\r
+extern void PMC_SelectExtOsc(void);\r
+extern void PMC_EnableExtOsc(void);\r
+extern void PMC_DisableExtOsc(void);\r
+extern void PMC_SelectExtBypassOsc(void);\r
+extern void PMC_EnableIntRC4_8_12MHz(uint32_t fastRcFreq);\r
+extern void PMC_DisableIntRC4_8_12MHz(void);\r
+extern void PMC_SetPllaClock(uint32_t mul, uint32_t div);\r
+extern void PMC_SetPllbClock(uint32_t mul, uint32_t div);\r
+extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler);\r
+extern void PMC_DisableAllClocks(void);\r
+extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, \r
+ uint32_t prescaler);\r
+extern void PMC_ConfigureMckWithPllb(uint32_t mul, uint32_t div, \r
+ uint32_t prescaler);\r
+extern void PMC_EnableXT32KFME(void);\r
+extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PMC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Configures PWM clocks A & B to run at the given frequencies using\r
+ * \ref PWMC_ConfigureClocks().\r
+ * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt()\r
+ * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime().\r
+ * -# Enable & disable channel using \ref PWMC_EnableChannel() and\r
+ * \ref PWMC_DisableChannel().\r
+ * -# Enable & disable the period interrupt for the given PWM channel using\r
+ * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt().\r
+ * -# Enable & disable the selected interrupts sources on a PWMC peripheral\r
+ * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt().\r
+ * -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(),\r
+ * \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock().\r
+ * -# Control PWM override output using \ref PWMC_SetOverrideValue(),\r
+ * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput().\r
+ * -# Send data through the transmitter using \ref PWMC_WriteBuffer().\r
+ *\r
+ */\r
+\r
+#ifndef _PWMC_\r
+#define _PWMC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void PWMC_ConfigureChannel(\r
+ Pwm* pPwm,\r
+ uint8_t channel,\r
+ uint32_t prescaler,\r
+ uint32_t alignment,\r
+ uint32_t polarity);\r
+extern void PWMC_ConfigureChannelExt(\r
+ Pwm* pPwm,\r
+ uint8_t channel,\r
+ uint32_t prescaler,\r
+ uint32_t alignment,\r
+ uint32_t polarity,\r
+ uint32_t countEventSelect,\r
+ uint32_t DTEnable,\r
+ uint32_t DTHInverte,\r
+ uint32_t DTLInverte);\r
+extern void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t clka, uint32_t clkb, uint32_t mck);\r
+extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period);\r
+extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty);\r
+extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL);\r
+extern void PWMC_ConfigureSyncChannel( Pwm* pPwm,\r
+ uint32_t channels,\r
+ uint32_t updateMode,\r
+ uint32_t requestMode,\r
+ uint32_t requestComparisonSelect);\r
+extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period);\r
+extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm );\r
+extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel);\r
+extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel);\r
+extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel);\r
+extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel);\r
+extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);\r
+extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);\r
+extern uint8_t PWMC_WriteBuffer(Pwm *pwmc,\r
+ void *buffer,\r
+ uint32_t length);\r
+extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value);\r
+extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);\r
+extern void PWMC_OutputOverrideSelection( Pwm* pPwm, uint32_t value );\r
+extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);\r
+extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode);\r
+extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault);\r
+extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value);\r
+extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value);\r
+extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode);\r
+extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode);\r
+extern uint32_t PWMC_GetStatus2( Pwm* pPwm);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PWMC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Serial Peripheral Interface (SPI) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _QSPI_\r
+#define _QSPI_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ *\r
+ * Here are several macros which should be used when configuring a SPI\r
+ * peripheral.\r
+ *\r
+ * \section qspi_configuration_macros SPI Configuration Macros\r
+ * - \ref QSPI_PCS\r
+ * - \ref QSPI_SCBR\r
+ * - \ref QSPI_DLYBS\r
+ * - \ref QSPI_DLYBCT\r
+ */\r
+\r
+\r
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */\r
+#define QSPI_SCBR(baudrate, masterClock) ((uint32_t) (masterClock / baudrate) << 8)\r
+\r
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */\r
+#define QSPI_DLYBS(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)\r
+\r
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */\r
+#define QSPI_DLYBCT(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)\r
+\r
+/*------------------------------------------------------------------------------ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+ \r
+typedef enum{\r
+ Device_Read,\r
+ Device_Write\r
+}AccesType;\r
+ \r
+\r
+typedef struct {\r
+ uint8_t Instruction;\r
+ uint8_t InstAddrFlag; \r
+ uint8_t Option;\r
+ uint8_t OptionEn;\r
+ uint8_t OptionLen;\r
+ uint8_t ContinuousRead;\r
+ uint8_t DummyCycles;\r
+ uint8_t spiMode; \r
+ uint32_t DataSize;\r
+ uint32_t InstAddr;\r
+ uint8_t *pData;\r
+}qspiFrame;\r
+\r
+extern volatile uint8_t INSTRE_Flag;\r
+extern void QSPI_Enable( Qspi* qspi ) ;\r
+extern void QSPI_Disable( Qspi* qspi ) ;\r
+extern void QSPI_EnableIt( Qspi* qspi, uint32_t dwSources ) ;\r
+extern void QSPI_DisableIt( Qspi* qspi, uint32_t dwSources ) ;\r
+extern uint32_t QSPI_GetItMask( Qspi* qspi );\r
+\r
+extern void QSPI_Configure( Qspi* qspi, uint32_t dwConfiguration ) ;\r
+void QSPI_ConfigureClock( Qspi* qspi,uint32_t dwConfiguration );\r
+extern void QSPI_SwReset( Qspi* qspi );\r
+\r
+extern void QSPI_ConfigureCs( Qspi* qspi, uint8_t spiCs );\r
+\r
+extern int QSPI_RxEmpty(Qspi *qspi);\r
+extern int QSPI_TxRdy(Qspi *qspi);\r
+\r
+extern uint32_t QSPI_Read( Qspi* qspi ) ;\r
+extern void QSPI_Write( Qspi* qspi, uint16_t wData ) ;\r
+extern void QSPI_WriteLast( Qspi* qspi, uint16_t wData );\r
+\r
+extern uint32_t QSPI_GetStatus( Qspi* qspi ) ;\r
+extern uint32_t QSPI_IsFinished( Qspi* pQspi ) ;\r
+\r
+extern uint32_t QSPI_IsEOFInst( Qspi* qspi );\r
+extern uint32_t QSPI_IsCsRise( Qspi* qspi );\r
+extern uint32_t QSPI_IsCsAsserted( Qspi* qspi );\r
+\r
+extern void QSPI_SendFrame( Qspi* qspi, qspiFrame *pFrame, AccesType ReadWrite);\r
+\r
+extern void QSPI_SendFrameToMem( Qspi* qspi, qspiFrame *pFrame, AccesType ReadWrite );\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _QSPI_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of SPI driver, transfer data through DMA.\r
+ *\r
+ */\r
+\r
+#ifndef _QSPI_DMA_\r
+#define _QSPI_DMA_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** An unspecified error has occured.*/\r
+#define QSPID_ERROR 1\r
+\r
+/** SPI driver is currently in use.*/\r
+#define QSPID_ERROR_LOCK 2\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/\r
+#define QSPID_CSR_SCBR(mck, spck) QSPI_CSR_SCBR((mck) / (spck))\r
+\r
+/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/\r
+#define QSPID_CSR_DLYBS(mck, delay) QSPI_CSR_DLYBS((((delay) * ((mck) / 1000000)) / 1000) + 1)\r
+\r
+/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/\r
+#define QSPID_CSR_DLYBCT(mck, delay) QSPI_CSR_DLYBCT((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** SPI transfer complete callback. */\r
+typedef void (*QspidCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief Qspi Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the SPI_SendCommand function to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct _QspidCmd\r
+{\r
+ /** Pointer to the Tx data. */\r
+ uint8_t *pTxBuff;\r
+ /** Tx size in bytes. */\r
+ uint8_t TxSize;\r
+ /** Pointer to the Rx data. */\r
+ uint8_t *pRxBuff;\r
+ /** Rx size in bytes. */\r
+ uint16_t RxSize;\r
+ /** Callback function invoked at the end of transfer. */\r
+ QspidCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+} QspidCmd ;\r
+\r
+/** Constant structure associated with SPI port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct _Qspid\r
+{\r
+ /** Pointer to SPI Hardware registers */\r
+ Qspi* pQspiHw ;\r
+ /** Current QspiCommand being processed */\r
+ QspidCmd *pCurrentCommand ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad;\r
+ /** SPI Id as defined in the product datasheet */\r
+ uint8_t spiId ;\r
+ /** Mutual exclusion semaphore. */\r
+ volatile int8_t semaphore ;\r
+} Qspid ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t QSPID_Configure( Qspid* pQspid,\r
+ Qspi* pQspiHw,\r
+ uint8_t spiId,\r
+ uint8_t QspiMode,\r
+ sXdmad* pXdmad ) ;\r
+\r
+extern void QSPID_ConfigureCS( Qspid* pQspid, uint32_t dwCS, uint32_t dwCsr ) ;\r
+\r
+extern uint32_t QSPID_SendCommand( Qspid* pQspid, QspidCmd* pCommand ) ;\r
+\r
+extern void QSPID_Handler( Qspid* pQspid ) ;\r
+\r
+extern void QSPID_DmaHandler( Qspid *pQspid );\r
+\r
+extern uint32_t QSPID_IsBusy( const Qspid* pQspid ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _SPI_DMA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _RSTC_H\r
+#define _RSTC_H\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Includes\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+extern void RSTC_ConfigureMode(uint32_t rmr);\r
+\r
+extern void RSTC_SetUserResetEnable(uint8_t enable);\r
+\r
+extern void RSTC_SetUserResetInterruptEnable(uint8_t enable);\r
+\r
+extern void RSTC_SetExtResetLength(uint8_t powl);\r
+\r
+extern void RSTC_ProcessorReset(void);\r
+\r
+extern void RSTC_PeripheralReset(void);\r
+\r
+extern void RSTC_ExtReset(void);\r
+\r
+extern uint8_t RSTC_GetNrstLevel(void);\r
+\r
+extern uint8_t RSTC_IsUserResetDetected(void);\r
+\r
+extern uint8_t RSTC_IsBusy(void);\r
+\r
+extern uint32_t RSTC_GetStatus(void);\r
+\r
+#endif /* #ifndef _RSTC_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Real Time Clock (RTC) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _RTC_\r
+#define _RTC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define RTC_HOUR_BIT_LEN_MASK 0x3F\r
+#define RTC_MIN_BIT_LEN_MASK 0x7F\r
+#define RTC_SEC_BIT_LEN_MASK 0x7F\r
+#define RTC_CENT_BIT_LEN_MASK 0x7F\r
+#define RTC_YEAR_BIT_LEN_MASK 0xFF\r
+#define RTC_MONTH_BIT_LEN_MASK 0x1F\r
+#define RTC_DATE_BIT_LEN_MASK 0x3F\r
+#define RTC_WEEK_BIT_LEN_MASK 0x07\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ;\r
+\r
+extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ;\r
+\r
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ;\r
+\r
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ;\r
+\r
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) ;\r
+\r
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;\r
+\r
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;\r
+\r
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) ;\r
+\r
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) ;\r
+\r
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ;\r
+\r
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ;\r
+\r
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ;\r
+\r
+#if defined(sam3s8) || defined(sam3sd8)\r
+extern void RTC_SetWaveForm( Rtc* pRtc, uint32_t dwWaveMode );\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _RTC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Interface for Real Time Timer (RTT) controller.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Changes the prescaler value of the given RTT and restarts it\r
+ * using \ref RTT_SetPrescaler().\r
+ * -# Get current value of the RTT using \ref RTT_GetTime().\r
+ * -# Enables the specified RTT interrupt using \ref RTT_EnableIT().\r
+ * -# Get the status register value of the given RTT using \ref RTT_GetStatus().\r
+ * -# Configures the RTT to generate an alarm at the given time\r
+ * using \ref RTT_SetAlarm().\r
+ */\r
+\r
+#ifndef _RTT_\r
+#define _RTT_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ;\r
+\r
+extern uint32_t RTT_GetTime( Rtt* pRtt ) ;\r
+\r
+extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ;\r
+\r
+extern uint32_t RTT_GetStatus( Rtt *pRtt ) ;\r
+\r
+extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef RTT_H */\r
+\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ACC_COMPONENT_\r
+#define _SAM_ACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_ACC Analog Comparator Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Acc hardware registers */\r
+typedef struct {\r
+ __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */\r
+ __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[7];\r
+ __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */\r
+ __I uint32_t Reserved2[24];\r
+ __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */\r
+ __I uint32_t Reserved3[19];\r
+ __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t ACC_VER; /**< \brief (Acc Offset: 0xFC) Version Register */\r
+} Acc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */\r
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */\r
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */\r
+#define ACC_MR_SELMINUS_Pos 0\r
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */\r
+#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */\r
+#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */\r
+#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */\r
+#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */\r
+#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_Pos 4\r
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */\r
+#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */\r
+#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */\r
+#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */\r
+#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */\r
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */\r
+#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */\r
+#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */\r
+#define ACC_MR_EDGETYP_Pos 9\r
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */\r
+#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */\r
+#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */\r
+#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */\r
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */\r
+#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */\r
+#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */\r
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */\r
+#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) The CF flag is used to drive the FAULT output. */\r
+#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */\r
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */\r
+#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */\r
+#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */\r
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */\r
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */\r
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */\r
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */\r
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */\r
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */\r
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */\r
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */\r
+#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */\r
+#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */\r
+#define ACC_ACR_HYST_Pos 1\r
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */\r
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))\r
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */\r
+#define ACC_WPMR_WPKEY_Pos 8\r
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */\r
+#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */\r
+/* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */\r
+#define ACC_VER_VERSION_Pos 0\r
+#define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */\r
+#define ACC_VER_MFN_Pos 16\r
+#define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_ACC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AES_COMPONENT_\r
+#define _SAM_AES_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_AES Advanced Encryption Standard */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aes hardware registers */\r
+typedef struct {\r
+ __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */\r
+ __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */\r
+ __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */\r
+ __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */\r
+ __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */\r
+ __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */\r
+ __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */\r
+ __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */\r
+ __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */\r
+ __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */\r
+ __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */\r
+ __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H World Register */\r
+ __I uint32_t Reserved2[20];\r
+ __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */\r
+} Aes;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */\r
+#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */\r
+#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */\r
+/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */\r
+#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */\r
+#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */\r
+#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */\r
+#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */\r
+#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */\r
+#define AES_MR_PROCDLY_Pos 4\r
+#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */\r
+#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))\r
+#define AES_MR_SMOD_Pos 8\r
+#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */\r
+#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */\r
+#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */\r
+#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode */\r
+#define AES_MR_KEYSIZE_Pos 10\r
+#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */\r
+#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */\r
+#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */\r
+#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */\r
+#define AES_MR_OPMOD_Pos 12\r
+#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */\r
+#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */\r
+#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */\r
+#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */\r
+#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */\r
+#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */\r
+#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois Counter mode */\r
+#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */\r
+#define AES_MR_CFBS_Pos 16\r
+#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */\r
+#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */\r
+#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */\r
+#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */\r
+#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */\r
+#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */\r
+#define AES_MR_CKEY_Pos 20\r
+#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */\r
+#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0. */\r
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */\r
+#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */\r
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */\r
+#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */\r
+#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */\r
+#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready */\r
+#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status */\r
+#define AES_ISR_URAT_Pos 12\r
+#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access: */\r
+#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */\r
+#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */\r
+#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */\r
+#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */\r
+#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */\r
+#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */\r
+#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */\r
+/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */\r
+#define AES_KEYWR_KEYW_Pos 0\r
+#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */\r
+#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))\r
+/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */\r
+#define AES_IDATAR_IDATA_Pos 0\r
+#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */\r
+#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))\r
+/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */\r
+#define AES_ODATAR_ODATA_Pos 0\r
+#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */\r
+/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */\r
+#define AES_IVR_IV_Pos 0\r
+#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */\r
+#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))\r
+/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */\r
+#define AES_AADLENR_AADLEN_Pos 0\r
+#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) AAD Length */\r
+#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))\r
+/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */\r
+#define AES_CLENR_CLEN_Pos 0\r
+#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */\r
+#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))\r
+/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */\r
+#define AES_GHASHR_GHASH_Pos 0\r
+#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */\r
+#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))\r
+/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */\r
+#define AES_TAGR_TAG_Pos 0\r
+#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */\r
+/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */\r
+#define AES_CTRR_CTR_Pos 0\r
+#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */\r
+/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H World Register -------- */\r
+#define AES_GCMHR_H_Pos 0\r
+#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H word x */\r
+#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))\r
+/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */\r
+#define AES_VERSION_VERSION_Pos 0\r
+#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */\r
+#define AES_VERSION_MFN_Pos 16\r
+#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_AES_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AFEC_COMPONENT_\r
+#define _SAM_AFEC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-Front-End Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_AFEC Analog-Front-End Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Afec hardware registers */\r
+typedef struct {\r
+ __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */\r
+ __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */\r
+ __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */\r
+ __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */\r
+ __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */\r
+ __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */\r
+ __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */\r
+ __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */\r
+ __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */\r
+ __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */\r
+ __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */\r
+ __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */\r
+ __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */\r
+ __I uint32_t Reserved1[6];\r
+ __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */\r
+ __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */\r
+ __IO uint32_t AFEC_CG1R; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain 1 Register */\r
+ __IO uint32_t AFEC_CG2R; /**< \brief (Afec Offset: 0x58) AFEC Channel Gain 2 Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */\r
+ __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Register Selection */\r
+ __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */\r
+ __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */\r
+ __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */\r
+ __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */\r
+ __I uint32_t Reserved3[7];\r
+ __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */\r
+ __I uint32_t Reserved4[2];\r
+ __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */\r
+ __I uint32_t Reserved5[11];\r
+ __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */\r
+ __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */\r
+ __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */\r
+ __I uint32_t Reserved6[2];\r
+ __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */\r
+ __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */\r
+ __I uint32_t Reserved7[4];\r
+ __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */\r
+} Afec;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */\r
+#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */\r
+#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */\r
+/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */\r
+#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */\r
+#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */\r
+#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */\r
+#define AFEC_MR_TRGSEL_Pos 1\r
+#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) ADC_TRIG0 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) ADC_TRIG1 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) ADC_TRIG2 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) ADC_TRIG3 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) ADC_TRIG4 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) ADC_TRIG5 */\r
+#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) ADC_TRIG6 */\r
+#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */\r
+#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal Mode: The AFEC Core and reference voltage circuitry are kept ON between conversions */\r
+#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode: The AFEC Core and reference voltage circuitry are OFF between conversions */\r
+#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */\r
+#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */\r
+#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF */\r
+#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */\r
+#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal Mode */\r
+#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode: Never wait for any trigger. */\r
+#define AFEC_MR_PRESCAL_Pos 8\r
+#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */\r
+#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))\r
+#define AFEC_MR_STARTUP_Pos 16\r
+#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */\r
+#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFEClock */\r
+#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFEClock */\r
+#define AFEC_MR_ANACH (0x1u << 23) /**< \brief (AFEC_MR) Analog Change */\r
+#define AFEC_MR_ANACH_NONE (0x0u << 23) /**< \brief (AFEC_MR) No analog change on channel switching: DIFF0, GAIN0 are used for all channels */\r
+#define AFEC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (AFEC_MR) Allows different analog settings for each channel. See AFEC_CGR. */\r
+#define AFEC_MR_TRACKTIM_Pos 24\r
+#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */\r
+#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))\r
+#define AFEC_MR_TRANSFER_Pos 28\r
+#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */\r
+#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))\r
+#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) Use Sequence Enable */\r
+#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal Mode: The controller converts channels in a simple numeric order. */\r
+#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Mode: The sequence respects what is defined in AFEC_SEQR1 and AFEC_SEQR2. */\r
+/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */\r
+#define AFEC_EMR_CMPMODE_Pos 0\r
+#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */\r
+#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define AFEC_EMR_CMPSEL_Pos 3\r
+#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */\r
+#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))\r
+#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */\r
+#define AFEC_EMR_CMPFILTER_Pos 12\r
+#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */\r
+#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))\r
+#define AFEC_EMR_RES_Pos 16\r
+#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */\r
+#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFEC sample rate is maximum (no averaging). */\r
+#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFEC sample rate divided by 4 (averaging). */\r
+#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFEC sample rate divided by 16 (averaging). */\r
+#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFEC sample rate divided by 64 (averaging). */\r
+#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFEC sample rate divided by 256 (averaging). */\r
+#define AFEC_EMR_AFEMODE_Pos 20\r
+#define AFEC_EMR_AFEMODE_Msk (0x3u << AFEC_EMR_AFEMODE_Pos) /**< \brief (AFEC_EMR) AFE Running Mode */\r
+#define AFEC_EMR_AFEMODE_NORMAL (0x0u << 20) /**< \brief (AFEC_EMR) Normal mode of operation. */\r
+#define AFEC_EMR_AFEMODE_OFFSET_ERROR (0x1u << 20) /**< \brief (AFEC_EMR) Offset Error mode to measure the offset error. See Table 1-9 on page 35. */\r
+#define AFEC_EMR_AFEMODE_GAIN_ERROR_HIGH (0x2u << 20) /**< \brief (AFEC_EMR) Gain Error mode to measure the gain error. See Table 1-9 on page 35. */\r
+#define AFEC_EMR_AFEMODE_GAIN_ERROR_LOW (0x3u << 20) /**< \brief (AFEC_EMR) */\r
+#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */\r
+#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */\r
+#define AFEC_EMR_SIGNMODE_Pos 28\r
+#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */\r
+#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended Channels: Unsigned conversions.Differential Channels: Signed conversions. */\r
+#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended Channels: Signed conversions.Differential Channels: Unsigned conversions. */\r
+#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All Channels: Unsigned conversions. */\r
+#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All Channels: Signed conversions. */\r
+/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */\r
+#define AFEC_SEQ1R_USCH0_Pos 0\r
+#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */\r
+#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))\r
+#define AFEC_SEQ1R_USCH1_Pos 4\r
+#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */\r
+#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))\r
+#define AFEC_SEQ1R_USCH2_Pos 8\r
+#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */\r
+#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))\r
+#define AFEC_SEQ1R_USCH3_Pos 12\r
+#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */\r
+#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))\r
+#define AFEC_SEQ1R_USCH4_Pos 16\r
+#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */\r
+#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))\r
+#define AFEC_SEQ1R_USCH5_Pos 20\r
+#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */\r
+#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))\r
+#define AFEC_SEQ1R_USCH6_Pos 24\r
+#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */\r
+#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))\r
+#define AFEC_SEQ1R_USCH7_Pos 28\r
+#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */\r
+#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))\r
+/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */\r
+#define AFEC_SEQ2R_USCH8_Pos 0\r
+#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */\r
+#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))\r
+#define AFEC_SEQ2R_USCH9_Pos 4\r
+#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */\r
+#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))\r
+#define AFEC_SEQ2R_USCH10_Pos 8\r
+#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */\r
+#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))\r
+#define AFEC_SEQ2R_USCH11_Pos 12\r
+#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */\r
+#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))\r
+#define AFEC_SEQ2R_USCH12_Pos 16\r
+#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */\r
+#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))\r
+#define AFEC_SEQ2R_USCH13_Pos 20\r
+#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */\r
+#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))\r
+#define AFEC_SEQ2R_USCH14_Pos 24\r
+#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */\r
+#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))\r
+#define AFEC_SEQ2R_USCH15_Pos 28\r
+#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */\r
+#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))\r
+/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */\r
+#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */\r
+#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */\r
+#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */\r
+#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */\r
+#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */\r
+#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */\r
+#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */\r
+#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */\r
+#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */\r
+#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */\r
+#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */\r
+#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */\r
+/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */\r
+#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */\r
+#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */\r
+#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */\r
+#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */\r
+#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */\r
+#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */\r
+#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */\r
+#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */\r
+#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */\r
+#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */\r
+#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */\r
+#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */\r
+/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */\r
+#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */\r
+#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */\r
+#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */\r
+#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */\r
+#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */\r
+#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */\r
+#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */\r
+#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */\r
+#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */\r
+#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */\r
+#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */\r
+#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */\r
+/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */\r
+#define AFEC_LCDR_LDATA_Pos 0\r
+#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */\r
+#define AFEC_LCDR_CHNB_Pos 24\r
+#define AFEC_LCDR_CHNB_Msk (0x1fu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */\r
+/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */\r
+#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */\r
+#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */\r
+#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */\r
+#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */\r
+#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */\r
+#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */\r
+#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */\r
+#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */\r
+#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */\r
+#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */\r
+#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */\r
+#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */\r
+#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */\r
+#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */\r
+#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */\r
+#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */\r
+/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */\r
+#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */\r
+#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */\r
+#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */\r
+#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */\r
+/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */\r
+#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */\r
+#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */\r
+#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */\r
+#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */\r
+/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */\r
+#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 */\r
+#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 */\r
+#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 */\r
+#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 */\r
+#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 */\r
+#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 */\r
+#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 */\r
+#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 */\r
+#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 */\r
+#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 */\r
+#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 */\r
+#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 */\r
+#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready */\r
+#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error */\r
+#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error */\r
+#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change */\r
+/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */\r
+#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */\r
+#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */\r
+#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */\r
+#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */\r
+#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */\r
+#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */\r
+#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */\r
+#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */\r
+#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */\r
+#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */\r
+#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */\r
+#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */\r
+/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */\r
+#define AFEC_CWR_LOWTHRES_Pos 0\r
+#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */\r
+#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))\r
+#define AFEC_CWR_HIGHTHRES_Pos 16\r
+#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */\r
+#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))\r
+/* -------- AFEC_CG1R : (AFEC Offset: 0x54) AFEC Channel Gain 1 Register -------- */\r
+#define AFEC_CG1R_GAIN0_Pos 0\r
+#define AFEC_CG1R_GAIN0_Msk (0x3u << AFEC_CG1R_GAIN0_Pos) /**< \brief (AFEC_CG1R) Gain for channel 0 */\r
+#define AFEC_CG1R_GAIN0(value) ((AFEC_CG1R_GAIN0_Msk & ((value) << AFEC_CG1R_GAIN0_Pos)))\r
+#define AFEC_CG1R_GAIN1_Pos 2\r
+#define AFEC_CG1R_GAIN1_Msk (0x3u << AFEC_CG1R_GAIN1_Pos) /**< \brief (AFEC_CG1R) Gain for channel 1 */\r
+#define AFEC_CG1R_GAIN1(value) ((AFEC_CG1R_GAIN1_Msk & ((value) << AFEC_CG1R_GAIN1_Pos)))\r
+#define AFEC_CG1R_GAIN2_Pos 4\r
+#define AFEC_CG1R_GAIN2_Msk (0x3u << AFEC_CG1R_GAIN2_Pos) /**< \brief (AFEC_CG1R) Gain for channel 2 */\r
+#define AFEC_CG1R_GAIN2(value) ((AFEC_CG1R_GAIN2_Msk & ((value) << AFEC_CG1R_GAIN2_Pos)))\r
+#define AFEC_CG1R_GAIN3_Pos 6\r
+#define AFEC_CG1R_GAIN3_Msk (0x3u << AFEC_CG1R_GAIN3_Pos) /**< \brief (AFEC_CG1R) Gain for channel 3 */\r
+#define AFEC_CG1R_GAIN3(value) ((AFEC_CG1R_GAIN3_Msk & ((value) << AFEC_CG1R_GAIN3_Pos)))\r
+#define AFEC_CG1R_GAIN4_Pos 8\r
+#define AFEC_CG1R_GAIN4_Msk (0x3u << AFEC_CG1R_GAIN4_Pos) /**< \brief (AFEC_CG1R) Gain for channel 4 */\r
+#define AFEC_CG1R_GAIN4(value) ((AFEC_CG1R_GAIN4_Msk & ((value) << AFEC_CG1R_GAIN4_Pos)))\r
+#define AFEC_CG1R_GAIN5_Pos 10\r
+#define AFEC_CG1R_GAIN5_Msk (0x3u << AFEC_CG1R_GAIN5_Pos) /**< \brief (AFEC_CG1R) Gain for channel 5 */\r
+#define AFEC_CG1R_GAIN5(value) ((AFEC_CG1R_GAIN5_Msk & ((value) << AFEC_CG1R_GAIN5_Pos)))\r
+#define AFEC_CG1R_GAIN6_Pos 12\r
+#define AFEC_CG1R_GAIN6_Msk (0x3u << AFEC_CG1R_GAIN6_Pos) /**< \brief (AFEC_CG1R) Gain for channel 6 */\r
+#define AFEC_CG1R_GAIN6(value) ((AFEC_CG1R_GAIN6_Msk & ((value) << AFEC_CG1R_GAIN6_Pos)))\r
+#define AFEC_CG1R_GAIN7_Pos 14\r
+#define AFEC_CG1R_GAIN7_Msk (0x3u << AFEC_CG1R_GAIN7_Pos) /**< \brief (AFEC_CG1R) Gain for channel 7 */\r
+#define AFEC_CG1R_GAIN7(value) ((AFEC_CG1R_GAIN7_Msk & ((value) << AFEC_CG1R_GAIN7_Pos)))\r
+#define AFEC_CG1R_GAIN8_Pos 16\r
+#define AFEC_CG1R_GAIN8_Msk (0x3u << AFEC_CG1R_GAIN8_Pos) /**< \brief (AFEC_CG1R) Gain for channel 8 */\r
+#define AFEC_CG1R_GAIN8(value) ((AFEC_CG1R_GAIN8_Msk & ((value) << AFEC_CG1R_GAIN8_Pos)))\r
+#define AFEC_CG1R_GAIN9_Pos 18\r
+#define AFEC_CG1R_GAIN9_Msk (0x3u << AFEC_CG1R_GAIN9_Pos) /**< \brief (AFEC_CG1R) Gain for channel 9 */\r
+#define AFEC_CG1R_GAIN9(value) ((AFEC_CG1R_GAIN9_Msk & ((value) << AFEC_CG1R_GAIN9_Pos)))\r
+#define AFEC_CG1R_GAIN10_Pos 20\r
+#define AFEC_CG1R_GAIN10_Msk (0x3u << AFEC_CG1R_GAIN10_Pos) /**< \brief (AFEC_CG1R) Gain for channel 10 */\r
+#define AFEC_CG1R_GAIN10(value) ((AFEC_CG1R_GAIN10_Msk & ((value) << AFEC_CG1R_GAIN10_Pos)))\r
+#define AFEC_CG1R_GAIN11_Pos 22\r
+#define AFEC_CG1R_GAIN11_Msk (0x3u << AFEC_CG1R_GAIN11_Pos) /**< \brief (AFEC_CG1R) Gain for channel 11 */\r
+#define AFEC_CG1R_GAIN11(value) ((AFEC_CG1R_GAIN11_Msk & ((value) << AFEC_CG1R_GAIN11_Pos)))\r
+/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */\r
+#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */\r
+#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */\r
+#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */\r
+#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */\r
+#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */\r
+#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */\r
+#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */\r
+#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */\r
+#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */\r
+#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */\r
+#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */\r
+#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */\r
+/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Register Selection -------- */\r
+#define AFEC_CSELR_CSEL_Pos 0\r
+#define AFEC_CSELR_CSEL_Msk (0x1fu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */\r
+#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))\r
+/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */\r
+#define AFEC_CDR_DATA_Pos 0\r
+#define AFEC_CDR_DATA_Msk (0xfffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */\r
+/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */\r
+#define AFEC_COCR_AOFF_Pos 0\r
+#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */\r
+#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))\r
+/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */\r
+#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger mode */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4\r
+#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */\r
+#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */\r
+/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */\r
+#define AFEC_TEMPCWR_TLOWTHRES_Pos 0\r
+#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */\r
+#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))\r
+#define AFEC_TEMPCWR_THIGHTHRES_Pos 16\r
+#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */\r
+#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))\r
+/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */\r
+#define AFEC_ACR_IBCTL_Pos 8\r
+#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFEC Bias Current Control */\r
+#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))\r
+/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */\r
+#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */\r
+#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */\r
+#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */\r
+#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */\r
+#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */\r
+#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */\r
+#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */\r
+#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */\r
+#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */\r
+#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */\r
+#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */\r
+#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */\r
+/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */\r
+#define AFEC_COSR_CSEL_Pos 0\r
+#define AFEC_COSR_CSEL_Msk (0x1fu << AFEC_COSR_CSEL_Pos) /**< \brief (AFEC_COSR) 2 Correction Select */\r
+#define AFEC_COSR_CSEL(value) ((AFEC_COSR_CSEL_Msk & ((value) << AFEC_COSR_CSEL_Pos)))\r
+/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */\r
+#define AFEC_CVR_OFFSETCORR_Pos 0\r
+#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */\r
+#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))\r
+#define AFEC_CVR_GAINCORR_Pos 16\r
+#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */\r
+#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))\r
+/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */\r
+#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */\r
+#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */\r
+#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */\r
+#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */\r
+#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */\r
+#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */\r
+#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */\r
+#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */\r
+#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */\r
+#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */\r
+#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */\r
+#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */\r
+/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */\r
+#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */\r
+#define AFEC_WPMR_WPKEY_Pos 8\r
+#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */\r
+#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */\r
+#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */\r
+#define AFEC_WPSR_WPVSRC_Pos 8\r
+#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */\r
+/* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */\r
+#define AFEC_VERSION_VERSION_Pos 0\r
+#define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */\r
+#define AFEC_VERSION_MFN_Pos 16\r
+#define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_AFEC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_CHIPID_COMPONENT_\r
+#define _SAM_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */\r
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */\r
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */\r
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM4SH2 (0x45u << 20) /**< \brief (CHIPID_CIDR) AT91SAM4SH2 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */\r
+#define CHIPID_CIDR_ARCH_SAM4CxxC (0x64u << 20) /**< \brief (CHIPID_CIDR) SAM4CxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4CxxE (0x66u << 20) /**< \brief (CHIPID_CIDR) SAM4CxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */\r
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */\r
+#define CHIPID_CIDR_ARCH_SAM4LxA (0xB0u << 20) /**< \brief (CHIPID_CIDR) SAM4LxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4LxB (0xB1u << 20) /**< \brief (CHIPID_CIDR) SAM4LxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4LxC (0xB2u << 20) /**< \brief (CHIPID_CIDR) SAM4LxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_CHIPID_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_DACC_COMPONENT_\r
+#define _SAM_DACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_DACC Digital-to-Analog Converter Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Dacc hardware registers */\r
+typedef struct {\r
+ __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */\r
+ __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */\r
+ __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */\r
+ __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */\r
+ __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */\r
+ __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */\r
+ __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */\r
+ __I uint32_t Reserved2[24];\r
+ __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */\r
+ __I uint32_t Reserved3[19];\r
+ __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */\r
+ __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */\r
+} Dacc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */\r
+#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */\r
+#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */\r
+#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */\r
+#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */\r
+#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */\r
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */\r
+#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */\r
+#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */\r
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */\r
+#define DACC_MR_SLEEP_DISABLED (0x0u << 5) /**< \brief (DACC_MR) The DAC Core and reference voltage circuitry are kept ON between conversions.For the first conversion, a startup time defined by the analog cell is applied. Note that in this mode, STARTUP time is only required once, at start up. */\r
+#define DACC_MR_SLEEP_ENABLED (0x1u << 5) /**< \brief (DACC_MR) The DAC Core and reference voltage circuitry are OFF between conversions. */\r
+#define DACC_MR_REFRESH_Pos 8\r
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */\r
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))\r
+#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */\r
+#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */\r
+#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */\r
+#define DACC_MR_PRESCALER_Pos 24\r
+#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */\r
+#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))\r
+/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */\r
+#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */\r
+#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */\r
+#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */\r
+#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */\r
+#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */\r
+#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */\r
+#define DACC_TRIGR_TRGSEL0_Pos 4\r
+#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_Pos 8\r
+#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */\r
+#define DACC_TRIGR_OSR0_Pos 16\r
+#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */\r
+#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */\r
+#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */\r
+#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */\r
+#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */\r
+#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */\r
+#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */\r
+#define DACC_TRIGR_OSR1_Pos 20\r
+#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */\r
+#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */\r
+#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */\r
+#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */\r
+#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */\r
+#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */\r
+#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */\r
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */\r
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */\r
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */\r
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */\r
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */\r
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */\r
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */\r
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */\r
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */\r
+#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */\r
+#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */\r
+/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA0_Pos 0\r
+#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */\r
+#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))\r
+#define DACC_CDR_DATA1_Pos 16\r
+#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */\r
+#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */\r
+#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */\r
+#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */\r
+#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */\r
+#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */\r
+#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */\r
+#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */\r
+#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */\r
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */\r
+#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */\r
+#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */\r
+#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */\r
+#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */\r
+#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */\r
+#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */\r
+#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */\r
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */\r
+#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */\r
+#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */\r
+#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */\r
+#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */\r
+#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */\r
+#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */\r
+#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */\r
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */\r
+#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */\r
+#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */\r
+#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */\r
+#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */\r
+#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */\r
+#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */\r
+#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */\r
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */\r
+#define DACC_ACR_IBCTLCH0_Pos 0\r
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))\r
+#define DACC_ACR_IBCTLCH1_Pos 2\r
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */\r
+#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */\r
+#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */\r
+#define DACC_WPSR_WPVSRC_Pos 8\r
+#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_DACC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_EFC_COMPONENT_\r
+#define _SAM_EFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_EFC Embedded Flash Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Efc hardware registers */\r
+typedef struct {\r
+ __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */\r
+ __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */\r
+ __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */\r
+ __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */\r
+ __I uint32_t Reserved1[1];\r
+ __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */\r
+} Efc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */\r
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */\r
+#define EEFC_FMR_FWS_Pos 8\r
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */\r
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))\r
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */\r
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */\r
+#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */\r
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */\r
+#define EEFC_FCR_FCMD_Pos 0\r
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */\r
+#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */\r
+#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */\r
+#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */\r
+#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */\r
+#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */\r
+#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */\r
+#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */\r
+#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */\r
+#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */\r
+#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */\r
+#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */\r
+#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */\r
+#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */\r
+#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */\r
+#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */\r
+#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */\r
+#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */\r
+#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */\r
+#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */\r
+#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */\r
+#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */\r
+#define EEFC_FCR_FARG_Pos 8\r
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */\r
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))\r
+#define EEFC_FCR_FKEY_Pos 24\r
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */\r
+#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */\r
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */\r
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */\r
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */\r
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */\r
+#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */\r
+#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus */\r
+#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus */\r
+#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus */\r
+#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus */\r
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */\r
+#define EEFC_FRR_FVALUE_Pos 0\r
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */\r
+/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */\r
+#define EEFC_VERSION_VERSION_Pos 0\r
+#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */\r
+#define EEFC_VERSION_MFN_Pos 16\r
+#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_EFC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_GMAC_COMPONENT_\r
+#define _SAM_GMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_GMAC Gigabit Ethernet MAC */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief GmacSa hardware registers */\r
+typedef struct {\r
+ __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */\r
+ __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */\r
+} GmacSa;\r
+/** \brief Gmac hardware registers */\r
+#define GMACSA_NUMBER 4\r
+typedef struct {\r
+ __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */\r
+ __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */\r
+ __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */\r
+ __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */\r
+ __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */\r
+ __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */\r
+ __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */\r
+ __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */\r
+ __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */\r
+ __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */\r
+ __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */\r
+ __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */\r
+ __I uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */\r
+ __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */\r
+ __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */\r
+ __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */\r
+ __I uint32_t Reserved1[16];\r
+ __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */\r
+ __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */\r
+ GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */\r
+ __IO uint32_t GMAC_TIDM[4]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */\r
+ __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */\r
+ __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */\r
+ __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */\r
+ __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */\r
+ __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */\r
+ __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */\r
+ __I uint32_t Reserved2[11];\r
+ __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */\r
+ __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */\r
+ __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */\r
+ __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */\r
+ __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */\r
+ __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */\r
+ __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */\r
+ __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */\r
+ __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */\r
+ __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */\r
+ __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */\r
+ __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */\r
+ __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */\r
+ __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */\r
+ __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */\r
+ __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */\r
+ __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */\r
+ __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */\r
+ __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */\r
+ __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */\r
+ __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */\r
+ __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */\r
+ __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */\r
+ __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */\r
+ __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */\r
+ __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */\r
+ __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */\r
+ __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */\r
+ __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */\r
+ __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */\r
+ __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */\r
+ __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */\r
+ __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */\r
+ __I uint32_t Reserved3[5];\r
+ __IO uint32_t GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */\r
+ __IO uint32_t GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+ __IO uint32_t GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */\r
+ __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */\r
+ __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */\r
+ __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */\r
+ __I uint32_t GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */\r
+ __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */\r
+ __I uint32_t GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */\r
+ __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */\r
+ __I uint32_t GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */\r
+ __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */\r
+ __I uint32_t GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */\r
+ __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */\r
+ __I uint32_t Reserved4[128];\r
+ __I uint32_t GMAC_ISRPQ[7]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue */\r
+ __I uint32_t Reserved5[9];\r
+ __IO uint32_t GMAC_TBQBAPQ[7]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue */\r
+ __I uint32_t Reserved6[9];\r
+ __IO uint32_t GMAC_RBQBAPQ[7]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Priority Queue */\r
+ __I uint32_t Reserved7[1];\r
+ __IO uint32_t GMAC_RBSRPQ[7]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue */\r
+ __I uint32_t Reserved8[17];\r
+ __IO uint32_t GMAC_ST1RPQ[16]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue */\r
+ __IO uint32_t GMAC_ST2RPQ[16]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue */\r
+ __I uint32_t Reserved9[32];\r
+ __O uint32_t GMAC_IERPQ[7]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue */\r
+ __I uint32_t Reserved10[1];\r
+ __O uint32_t GMAC_IDRPQ[7]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue */\r
+ __I uint32_t Reserved11[1];\r
+ __IO uint32_t GMAC_IMRPQ[7]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue */\r
+} Gmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */\r
+#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */\r
+#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */\r
+#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */\r
+#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */\r
+#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */\r
+#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */\r
+#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */\r
+#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */\r
+#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */\r
+#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */\r
+#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */\r
+#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */\r
+#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */\r
+#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */\r
+#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */\r
+#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */\r
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */\r
+#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */\r
+#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */\r
+#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */\r
+#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */\r
+#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */\r
+#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */\r
+#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */\r
+#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */\r
+#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */\r
+#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */\r
+#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */\r
+#define GMAC_NCFGR_RXBUFO_Pos 14\r
+#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */\r
+#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))\r
+#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */\r
+#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */\r
+#define GMAC_NCFGR_CLK_Pos 18\r
+#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */\r
+#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */\r
+#define GMAC_NCFGR_DBW_Pos 21\r
+#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */\r
+#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))\r
+#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */\r
+#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */\r
+#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */\r
+#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */\r
+#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */\r
+#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */\r
+#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */\r
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */\r
+#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */\r
+#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */\r
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */\r
+#define GMAC_UR_RMIIMII (0x1u << 0) /**< \brief (GMAC_UR) */\r
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */\r
+#define GMAC_DCFGR_FBLDO_Pos 0\r
+#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */\r
+#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */\r
+#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */\r
+#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */\r
+#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */\r
+#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */\r
+#define GMAC_DCFGR_DRBS_Pos 16\r
+#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */\r
+#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))\r
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */\r
+#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */\r
+#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */\r
+#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */\r
+#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */\r
+#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */\r
+#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */\r
+#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */\r
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */\r
+#define GMAC_RBQB_ADDR_Pos 2\r
+#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */\r
+#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))\r
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */\r
+#define GMAC_TBQB_ADDR_Pos 2\r
+#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */\r
+#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))\r
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */\r
+#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */\r
+#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */\r
+#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */\r
+#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */\r
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */\r
+#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */\r
+#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */\r
+#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */\r
+#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */\r
+#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */\r
+#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */\r
+#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */\r
+#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */\r
+#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */\r
+#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */\r
+#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */\r
+#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */\r
+#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */\r
+#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */\r
+#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */\r
+#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */\r
+#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */\r
+#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */\r
+#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */\r
+#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */\r
+/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */\r
+#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */\r
+#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */\r
+#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */\r
+#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */\r
+#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */\r
+#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */\r
+#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */\r
+#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */\r
+#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */\r
+#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */\r
+#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */\r
+#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */\r
+#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */\r
+#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */\r
+#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */\r
+#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */\r
+#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */\r
+#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */\r
+#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */\r
+#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */\r
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */\r
+#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */\r
+#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */\r
+#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */\r
+#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */\r
+#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */\r
+#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */\r
+#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */\r
+#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */\r
+#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */\r
+#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */\r
+#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */\r
+#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */\r
+#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */\r
+#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */\r
+#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */\r
+#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */\r
+#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */\r
+#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */\r
+#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */\r
+#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */\r
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */\r
+#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */\r
+#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */\r
+#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */\r
+#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */\r
+#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */\r
+#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */\r
+#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */\r
+#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */\r
+#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */\r
+#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */\r
+#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */\r
+#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */\r
+#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */\r
+#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */\r
+#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */\r
+#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */\r
+#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */\r
+#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */\r
+#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */\r
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */\r
+#define GMAC_MAN_DATA_Pos 0\r
+#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */\r
+#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))\r
+#define GMAC_MAN_WTN_Pos 16\r
+#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */\r
+#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))\r
+#define GMAC_MAN_REGA_Pos 18\r
+#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */\r
+#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))\r
+#define GMAC_MAN_PHYA_Pos 23\r
+#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */\r
+#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))\r
+#define GMAC_MAN_OP_Pos 28\r
+#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */\r
+#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))\r
+#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */\r
+#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */\r
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */\r
+#define GMAC_RPQ_RPQ_Pos 0\r
+#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */\r
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */\r
+#define GMAC_TPQ_TPQ_Pos 0\r
+#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */\r
+#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))\r
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */\r
+#define GMAC_HRB_ADDR_Pos 0\r
+#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */\r
+#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))\r
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */\r
+#define GMAC_HRT_ADDR_Pos 0\r
+#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */\r
+#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))\r
+/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB1_ADDR_Pos 0\r
+#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */\r
+#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos)))\r
+/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */\r
+#define GMAC_SAT1_ADDR_Pos 0\r
+#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */\r
+#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos)))\r
+/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB2_ADDR_Pos 0\r
+#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */\r
+#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos)))\r
+/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */\r
+#define GMAC_SAT2_ADDR_Pos 0\r
+#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */\r
+#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos)))\r
+/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB3_ADDR_Pos 0\r
+#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */\r
+#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos)))\r
+/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */\r
+#define GMAC_SAT3_ADDR_Pos 0\r
+#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */\r
+#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos)))\r
+/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */\r
+#define GMAC_SAB4_ADDR_Pos 0\r
+#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */\r
+#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos)))\r
+/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */\r
+#define GMAC_SAT4_ADDR_Pos 0\r
+#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */\r
+#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos)))\r
+/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */\r
+#define GMAC_TIDM_TID_Pos 0\r
+#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */\r
+#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos)))\r
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */\r
+#define GMAC_WOL_IP_Pos 0\r
+#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */\r
+#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))\r
+#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */\r
+#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */\r
+#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */\r
+#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */\r
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */\r
+#define GMAC_IPGS_FL_Pos 0\r
+#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */\r
+#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))\r
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */\r
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0\r
+#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */\r
+#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))\r
+#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */\r
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */\r
+#define GMAC_TPFCP_PEV_Pos 0\r
+#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */\r
+#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))\r
+#define GMAC_TPFCP_PQ_Pos 8\r
+#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */\r
+#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))\r
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */\r
+#define GMAC_SAMB1_ADDR_Pos 0\r
+#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */\r
+#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))\r
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */\r
+#define GMAC_SAMT1_ADDR_Pos 0\r
+#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */\r
+#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))\r
+/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */\r
+#define GMAC_MID_MREV_Pos 0\r
+#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */\r
+#define GMAC_MID_MID_Pos 16\r
+#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */\r
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */\r
+#define GMAC_OTLO_TXO_Pos 0\r
+#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */\r
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */\r
+#define GMAC_OTHI_TXO_Pos 0\r
+#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */\r
+/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */\r
+#define GMAC_FT_FTX_Pos 0\r
+#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */\r
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */\r
+#define GMAC_BCFT_BFTX_Pos 0\r
+#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */\r
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */\r
+#define GMAC_MFT_MFTX_Pos 0\r
+#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */\r
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */\r
+#define GMAC_PFT_PFTX_Pos 0\r
+#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */\r
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */\r
+#define GMAC_BFT64_NFTX_Pos 0\r
+#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT127_NFTX_Pos 0\r
+#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT255_NFTX_Pos 0\r
+#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT511_NFTX_Pos 0\r
+#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1023_NFTX_Pos 0\r
+#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1518_NFTX_Pos 0\r
+#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_GTBFT1518_NFTX_Pos 0\r
+#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */\r
+#define GMAC_TUR_TXUNR_Pos 0\r
+#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */\r
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */\r
+#define GMAC_SCF_SCOL_Pos 0\r
+#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */\r
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */\r
+#define GMAC_MCF_MCOL_Pos 0\r
+#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */\r
+/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */\r
+#define GMAC_EC_XCOL_Pos 0\r
+#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */\r
+/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */\r
+#define GMAC_LC_LCOL_Pos 0\r
+#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */\r
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */\r
+#define GMAC_DTF_DEFT_Pos 0\r
+#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */\r
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */\r
+#define GMAC_CSE_CSR_Pos 0\r
+#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */\r
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */\r
+#define GMAC_ORLO_RXO_Pos 0\r
+#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */\r
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */\r
+#define GMAC_ORHI_RXO_Pos 0\r
+#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */\r
+/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */\r
+#define GMAC_FR_FRX_Pos 0\r
+#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */\r
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */\r
+#define GMAC_BCFR_BFRX_Pos 0\r
+#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */\r
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */\r
+#define GMAC_MFR_MFRX_Pos 0\r
+#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */\r
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */\r
+#define GMAC_PFR_PFRX_Pos 0\r
+#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */\r
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */\r
+#define GMAC_BFR64_NFRX_Pos 0\r
+#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR127_NFRX_Pos 0\r
+#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR255_NFRX_Pos 0\r
+#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */\r
+#define GMAC_TBFR511_NFRX_Pos 0\r
+#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1023_NFRX_Pos 0\r
+#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1518_NFRX_Pos 0\r
+#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */\r
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */\r
+#define GMAC_TMXBFR_NFRX_Pos 0\r
+#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */\r
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */\r
+#define GMAC_UFR_UFRX_Pos 0\r
+#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */\r
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */\r
+#define GMAC_OFR_OFRX_Pos 0\r
+#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */\r
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */\r
+#define GMAC_JR_JRX_Pos 0\r
+#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */\r
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */\r
+#define GMAC_FCSE_FCKR_Pos 0\r
+#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */\r
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */\r
+#define GMAC_LFFE_LFER_Pos 0\r
+#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */\r
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */\r
+#define GMAC_RSE_RXSE_Pos 0\r
+#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */\r
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */\r
+#define GMAC_AE_AER_Pos 0\r
+#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */\r
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */\r
+#define GMAC_RRE_RXRER_Pos 0\r
+#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */\r
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */\r
+#define GMAC_ROE_RXOVR_Pos 0\r
+#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */\r
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */\r
+#define GMAC_IHCE_HCKER_Pos 0\r
+#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */\r
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */\r
+#define GMAC_TCE_TCKER_Pos 0\r
+#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */\r
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */\r
+#define GMAC_UCE_UCKER_Pos 0\r
+#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */\r
+/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */\r
+#define GMAC_TSSS_VTS_Pos 0\r
+#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */\r
+#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos)))\r
+/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */\r
+#define GMAC_TSSN_VTN_Pos 0\r
+#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */\r
+#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos)))\r
+/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */\r
+#define GMAC_TS_TCS_Pos 0\r
+#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */\r
+#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos)))\r
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */\r
+#define GMAC_TN_TNS_Pos 0\r
+#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */\r
+#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))\r
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */\r
+#define GMAC_TA_ITDT_Pos 0\r
+#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */\r
+#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))\r
+#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */\r
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */\r
+#define GMAC_TI_CNS_Pos 0\r
+#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */\r
+#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))\r
+#define GMAC_TI_ACNS_Pos 8\r
+#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */\r
+#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))\r
+#define GMAC_TI_NIT_Pos 16\r
+#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */\r
+#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))\r
+/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */\r
+#define GMAC_EFTS_RUD_Pos 0\r
+#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */\r
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */\r
+#define GMAC_EFTN_RUD_Pos 0\r
+#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */\r
+/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */\r
+#define GMAC_EFRS_RUD_Pos 0\r
+#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */\r
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */\r
+#define GMAC_EFRN_RUD_Pos 0\r
+#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */\r
+/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */\r
+#define GMAC_PEFTS_RUD_Pos 0\r
+#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */\r
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */\r
+#define GMAC_PEFTN_RUD_Pos 0\r
+#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */\r
+/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */\r
+#define GMAC_PEFRS_RUD_Pos 0\r
+#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */\r
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */\r
+#define GMAC_PEFRN_RUD_Pos 0\r
+#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */\r
+/* -------- GMAC_ISRPQ[7] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue -------- */\r
+#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[7]) Receive Complete */\r
+#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[7]) RX Used Bit Read */\r
+#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[7]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[7]) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[7]) Transmit Complete */\r
+#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[7]) Receive Overrun */\r
+#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[7]) HRESP Not OK */\r
+/* -------- GMAC_TBQBAPQ[7] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue -------- */\r
+#define GMAC_TBQBAPQ_TXBQBA_Pos 2\r
+#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[7]) Transmit Buffer Queue Base Address */\r
+#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))\r
+/* -------- GMAC_RBQBAPQ[7] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Priority Queue -------- */\r
+#define GMAC_RBQBAPQ_RXBQBA_Pos 2\r
+#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[7]) Receive Buffer Queue Base Address */\r
+#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))\r
+/* -------- GMAC_RBSRPQ[7] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue -------- */\r
+#define GMAC_RBSRPQ_RBS_Pos 0\r
+#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[7]) Receive Buffer Size */\r
+#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))\r
+/* -------- GMAC_ST1RPQ[16] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue -------- */\r
+#define GMAC_ST1RPQ_QNB_Pos 0\r
+#define GMAC_ST1RPQ_QNB_Msk (0xfu << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[16]) Que Number (0->7) */\r
+#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))\r
+#define GMAC_ST1RPQ_DSTCM_Pos 4\r
+#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match */\r
+#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))\r
+#define GMAC_ST1RPQ_UDPM_Pos 12\r
+#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match */\r
+#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))\r
+#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match Enable */\r
+#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match Enable */\r
+/* -------- GMAC_ST2RPQ[16] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue -------- */\r
+#define GMAC_ST2RPQ_QNB_Pos 0\r
+#define GMAC_ST2RPQ_QNB_Msk (0xfu << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[16]) Que Number (0->7) */\r
+#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))\r
+#define GMAC_ST2RPQ_VLANP_Pos 4\r
+#define GMAC_ST2RPQ_VLANP_Msk (0xfu << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[16]) VLAN Priority */\r
+#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))\r
+#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[16]) VLAN Enable */\r
+/* -------- GMAC_IERPQ[7] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue -------- */\r
+#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[7]) Receive Complete */\r
+#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[7]) RX Used Bit Read */\r
+#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[7]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[7]) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[7]) Transmit Complete */\r
+#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[7]) Receive Overrun */\r
+#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[7]) HRESP Not OK */\r
+/* -------- GMAC_IDRPQ[7] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue -------- */\r
+#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[7]) Receive Complete */\r
+#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[7]) RX Used Bit Read */\r
+#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[7]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[7]) Transmit Frame Corruption due to AHB error */\r
+#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[7]) Transmit Complete */\r
+#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[7]) Receive Overrun */\r
+#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[7]) HRESP Not OK */\r
+/* -------- GMAC_IMRPQ[7] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue -------- */\r
+#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[7]) Receive Complete */\r
+#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[7]) RX Used Bit Read */\r
+#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[7]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[7]) AHB Error */\r
+#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[7]) Transmit Complete */\r
+#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[7]) Receive Overrun */\r
+#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[7]) HRESP Not OK */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_GMAC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_GPBR_COMPONENT_\r
+#define _SAM_GPBR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_GPBR General Purpose Backup Registers */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Gpbr hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */\r
+} Gpbr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */\r
+#define SYS_GPBR_GPBR_VALUE_Pos 0\r
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */\r
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_GPBR_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_HSMCI_COMPONENT_\r
+#define _SAM_HSMCI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_HSMCI High Speed MultiMedia Card Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Hsmci hardware registers */\r
+typedef struct {\r
+ __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */\r
+ __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */\r
+ __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */\r
+ __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */\r
+ __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */\r
+ __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */\r
+ __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */\r
+ __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */\r
+ __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */\r
+ __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */\r
+ __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */\r
+ __I uint32_t Reserved1[2];\r
+ __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */\r
+ __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */\r
+ __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */\r
+ __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */\r
+ __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */\r
+ __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */\r
+ __I uint32_t Reserved2[35];\r
+ __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved3[4];\r
+ __I uint32_t HSMCI_VERSION; /**< \brief (Hsmci Offset: 0xFC) Version Register */\r
+ __I uint32_t Reserved4[64];\r
+ __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */\r
+} Hsmci;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */\r
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */\r
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */\r
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */\r
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */\r
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */\r
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */\r
+#define HSMCI_MR_CLKDIV_Pos 0\r
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */\r
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))\r
+#define HSMCI_MR_PWSDIV_Pos 8\r
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */\r
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))\r
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */\r
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */\r
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */\r
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */\r
+#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */\r
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */\r
+#define HSMCI_DTOR_DTOCYC_Pos 0\r
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */\r
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))\r
+#define HSMCI_DTOR_DTOMUL_Pos 4\r
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */\r
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */\r
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */\r
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */\r
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */\r
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */\r
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */\r
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */\r
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */\r
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */\r
+#define HSMCI_SDCR_SDCSEL_Pos 0\r
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */\r
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */\r
+#define HSMCI_SDCR_SDCBUS_Pos 6\r
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */\r
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */\r
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */\r
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */\r
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */\r
+#define HSMCI_ARGR_ARG_Pos 0\r
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */\r
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))\r
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */\r
+#define HSMCI_CMDR_CMDNB_Pos 0\r
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */\r
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))\r
+#define HSMCI_CMDR_RSPTYP_Pos 6\r
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */\r
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */\r
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */\r
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */\r
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */\r
+#define HSMCI_CMDR_SPCMD_Pos 8\r
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */\r
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */\r
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */\r
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */\r
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */\r
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */\r
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */\r
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */\r
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */\r
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */\r
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */\r
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */\r
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */\r
+#define HSMCI_CMDR_TRCMD_Pos 16\r
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */\r
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */\r
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */\r
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */\r
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */\r
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */\r
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */\r
+#define HSMCI_CMDR_TRTYP_Pos 19\r
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */\r
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */\r
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */\r
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */\r
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */\r
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */\r
+#define HSMCI_CMDR_IOSPCMD_Pos 24\r
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */\r
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */\r
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */\r
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */\r
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */\r
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */\r
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */\r
+#define HSMCI_BLKR_BCNT_Pos 0\r
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */\r
+#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))\r
+#define HSMCI_BLKR_BLKLEN_Pos 16\r
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */\r
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))\r
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */\r
+#define HSMCI_CSTOR_CSTOCYC_Pos 0\r
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */\r
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))\r
+#define HSMCI_CSTOR_CSTOMUL_Pos 4\r
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */\r
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */\r
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */\r
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */\r
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */\r
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */\r
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */\r
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */\r
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */\r
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */\r
+#define HSMCI_RSPR_RSP_Pos 0\r
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */\r
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */\r
+#define HSMCI_RDR_DATA_Pos 0\r
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */\r
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */\r
+#define HSMCI_TDR_DATA_Pos 0\r
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */\r
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))\r
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */\r
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */\r
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */\r
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */\r
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */\r
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */\r
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */\r
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */\r
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */\r
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */\r
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */\r
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */\r
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */\r
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */\r
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */\r
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */\r
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */\r
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */\r
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */\r
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */\r
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */\r
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */\r
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */\r
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */\r
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */\r
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */\r
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */\r
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */\r
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */\r
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */\r
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */\r
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */\r
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */\r
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */\r
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */\r
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */\r
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */\r
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */\r
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */\r
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */\r
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */\r
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */\r
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */\r
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */\r
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */\r
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */\r
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */\r
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */\r
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */\r
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */\r
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */\r
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */\r
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */\r
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */\r
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */\r
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */\r
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */\r
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */\r
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */\r
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */\r
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */\r
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */\r
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */\r
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */\r
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */\r
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */\r
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */\r
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */\r
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */\r
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */\r
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */\r
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */\r
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */\r
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */\r
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */\r
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */\r
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */\r
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */\r
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */\r
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */\r
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */\r
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */\r
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */\r
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */\r
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */\r
+#define HSMCI_DMA_CHKSIZE_Pos 4\r
+#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */\r
+#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */\r
+#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */\r
+#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */\r
+#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */\r
+#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */\r
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */\r
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */\r
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */\r
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */\r
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */\r
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */\r
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */\r
+#define HSMCI_WPMR_WPKEY_Pos 8\r
+#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */\r
+#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */\r
+#define HSMCI_WPSR_WPVSRC_Pos 8\r
+#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */\r
+/* -------- HSMCI_VERSION : (HSMCI Offset: 0xFC) Version Register -------- */\r
+#define HSMCI_VERSION_VERSION_Pos 0\r
+#define HSMCI_VERSION_VERSION_Msk (0xfffu << HSMCI_VERSION_VERSION_Pos) /**< \brief (HSMCI_VERSION) Hardware Module Version */\r
+#define HSMCI_VERSION_MFN_Pos 16\r
+#define HSMCI_VERSION_MFN_Msk (0x7u << HSMCI_VERSION_MFN_Pos) /**< \brief (HSMCI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_HSMCI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ICM_COMPONENT_\r
+#define _SAM_ICM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_ICM Integrity Check Monitor */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Icm hardware registers */\r
+typedef struct {\r
+ __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */\r
+ __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */\r
+ __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */\r
+ __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */\r
+ __I uint32_t Reserved2[3];\r
+ __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */\r
+ __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */\r
+ __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */\r
+ __I uint32_t Reserved3[37];\r
+ __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */\r
+ __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */\r
+ __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */\r
+ __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */\r
+} Icm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */\r
+#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */\r
+#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */\r
+#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */\r
+#define ICM_CFG_BBC_Pos 4\r
+#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */\r
+#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))\r
+#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */\r
+#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */\r
+#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */\r
+#define ICM_CFG_UALGO_Pos 13\r
+#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */\r
+#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */\r
+#define ICM_CFG_HAPROT_Pos 16\r
+#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */\r
+#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))\r
+#define ICM_CFG_DAPROT_Pos 24\r
+#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */\r
+#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))\r
+/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */\r
+#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */\r
+#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */\r
+#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */\r
+#define ICM_CTRL_REHASH_Pos 4\r
+#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */\r
+#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))\r
+#define ICM_CTRL_RMDIS_Pos 8\r
+#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */\r
+#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))\r
+#define ICM_CTRL_RMEN_Pos 12\r
+#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */\r
+#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))\r
+/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */\r
+#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */\r
+#define ICM_SR_RAWRMDIS_Pos 8\r
+#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */\r
+#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))\r
+#define ICM_SR_RMDIS_Pos 12\r
+#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */\r
+#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))\r
+/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */\r
+#define ICM_IER_RHC_Pos 0\r
+#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */\r
+#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))\r
+#define ICM_IER_RDM_Pos 4\r
+#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */\r
+#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))\r
+#define ICM_IER_RBE_Pos 8\r
+#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */\r
+#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))\r
+#define ICM_IER_RWC_Pos 12\r
+#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */\r
+#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))\r
+#define ICM_IER_REC_Pos 16\r
+#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */\r
+#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))\r
+#define ICM_IER_RSU_Pos 20\r
+#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */\r
+#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))\r
+#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */\r
+/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */\r
+#define ICM_IDR_RHC_Pos 0\r
+#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */\r
+#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))\r
+#define ICM_IDR_RDM_Pos 4\r
+#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */\r
+#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))\r
+#define ICM_IDR_RBE_Pos 8\r
+#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */\r
+#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))\r
+#define ICM_IDR_RWC_Pos 12\r
+#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */\r
+#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))\r
+#define ICM_IDR_REC_Pos 16\r
+#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */\r
+#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))\r
+#define ICM_IDR_RSU_Pos 20\r
+#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */\r
+#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))\r
+#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */\r
+/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */\r
+#define ICM_IMR_RHC_Pos 0\r
+#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */\r
+#define ICM_IMR_RDM_Pos 4\r
+#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */\r
+#define ICM_IMR_RBE_Pos 8\r
+#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */\r
+#define ICM_IMR_RWC_Pos 12\r
+#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */\r
+#define ICM_IMR_REC_Pos 16\r
+#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */\r
+#define ICM_IMR_RSU_Pos 20\r
+#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */\r
+#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */\r
+/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */\r
+#define ICM_ISR_RHC_Pos 0\r
+#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */\r
+#define ICM_ISR_RDM_Pos 4\r
+#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */\r
+#define ICM_ISR_RBE_Pos 8\r
+#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */\r
+#define ICM_ISR_RWC_Pos 12\r
+#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */\r
+#define ICM_ISR_REC_Pos 16\r
+#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */\r
+#define ICM_ISR_RSU_Pos 20\r
+#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */\r
+#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */\r
+/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */\r
+#define ICM_UASR_URAT_Pos 0\r
+#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */\r
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */\r
+#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */\r
+#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */\r
+#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */\r
+#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */\r
+/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */\r
+#define ICM_DSCR_DASA_Pos 6\r
+#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */\r
+#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))\r
+/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */\r
+#define ICM_HASH_HASA_Pos 7\r
+#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */\r
+#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))\r
+/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */\r
+#define ICM_UIHVAL_VAL_Pos 0\r
+#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */\r
+#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))\r
+/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */\r
+#define ICM_ADDRSIZE_ADDRSIZE_Pos 0\r
+#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */\r
+/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */\r
+#define ICM_IPNAME_IPNAME_Pos 0\r
+#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */\r
+/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */\r
+#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */\r
+#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */\r
+#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */\r
+#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */\r
+#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */\r
+#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */\r
+#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */\r
+#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */\r
+#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */\r
+#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */\r
+#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */\r
+/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */\r
+#define ICM_VERSION_VERSION_Pos 0\r
+#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */\r
+#define ICM_VERSION_MFN_Pos 16\r
+#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_ICM_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ISI_COMPONENT_\r
+#define _SAM_ISI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Image Sensor Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_ISI Image Sensor Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Isi hardware registers */\r
+typedef struct {\r
+ __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */\r
+ __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */\r
+ __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */\r
+ __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */\r
+ __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */\r
+ __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */\r
+ __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */\r
+ __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */\r
+ __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */\r
+ __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */\r
+ __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */\r
+ __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */\r
+ __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */\r
+ __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */\r
+ __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */\r
+ __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */\r
+ __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */\r
+ __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */\r
+ __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */\r
+ __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */\r
+ __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */\r
+ __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */\r
+ __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */\r
+ __I uint32_t Reserved1[34];\r
+ __IO uint32_t ISI_WPCR; /**< \brief (Isi Offset: 0xE4) Write Protection Control Register */\r
+ __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved2[4];\r
+ __I uint32_t ISI_VERSION; /**< \brief (Isi Offset: 0xFC) Version Register */\r
+} Isi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */\r
+#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */\r
+#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */\r
+#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */\r
+#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */\r
+#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */\r
+#define ISI_CFG1_FRATE_Pos 8\r
+#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */\r
+#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))\r
+#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */\r
+#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */\r
+#define ISI_CFG1_THMASK_Pos 13\r
+#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */\r
+#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */\r
+#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */\r
+#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */\r
+#define ISI_CFG1_SLD_Pos 16\r
+#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */\r
+#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))\r
+#define ISI_CFG1_SFD_Pos 24\r
+#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */\r
+#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))\r
+/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */\r
+#define ISI_CFG2_IM_VSIZE_Pos 0\r
+#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */\r
+#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))\r
+#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */\r
+#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */\r
+#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */\r
+#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */\r
+#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */\r
+#define ISI_CFG2_IM_HSIZE_Pos 16\r
+#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */\r
+#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))\r
+#define ISI_CFG2_YCC_SWAP_Pos 28\r
+#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */\r
+#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */\r
+#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */\r
+#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */\r
+#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */\r
+#define ISI_CFG2_RGB_CFG_Pos 30\r
+#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */\r
+#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */\r
+#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */\r
+#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */\r
+#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */\r
+/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */\r
+#define ISI_PSIZE_PREV_VSIZE_Pos 0\r
+#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */\r
+#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))\r
+#define ISI_PSIZE_PREV_HSIZE_Pos 16\r
+#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */\r
+#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))\r
+/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */\r
+#define ISI_PDECF_DEC_FACTOR_Pos 0\r
+#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */\r
+#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))\r
+/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */\r
+#define ISI_Y2R_SET0_C0_Pos 0\r
+#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */\r
+#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))\r
+#define ISI_Y2R_SET0_C1_Pos 8\r
+#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */\r
+#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))\r
+#define ISI_Y2R_SET0_C2_Pos 16\r
+#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */\r
+#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))\r
+#define ISI_Y2R_SET0_C3_Pos 24\r
+#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */\r
+#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))\r
+/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */\r
+#define ISI_Y2R_SET1_C4_Pos 0\r
+#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */\r
+#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))\r
+#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */\r
+#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */\r
+#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */\r
+/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */\r
+#define ISI_R2Y_SET0_C0_Pos 0\r
+#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */\r
+#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))\r
+#define ISI_R2Y_SET0_C1_Pos 8\r
+#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */\r
+#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))\r
+#define ISI_R2Y_SET0_C2_Pos 16\r
+#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */\r
+#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))\r
+#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */\r
+/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */\r
+#define ISI_R2Y_SET1_C3_Pos 0\r
+#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */\r
+#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))\r
+#define ISI_R2Y_SET1_C4_Pos 8\r
+#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */\r
+#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))\r
+#define ISI_R2Y_SET1_C5_Pos 16\r
+#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */\r
+#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))\r
+#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */\r
+/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */\r
+#define ISI_R2Y_SET2_C6_Pos 0\r
+#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */\r
+#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))\r
+#define ISI_R2Y_SET2_C7_Pos 8\r
+#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */\r
+#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))\r
+#define ISI_R2Y_SET2_C8_Pos 16\r
+#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */\r
+#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))\r
+#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */\r
+/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */\r
+#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */\r
+#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */\r
+#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */\r
+#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */\r
+/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */\r
+#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */\r
+#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated */\r
+#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated */\r
+#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */\r
+#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization */\r
+#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated */\r
+#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated */\r
+#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */\r
+#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow */\r
+#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow */\r
+#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error */\r
+#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun */\r
+/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */\r
+#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */\r
+#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */\r
+#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */\r
+#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */\r
+#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */\r
+#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */\r
+#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */\r
+#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */\r
+#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */\r
+/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */\r
+#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */\r
+#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */\r
+#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */\r
+#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */\r
+#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */\r
+#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */\r
+#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */\r
+#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */\r
+#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */\r
+/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */\r
+#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */\r
+#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */\r
+#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */\r
+#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Interrupt */\r
+#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Interrupt */\r
+#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) FIFO Preview Overflow */\r
+#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) FIFO Codec Overflow */\r
+#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */\r
+#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */\r
+/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */\r
+#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */\r
+#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */\r
+/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */\r
+#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */\r
+#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */\r
+/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */\r
+#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */\r
+#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */\r
+/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */\r
+#define ISI_DMA_P_ADDR_P_ADDR_Pos 2\r
+#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */\r
+#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))\r
+/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */\r
+#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */\r
+#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */\r
+#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */\r
+#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */\r
+/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */\r
+#define ISI_DMA_P_DSCR_P_DSCR_Pos 2\r
+#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */\r
+#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))\r
+/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */\r
+#define ISI_DMA_C_ADDR_C_ADDR_Pos 2\r
+#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */\r
+#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))\r
+/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */\r
+#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */\r
+#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */\r
+#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */\r
+#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */\r
+/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */\r
+#define ISI_DMA_C_DSCR_C_DSCR_Pos 2\r
+#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */\r
+#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))\r
+/* -------- ISI_WPCR : (ISI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define ISI_WPCR_WPEN (0x1u << 0) /**< \brief (ISI_WPCR) Write Protection Enable */\r
+#define ISI_WPCR_WPKEY_Pos 8\r
+#define ISI_WPCR_WPKEY_Msk (0xffffffu << ISI_WPCR_WPKEY_Pos) /**< \brief (ISI_WPCR) Write Protection Key Password */\r
+#define ISI_WPCR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPCR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */\r
+#define ISI_WPSR_WPVSRC_Pos 8\r
+#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */\r
+/* -------- ISI_VERSION : (ISI Offset: 0xFC) Version Register -------- */\r
+#define ISI_VERSION_VERSION_Pos 0\r
+#define ISI_VERSION_VERSION_Msk (0xfffu << ISI_VERSION_VERSION_Pos) /**< \brief (ISI_VERSION) Version of the Hardware Module */\r
+#define ISI_VERSION_MFN_Pos 16\r
+#define ISI_VERSION_MFN_Msk (0x7u << ISI_VERSION_MFN_Pos) /**< \brief (ISI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_ISI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_MATRIX_COMPONENT_\r
+#define _SAM_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_MATRIX AHB Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief MatrixPr hardware registers */\r
+typedef struct {\r
+ __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */\r
+ __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */\r
+} MatrixPr;\r
+/** \brief Matrix hardware registers */\r
+#define MATRIXPR_NUMBER 16\r
+typedef struct {\r
+ __IO uint32_t MATRIX_MCFG[16]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */\r
+ __IO uint32_t MATRIX_SCFG[16]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */\r
+ MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 15 */\r
+ __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */\r
+ __I uint32_t Reserved1[3];\r
+ __IO uint32_t MATRIX_SFR[16]; /**< \brief (Matrix Offset: 0x0110) Special Function Register */\r
+ __O uint32_t MATRIX_MEIER; /**< \brief (Matrix Offset: 0x0150) Master Error Interrupt Enable Register */\r
+ __O uint32_t MATRIX_MEIDR; /**< \brief (Matrix Offset: 0x0154) Master Error Interrupt Disable Register */\r
+ __I uint32_t MATRIX_MEIMR; /**< \brief (Matrix Offset: 0x0158) Master Error Interrupt Mask Register */\r
+ __I uint32_t MATRIX_MESR; /**< \brief (Matrix Offset: 0x015C) Master Error Status Register */\r
+ __I uint32_t MATRIX_MEAR[16]; /**< \brief (Matrix Offset: 0x0160) Master 0 Error Address Register */\r
+ __I uint32_t Reserved2[17];\r
+ __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */\r
+ __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */\r
+ __I uint32_t Reserved3[4];\r
+ __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */\r
+ __IO uint32_t MATRIX_SSR[16]; /**< \brief (Matrix Offset: 0x0200) Security Slave 0 Register */\r
+ __IO uint32_t MATRIX_SASSR[16]; /**< \brief (Matrix Offset: 0x0240) Security Areas Split Slave 0 Register */\r
+ __IO uint32_t MATRIX_SRTSR[16]; /**< \brief (Matrix Offset: 0x0280) Security Region Top Slave 0 Register */\r
+ __IO uint32_t MATRIX_SPSELR[3]; /**< \brief (Matrix Offset: 0x02C0) Security Peripheral Select 1 Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG[16] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */\r
+#define MATRIX_MCFG_ULBT_Pos 0\r
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[16]) Undefined Length Burst Type */\r
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))\r
+/* -------- MATRIX_SCFG[16] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */\r
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[16]) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[16]) Default Master Type */\r
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[16]) Fixed Default Master */\r
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS_M0PR_Pos 0\r
+#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */\r
+#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))\r
+#define MATRIX_PRAS_M1PR_Pos 4\r
+#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */\r
+#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))\r
+#define MATRIX_PRAS_M2PR_Pos 8\r
+#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */\r
+#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))\r
+#define MATRIX_PRAS_M3PR_Pos 12\r
+#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */\r
+#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))\r
+#define MATRIX_PRAS_M4PR_Pos 16\r
+#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */\r
+#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))\r
+#define MATRIX_PRAS_M5PR_Pos 20\r
+#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */\r
+#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))\r
+#define MATRIX_PRAS_M6PR_Pos 24\r
+#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */\r
+#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))\r
+#define MATRIX_PRAS_M7PR_Pos 28\r
+#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */\r
+#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))\r
+/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */\r
+#define MATRIX_PRBS_M8PR_Pos 0\r
+#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */\r
+#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))\r
+#define MATRIX_PRBS_M9PR_Pos 4\r
+#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */\r
+#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))\r
+#define MATRIX_PRBS_M10PR_Pos 8\r
+#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */\r
+#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))\r
+#define MATRIX_PRBS_M11PR_Pos 12\r
+#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */\r
+#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))\r
+#define MATRIX_PRBS_M12PR_Pos 16\r
+#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */\r
+#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)))\r
+#define MATRIX_PRBS_M13PR_Pos 20\r
+#define MATRIX_PRBS_M13PR_Msk (0x3u << MATRIX_PRBS_M13PR_Pos) /**< \brief (MATRIX_PRBS) Master 13 Priority */\r
+#define MATRIX_PRBS_M13PR(value) ((MATRIX_PRBS_M13PR_Msk & ((value) << MATRIX_PRBS_M13PR_Pos)))\r
+#define MATRIX_PRBS_M14PR_Pos 24\r
+#define MATRIX_PRBS_M14PR_Msk (0x3u << MATRIX_PRBS_M14PR_Pos) /**< \brief (MATRIX_PRBS) Master 14 Priority */\r
+#define MATRIX_PRBS_M14PR(value) ((MATRIX_PRBS_M14PR_Msk & ((value) << MATRIX_PRBS_M14PR_Pos)))\r
+#define MATRIX_PRBS_M15PR_Pos 28\r
+#define MATRIX_PRBS_M15PR_Msk (0x3u << MATRIX_PRBS_M15PR_Pos) /**< \brief (MATRIX_PRBS) Master 15 Priority */\r
+#define MATRIX_PRBS_M15PR(value) ((MATRIX_PRBS_M15PR_Msk & ((value) << MATRIX_PRBS_M15PR_Pos)))\r
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */\r
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB13 (0x1u << 13) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB14 (0x1u << 14) /**< \brief (MATRIX_MRCR) */\r
+#define MATRIX_MRCR_RCB15 (0x1u << 15) /**< \brief (MATRIX_MRCR) */\r
+/* -------- MATRIX_SFR[16] : (MATRIX Offset: 0x0110) Special Function Register -------- */\r
+#define MATRIX_SFR_SFR_Pos 0\r
+#define MATRIX_SFR_SFR_Msk (0xffffffffu << MATRIX_SFR_SFR_Pos) /**< \brief (MATRIX_SFR[16]) Special Function Register Fields */\r
+#define MATRIX_SFR_SFR(value) ((MATRIX_SFR_SFR_Msk & ((value) << MATRIX_SFR_SFR_Pos)))\r
+/* -------- MATRIX_MEIER : (MATRIX Offset: 0x0150) Master Error Interrupt Enable Register -------- */\r
+#define MATRIX_MEIER_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIER) Master 0 Access Error */\r
+#define MATRIX_MEIER_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIER) Master 1 Access Error */\r
+#define MATRIX_MEIER_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIER) Master 2 Access Error */\r
+#define MATRIX_MEIER_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIER) Master 3 Access Error */\r
+#define MATRIX_MEIER_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIER) Master 4 Access Error */\r
+#define MATRIX_MEIER_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIER) Master 5 Access Error */\r
+#define MATRIX_MEIER_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIER) Master 6 Access Error */\r
+#define MATRIX_MEIER_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIER) Master 7 Access Error */\r
+#define MATRIX_MEIER_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIER) Master 8 Access Error */\r
+#define MATRIX_MEIER_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIER) Master 9 Access Error */\r
+#define MATRIX_MEIER_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIER) Master 10 Access Error */\r
+#define MATRIX_MEIER_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIER) Master 11 Access Error */\r
+#define MATRIX_MEIER_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIER) Master 12 Access Error */\r
+#define MATRIX_MEIER_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIER) Master 13 Access Error */\r
+#define MATRIX_MEIER_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIER) Master 14 Access Error */\r
+#define MATRIX_MEIER_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIER) Master 15 Access Error */\r
+/* -------- MATRIX_MEIDR : (MATRIX Offset: 0x0154) Master Error Interrupt Disable Register -------- */\r
+#define MATRIX_MEIDR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIDR) Master 0 Access Error */\r
+#define MATRIX_MEIDR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIDR) Master 1 Access Error */\r
+#define MATRIX_MEIDR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIDR) Master 2 Access Error */\r
+#define MATRIX_MEIDR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIDR) Master 3 Access Error */\r
+#define MATRIX_MEIDR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIDR) Master 4 Access Error */\r
+#define MATRIX_MEIDR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIDR) Master 5 Access Error */\r
+#define MATRIX_MEIDR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIDR) Master 6 Access Error */\r
+#define MATRIX_MEIDR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIDR) Master 7 Access Error */\r
+#define MATRIX_MEIDR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIDR) Master 8 Access Error */\r
+#define MATRIX_MEIDR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIDR) Master 9 Access Error */\r
+#define MATRIX_MEIDR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIDR) Master 10 Access Error */\r
+#define MATRIX_MEIDR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIDR) Master 11 Access Error */\r
+#define MATRIX_MEIDR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIDR) Master 12 Access Error */\r
+#define MATRIX_MEIDR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIDR) Master 13 Access Error */\r
+#define MATRIX_MEIDR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIDR) Master 14 Access Error */\r
+#define MATRIX_MEIDR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIDR) Master 15 Access Error */\r
+/* -------- MATRIX_MEIMR : (MATRIX Offset: 0x0158) Master Error Interrupt Mask Register -------- */\r
+#define MATRIX_MEIMR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIMR) Master 0 Access Error */\r
+#define MATRIX_MEIMR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIMR) Master 1 Access Error */\r
+#define MATRIX_MEIMR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIMR) Master 2 Access Error */\r
+#define MATRIX_MEIMR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIMR) Master 3 Access Error */\r
+#define MATRIX_MEIMR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIMR) Master 4 Access Error */\r
+#define MATRIX_MEIMR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIMR) Master 5 Access Error */\r
+#define MATRIX_MEIMR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIMR) Master 6 Access Error */\r
+#define MATRIX_MEIMR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIMR) Master 7 Access Error */\r
+#define MATRIX_MEIMR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIMR) Master 8 Access Error */\r
+#define MATRIX_MEIMR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIMR) Master 9 Access Error */\r
+#define MATRIX_MEIMR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIMR) Master 10 Access Error */\r
+#define MATRIX_MEIMR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIMR) Master 11 Access Error */\r
+#define MATRIX_MEIMR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIMR) Master 12 Access Error */\r
+#define MATRIX_MEIMR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIMR) Master 13 Access Error */\r
+#define MATRIX_MEIMR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIMR) Master 14 Access Error */\r
+#define MATRIX_MEIMR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIMR) Master 15 Access Error */\r
+/* -------- MATRIX_MESR : (MATRIX Offset: 0x015C) Master Error Status Register -------- */\r
+#define MATRIX_MESR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MESR) Master 0 Access Error */\r
+#define MATRIX_MESR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MESR) Master 1 Access Error */\r
+#define MATRIX_MESR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MESR) Master 2 Access Error */\r
+#define MATRIX_MESR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MESR) Master 3 Access Error */\r
+#define MATRIX_MESR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MESR) Master 4 Access Error */\r
+#define MATRIX_MESR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MESR) Master 5 Access Error */\r
+#define MATRIX_MESR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MESR) Master 6 Access Error */\r
+#define MATRIX_MESR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MESR) Master 7 Access Error */\r
+#define MATRIX_MESR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MESR) Master 8 Access Error */\r
+#define MATRIX_MESR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MESR) Master 9 Access Error */\r
+#define MATRIX_MESR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MESR) Master 10 Access Error */\r
+#define MATRIX_MESR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MESR) Master 11 Access Error */\r
+#define MATRIX_MESR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MESR) Master 12 Access Error */\r
+#define MATRIX_MESR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MESR) Master 13 Access Error */\r
+#define MATRIX_MESR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MESR) Master 14 Access Error */\r
+#define MATRIX_MESR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MESR) Master 15 Access Error */\r
+/* -------- MATRIX_MEAR[16] : (MATRIX Offset: 0x0160) Master 0 Error Address Register -------- */\r
+#define MATRIX_MEAR_ERRADD_Pos 0\r
+#define MATRIX_MEAR_ERRADD_Msk (0xffffffffu << MATRIX_MEAR_ERRADD_Pos) /**< \brief (MATRIX_MEAR[16]) Master Error Address */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */\r
+/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */\r
+#define MATRIX_VERSION_VERSION_Pos 0\r
+#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) */\r
+#define MATRIX_VERSION_MFN_Pos 16\r
+#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) */\r
+/* -------- MATRIX_SSR[16] : (MATRIX Offset: 0x0200) Security Slave 0 Register -------- */\r
+#define MATRIX_SSR_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+#define MATRIX_SSR_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */\r
+/* -------- MATRIX_SASSR[16] : (MATRIX Offset: 0x0240) Security Areas Split Slave 0 Register -------- */\r
+#define MATRIX_SASSR_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR_SASPLIT0_Msk (0xfu << MATRIX_SASSR_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT0(value) ((MATRIX_SASSR_SASPLIT0_Msk & ((value) << MATRIX_SASSR_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR_SASPLIT1_Msk (0xfu << MATRIX_SASSR_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT1(value) ((MATRIX_SASSR_SASPLIT1_Msk & ((value) << MATRIX_SASSR_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR_SASPLIT2_Msk (0xfu << MATRIX_SASSR_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT2(value) ((MATRIX_SASSR_SASPLIT2_Msk & ((value) << MATRIX_SASSR_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR_SASPLIT3_Msk (0xfu << MATRIX_SASSR_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT3(value) ((MATRIX_SASSR_SASPLIT3_Msk & ((value) << MATRIX_SASSR_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR_SASPLIT4_Msk (0xfu << MATRIX_SASSR_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT4(value) ((MATRIX_SASSR_SASPLIT4_Msk & ((value) << MATRIX_SASSR_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR_SASPLIT5_Msk (0xfu << MATRIX_SASSR_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT5(value) ((MATRIX_SASSR_SASPLIT5_Msk & ((value) << MATRIX_SASSR_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR_SASPLIT6_Msk (0xfu << MATRIX_SASSR_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT6(value) ((MATRIX_SASSR_SASPLIT6_Msk & ((value) << MATRIX_SASSR_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR_SASPLIT7_Msk (0xfu << MATRIX_SASSR_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR_SASPLIT7(value) ((MATRIX_SASSR_SASPLIT7_Msk & ((value) << MATRIX_SASSR_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SRTSR[16] : (MATRIX Offset: 0x0280) Security Region Top Slave 0 Register -------- */\r
+#define MATRIX_SRTSR_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR_SRTOP0_Msk (0xfu << MATRIX_SRTSR_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP0(value) ((MATRIX_SRTSR_SRTOP0_Msk & ((value) << MATRIX_SRTSR_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR_SRTOP1_Msk (0xfu << MATRIX_SRTSR_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP1(value) ((MATRIX_SRTSR_SRTOP1_Msk & ((value) << MATRIX_SRTSR_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR_SRTOP2_Msk (0xfu << MATRIX_SRTSR_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP2(value) ((MATRIX_SRTSR_SRTOP2_Msk & ((value) << MATRIX_SRTSR_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR_SRTOP3_Msk (0xfu << MATRIX_SRTSR_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP3(value) ((MATRIX_SRTSR_SRTOP3_Msk & ((value) << MATRIX_SRTSR_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR_SRTOP4_Msk (0xfu << MATRIX_SRTSR_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP4(value) ((MATRIX_SRTSR_SRTOP4_Msk & ((value) << MATRIX_SRTSR_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR_SRTOP5_Msk (0xfu << MATRIX_SRTSR_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP5(value) ((MATRIX_SRTSR_SRTOP5_Msk & ((value) << MATRIX_SRTSR_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR_SRTOP6_Msk (0xfu << MATRIX_SRTSR_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP6(value) ((MATRIX_SRTSR_SRTOP6_Msk & ((value) << MATRIX_SRTSR_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR_SRTOP7_Msk (0xfu << MATRIX_SRTSR_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */\r
+#define MATRIX_SRTSR_SRTOP7(value) ((MATRIX_SRTSR_SRTOP7_Msk & ((value) << MATRIX_SRTSR_SRTOP7_Pos)))\r
+/* -------- MATRIX_SPSELR[3] : (MATRIX Offset: 0x02C0) Security Peripheral Select 1 Register -------- */\r
+#define MATRIX_SPSELR_NSECP0 (0x1u << 0) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP1 (0x1u << 1) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP2 (0x1u << 2) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP3 (0x1u << 3) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP4 (0x1u << 4) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP5 (0x1u << 5) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP6 (0x1u << 6) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP7 (0x1u << 7) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP8 (0x1u << 8) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP9 (0x1u << 9) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP10 (0x1u << 10) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP11 (0x1u << 11) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP12 (0x1u << 12) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP13 (0x1u << 13) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP14 (0x1u << 14) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP15 (0x1u << 15) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP16 (0x1u << 16) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP17 (0x1u << 17) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP18 (0x1u << 18) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP19 (0x1u << 19) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP20 (0x1u << 20) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP21 (0x1u << 21) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP22 (0x1u << 22) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP23 (0x1u << 23) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP24 (0x1u << 24) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP25 (0x1u << 25) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP26 (0x1u << 26) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP27 (0x1u << 27) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP28 (0x1u << 28) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP29 (0x1u << 29) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP30 (0x1u << 30) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+#define MATRIX_SPSELR_NSECP31 (0x1u << 31) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_MATRIX_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIO_COMPONENT_\r
+#define _SAM_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pio hardware registers */\r
+typedef struct {\r
+ __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */\r
+ __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */\r
+ __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */\r
+ __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */\r
+ __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */\r
+ __I uint32_t Reserved2[1];\r
+ __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */\r
+ __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */\r
+ __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */\r
+ __I uint32_t Reserved3[1];\r
+ __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */\r
+ __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */\r
+ __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */\r
+ __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */\r
+ __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */\r
+ __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */\r
+ __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */\r
+ __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */\r
+ __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */\r
+ __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */\r
+ __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */\r
+ __I uint32_t Reserved4[1];\r
+ __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */\r
+ __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */\r
+ __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */\r
+ __I uint32_t Reserved5[1];\r
+ __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */\r
+ __I uint32_t Reserved6[2];\r
+ __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */\r
+ __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */\r
+ __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */\r
+ __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */\r
+ __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */\r
+ __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */\r
+ __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */\r
+ __I uint32_t Reserved7[1];\r
+ __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */\r
+ __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */\r
+ __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */\r
+ __I uint32_t Reserved8[1];\r
+ __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */\r
+ __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */\r
+ __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */\r
+ __I uint32_t Reserved9[1];\r
+ __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */\r
+ __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */\r
+ __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */\r
+ __I uint32_t Reserved10[1];\r
+ __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */\r
+ __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High-Level Select Register */\r
+ __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */\r
+ __I uint32_t Reserved11[1];\r
+ __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */\r
+ __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */\r
+ __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */\r
+ __I uint32_t Reserved12[4];\r
+ __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */\r
+ __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */\r
+ __I uint32_t Reserved13[7];\r
+ __IO uint32_t PIO_KER; /**< \brief (Pio Offset: 0x0120) Keypad Controller Enable Register */\r
+ __IO uint32_t PIO_KRCR; /**< \brief (Pio Offset: 0x0124) Keypad Controller Row Column Register */\r
+ __IO uint32_t PIO_KDR; /**< \brief (Pio Offset: 0x0128) Keypad Controller Debouncing Register */\r
+ __I uint32_t Reserved14[1];\r
+ __O uint32_t PIO_KIER; /**< \brief (Pio Offset: 0x0130) Keypad Controller Interrupt Enable Register */\r
+ __O uint32_t PIO_KIDR; /**< \brief (Pio Offset: 0x0134) Keypad Controller Interrupt Disable Register */\r
+ __I uint32_t PIO_KIMR; /**< \brief (Pio Offset: 0x0138) Keypad Controller Interrupt Mask Register */\r
+ __I uint32_t PIO_KSR; /**< \brief (Pio Offset: 0x013C) Keypad Controller Status Register */\r
+ __I uint32_t PIO_KKPR; /**< \brief (Pio Offset: 0x0140) Keypad Controller Key Press Register */\r
+ __I uint32_t PIO_KKRR; /**< \brief (Pio Offset: 0x0144) Keypad Controller Key Release Register */\r
+ __I uint32_t Reserved15[2];\r
+ __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */\r
+ __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */\r
+ __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */\r
+ __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */\r
+ __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */\r
+ __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */\r
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */\r
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */\r
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */\r
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */\r
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */\r
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */\r
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */\r
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */\r
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */\r
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */\r
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */\r
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */\r
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */\r
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */\r
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */\r
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */\r
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */\r
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-Drive Enable */\r
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */\r
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-Drive Disable */\r
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */\r
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-Drive Status */\r
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */\r
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */\r
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */\r
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */\r
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */\r
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */\r
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */\r
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */\r
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */\r
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */\r
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */\r
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */\r
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */\r
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */\r
+#define PIO_SCDR_DIV_Pos 0\r
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */\r
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))\r
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */\r
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */\r
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */\r
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */\r
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */\r
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */\r
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */\r
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */\r
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */\r
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */\r
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */\r
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */\r
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */\r
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */\r
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */\r
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */\r
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */\r
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */\r
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */\r
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */\r
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status */\r
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */\r
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */\r
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */\r
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */\r
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */\r
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */\r
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */\r
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */\r
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High-Level Select Register -------- */\r
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */\r
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */\r
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */\r
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key. */\r
+#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */\r
+/* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */\r
+#define PIO_VERSION_VERSION_Pos 0\r
+#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */\r
+#define PIO_VERSION_MFN_Pos 16\r
+#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */\r
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */\r
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */\r
+/* -------- PIO_KER : (PIO Offset: 0x0120) Keypad Controller Enable Register -------- */\r
+#define PIO_KER_KCE (0x1u << 0) /**< \brief (PIO_KER) Keypad Controller Enable */\r
+/* -------- PIO_KRCR : (PIO Offset: 0x0124) Keypad Controller Row Column Register -------- */\r
+#define PIO_KRCR_NBR_Pos 0\r
+#define PIO_KRCR_NBR_Msk (0x7u << PIO_KRCR_NBR_Pos) /**< \brief (PIO_KRCR) Number of Columns of the Keypad Matrix */\r
+#define PIO_KRCR_NBR(value) ((PIO_KRCR_NBR_Msk & ((value) << PIO_KRCR_NBR_Pos)))\r
+#define PIO_KRCR_NBC_Pos 8\r
+#define PIO_KRCR_NBC_Msk (0x7u << PIO_KRCR_NBC_Pos) /**< \brief (PIO_KRCR) Number of Rows of the Keypad Matrix */\r
+#define PIO_KRCR_NBC(value) ((PIO_KRCR_NBC_Msk & ((value) << PIO_KRCR_NBC_Pos)))\r
+/* -------- PIO_KDR : (PIO Offset: 0x0128) Keypad Controller Debouncing Register -------- */\r
+#define PIO_KDR_DBC_Pos 0\r
+#define PIO_KDR_DBC_Msk (0x3ffu << PIO_KDR_DBC_Pos) /**< \brief (PIO_KDR) Debouncing Value */\r
+#define PIO_KDR_DBC(value) ((PIO_KDR_DBC_Msk & ((value) << PIO_KDR_DBC_Pos)))\r
+/* -------- PIO_KIER : (PIO Offset: 0x0130) Keypad Controller Interrupt Enable Register -------- */\r
+#define PIO_KIER_KPR (0x1u << 0) /**< \brief (PIO_KIER) Key Press Interrupt Enable */\r
+#define PIO_KIER_KRL (0x1u << 1) /**< \brief (PIO_KIER) Key Release Interrupt Enable */\r
+/* -------- PIO_KIDR : (PIO Offset: 0x0134) Keypad Controller Interrupt Disable Register -------- */\r
+#define PIO_KIDR_KPR (0x1u << 0) /**< \brief (PIO_KIDR) Key Press Interrupt Disable */\r
+#define PIO_KIDR_KRL (0x1u << 1) /**< \brief (PIO_KIDR) Key Release Interrupt Disable */\r
+/* -------- PIO_KIMR : (PIO Offset: 0x0138) Keypad Controller Interrupt Mask Register -------- */\r
+#define PIO_KIMR_KPR (0x1u << 0) /**< \brief (PIO_KIMR) Key Press Interrupt Mask */\r
+#define PIO_KIMR_KRL (0x1u << 1) /**< \brief (PIO_KIMR) Key Release Interrupt Mask */\r
+/* -------- PIO_KSR : (PIO Offset: 0x013C) Keypad Controller Status Register -------- */\r
+#define PIO_KSR_KPR (0x1u << 0) /**< \brief (PIO_KSR) Key Press Status */\r
+#define PIO_KSR_KRL (0x1u << 1) /**< \brief (PIO_KSR) Key Release Status */\r
+#define PIO_KSR_NBKPR_Pos 8\r
+#define PIO_KSR_NBKPR_Msk (0x3u << PIO_KSR_NBKPR_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Presses */\r
+#define PIO_KSR_NBKRL_Pos 16\r
+#define PIO_KSR_NBKRL_Msk (0x3u << PIO_KSR_NBKRL_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Releases */\r
+/* -------- PIO_KKPR : (PIO Offset: 0x0140) Keypad Controller Key Press Register -------- */\r
+#define PIO_KKPR_KEY0ROW_Pos 0\r
+#define PIO_KKPR_KEY0ROW_Msk (0x7u << PIO_KKPR_KEY0ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the First Detected Key Press */\r
+#define PIO_KKPR_KEY0COL_Pos 4\r
+#define PIO_KKPR_KEY0COL_Msk (0x7u << PIO_KKPR_KEY0COL_Pos) /**< \brief (PIO_KKPR) Column Index of the First Detected Key Press */\r
+#define PIO_KKPR_KEY1ROW_Pos 8\r
+#define PIO_KKPR_KEY1ROW_Msk (0x7u << PIO_KKPR_KEY1ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Second Detected Key Press */\r
+#define PIO_KKPR_KEY1COL_Pos 12\r
+#define PIO_KKPR_KEY1COL_Msk (0x7u << PIO_KKPR_KEY1COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Second Detected Key Press */\r
+#define PIO_KKPR_KEY2ROW_Pos 16\r
+#define PIO_KKPR_KEY2ROW_Msk (0x7u << PIO_KKPR_KEY2ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Third Detected Key Press */\r
+#define PIO_KKPR_KEY2COL_Pos 20\r
+#define PIO_KKPR_KEY2COL_Msk (0x7u << PIO_KKPR_KEY2COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Third Detected Key Press */\r
+#define PIO_KKPR_KEY3ROW_Pos 24\r
+#define PIO_KKPR_KEY3ROW_Msk (0x7u << PIO_KKPR_KEY3ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Fourth Detected Key Press */\r
+#define PIO_KKPR_KEY3COL_Pos 28\r
+#define PIO_KKPR_KEY3COL_Msk (0x7u << PIO_KKPR_KEY3COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Fourth Detected Key Press */\r
+/* -------- PIO_KKRR : (PIO Offset: 0x0144) Keypad Controller Key Release Register -------- */\r
+#define PIO_KKRR_KEY0ROW_Pos 0\r
+#define PIO_KKRR_KEY0ROW_Msk (0x7u << PIO_KKRR_KEY0ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the First Detected Key Release */\r
+#define PIO_KKRR_KEY0COL_Pos 4\r
+#define PIO_KKRR_KEY0COL_Msk (0x7u << PIO_KKRR_KEY0COL_Pos) /**< \brief (PIO_KKRR) Column Index of the First Detected Key Release */\r
+#define PIO_KKRR_KEY1ROW_Pos 8\r
+#define PIO_KKRR_KEY1ROW_Msk (0x7u << PIO_KKRR_KEY1ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Second Detected Key Release */\r
+#define PIO_KKRR_KEY1COL_Pos 12\r
+#define PIO_KKRR_KEY1COL_Msk (0x7u << PIO_KKRR_KEY1COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Second Detected Key Release */\r
+#define PIO_KKRR_KEY2ROW_Pos 16\r
+#define PIO_KKRR_KEY2ROW_Msk (0x7u << PIO_KKRR_KEY2ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Third Detected Key Release */\r
+#define PIO_KKRR_KEY2COL_Pos 20\r
+#define PIO_KKRR_KEY2COL_Msk (0x7u << PIO_KKRR_KEY2COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Third Detected Key Release */\r
+#define PIO_KKRR_KEY3ROW_Pos 24\r
+#define PIO_KKRR_KEY3ROW_Msk (0x7u << PIO_KKRR_KEY3ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Fourth Detected Key Release */\r
+#define PIO_KKRR_KEY3COL_Pos 28\r
+#define PIO_KKRR_KEY3COL_Msk (0x7u << PIO_KKRR_KEY3COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Fourth Detected Key Release */\r
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */\r
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */\r
+#define PIO_PCMR_DSIZE_Pos 4\r
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */\r
+#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */\r
+#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */\r
+#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */\r
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */\r
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */\r
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */\r
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */\r
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */\r
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */\r
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */\r
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */\r
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */\r
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */\r
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */\r
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */\r
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */\r
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */\r
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */\r
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */\r
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */\r
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */\r
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */\r
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */\r
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */\r
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */\r
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */\r
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */\r
+#define PIO_PCRHR_RDATA_Pos 0\r
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_PIO_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PMC_COMPONENT_\r
+#define _SAM_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */\r
+ __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ __I uint32_t Reserved3[1];\r
+ __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ __I uint32_t Reserved4[1];\r
+ __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock Register */\r
+ __I uint32_t Reserved5[1];\r
+ __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */\r
+ __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */\r
+ __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ __I uint32_t Reserved6[26];\r
+ __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */\r
+ __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */\r
+ __I uint32_t PMC_ADDRSIZE; /**< \brief (Pmc Offset: 0x00EC) Address Size Register */\r
+ __I uint32_t PMC_IPNAME[2]; /**< \brief (Pmc Offset: 0x00F0) IP Name1 Register */\r
+ __I uint32_t PMC_FEATURES; /**< \brief (Pmc Offset: 0x00F8) Features Register */\r
+ __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */\r
+ __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */\r
+ __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */\r
+ __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x114) SleepWalking Enable Register 0 */\r
+ __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x118) SleepWalking Disable Register 0 */\r
+ __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x11C) SleepWalking Status Register 0 */\r
+ __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x120) SleepWalking Activity Status Register 0 */\r
+ __I uint32_t Reserved7[3];\r
+ __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x130) PLL Maximum Multiplier Value Register */\r
+ __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x134) SleepWalking Enable Register 1 */\r
+ __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x138) SleepWalking Disable Register 1 */\r
+ __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x13C) SleepWalking Status Register 1 */\r
+ __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x140) SleepWalking Activity Status Register 1 */\r
+ __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x144) SleepWalking Activity In ProgressRegister */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */\r
+#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */\r
+#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */\r
+#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */\r
+#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */\r
+#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */\r
+#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */\r
+#define PMC_SCSR_PCK4 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */\r
+#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */\r
+#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */\r
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */\r
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */\r
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */\r
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */\r
+#define CKGR_UCKR_UPLLCOUNT_Pos 20\r
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */\r
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */\r
+#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCRCF_Pos 4\r
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */\r
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */\r
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */\r
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */\r
+#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */\r
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */\r
+#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front_End Divider */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 16\r
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */\r
+#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */\r
+#define PMC_MCKR_CSS_MCK_CLK (0x4u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */\r
+#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */\r
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */\r
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */\r
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */\r
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */\r
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */\r
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */\r
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */\r
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */\r
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */\r
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */\r
+#define PMC_FSMR_FLPM_Pos 21\r
+#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */\r
+#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */\r
+#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep-power-down mode when system enters Wait Mode */\r
+#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */\r
+#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */\r
+#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */\r
+/* -------- PMC_ADDRSIZE : (PMC Offset: 0x00EC) Address Size Register -------- */\r
+#define PMC_ADDRSIZE_ADDRSIZE_Pos 0\r
+#define PMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << PMC_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (PMC_ADDRSIZE) Peripheral Bus Address Area Size */\r
+/* -------- PMC_IPNAME[2] : (PMC Offset: 0x00F0) IP Name1 Register -------- */\r
+#define PMC_IPNAME_IPNAME_Pos 0\r
+#define PMC_IPNAME_IPNAME_Msk (0xffffffffu << PMC_IPNAME_IPNAME_Pos) /**< \brief (PMC_IPNAME[2]) IP Name in ASCII Format */\r
+/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */\r
+#define PMC_VERSION_VERSION_Pos 0\r
+#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */\r
+#define PMC_VERSION_MFN_Pos 16\r
+#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */\r
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */\r
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */\r
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */\r
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */\r
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */\r
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */\r
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */\r
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */\r
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */\r
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */\r
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */\r
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */\r
+#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */\r
+#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */\r
+#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */\r
+#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */\r
+#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */\r
+#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */\r
+#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */\r
+#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */\r
+#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */\r
+#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */\r
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */\r
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */\r
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */\r
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */\r
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */\r
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */\r
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */\r
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */\r
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */\r
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */\r
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */\r
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */\r
+#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */\r
+#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */\r
+#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */\r
+#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */\r
+#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */\r
+#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */\r
+#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */\r
+#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */\r
+#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */\r
+#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */\r
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */\r
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */\r
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */\r
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */\r
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */\r
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */\r
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */\r
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */\r
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */\r
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */\r
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */\r
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */\r
+#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */\r
+#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */\r
+#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */\r
+#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */\r
+#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */\r
+#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */\r
+#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */\r
+#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */\r
+#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */\r
+#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */\r
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */\r
+#define PMC_PCR_PID_Pos 0\r
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */\r
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))\r
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */\r
+#define PMC_PCR_DIV_Pos 16\r
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */\r
+#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */\r
+#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */\r
+#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */\r
+#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */\r
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */\r
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */\r
+#define PMC_OCR_CAL4_Pos 0\r
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */\r
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))\r
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */\r
+#define PMC_OCR_CAL8_Pos 8\r
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */\r
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))\r
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */\r
+#define PMC_OCR_CAL12_Pos 16\r
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */\r
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))\r
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */\r
+/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) SleepWalking Enable Register 0 -------- */\r
+#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */\r
+#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */\r
+/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) SleepWalking Disable Register 0 -------- */\r
+#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */\r
+#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */\r
+/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11C) SleepWalking Status Register 0 -------- */\r
+#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */\r
+#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */\r
+/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) SleepWalking Activity Status Register 0 -------- */\r
+#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */\r
+#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */\r
+/* -------- PMC_PMMR : (PMC Offset: 0x130) PLL Maximum Multiplier Value Register -------- */\r
+#define PMC_PMMR_PLLA_MMAX_Pos 0\r
+#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */\r
+#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))\r
+#define PMC_PMMR_PLLB_MMAX_Pos 16\r
+#define PMC_PMMR_PLLB_MMAX_Msk (0x7ffu << PMC_PMMR_PLLB_MMAX_Pos) /**< \brief (PMC_PMMR) PLLB Maximum Allowed Multiplier Value */\r
+#define PMC_PMMR_PLLB_MMAX(value) ((PMC_PMMR_PLLB_MMAX_Msk & ((value) << PMC_PMMR_PLLB_MMAX_Pos)))\r
+/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x134) SleepWalking Enable Register 1 -------- */\r
+#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID36 (0x1u << 4) /**< \brief (PMC_SLPWK_ER1) Peripheral 36 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID38 (0x1u << 6) /**< \brief (PMC_SLPWK_ER1) Peripheral 38 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID54 (0x1u << 22) /**< \brief (PMC_SLPWK_ER1) Peripheral 54 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID55 (0x1u << 23) /**< \brief (PMC_SLPWK_ER1) Peripheral 55 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */\r
+#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */\r
+/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x138) SleepWalking Disable Register 1 -------- */\r
+#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID36 (0x1u << 4) /**< \brief (PMC_SLPWK_DR1) Peripheral 36 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID38 (0x1u << 6) /**< \brief (PMC_SLPWK_DR1) Peripheral 38 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID54 (0x1u << 22) /**< \brief (PMC_SLPWK_DR1) Peripheral 54 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID55 (0x1u << 23) /**< \brief (PMC_SLPWK_DR1) Peripheral 55 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */\r
+#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */\r
+/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x13C) SleepWalking Status Register 1 -------- */\r
+#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID36 (0x1u << 4) /**< \brief (PMC_SLPWK_SR1) Peripheral 36 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID38 (0x1u << 6) /**< \brief (PMC_SLPWK_SR1) Peripheral 38 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID54 (0x1u << 22) /**< \brief (PMC_SLPWK_SR1) Peripheral 54 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID55 (0x1u << 23) /**< \brief (PMC_SLPWK_SR1) Peripheral 55 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalkingSleepWalking Status */\r
+#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalkingSleepWalking Status */\r
+/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x140) SleepWalking Activity Status Register 1 -------- */\r
+#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID36 (0x1u << 4) /**< \brief (PMC_SLPWK_ASR1) Peripheral 36 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID38 (0x1u << 6) /**< \brief (PMC_SLPWK_ASR1) Peripheral 38 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID54 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR1) Peripheral 54 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID55 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR1) Peripheral 55 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */\r
+#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */\r
+/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x144) SleepWalking Activity In ProgressRegister -------- */\r
+#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_PMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PWM_COMPONENT_\r
+#define _SAM_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 4\r
+typedef struct {\r
+ __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */\r
+ __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */\r
+ __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */\r
+ __I uint32_t Reserved1[3];\r
+ __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ __I uint32_t Reserved2[7];\r
+ __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */\r
+ __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */\r
+ __I uint32_t Reserved3[2];\r
+ __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ __I uint32_t Reserved4[3];\r
+ __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */\r
+ __I uint32_t Reserved5[8];\r
+ __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */\r
+ __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */\r
+ __I uint32_t Reserved6[4];\r
+ __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */\r
+ __I uint32_t Reserved7[12];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ __I uint32_t Reserved8[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */\r
+ __I uint32_t Reserved9[96];\r
+ __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */\r
+ __IO uint32_t PWM_CAE0; /**< \brief (Pwm Offset: 0x404) PWM Channel Additional Edge Register (ch_num = 0) */\r
+ __O uint32_t PWM_CAEUPD0; /**< \brief (Pwm Offset: 0x408) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+ __I uint32_t Reserved10[5];\r
+ __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */\r
+ __IO uint32_t PWM_CAE1; /**< \brief (Pwm Offset: 0x424) PWM Channel Additional Edge Register (ch_num = 1) */\r
+ __O uint32_t PWM_CAEUPD1; /**< \brief (Pwm Offset: 0x428) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+ __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */\r
+ __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ __I uint32_t Reserved11[3];\r
+ __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */\r
+ __IO uint32_t PWM_CAE2; /**< \brief (Pwm Offset: 0x444) PWM Channel Additional Edge Register (ch_num = 2) */\r
+ __O uint32_t PWM_CAEUPD2; /**< \brief (Pwm Offset: 0x448) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+ __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */\r
+ __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ __I uint32_t Reserved12[3];\r
+ __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */\r
+ __IO uint32_t PWM_CAE3; /**< \brief (Pwm Offset: 0x464) PWM Channel Additional Edge Register (ch_num = 3) */\r
+ __O uint32_t PWM_CAEUPD3; /**< \brief (Pwm Offset: 0x468) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+ __IO uint32_t PWM_ETRG3; /**< \brief (Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) */\r
+ __IO uint32_t PWM_LEBR3; /**< \brief (Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+#define PWM_CLK_CLKSEL (0x1u << 31) /**< \brief (PWM_CLK) CCK Source Clock Selection */\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */\r
+#define PWM_DMAR_DMADUTY_Pos 0\r
+#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */\r
+#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */\r
+#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */\r
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */\r
+#define PWM_FPE_FPE0_Pos 0\r
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */\r
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))\r
+#define PWM_FPE_FPE1_Pos 8\r
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */\r
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))\r
+#define PWM_FPE_FPE2_Pos 16\r
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */\r
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))\r
+#define PWM_FPE_FPE3_Pos 24\r
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */\r
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */\r
+#define PWM_SSPR_SPRD_Pos 0\r
+#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */\r
+#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))\r
+#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */\r
+/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */\r
+#define PWM_SSPUP_SPRDUP_Pos 0\r
+#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */\r
+#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */\r
+#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */\r
+#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */\r
+#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */\r
+#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */\r
+#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */\r
+#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */\r
+#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */\r
+#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */\r
+#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */\r
+#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */\r
+#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */\r
+#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */\r
+#define PWM_VERSION_VERSION_Pos 0\r
+#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */\r
+#define PWM_VERSION_MFN_Pos 16\r
+#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE_CCK (0x0u << 0) /**< \brief (PWM_CMR) Internal clock */\r
+#define PWM_CMR_CPRE_CCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Internal clock/2 */\r
+#define PWM_CMR_CPRE_CCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Internal clock/4 */\r
+#define PWM_CMR_CPRE_CCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Internal clock/8 */\r
+#define PWM_CMR_CPRE_CCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Internal clock/16 */\r
+#define PWM_CMR_CPRE_CCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Internal clock/32 */\r
+#define PWM_CMR_CPRE_CCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Internal clock/64 */\r
+#define PWM_CMR_CPRE_CCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Internal clock/128 */\r
+#define PWM_CMR_CPRE_CCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Internal clock/256 */\r
+#define PWM_CMR_CPRE_CCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Internal clock/512 */\r
+#define PWM_CMR_CPRE_CCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Internal clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */\r
+#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */\r
+#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */\r
+#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */\r
+#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */\r
+/* -------- PWM_CAE0 : (PWM Offset: 0x404) PWM Channel Additional Edge Register (ch_num = 0) -------- */\r
+#define PWM_CAE0_ADEDGV_Pos 0\r
+#define PWM_CAE0_ADEDGV_Msk (0xffffffu << PWM_CAE0_ADEDGV_Pos) /**< \brief (PWM_CAE0) Channel Additional Edge Value */\r
+#define PWM_CAE0_ADEDGV(value) ((PWM_CAE0_ADEDGV_Msk & ((value) << PWM_CAE0_ADEDGV_Pos)))\r
+#define PWM_CAE0_ADEDGM_Pos 24\r
+#define PWM_CAE0_ADEDGM_Msk (0x3u << PWM_CAE0_ADEDGM_Pos) /**< \brief (PWM_CAE0) Channel Additional Edge Mode */\r
+#define PWM_CAE0_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE0_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE0_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */\r
+/* -------- PWM_CAEUPD0 : (PWM Offset: 0x408) PWM Channel Additional Edge Update Register (ch_num = 0) -------- */\r
+#define PWM_CAEUPD0_ADEDGVUP_Pos 0\r
+#define PWM_CAEUPD0_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD0_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD0) Channel Additional Edge Value Update */\r
+#define PWM_CAEUPD0_ADEDGVUP(value) ((PWM_CAEUPD0_ADEDGVUP_Msk & ((value) << PWM_CAEUPD0_ADEDGVUP_Pos)))\r
+#define PWM_CAEUPD0_ADEDGMUP_Pos 24\r
+#define PWM_CAEUPD0_ADEDGMUP_Msk (0x3u << PWM_CAEUPD0_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD0) Channel Additional Edge Mode Update */\r
+#define PWM_CAEUPD0_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD0_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD0_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD0) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */\r
+/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */\r
+#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */\r
+#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */\r
+/* -------- PWM_CAE1 : (PWM Offset: 0x424) PWM Channel Additional Edge Register (ch_num = 1) -------- */\r
+#define PWM_CAE1_ADEDGV_Pos 0\r
+#define PWM_CAE1_ADEDGV_Msk (0xffffffu << PWM_CAE1_ADEDGV_Pos) /**< \brief (PWM_CAE1) Channel Additional Edge Value */\r
+#define PWM_CAE1_ADEDGV(value) ((PWM_CAE1_ADEDGV_Msk & ((value) << PWM_CAE1_ADEDGV_Pos)))\r
+#define PWM_CAE1_ADEDGM_Pos 24\r
+#define PWM_CAE1_ADEDGM_Msk (0x3u << PWM_CAE1_ADEDGM_Pos) /**< \brief (PWM_CAE1) Channel Additional Edge Mode */\r
+#define PWM_CAE1_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE1_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE1_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */\r
+/* -------- PWM_CAEUPD1 : (PWM Offset: 0x428) PWM Channel Additional Edge Update Register (ch_num = 1) -------- */\r
+#define PWM_CAEUPD1_ADEDGVUP_Pos 0\r
+#define PWM_CAEUPD1_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD1_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD1) Channel Additional Edge Value Update */\r
+#define PWM_CAEUPD1_ADEDGVUP(value) ((PWM_CAEUPD1_ADEDGVUP_Msk & ((value) << PWM_CAEUPD1_ADEDGVUP_Pos)))\r
+#define PWM_CAEUPD1_ADEDGMUP_Pos 24\r
+#define PWM_CAEUPD1_ADEDGMUP_Msk (0x3u << PWM_CAEUPD1_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD1) Channel Additional Edge Mode Update */\r
+#define PWM_CAEUPD1_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD1_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD1_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD1) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */\r
+/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */\r
+#define PWM_ETRG1_MAXCNT_Pos 0\r
+#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */\r
+#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))\r
+#define PWM_ETRG1_TRGMODE_Pos 24\r
+#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */\r
+#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */\r
+#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */\r
+#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */\r
+#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */\r
+#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */\r
+#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */\r
+#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */\r
+#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */\r
+#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */\r
+#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */\r
+/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */\r
+#define PWM_LEBR1_LEBDELAY_Pos 0\r
+#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */\r
+#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))\r
+#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */\r
+#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */\r
+#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */\r
+#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */\r
+/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */\r
+#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */\r
+#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */\r
+/* -------- PWM_CAE2 : (PWM Offset: 0x444) PWM Channel Additional Edge Register (ch_num = 2) -------- */\r
+#define PWM_CAE2_ADEDGV_Pos 0\r
+#define PWM_CAE2_ADEDGV_Msk (0xffffffu << PWM_CAE2_ADEDGV_Pos) /**< \brief (PWM_CAE2) Channel Additional Edge Value */\r
+#define PWM_CAE2_ADEDGV(value) ((PWM_CAE2_ADEDGV_Msk & ((value) << PWM_CAE2_ADEDGV_Pos)))\r
+#define PWM_CAE2_ADEDGM_Pos 24\r
+#define PWM_CAE2_ADEDGM_Msk (0x3u << PWM_CAE2_ADEDGM_Pos) /**< \brief (PWM_CAE2) Channel Additional Edge Mode */\r
+#define PWM_CAE2_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE2_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE2_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */\r
+/* -------- PWM_CAEUPD2 : (PWM Offset: 0x448) PWM Channel Additional Edge Update Register (ch_num = 2) -------- */\r
+#define PWM_CAEUPD2_ADEDGVUP_Pos 0\r
+#define PWM_CAEUPD2_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD2_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD2) Channel Additional Edge Value Update */\r
+#define PWM_CAEUPD2_ADEDGVUP(value) ((PWM_CAEUPD2_ADEDGVUP_Msk & ((value) << PWM_CAEUPD2_ADEDGVUP_Pos)))\r
+#define PWM_CAEUPD2_ADEDGMUP_Pos 24\r
+#define PWM_CAEUPD2_ADEDGMUP_Msk (0x3u << PWM_CAEUPD2_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD2) Channel Additional Edge Mode Update */\r
+#define PWM_CAEUPD2_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD2_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD2_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD2) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */\r
+/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */\r
+#define PWM_ETRG2_MAXCNT_Pos 0\r
+#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */\r
+#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))\r
+#define PWM_ETRG2_TRGMODE_Pos 24\r
+#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */\r
+#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */\r
+#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */\r
+#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */\r
+#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */\r
+#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */\r
+#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */\r
+#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */\r
+#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */\r
+#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */\r
+#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */\r
+/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */\r
+#define PWM_LEBR2_LEBDELAY_Pos 0\r
+#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */\r
+#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))\r
+#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */\r
+#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */\r
+#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */\r
+#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */\r
+/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */\r
+#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */\r
+#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */\r
+/* -------- PWM_CAE3 : (PWM Offset: 0x464) PWM Channel Additional Edge Register (ch_num = 3) -------- */\r
+#define PWM_CAE3_ADEDGV_Pos 0\r
+#define PWM_CAE3_ADEDGV_Msk (0xffffffu << PWM_CAE3_ADEDGV_Pos) /**< \brief (PWM_CAE3) Channel Additional Edge Value */\r
+#define PWM_CAE3_ADEDGV(value) ((PWM_CAE3_ADEDGV_Msk & ((value) << PWM_CAE3_ADEDGV_Pos)))\r
+#define PWM_CAE3_ADEDGM_Pos 24\r
+#define PWM_CAE3_ADEDGM_Msk (0x3u << PWM_CAE3_ADEDGM_Pos) /**< \brief (PWM_CAE3) Channel Additional Edge Mode */\r
+#define PWM_CAE3_ADEDGM_INC (0x0u << 24) /**< \brief (PWM_CAE3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE3_ADEDGM_DEC (0x1u << 24) /**< \brief (PWM_CAE3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV and the counter of the channel x is incrementing. */\r
+#define PWM_CAE3_ADEDGM_BOTH (0x2u << 24) /**< \brief (PWM_CAE3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGV, whether the counter is incrementing or not. */\r
+/* -------- PWM_CAEUPD3 : (PWM Offset: 0x468) PWM Channel Additional Edge Update Register (ch_num = 3) -------- */\r
+#define PWM_CAEUPD3_ADEDGVUP_Pos 0\r
+#define PWM_CAEUPD3_ADEDGVUP_Msk (0xffffffu << PWM_CAEUPD3_ADEDGVUP_Pos) /**< \brief (PWM_CAEUPD3) Channel Additional Edge Value Update */\r
+#define PWM_CAEUPD3_ADEDGVUP(value) ((PWM_CAEUPD3_ADEDGVUP_Msk & ((value) << PWM_CAEUPD3_ADEDGVUP_Pos)))\r
+#define PWM_CAEUPD3_ADEDGMUP_Pos 24\r
+#define PWM_CAEUPD3_ADEDGMUP_Msk (0x3u << PWM_CAEUPD3_ADEDGMUP_Pos) /**< \brief (PWM_CAEUPD3) Channel Additional Edge Mode Update */\r
+#define PWM_CAEUPD3_ADEDGMUP_INC (0x0u << 24) /**< \brief (PWM_CAEUPD3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD3_ADEDGMUP_DEC (0x1u << 24) /**< \brief (PWM_CAEUPD3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP and the counter of the channel x is incrementing. */\r
+#define PWM_CAEUPD3_ADEDGMUP_BOTH (0x2u << 24) /**< \brief (PWM_CAEUPD3) The additional edge of the channel x output waveform occurs when CCNTx reaches ADEDGVUP, whether the counter is incrementing or not. */\r
+/* -------- PWM_ETRG3 : (PWM Offset: 0x46C) PWM External Trigger Register (trg_num = 3) -------- */\r
+#define PWM_ETRG3_MAXCNT_Pos 0\r
+#define PWM_ETRG3_MAXCNT_Msk (0xffffffu << PWM_ETRG3_MAXCNT_Pos) /**< \brief (PWM_ETRG3) Maximum Counter value */\r
+#define PWM_ETRG3_MAXCNT(value) ((PWM_ETRG3_MAXCNT_Msk & ((value) << PWM_ETRG3_MAXCNT_Pos)))\r
+#define PWM_ETRG3_TRGMODE_Pos 24\r
+#define PWM_ETRG3_TRGMODE_Msk (0x3u << PWM_ETRG3_TRGMODE_Pos) /**< \brief (PWM_ETRG3) External Trigger Mode */\r
+#define PWM_ETRG3_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG3) External trigger is not enabled. */\r
+#define PWM_ETRG3_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG3) External PWM Reset Mode */\r
+#define PWM_ETRG3_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG3) External PWM Start Mode */\r
+#define PWM_ETRG3_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG3) Cycle-by-cycle Duty Mode */\r
+#define PWM_ETRG3_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG3) Edge Selection */\r
+#define PWM_ETRG3_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */\r
+#define PWM_ETRG3_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */\r
+#define PWM_ETRG3_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG3) Filtered input */\r
+#define PWM_ETRG3_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG3) Trigger Source */\r
+#define PWM_ETRG3_RFEN (0x1u << 31) /**< \brief (PWM_ETRG3) Recoverable Fault Enable */\r
+/* -------- PWM_LEBR3 : (PWM Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) -------- */\r
+#define PWM_LEBR3_LEBDELAY_Pos 0\r
+#define PWM_LEBR3_LEBDELAY_Msk (0x7fu << PWM_LEBR3_LEBDELAY_Pos) /**< \brief (PWM_LEBR3) Leading-Edge Blanking Delay for TRGINx */\r
+#define PWM_LEBR3_LEBDELAY(value) ((PWM_LEBR3_LEBDELAY_Msk & ((value) << PWM_LEBR3_LEBDELAY_Pos)))\r
+#define PWM_LEBR3_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR3) PWML Falling Edge Enable */\r
+#define PWM_LEBR3_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR3) PWML Rising Edge Enable */\r
+#define PWM_LEBR3_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR3) PWMH Falling Edge Enable */\r
+#define PWM_LEBR3_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR3) PWMH Rising Edge Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_PWM_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_QSPI_COMPONENT_\r
+#define _SAM_QSPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_QSPI Quad Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Qspi hardware registers */\r
+typedef struct {\r
+ __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */\r
+ __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */\r
+ __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */\r
+ __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */\r
+ __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */\r
+ __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */\r
+ __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */\r
+ __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */\r
+ __I uint32_t Reserved1[3];\r
+ __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */\r
+ __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */\r
+ __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */\r
+ __IO uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */\r
+ __I uint32_t Reserved3[39];\r
+ __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */\r
+} Qspi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */\r
+#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */\r
+#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */\r
+#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */\r
+#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */\r
+/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */\r
+#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */\r
+#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI Mode. */\r
+#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory Mode. */\r
+#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */\r
+#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */\r
+#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */\r
+#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */\r
+#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */\r
+#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI Mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */\r
+#define QSPI_MR_CSMODE_Pos 4\r
+#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */\r
+#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */\r
+#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */\r
+#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */\r
+#define QSPI_MR_NBBITS_Pos 8\r
+#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */\r
+#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */\r
+#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */\r
+#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */\r
+#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */\r
+#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */\r
+#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */\r
+#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */\r
+#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */\r
+#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */\r
+#define QSPI_MR_DLYBCT_Pos 16\r
+#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */\r
+#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))\r
+#define QSPI_MR_DLYCS_Pos 24\r
+#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive NPCS Delay */\r
+#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))\r
+/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */\r
+#define QSPI_RDR_RD_Pos 0\r
+#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */\r
+/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define QSPI_TDR_TD_Pos 0\r
+#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */\r
+#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))\r
+/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */\r
+#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */\r
+#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */\r
+#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */\r
+#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */\r
+#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */\r
+#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */\r
+#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */\r
+#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */\r
+/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */\r
+#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */\r
+#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */\r
+#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */\r
+#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */\r
+#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */\r
+/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */\r
+#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */\r
+#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */\r
+#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */\r
+#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */\r
+#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */\r
+/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */\r
+#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */\r
+#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */\r
+#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */\r
+#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */\r
+#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */\r
+/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */\r
+#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */\r
+#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */\r
+#define QSPI_SCR_SCBR_Pos 8\r
+#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */\r
+#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))\r
+#define QSPI_SCR_DLYBS_Pos 16\r
+#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before SPCK */\r
+#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))\r
+/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */\r
+#define QSPI_IAR_ADDR_Pos 0\r
+#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */\r
+#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))\r
+/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */\r
+#define QSPI_ICR_INST_Pos 0\r
+#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */\r
+#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))\r
+#define QSPI_ICR_OPT_Pos 16\r
+#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */\r
+#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))\r
+/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */\r
+#define QSPI_IFR_WIDTH_Pos 0\r
+#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */\r
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */\r
+#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */\r
+#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */\r
+#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */\r
+#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */\r
+#define QSPI_IFR_OPTL_Pos 8\r
+#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */\r
+#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */\r
+#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */\r
+#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */\r
+#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */\r
+#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */\r
+#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */\r
+#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */\r
+#define QSPI_IFR_TFRTYP_Pos 12\r
+#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */\r
+#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */\r
+#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */\r
+#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read Mode is disabled. */\r
+#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read Mode is enabled. */\r
+#define QSPI_IFR_NBDUM_Pos 16\r
+#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */\r
+#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))\r
+/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */\r
+#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */\r
+#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */\r
+#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */\r
+#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */\r
+/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */\r
+#define QSPI_SKR_USRK_Pos 0\r
+#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */\r
+#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))\r
+/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */\r
+#define QSPI_WPMR_WPKEY_Pos 8\r
+#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */\r
+#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */\r
+#define QSPI_WPSR_WPVSRC_Pos 8\r
+#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */\r
+/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */\r
+#define QSPI_VERSION_VERSION_Pos 0\r
+#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */\r
+#define QSPI_VERSION_MFN_Pos 16\r
+#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_QSPI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RSTC_COMPONENT_\r
+#define _SAM_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */\r
+#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up Reset */\r
+#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */\r
+#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */\r
+#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */\r
+#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_ERSTL_Pos 8\r
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */\r
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */\r
+#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_RSTC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RTC_COMPONENT_\r
+#define _SAM_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief RtcTs hardware registers */\r
+typedef struct {\r
+ __I uint32_t RTC_TSTR; /**< \brief (RtcTs Offset: 0x0) TimeStamp Time Register 0 */\r
+ __I uint32_t RTC_TSDR; /**< \brief (RtcTs Offset: 0x4) TimeStamp Date Register 0 */\r
+ __I uint32_t RTC_TSSR; /**< \brief (RtcTs Offset: 0x8) TimeStamp Source Register 0 */\r
+} RtcTs;\r
+/** \brief Rtc hardware registers */\r
+#define RTCTS_NUMBER 2\r
+typedef struct {\r
+ __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+ __I uint32_t Reserved1[32];\r
+ RtcTs RTC_TS[RTCTS_NUMBER]; /**< \brief (Rtc Offset: 0xB0) 0 .. 1 */\r
+ __I uint32_t Reserved2[7];\r
+ __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t Reserved3[5];\r
+ __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */\r
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */\r
+#define RTC_MR_CORRECTION_Pos 8\r
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */\r
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))\r
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */\r
+#define RTC_MR_OUT0_Pos 16\r
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */\r
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_OUT1_Pos 20\r
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */\r
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_THIGH_Pos 24\r
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */\r
+#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */\r
+#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */\r
+#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */\r
+#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */\r
+#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */\r
+#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */\r
+#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */\r
+#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */\r
+#define RTC_MR_TPERIOD_Pos 28\r
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */\r
+#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */\r
+#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */\r
+#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */\r
+#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */\r
+#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */\r
+#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */\r
+#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */\r
+#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */\r
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */\r
+#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */\r
+#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+/* -------- RTC_TSTR : (RTC Offset: N/A) TimeStamp Time Register 0 -------- */\r
+#define RTC_TSTR_SEC_Pos 0\r
+#define RTC_TSTR_SEC_Msk (0x7fu << RTC_TSTR_SEC_Pos) /**< \brief (RTC_TSTR) SEConds of the tamper */\r
+#define RTC_TSTR_MIN_Pos 8\r
+#define RTC_TSTR_MIN_Msk (0x7fu << RTC_TSTR_MIN_Pos) /**< \brief (RTC_TSTR) MINutes of the tamper */\r
+#define RTC_TSTR_HOUR_Pos 16\r
+#define RTC_TSTR_HOUR_Msk (0x3fu << RTC_TSTR_HOUR_Pos) /**< \brief (RTC_TSTR) HOURs of the tamper */\r
+#define RTC_TSTR_AMPM (0x1u << 22) /**< \brief (RTC_TSTR) AMPM indicator of the tamper */\r
+#define RTC_TSTR_TEVCNT_Pos 24\r
+#define RTC_TSTR_TEVCNT_Msk (0xfu << RTC_TSTR_TEVCNT_Pos) /**< \brief (RTC_TSTR) Tamper events counter */\r
+#define RTC_TSTR_BACKUP (0x1u << 31) /**< \brief (RTC_TSTR) System mode of the tamper */\r
+/* -------- RTC_TSDR : (RTC Offset: N/A) TimeStamp Date Register 0 -------- */\r
+#define RTC_TSDR_CENT_Pos 0\r
+#define RTC_TSDR_CENT_Msk (0x7fu << RTC_TSDR_CENT_Pos) /**< \brief (RTC_TSDR) Century of the tamper */\r
+#define RTC_TSDR_YEAR_Pos 8\r
+#define RTC_TSDR_YEAR_Msk (0xffu << RTC_TSDR_YEAR_Pos) /**< \brief (RTC_TSDR) Year of the tamper */\r
+#define RTC_TSDR_MONTH_Pos 16\r
+#define RTC_TSDR_MONTH_Msk (0x1fu << RTC_TSDR_MONTH_Pos) /**< \brief (RTC_TSDR) Month of the tamper */\r
+#define RTC_TSDR_DAY_Pos 21\r
+#define RTC_TSDR_DAY_Msk (0x7u << RTC_TSDR_DAY_Pos) /**< \brief (RTC_TSDR) Day of the tamper */\r
+#define RTC_TSDR_DATE_Pos 24\r
+#define RTC_TSDR_DATE_Msk (0x3fu << RTC_TSDR_DATE_Pos) /**< \brief (RTC_TSDR) Date of the tamper */\r
+/* -------- RTC_TSSR : (RTC Offset: N/A) TimeStamp Source Register 0 -------- */\r
+#define RTC_TSSR_TSRC_Pos 0\r
+#define RTC_TSSR_TSRC_Msk (0x3u << RTC_TSSR_TSRC_Pos) /**< \brief (RTC_TSSR) Tamper Source */\r
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */\r
+#define RTC_WPMR_WPKEY_Pos 8\r
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protect KEY */\r
+#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */\r
+#define RTC_VERSION_VERSION_Pos 0\r
+#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */\r
+#define RTC_VERSION_MFN_Pos 16\r
+#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_RTC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RTT_COMPONENT_\r
+#define _SAM_RTT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_RTT Real-time Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtt hardware registers */\r
+typedef struct {\r
+ __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */\r
+ __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */\r
+ __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */\r
+ __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */\r
+} Rtt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */\r
+#define RTT_MR_RTPRES_Pos 0\r
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */\r
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))\r
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */\r
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */\r
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */\r
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */\r
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1 Hz Clock Selection */\r
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */\r
+#define RTT_AR_ALMV_Pos 0\r
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */\r
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))\r
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */\r
+#define RTT_VR_CRTV_Pos 0\r
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */\r
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */\r
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */\r
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_RTT_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SDRAMC_COMPONENT_\r
+#define _SAM_SDRAMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR SDRAM Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_SDRAMC SDRAM Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sdramc hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */\r
+ __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */\r
+ __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */\r
+ __IO uint32_t SDRAMC_HSR; /**< \brief (Sdramc Offset: 0x0C) SDRAMC High Speed Register */\r
+ __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */\r
+ __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */\r
+ __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */\r
+ __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */\r
+ __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */\r
+ __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */\r
+ __IO uint32_t SDRAMC_CR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */\r
+ __I uint32_t Reserved1[52];\r
+ __I uint32_t SDRAMC_VERSION; /**< \brief (Sdramc Offset: 0xFC) SDRAMC Version Register */\r
+} Sdramc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */\r
+#define SDRAMC_MR_MODE_Pos 0\r
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */\r
+#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */\r
+#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */\r
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */\r
+#define SDRAMC_TR_COUNT_Pos 0\r
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */\r
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))\r
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */\r
+#define SDRAMC_CR_NC_Pos 0\r
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */\r
+#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */\r
+#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */\r
+#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */\r
+#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */\r
+#define SDRAMC_CR_NR_Pos 2\r
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */\r
+#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */\r
+#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */\r
+#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */\r
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */\r
+#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */\r
+#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */\r
+#define SDRAMC_CR_CAS_Pos 5\r
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */\r
+#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */\r
+#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */\r
+#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */\r
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */\r
+#define SDRAMC_CR_TWR_Pos 8\r
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */\r
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))\r
+#define SDRAMC_CR_TRC_TRFC_Pos 12\r
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */\r
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))\r
+#define SDRAMC_CR_TRP_Pos 16\r
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */\r
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))\r
+#define SDRAMC_CR_TRCD_Pos 20\r
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */\r
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))\r
+#define SDRAMC_CR_TRAS_Pos 24\r
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */\r
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))\r
+#define SDRAMC_CR_TXSR_Pos 28\r
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */\r
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))\r
+/* -------- SDRAMC_HSR : (SDRAMC Offset: 0x0C) SDRAMC High Speed Register -------- */\r
+#define SDRAMC_HSR_DA (0x1u << 0) /**< \brief (SDRAMC_HSR) Decode Cycle Enable */\r
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */\r
+#define SDRAMC_LPR_LPCB_Pos 0\r
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */\r
+#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */\r
+#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */\r
+#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */\r
+#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */\r
+#define SDRAMC_LPR_PASR_Pos 4\r
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))\r
+#define SDRAMC_LPR_TCSR_Pos 8\r
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))\r
+#define SDRAMC_LPR_DS_Pos 10\r
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))\r
+#define SDRAMC_LPR_TIMEOUT_Pos 12\r
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */\r
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */\r
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */\r
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */\r
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */\r
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */\r
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */\r
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */\r
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */\r
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */\r
+#define SDRAMC_MDR_MD_Pos 0\r
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */\r
+#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */\r
+#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */\r
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */\r
+#define SDRAMC_CR1_NC_Pos 0\r
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */\r
+#define SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */\r
+#define SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */\r
+#define SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */\r
+#define SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */\r
+#define SDRAMC_CR1_NR_Pos 2\r
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */\r
+#define SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */\r
+#define SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */\r
+#define SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */\r
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */\r
+#define SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */\r
+#define SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */\r
+#define SDRAMC_CR1_CAS_Pos 5\r
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */\r
+#define SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */\r
+#define SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */\r
+#define SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */\r
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */\r
+#define SDRAMC_CR1_TWR_Pos 8\r
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */\r
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))\r
+#define SDRAMC_CR1_TRC_TRFC_Pos 12\r
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */\r
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))\r
+#define SDRAMC_CR1_TRP_Pos 16\r
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */\r
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))\r
+#define SDRAMC_CR1_TRCD_Pos 20\r
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */\r
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))\r
+#define SDRAMC_CR1_TRAS_Pos 24\r
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */\r
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))\r
+#define SDRAMC_CR1_TXSR_Pos 28\r
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */\r
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))\r
+/* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */\r
+#define SDRAMC_VERSION_VERSION_Pos 0\r
+#define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos) /**< \brief (SDRAMC_VERSION) */\r
+#define SDRAMC_VERSION_MFN_Pos 16\r
+#define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos) /**< \brief (SDRAMC_VERSION) */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_SDRAMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SMC_COMPONENT_\r
+#define _SAM_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */\r
+ __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */\r
+ __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */\r
+ __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief Smc hardware registers */\r
+#define SMCCS_NUMBER_NUMBER 4\r
+typedef struct {\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */\r
+ __I uint32_t Reserved1[16];\r
+ __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */\r
+ __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */\r
+ __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */\r
+ __I uint32_t Reserved2[22];\r
+ __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */\r
+ __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */\r
+ __I uint32_t SMC_ADDRSIZE; /**< \brief (Smc Offset: 0xEC) SMC Address Size Register */\r
+ __I uint32_t SMC_IPNAME[2]; /**< \brief (Smc Offset: 0xF0) SMC IP Name 1 Register */\r
+ __I uint32_t SMC_FEATURES; /**< \brief (Smc Offset: 0xF8) SMC Features Register */\r
+ __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */\r
+#define SMC_SETUP_NWE_SETUP_Pos 0\r
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */\r
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */\r
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define SMC_SETUP_NRD_SETUP_Pos 16\r
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */\r
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */\r
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */\r
+#define SMC_PULSE_NWE_PULSE_Pos 0\r
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */\r
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define SMC_PULSE_NRD_PULSE_Pos 16\r
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */\r
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */\r
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */\r
+#define SMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */\r
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define SMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */\r
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */\r
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_EXNW_MODE_Pos 4\r
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */\r
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */\r
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */\r
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */\r
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */\r
+#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */\r
+#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */\r
+#define SMC_MODE_TDF_CYCLES_Pos 16\r
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */\r
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))\r
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */\r
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */\r
+#define SMC_MODE_PS_Pos 28\r
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */\r
+#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */\r
+#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */\r
+#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */\r
+#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */\r
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */\r
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */\r
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */\r
+#define SMC_KEY1_KEY1_Pos 0\r
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))\r
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */\r
+#define SMC_KEY2_KEY2_Pos 0\r
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))\r
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */\r
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */\r
+#define SMC_WPMR_WPKEY_Pos 8\r
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */\r
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))\r
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */\r
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */\r
+#define SMC_WPSR_WPVSRC_Pos 8\r
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */\r
+/* -------- SMC_ADDRSIZE : (SMC Offset: 0xEC) SMC Address Size Register -------- */\r
+#define SMC_ADDRSIZE_ADDRSIZE_Pos 0\r
+#define SMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << SMC_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (SMC_ADDRSIZE) User Interface Address Size */\r
+/* -------- SMC_IPNAME[2] : (SMC Offset: 0xF0) SMC IP Name 1 Register -------- */\r
+#define SMC_IPNAME_IPNAME_Pos 0\r
+#define SMC_IPNAME_IPNAME_Msk (0xffffffffu << SMC_IPNAME_IPNAME_Pos) /**< \brief (SMC_IPNAME[2]) ASCII Report of the IP Name */\r
+/* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */\r
+#define SMC_VERSION_VERSION_Pos 0\r
+#define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */\r
+#define SMC_VERSION_MFN_Pos 16\r
+#define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_SMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SPI_COMPONENT_\r
+#define _SAM_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ __I uint32_t Reserved1[4];\r
+ __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ __I uint32_t Reserved2[41];\r
+ __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */\r
+ __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved3[4];\r
+ __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0x00FC) Version Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protect Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protect Key */\r
+#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_VERSION : (SPI Offset: 0x00FC) Version Register -------- */\r
+#define SPI_VERSION_VERSION_Pos 0\r
+#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */\r
+#define SPI_VERSION_MFN_Pos 16\r
+#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_SPI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SSC_COMPONENT_\r
+#define _SAM_SSC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_SSC Synchronous Serial Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Ssc hardware registers */\r
+typedef struct {\r
+ __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */\r
+ __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */\r
+ __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */\r
+ __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */\r
+ __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */\r
+ __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */\r
+ __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */\r
+ __I uint32_t Reserved2[2];\r
+ __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */\r
+ __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */\r
+ __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */\r
+ __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */\r
+ __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */\r
+ __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */\r
+ __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */\r
+ __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */\r
+ __I uint32_t Reserved3[37];\r
+ __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */\r
+ __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */\r
+} Ssc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */\r
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */\r
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */\r
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */\r
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */\r
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */\r
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */\r
+#define SSC_CMR_DIV_Pos 0\r
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */\r
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))\r
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */\r
+#define SSC_RCMR_CKS_Pos 0\r
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */\r
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */\r
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */\r
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */\r
+#define SSC_RCMR_CKO_Pos 2\r
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */\r
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */\r
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */\r
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */\r
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */\r
+#define SSC_RCMR_CKG_Pos 6\r
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */\r
+#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */\r
+#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */\r
+#define SSC_RCMR_START_Pos 8\r
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */\r
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */\r
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */\r
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */\r
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */\r
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */\r
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */\r
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */\r
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */\r
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */\r
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */\r
+#define SSC_RCMR_STTDLY_Pos 16\r
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */\r
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))\r
+#define SSC_RCMR_PERIOD_Pos 24\r
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */\r
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))\r
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */\r
+#define SSC_RFMR_DATLEN_Pos 0\r
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */\r
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))\r
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */\r
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */\r
+#define SSC_RFMR_DATNB_Pos 8\r
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */\r
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))\r
+#define SSC_RFMR_FSLEN_Pos 16\r
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */\r
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))\r
+#define SSC_RFMR_FSOS_Pos 20\r
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */\r
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */\r
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */\r
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */\r
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */\r
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */\r
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */\r
+#define SSC_RFMR_FSLEN_EXT_Pos 28\r
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */\r
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */\r
+#define SSC_TCMR_CKS_Pos 0\r
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */\r
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */\r
+#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */\r
+#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */\r
+#define SSC_TCMR_CKO_Pos 2\r
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */\r
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */\r
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */\r
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */\r
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */\r
+#define SSC_TCMR_CKG_Pos 6\r
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */\r
+#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */\r
+#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */\r
+#define SSC_TCMR_START_Pos 8\r
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */\r
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data */\r
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */\r
+#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */\r
+#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */\r
+#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */\r
+#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */\r
+#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */\r
+#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */\r
+#define SSC_TCMR_STTDLY_Pos 16\r
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */\r
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))\r
+#define SSC_TCMR_PERIOD_Pos 24\r
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */\r
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))\r
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */\r
+#define SSC_TFMR_DATLEN_Pos 0\r
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */\r
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))\r
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */\r
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */\r
+#define SSC_TFMR_DATNB_Pos 8\r
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */\r
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))\r
+#define SSC_TFMR_FSLEN_Pos 16\r
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */\r
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))\r
+#define SSC_TFMR_FSOS_Pos 20\r
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */\r
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, RF pin is an input */\r
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, RF pin is an output */\r
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, RF pin is an output */\r
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */\r
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */\r
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */\r
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */\r
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */\r
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */\r
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */\r
+#define SSC_TFMR_FSLEN_EXT_Pos 28\r
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */\r
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */\r
+#define SSC_RHR_RDAT_Pos 0\r
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */\r
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */\r
+#define SSC_THR_TDAT_Pos 0\r
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */\r
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))\r
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */\r
+#define SSC_RSHR_RSDAT_Pos 0\r
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */\r
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */\r
+#define SSC_TSHR_TSDAT_Pos 0\r
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */\r
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))\r
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */\r
+#define SSC_RC0R_CP0_Pos 0\r
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */\r
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))\r
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */\r
+#define SSC_RC1R_CP1_Pos 0\r
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */\r
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))\r
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */\r
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */\r
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */\r
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */\r
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */\r
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */\r
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */\r
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */\r
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */\r
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */\r
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */\r
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */\r
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */\r
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */\r
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */\r
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */\r
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */\r
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */\r
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */\r
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */\r
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */\r
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */\r
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */\r
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */\r
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */\r
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */\r
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */\r
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */\r
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */\r
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */\r
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */\r
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */\r
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */\r
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */\r
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */\r
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */\r
+#define SSC_WPMR_WPKEY_Pos 8\r
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */\r
+#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */\r
+#define SSC_VERSION_VERSION_Pos 0\r
+#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */\r
+#define SSC_VERSION_MFN_Pos 16\r
+#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_SSC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SUPC_COMPONENT_\r
+#define _SAM_SUPC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Supply Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_SUPC Supply Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Supc hardware registers */\r
+typedef struct {\r
+ __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */\r
+ __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */\r
+ __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */\r
+ __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */\r
+ __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */\r
+ __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */\r
+ __I uint32_t Reserved1[57];\r
+ __I uint32_t SYSC_VERSION; /**< \brief (Supc Offset: 0xFC) Version Register */\r
+} Supc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */\r
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */\r
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */\r
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. */\r
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */\r
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */\r
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, switches the slow clock on the crystal oscillator output. */\r
+#define SUPC_CR_KEY_Pos 24\r
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */\r
+#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */\r
+#define SUPC_SMMR_SMTH_Pos 0\r
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */\r
+#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))\r
+#define SUPC_SMMR_SMSMPL_Pos 8\r
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */\r
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */\r
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */\r
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */\r
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */\r
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */\r
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */\r
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */\r
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */\r
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */\r
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */\r
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */\r
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */\r
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */\r
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */\r
+#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */\r
+#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */\r
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */\r
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on XTALSEL value. */\r
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is selected and put in bypass mode. */\r
+#define SUPC_MR_KEY_Pos 24\r
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */\r
+#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */\r
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */\r
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */\r
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */\r
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */\r
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */\r
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */\r
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */\r
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */\r
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low Power Debouncer Enable WKUP0 */\r
+#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected with low power debouncer and can force a core wake-up. */\r
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low Power Debouncer Enable WKUP1 */\r
+#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected with low power debouncer and can force a core wake-up. */\r
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low Power Debouncer Clear */\r
+#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low power debounce event does not create an immediate clear on the first half of GPBR registers. */\r
+#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */\r
+#define SUPC_WUMR_WKUPDBC_Pos 12\r
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */\r
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_LPDBC_Pos 16\r
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power Debouncer Period */\r
+#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncers. */\r
+#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUT0 periods */\r
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */\r
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */\r
+#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */\r
+#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */\r
+#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */\r
+#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */\r
+#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */\r
+#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */\r
+#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */\r
+#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */\r
+#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */\r
+#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */\r
+#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */\r
+#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */\r
+#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */\r
+#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */\r
+#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */\r
+#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */\r
+#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */\r
+#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */\r
+#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */\r
+#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */\r
+#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */\r
+#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */\r
+#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */\r
+#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */\r
+#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */\r
+#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */\r
+#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */\r
+#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */\r
+#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */\r
+#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */\r
+#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */\r
+#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */\r
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */\r
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */\r
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status */\r
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */\r
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */\r
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */\r
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */\r
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */\r
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */\r
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */\r
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK is generated by the embedded 32 kHz RC oscillator. */\r
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK is generated by the 32 kHz crystal oscillator. */\r
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP0 */\r
+#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake-up Status on WKUP1 */\r
+#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */\r
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */\r
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */\r
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */\r
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */\r
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */\r
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */\r
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */\r
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */\r
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */\r
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */\r
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */\r
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */\r
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */\r
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */\r
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */\r
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+/* -------- SYSC_VERSION : (SUPC Offset: 0xFC) Version Register -------- */\r
+#define SYSC_VERSION_VERSION_Pos 0\r
+#define SYSC_VERSION_VERSION_Msk (0xfffu << SYSC_VERSION_VERSION_Pos) /**< \brief (SYSC_VERSION) Version of the Hardware Module */\r
+#define SYSC_VERSION_MFN_Pos 16\r
+#define SYSC_VERSION_MFN_Msk (0x7u << SYSC_VERSION_MFN_Pos) /**< \brief (SYSC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_SUPC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TC_COMPONENT_\r
+#define _SAM_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */\r
+ __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */\r
+ __I uint32_t Reserved1[3];\r
+} TcChannel;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t Reserved2[5];\r
+ __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_SBSMPLR_Pos 20\r
+#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */\r
+#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */\r
+#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */\r
+#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */\r
+#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */\r
+#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */\r
+/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */\r
+#define TC_RAB_RAB_Pos 0\r
+#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */\r
+#define TC_EMR_TRIGSRCA_Pos 0\r
+#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input A */\r
+#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */\r
+#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */\r
+#define TC_EMR_TRIGSRCB_Pos 4\r
+#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) TRIGger SouRCe for input B */\r
+#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */\r
+#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */\r
+#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) NO DIVided CLocK */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */\r
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) Glitch Filter */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */\r
+#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */\r
+#define TC_VER_VERSION_Pos 0\r
+#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */\r
+#define TC_VER_MFN_Pos 16\r
+#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_TC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TRNG_COMPONENT_\r
+#define _SAM_TRNG_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR True Random Number Generator */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_TRNG True Random Number Generator */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Trng hardware registers */\r
+typedef struct {\r
+ __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */\r
+ __I uint32_t Reserved1[3];\r
+ __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */\r
+ __I uint32_t Reserved2[12];\r
+ __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */\r
+ __I uint32_t Reserved3[42];\r
+ __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */\r
+} Trng;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */\r
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */\r
+#define TRNG_CR_KEY_Pos 8\r
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */\r
+#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */\r
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */\r
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */\r
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */\r
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */\r
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */\r
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */\r
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */\r
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */\r
+#define TRNG_ODATA_ODATA_Pos 0\r
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */\r
+/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */\r
+#define TRNG_VERSION_VERSION_Pos 0\r
+#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */\r
+#define TRNG_VERSION_MFN_Pos 16\r
+#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_TRNG_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TWI_COMPONENT_\r
+#define _SAM_TWI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_TWI Two-wire Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */\r
+ __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */\r
+ __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */\r
+ __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */\r
+ __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */\r
+ __I uint32_t Reserved1[3];\r
+ __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */\r
+ __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */\r
+ __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */\r
+ __I uint32_t Reserved2[43];\r
+ __IO uint32_t TWI_WPMR; /**< \brief (Twi Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t TWI_WPSR; /**< \brief (Twi Offset: 0xE8) Write Protection Status Register */\r
+} Twi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+#define TWI_CWGR_HOLD_Pos 24\r
+#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time versus TWCK falling */\r
+#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))\r
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */\r
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+/* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */\r
+#define TWI_WPMR_WPKEY_Pos 8\r
+#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */\r
+#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protection Violation Status */\r
+#define TWI_WPSR_WPVSRC_Pos 8\r
+#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_TWI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TWIHS_COMPONENT_\r
+#define _SAM_TWIHS_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_TWIHS Two-wire Interface High Speed */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twihs hardware registers */\r
+typedef struct {\r
+ __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */\r
+ __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */\r
+ __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */\r
+ __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */\r
+ __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */\r
+ __I uint32_t Reserved1[3];\r
+ __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */\r
+ __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */\r
+ __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */\r
+ __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t TWIHS_ACR; /**< \brief (Twihs Offset: 0x40) Alternative Command Register */\r
+ __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */\r
+ __I uint32_t Reserved3[1];\r
+ __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */\r
+ __I uint32_t Reserved4[32];\r
+ __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */\r
+ __I uint32_t Reserved5[4];\r
+ __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Protection Mode Register */\r
+ __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Protection Status Register */\r
+ __I uint32_t Reserved6[4];\r
+ __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */\r
+} Twihs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */\r
+#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */\r
+#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */\r
+#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWI Master Mode Enabled */\r
+#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWI Master Mode Disabled */\r
+#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWI Slave Mode Enabled */\r
+#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWI Slave Mode Disabled */\r
+#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBUS Quick Command */\r
+#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */\r
+#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWI High-Speed Mode Enabled */\r
+#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWI High-Speed Mode Disabled */\r
+#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */\r
+#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */\r
+#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */\r
+#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */\r
+#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */\r
+#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */\r
+#define TWIHS_CR_ACMEN (0x1u << 16) /**< \brief (TWIHS_CR) Alternative Command Mode Enable */\r
+#define TWIHS_CR_ACMDIS (0x1u << 17) /**< \brief (TWIHS_CR) Alternative Command Mode Disable */\r
+/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */\r
+#define TWIHS_MMR_IADRSZ_Pos 8\r
+#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */\r
+#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */\r
+#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */\r
+#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */\r
+#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */\r
+#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */\r
+#define TWIHS_MMR_DADR_Pos 16\r
+#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */\r
+#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))\r
+/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */\r
+#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */\r
+#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */\r
+#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */\r
+#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */\r
+#define TWIHS_SMR_MASK_Pos 8\r
+#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */\r
+#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))\r
+#define TWIHS_SMR_SADR_Pos 16\r
+#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */\r
+#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))\r
+#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */\r
+#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */\r
+#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */\r
+#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */\r
+/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */\r
+#define TWIHS_IADR_IADR_Pos 0\r
+#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */\r
+#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))\r
+/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWIHS_CWGR_CLDIV_Pos 0\r
+#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */\r
+#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))\r
+#define TWIHS_CWGR_CHDIV_Pos 8\r
+#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */\r
+#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))\r
+#define TWIHS_CWGR_CKDIV_Pos 16\r
+#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */\r
+#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))\r
+#define TWIHS_CWGR_HOLD_Pos 24\r
+#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */\r
+#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))\r
+/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */\r
+#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (automatically set / reset) */\r
+#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read (automatically set / reset) */\r
+#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access (automatically set / reset) */\r
+#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (clear on read) */\r
+#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (clear on read) */\r
+#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (clear on read) */\r
+#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (clear on read) */\r
+#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (clear on read) */\r
+#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State (automatically set / reset) */\r
+#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (clear on read) */\r
+#define TWIHS_SR_ENDRX (0x1u << 12) /**< \brief (TWIHS_SR) End of RX Buffer */\r
+#define TWIHS_SR_ENDTX (0x1u << 13) /**< \brief (TWIHS_SR) End of TX Buffer */\r
+#define TWIHS_SR_RXBUFF (0x1u << 14) /**< \brief (TWIHS_SR) RX Buffer Full */\r
+#define TWIHS_SR_TXBUFE (0x1u << 15) /**< \brief (TWIHS_SR) TX Buffer Empty */\r
+#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge */\r
+#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error */\r
+#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error */\r
+#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match */\r
+#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match */\r
+#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */\r
+#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */\r
+/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */\r
+#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */\r
+#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */\r
+#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */\r
+#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */\r
+#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */\r
+#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */\r
+#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */\r
+#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */\r
+#define TWIHS_IER_ENDRX (0x1u << 12) /**< \brief (TWIHS_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWIHS_IER_ENDTX (0x1u << 13) /**< \brief (TWIHS_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWIHS_IER_RXBUFF (0x1u << 14) /**< \brief (TWIHS_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWIHS_IER_TXBUFE (0x1u << 15) /**< \brief (TWIHS_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */\r
+#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */\r
+#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */\r
+#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */\r
+#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */\r
+/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */\r
+#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */\r
+#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */\r
+#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */\r
+#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */\r
+#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */\r
+#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWIHS_IDR_ENDRX (0x1u << 12) /**< \brief (TWIHS_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWIHS_IDR_ENDTX (0x1u << 13) /**< \brief (TWIHS_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWIHS_IDR_RXBUFF (0x1u << 14) /**< \brief (TWIHS_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWIHS_IDR_TXBUFE (0x1u << 15) /**< \brief (TWIHS_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */\r
+#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */\r
+#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */\r
+#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */\r
+#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */\r
+/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */\r
+#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */\r
+#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */\r
+#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */\r
+#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */\r
+#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */\r
+#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWIHS_IMR_ENDRX (0x1u << 12) /**< \brief (TWIHS_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWIHS_IMR_ENDTX (0x1u << 13) /**< \brief (TWIHS_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWIHS_IMR_RXBUFF (0x1u << 14) /**< \brief (TWIHS_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWIHS_IMR_TXBUFE (0x1u << 15) /**< \brief (TWIHS_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */\r
+#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */\r
+#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */\r
+#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */\r
+#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */\r
+/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */\r
+#define TWIHS_RHR_RXDATA_Pos 0\r
+#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWIHS_THR_TXDATA_Pos 0\r
+#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */\r
+#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))\r
+/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */\r
+#define TWIHS_SMBTR_PRESC_Pos 0\r
+#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */\r
+#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))\r
+#define TWIHS_SMBTR_TLOWS_Pos 8\r
+#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */\r
+#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))\r
+#define TWIHS_SMBTR_TLOWM_Pos 16\r
+#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */\r
+#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))\r
+#define TWIHS_SMBTR_THMAX_Pos 24\r
+#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */\r
+#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))\r
+/* -------- TWIHS_ACR : (TWIHS Offset: 0x40) Alternative Command Register -------- */\r
+#define TWIHS_ACR_DATAL_Pos 0\r
+#define TWIHS_ACR_DATAL_Msk (0xffu << TWIHS_ACR_DATAL_Pos) /**< \brief (TWIHS_ACR) Data Length */\r
+#define TWIHS_ACR_DATAL(value) ((TWIHS_ACR_DATAL_Msk & ((value) << TWIHS_ACR_DATAL_Pos)))\r
+#define TWIHS_ACR_DIR (0x1u << 8) /**< \brief (TWIHS_ACR) Transfer Direction */\r
+#define TWIHS_ACR_PEC (0x1u << 9) /**< \brief (TWIHS_ACR) PEC Request (SMBus Mode only) */\r
+#define TWIHS_ACR_NDATAL_Pos 16\r
+#define TWIHS_ACR_NDATAL_Msk (0xffu << TWIHS_ACR_NDATAL_Pos) /**< \brief (TWIHS_ACR) Next Data Length */\r
+#define TWIHS_ACR_NDATAL(value) ((TWIHS_ACR_NDATAL_Msk & ((value) << TWIHS_ACR_NDATAL_Pos)))\r
+#define TWIHS_ACR_NDIR (0x1u << 24) /**< \brief (TWIHS_ACR) Next Transfer Direction */\r
+#define TWIHS_ACR_NPEC (0x1u << 25) /**< \brief (TWIHS_ACR) Next PEC Request (SMBus Mode only) */\r
+/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */\r
+#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */\r
+#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */\r
+#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */\r
+#define TWIHS_FILTR_THRES_Pos 8\r
+#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */\r
+#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))\r
+/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */\r
+#define TWIHS_SWMR_SADR1_Pos 0\r
+#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */\r
+#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))\r
+#define TWIHS_SWMR_SADR2_Pos 8\r
+#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */\r
+#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))\r
+#define TWIHS_SWMR_SADR3_Pos 16\r
+#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */\r
+#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))\r
+#define TWIHS_SWMR_DATAM_Pos 24\r
+#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */\r
+#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))\r
+/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */\r
+#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */\r
+#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */\r
+#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */\r
+#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */\r
+/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Protection Mode Register -------- */\r
+#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */\r
+#define TWIHS_WPMR_WPKEY_Pos 8\r
+#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */\r
+#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Protection Status Register -------- */\r
+#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protect Violation Status */\r
+#define TWIHS_WPSR_WPVSRC_Pos 8\r
+#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */\r
+/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */\r
+#define TWIHS_VER_VERSION_Pos 0\r
+#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */\r
+#define TWIHS_VER_MFN_Pos 16\r
+#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_TWIHS_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART_COMPONENT_\r
+#define _SAM_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */\r
+ __I uint32_t Reserved1[47];\r
+ __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */\r
+#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */\r
+#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */\r
+#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */\r
+#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */\r
+#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral MCK */\r
+#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC Programmable clock PCK (see PMC section). */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */\r
+#define UART_CMPR_VAL1_Pos 0\r
+#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */\r
+#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))\r
+#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */\r
+#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */\r
+#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */\r
+#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */\r
+#define UART_CMPR_VAL2_Pos 16\r
+#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */\r
+#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))\r
+/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */\r
+#define UART_WPMR_WPKEY_Pos 8\r
+#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */\r
+#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_UART_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UOTGHS_COMPONENT_\r
+#define _SAM_UOTGHS_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_UOTGHS USB On-The-Go Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief UotghsDevdma hardware registers */\r
+typedef struct {\r
+ __IO uint32_t UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */\r
+ __IO uint32_t UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */\r
+ __IO uint32_t UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */\r
+ __IO uint32_t UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */\r
+} UotghsDevdma;\r
+/** \brief UotghsHstdma hardware registers */\r
+typedef struct {\r
+ __IO uint32_t UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */\r
+ __IO uint32_t UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */\r
+ __IO uint32_t UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */\r
+ __IO uint32_t UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */\r
+} UotghsHstdma;\r
+/** \brief Uotghs hardware registers */\r
+#define UOTGHSDEVDMA_NUMBER 7\r
+#define UOTGHSHSTDMA_NUMBER 7\r
+typedef struct {\r
+ __IO uint32_t UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */\r
+ __I uint32_t UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */\r
+ __O uint32_t UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */\r
+ __O uint32_t UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */\r
+ __I uint32_t UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */\r
+ __O uint32_t UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */\r
+ __O uint32_t UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */\r
+ __IO uint32_t UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */\r
+ __I uint32_t UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */\r
+ __I uint32_t Reserved1[55];\r
+ __IO uint32_t UOTGHS_DEVEPTCFG[12]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */\r
+ __I uint32_t UOTGHS_DEVEPTISR[12]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */\r
+ __O uint32_t UOTGHS_DEVEPTICR[12]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */\r
+ __O uint32_t UOTGHS_DEVEPTIFR[12]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */\r
+ __I uint32_t UOTGHS_DEVEPTIMR[12]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */\r
+ __O uint32_t UOTGHS_DEVEPTIER[12]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */\r
+ __O uint32_t UOTGHS_DEVEPTIDR[12]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */\r
+ __I uint32_t Reserved2[48];\r
+ UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */\r
+ __I uint32_t Reserved3[32];\r
+ __IO uint32_t UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */\r
+ __I uint32_t UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */\r
+ __O uint32_t UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */\r
+ __O uint32_t UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */\r
+ __I uint32_t UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */\r
+ __O uint32_t UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */\r
+ __O uint32_t UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */\r
+ __IO uint32_t UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */\r
+ __IO uint32_t UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */\r
+ __IO uint32_t UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */\r
+ __IO uint32_t UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */\r
+ __IO uint32_t UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */\r
+ __I uint32_t Reserved4[52];\r
+ __IO uint32_t UOTGHS_HSTPIPCFG[12]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */\r
+ __I uint32_t UOTGHS_HSTPIPISR[12]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */\r
+ __O uint32_t UOTGHS_HSTPIPICR[12]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */\r
+ __O uint32_t UOTGHS_HSTPIPIFR[12]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */\r
+ __I uint32_t UOTGHS_HSTPIPIMR[12]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */\r
+ __O uint32_t UOTGHS_HSTPIPIER[12]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */\r
+ __O uint32_t UOTGHS_HSTPIPIDR[12]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */\r
+ __IO uint32_t UOTGHS_HSTPIPINRQ[12]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */\r
+ __IO uint32_t UOTGHS_HSTPIPERR[12]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */\r
+ __I uint32_t Reserved5[24];\r
+ UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */\r
+ __I uint32_t Reserved6[32];\r
+ __IO uint32_t UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */\r
+ __I uint32_t UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */\r
+ __O uint32_t UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */\r
+ __O uint32_t UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */\r
+ __IO uint32_t UOTGHS_TSTA1; /**< \brief (Uotghs Offset: 0x0810) General Test A1 Register */\r
+ __IO uint32_t UOTGHS_TSTA2; /**< \brief (Uotghs Offset: 0x0814) General Test A2 Register */\r
+ __I uint32_t UOTGHS_VERSION; /**< \brief (Uotghs Offset: 0x0818) General Version Register */\r
+ __I uint32_t UOTGHS_FEATURES; /**< \brief (Uotghs Offset: 0x081C) General Features Register */\r
+ __I uint32_t UOTGHS_ADDRSIZE; /**< \brief (Uotghs Offset: 0x0820) General APB Address Size Register */\r
+ __I uint32_t UOTGHS_IPNAME1; /**< \brief (Uotghs Offset: 0x0824) General Name Register 1 */\r
+ __I uint32_t UOTGHS_IPNAME2; /**< \brief (Uotghs Offset: 0x0828) General Name Register 2 */\r
+ __I uint32_t UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */\r
+} Uotghs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */\r
+#define UOTGHS_DEVCTRL_UADD_Pos 0\r
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */\r
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))\r
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */\r
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */\r
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */\r
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10\r
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */\r
+#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */\r
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */\r
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */\r
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */\r
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */\r
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */\r
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */\r
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */\r
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */\r
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */\r
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */\r
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */\r
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */\r
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */\r
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVISR) Endpoint 10 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVISR) Endpoint 11 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVISR) DMA Channel 7 Interrupt */\r
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */\r
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */\r
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */\r
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */\r
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */\r
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */\r
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */\r
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */\r
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */\r
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */\r
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */\r
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */\r
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */\r
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */\r
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */\r
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIFR) DMA Channel 7 Interrupt Set */\r
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */\r
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */\r
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */\r
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */\r
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */\r
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */\r
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */\r
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIMR) Endpoint 10 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIMR) Endpoint 11 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIMR) DMA Channel 7 Interrupt Mask */\r
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */\r
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */\r
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */\r
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */\r
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */\r
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */\r
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */\r
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIDR) Endpoint 10 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIDR) Endpoint 11 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIDR) DMA Channel 7 Interrupt Disable */\r
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */\r
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */\r
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */\r
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */\r
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */\r
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */\r
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */\r
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIER) Endpoint 10 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIER) Endpoint 11 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIER) DMA Channel 7 Interrupt Enable */\r
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */\r
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */\r
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */\r
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */\r
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */\r
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */\r
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */\r
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */\r
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */\r
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */\r
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */\r
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */\r
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */\r
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */\r
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */\r
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */\r
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */\r
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */\r
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */\r
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */\r
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0\r
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */\r
+#define UOTGHS_DEVFNUM_FNUM_Pos 3\r
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */\r
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */\r
+/* -------- UOTGHS_DEVEPTCFG[12] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Memory Allocate */\r
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2\r
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Banks */\r
+#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Single-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Double-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Triple-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Size */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 8 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 16 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 32 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 64 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 128 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 256 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 512 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 1024 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Direction */\r
+#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is OUT. */\r
+#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is IN (nor for control endpoints). */\r
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[12]) Automatic Switch */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Type */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Control */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Isochronous */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Bulk */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Interrupt */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Number of transaction per microframe for isochronous endpoint */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) default value: one transaction per micro-frame. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */\r
+/* -------- UOTGHS_DEVEPTISR[12] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[12]) Transmitted IN Data Interrupt */\r
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[12]) Received OUT Data Interrupt */\r
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Received SETUP Interrupt */\r
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed OUT Interrupt */\r
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed IN Interrupt */\r
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[12]) Overflow Interrupt */\r
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) STALLed Interrupt */\r
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[12]) Short Packet Interrupt */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8\r
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Data Toggle Sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data0 toggle sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data1 toggle sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Number of Busy Banks */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 0 busy bank (all banks free) */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 1 busy bank */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 2 busy banks */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 3 busy banks */\r
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14\r
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Current Bank */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank0 */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank1 */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank2 */\r
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[12]) Read-write Allowed */\r
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[12]) Control Direction */\r
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[12]) Configuration OK Status */\r
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20\r
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Byte Count */\r
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Underflow Interrupt */\r
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Underflow Error Interrupt */\r
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Flush Interrupt */\r
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) CRC Error Interrupt */\r
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[12]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */\r
+/* -------- UOTGHS_DEVEPTICR[12] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[12]) Transmitted IN Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[12]) Received OUT Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Received SETUP Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed OUT Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[12]) Overflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) STALLed Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[12]) Short Packet Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Underflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) High bandwidth isochronous IN Underflow Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) CRC Error Interrupt Clear */\r
+/* -------- UOTGHS_DEVEPTIFR[12] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[12]) Transmitted IN Data Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received OUT Data Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received SETUP Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed OUT Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed IN Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[12]) Overflow Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) STALLed Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[12]) Short Packet Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[12]) Number of Busy Banks Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Underflow Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) High bandwidth isochronous IN Underflow Error Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) High Bandwidth Isochronous IN Flush Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) CRC Error Interrupt Set */\r
+/* -------- UOTGHS_DEVEPTIMR[12] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transmitted IN Data Interrupt */\r
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received OUT Data Interrupt */\r
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received SETUP Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed OUT Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed IN Interrupt */\r
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[12]) Overflow Interrupt */\r
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALLed Interrupt */\r
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[12]) Short Packet Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[12]) Number of Busy Banks Interrupt */\r
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[12]) Kill IN Bank */\r
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[12]) FIFO Control */\r
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[12]) Endpoint Interrupts Disable HDMA Request */\r
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[12]) NYET Token Disable */\r
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[12]) Reset Data Toggle */\r
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALL Request */\r
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Underflow Interrupt */\r
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Error Interrupt */\r
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Flush Interrupt */\r
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) CRC Error Interrupt */\r
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[12]) MData Interrupt */\r
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[12]) DataX Interrupt */\r
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transaction Error Interrupt */\r
+/* -------- UOTGHS_DEVEPTIER[12] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[12]) Transmitted IN Data Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[12]) Received OUT Data Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Received SETUP Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed OUT Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed IN Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[12]) Overflow Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) STALLed Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[12]) Short Packet Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[12]) Number of Busy Banks Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[12]) Kill IN Bank */\r
+#define UOTGHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIER[12]) FIFO Control */\r
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[12]) Endpoint Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[12]) NYET Token Disable Enable */\r
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[12]) Reset Data Toggle Enable */\r
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[12]) STALL Request Enable */\r
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Underflow Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Error Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Flush Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) CRC Error Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[12]) MData Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[12]) DataX Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[12]) Transaction Error Interrupt Enable */\r
+/* -------- UOTGHS_DEVEPTIDR[12] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transmitted IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received OUT Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received SETUP Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed OUT Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[12]) Overflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALLed Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[12]) Shortpacket Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[12]) Number of Busy Banks Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[12]) FIFO Control Clear */\r
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[12]) Endpoint Interrupts Disable HDMA Request Clear */\r
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[12]) NYET Token Disable Clear */\r
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALL Request Clear */\r
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Underflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) CRC Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[12]) MData Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[12]) DataX Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transaction Error Interrupt Clear */\r
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))\r
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))\r
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */\r
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */\r
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */\r
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */\r
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */\r
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))\r
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */\r
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */\r
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */\r
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */\r
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */\r
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))\r
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */\r
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */\r
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */\r
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */\r
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12\r
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */\r
+#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */\r
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */\r
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */\r
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */\r
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */\r
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */\r
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */\r
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */\r
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */\r
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTISR) Pipe 10 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTISR) Pipe 11 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTISR) DMA Channel 7 Interrupt */\r
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */\r
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */\r
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */\r
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */\r
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */\r
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */\r
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */\r
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */\r
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */\r
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */\r
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */\r
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */\r
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */\r
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */\r
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */\r
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIFR) DMA Channel 7 Interrupt Set */\r
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */\r
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */\r
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */\r
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIMR) Pipe 10 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIMR) Pipe 11 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIMR) DMA Channel 7 Interrupt Enable */\r
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */\r
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */\r
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */\r
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIDR) Pipe 10 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIDR) Pipe 11 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIDR) DMA Channel 7 Interrupt Disable */\r
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */\r
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */\r
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */\r
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */\r
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */\r
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */\r
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */\r
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIER) Pipe 10 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIER) Pipe 11 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIER) DMA Channel 7 Interrupt Enable */\r
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */\r
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */\r
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */\r
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */\r
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */\r
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */\r
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */\r
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */\r
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */\r
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */\r
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */\r
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */\r
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */\r
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */\r
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */\r
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */\r
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */\r
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */\r
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */\r
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */\r
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0\r
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */\r
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))\r
+#define UOTGHS_HSTFNUM_FNUM_Pos 3\r
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */\r
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))\r
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16\r
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */\r
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))\r
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */\r
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0\r
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8\r
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16\r
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24\r
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))\r
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */\r
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0\r
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8\r
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16\r
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24\r
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))\r
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */\r
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0\r
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */\r
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))\r
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8\r
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */\r
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))\r
+/* -------- UOTGHS_HSTPIPCFG[12] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Memory Allocate */\r
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2\r
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Banks */\r
+#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Single-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Double-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Triple-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4\r
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Size */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 8 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 16 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 32 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 64 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 128 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 256 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 512 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 1024 bytes */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Token */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) SETUP */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) IN */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) OUT */\r
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[12]) Automatic Switch */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12\r
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Type */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Control */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Isochronous */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Bulk */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Interrupt */\r
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16\r
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Endpoint Number */\r
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))\r
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24\r
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Interrupt Request Frequency */\r
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))\r
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[12]) Ping Enable */\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Binterval Parameter for the Bulk-Out/Ping Transaction */\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))\r
+/* -------- UOTGHS_HSTPIPISR[12] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[12]) Received IN Data Interrupt */\r
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted OUT Data Interrupt */\r
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted SETUP Interrupt */\r
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Error Interrupt */\r
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[12]) NAKed Interrupt */\r
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[12]) Overflow Interrupt */\r
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) Received STALLed Interrupt */\r
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[12]) Short Packet Interrupt */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8\r
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Data Toggle Sequence */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data0 toggle sequence */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data1 toggle sequence */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Number of Busy Banks */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 0 busy bank (all banks free) */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 1 busy bank */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 2 busy banks */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 3 busy banks */\r
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14\r
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Current Bank */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank0 */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank1 */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank2 */\r
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[12]) Read-write Allowed */\r
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[12]) Configuration OK Status */\r
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20\r
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Byte Count */\r
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Underflow Interrupt */\r
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) CRC Error Interrupt */\r
+/* -------- UOTGHS_HSTPIPICR[12] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[12]) Received IN Data Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted OUT Data Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted SETUP Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[12]) NAKed Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[12]) Overflow Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) Received STALLed Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[12]) Short Packet Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Underflow Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) CRC Error Interrupt Clear */\r
+/* -------- UOTGHS_HSTPIPIFR[12] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received IN Data Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted OUT Data Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted SETUP Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[12]) Pipe Error Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[12]) NAKed Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[12]) Overflow Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received STALLed Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[12]) Short Packet Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[12]) Number of Busy Banks Set */\r
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Underflow Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) CRC Error Interrupt Set */\r
+/* -------- UOTGHS_HSTPIPIMR[12] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received IN Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted OUT Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted SETUP Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[12]) NAKed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[12]) Overflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received STALLed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[12]) Short Packet Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[12]) Number of Busy Banks Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[12]) FIFO Control */\r
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Freeze */\r
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[12]) Reset Data Toggle */\r
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Underflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) CRC Error Interrupt Enable */\r
+/* -------- UOTGHS_HSTPIPIER[12] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[12]) Received IN Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted OUT Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted SETUP Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[12]) NAKed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[12]) Overflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) Received STALLed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[12]) Short Packet Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[12]) Number of Busy Banks Enable */\r
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Freeze Enable */\r
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[12]) Reset Data Toggle Enable */\r
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Underflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) CRC Error Interrupt Enable */\r
+/* -------- UOTGHS_HSTPIPIDR[12] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received IN Data Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted OUT Data Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted SETUP Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Error Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[12]) NAKed Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[12]) Overflow Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received STALLed Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[12]) Short Packet Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[12]) Number of Busy Banks Disable */\r
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[12]) FIFO Control Disable */\r
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Interrupts Disable HDMA Request Disable */\r
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Freeze Disable */\r
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Underflow Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) CRC Error Interrupt Disable */\r
+/* -------- UOTGHS_HSTPIPINRQ[12] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0\r
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Number before Freeze */\r
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))\r
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Mode */\r
+/* -------- UOTGHS_HSTPIPERR[12] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[12]) Data Toggle Error */\r
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[12]) Data PID Error */\r
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[12]) PID Error */\r
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[12]) Time-Out Error */\r
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[12]) CRC16 Error */\r
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5\r
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[12]) Error Counter */\r
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))\r
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))\r
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))\r
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */\r
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */\r
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */\r
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */\r
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */\r
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))\r
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */\r
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */\r
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */\r
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */\r
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */\r
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))\r
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */\r
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */\r
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */\r
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */\r
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */\r
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */\r
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */\r
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */\r
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */\r
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */\r
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */\r
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */\r
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */\r
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */\r
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */\r
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */\r
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */\r
+#define UOTGHS_CTRL_TIMVALUE_Pos 16\r
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */\r
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))\r
+#define UOTGHS_CTRL_TIMPAGE_Pos 20\r
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */\r
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))\r
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */\r
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */\r
+#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */\r
+#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */\r
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */\r
+#define UOTGHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */\r
+#define UOTGHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */\r
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */\r
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */\r
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */\r
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */\r
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */\r
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */\r
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */\r
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */\r
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */\r
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */\r
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */\r
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */\r
+#define UOTGHS_SR_SPEED_Pos 12\r
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */\r
+#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */\r
+#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */\r
+#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */\r
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */\r
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */\r
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */\r
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */\r
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */\r
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */\r
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */\r
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */\r
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */\r
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */\r
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */\r
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */\r
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */\r
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */\r
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */\r
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */\r
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */\r
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */\r
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */\r
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */\r
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */\r
+/* -------- UOTGHS_TSTA1 : (UOTGHS Offset: 0x0810) General Test A1 Register -------- */\r
+#define UOTGHS_TSTA1_CounterA_Pos 0\r
+#define UOTGHS_TSTA1_CounterA_Msk (0x7fffu << UOTGHS_TSTA1_CounterA_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterA */\r
+#define UOTGHS_TSTA1_CounterA(value) ((UOTGHS_TSTA1_CounterA_Msk & ((value) << UOTGHS_TSTA1_CounterA_Pos)))\r
+#define UOTGHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (UOTGHS_TSTA1) Load CounterA */\r
+#define UOTGHS_TSTA1_CounterB_Pos 16\r
+#define UOTGHS_TSTA1_CounterB_Msk (0x3fu << UOTGHS_TSTA1_CounterB_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterB */\r
+#define UOTGHS_TSTA1_CounterB(value) ((UOTGHS_TSTA1_CounterB_Msk & ((value) << UOTGHS_TSTA1_CounterB_Pos)))\r
+#define UOTGHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (UOTGHS_TSTA1) Load CounterB */\r
+#define UOTGHS_TSTA1_SOFCntMa1_Pos 24\r
+#define UOTGHS_TSTA1_SOFCntMa1_Msk (0x7fu << UOTGHS_TSTA1_SOFCntMa1_Pos) /**< \brief (UOTGHS_TSTA1) SOF Counter Max */\r
+#define UOTGHS_TSTA1_SOFCntMa1(value) ((UOTGHS_TSTA1_SOFCntMa1_Msk & ((value) << UOTGHS_TSTA1_SOFCntMa1_Pos)))\r
+#define UOTGHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (UOTGHS_TSTA1) Load SOF Counter */\r
+/* -------- UOTGHS_TSTA2 : (UOTGHS Offset: 0x0814) General Test A2 Register -------- */\r
+#define UOTGHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (UOTGHS_TSTA2) Full Detach Enable */\r
+#define UOTGHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (UOTGHS_TSTA2) HS Serial Mode */\r
+#define UOTGHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (UOTGHS_TSTA2) Loop-back Mode */\r
+#define UOTGHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (UOTGHS_TSTA2) Disable Gated Clock */\r
+#define UOTGHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (UOTGHS_TSTA2) Force SuspendM to 1 */\r
+#define UOTGHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (UOTGHS_TSTA2) Bypass DPLL */\r
+#define UOTGHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (UOTGHS_TSTA2) Host HS Disconnect Disable */\r
+#define UOTGHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (UOTGHS_TSTA2) Force HS Reset to 50 ms */\r
+#define UOTGHS_TSTA2_UTMIReset (0x1u << 8) /**< \brief (UOTGHS_TSTA2) UTMI Reset */\r
+#define UOTGHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (UOTGHS_TSTA2) Remove Pull-up When TX */\r
+/* -------- UOTGHS_VERSION : (UOTGHS Offset: 0x0818) General Version Register -------- */\r
+#define UOTGHS_VERSION_VERSION_Pos 0\r
+#define UOTGHS_VERSION_VERSION_Msk (0xfffu << UOTGHS_VERSION_VERSION_Pos) /**< \brief (UOTGHS_VERSION) Version Number */\r
+#define UOTGHS_VERSION_VARIANT_Pos 16\r
+#define UOTGHS_VERSION_VARIANT_Msk (0xfu << UOTGHS_VERSION_VARIANT_Pos) /**< \brief (UOTGHS_VERSION) Variant Number */\r
+/* -------- UOTGHS_FEATURES : (UOTGHS Offset: 0x081C) General Features Register -------- */\r
+#define UOTGHS_FEATURES_EPTNBRMAX_Pos 0\r
+#define UOTGHS_FEATURES_EPTNBRMAX_Msk (0xfu << UOTGHS_FEATURES_EPTNBRMAX_Pos) /**< \brief (UOTGHS_FEATURES) Maximal Number of Pipes/Endpoints */\r
+#define UOTGHS_FEATURES_EPTNBRMAX_16_P_E (0x0u << 0) /**< \brief (UOTGHS_FEATURES) 16 pipes/endpoints */\r
+#define UOTGHS_FEATURES_EPTNBRMAX_1_P_E (0x1u << 0) /**< \brief (UOTGHS_FEATURES) 1 pipe/endpoint */\r
+#define UOTGHS_FEATURES_EPTNBRMAX_2_P_E (0x2u << 0) /**< \brief (UOTGHS_FEATURES) 2 pipes/endpoints */\r
+#define UOTGHS_FEATURES_EPTNBRMAX_15_P_E (0xFu << 0) /**< \brief (UOTGHS_FEATURES) 15 pipes/endpoints */\r
+#define UOTGHS_FEATURES_DMACHANNELNBR_Pos 4\r
+#define UOTGHS_FEATURES_DMACHANNELNBR_Msk (0x7u << UOTGHS_FEATURES_DMACHANNELNBR_Pos) /**< \brief (UOTGHS_FEATURES) Number of DMA Channels */\r
+#define UOTGHS_FEATURES_DMACHANNELNBR_1_DMA_CH (0x1u << 4) /**< \brief (UOTGHS_FEATURES) 1 DMA channel */\r
+#define UOTGHS_FEATURES_DMACHANNELNBR_2_DMA_CH (0x2u << 4) /**< \brief (UOTGHS_FEATURES) 2 DMA channels */\r
+#define UOTGHS_FEATURES_DMACHANNELNBR_7_DMA_CH (0x7u << 4) /**< \brief (UOTGHS_FEATURES) 7 DMA channels */\r
+#define UOTGHS_FEATURES_DMABUFFERSIZE (0x1u << 7) /**< \brief (UOTGHS_FEATURES) DMA Buffer Size */\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos 8\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Msk (0xfu << UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos) /**< \brief (UOTGHS_FEATURES) DMA FIFO Depth in Words */\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_16_DMA_F_D (0x0u << 8) /**< \brief (UOTGHS_FEATURES) 16 DMA FIFO depth */\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_1_DMA_F_D (0x1u << 8) /**< \brief (UOTGHS_FEATURES) 1 DMA FIFO depth */\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_2_DMA_F_D (0x2u << 8) /**< \brief (UOTGHS_FEATURES) 2 DMA FIFO depth */\r
+#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_15_DMA_F_D (0xFu << 8) /**< \brief (UOTGHS_FEATURES) 15 DMA FIFO depth */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_Pos 12\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_Msk (0x7u << UOTGHS_FEATURES_FIFOMAXSIZE_Pos) /**< \brief (UOTGHS_FEATURES) Maximal FIFO Size */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_256_BYTE (0x0u << 12) /**< \brief (UOTGHS_FEATURES) < 256 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_512_BYTE (0x1u << 12) /**< \brief (UOTGHS_FEATURES) < 512 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_1024_BYTE (0x2u << 12) /**< \brief (UOTGHS_FEATURES) < 1024 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_2048_BYTE (0x3u << 12) /**< \brief (UOTGHS_FEATURES) < 2048 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_4096_BYTE (0x4u << 12) /**< \brief (UOTGHS_FEATURES) < 4096 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_8192_BYTE (0x5u << 12) /**< \brief (UOTGHS_FEATURES) < 8192 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_16384_BYTE (0x6u << 12) /**< \brief (UOTGHS_FEATURES) < 16384 bytes */\r
+#define UOTGHS_FEATURES_FIFOMAXSIZE_P16384_BYTE (0x7u << 12) /**< \brief (UOTGHS_FEATURES) >= 16384 bytes */\r
+#define UOTGHS_FEATURES_BYTEWRITEDPRAM (0x1u << 15) /**< \brief (UOTGHS_FEATURES) DPRAM Byte-Write Capability */\r
+#define UOTGHS_FEATURES_DATABUS (0x1u << 16) /**< \brief (UOTGHS_FEATURES) Data Bus 16-8 */\r
+#define UOTGHS_FEATURES_ENHBISO1 (0x1u << 17) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 1 */\r
+#define UOTGHS_FEATURES_ENHBISO2 (0x1u << 18) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 2 */\r
+#define UOTGHS_FEATURES_ENHBISO3 (0x1u << 19) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 3 */\r
+#define UOTGHS_FEATURES_ENHBISO4 (0x1u << 20) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 4 */\r
+#define UOTGHS_FEATURES_ENHBISO5 (0x1u << 21) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 5 */\r
+#define UOTGHS_FEATURES_ENHBISO6 (0x1u << 22) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 6 */\r
+#define UOTGHS_FEATURES_ENHBISO7 (0x1u << 23) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 7 */\r
+/* -------- UOTGHS_ADDRSIZE : (UOTGHS Offset: 0x0820) General APB Address Size Register -------- */\r
+#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos 0\r
+#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Msk (0xffffffffu << UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos) /**< \brief (UOTGHS_ADDRSIZE) IP APB Address Size */\r
+/* -------- UOTGHS_IPNAME1 : (UOTGHS Offset: 0x0824) General Name Register 1 -------- */\r
+#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos 0\r
+#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Msk (0xffffffffu << UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos) /**< \brief (UOTGHS_IPNAME1) IP Name Part One */\r
+/* -------- UOTGHS_IPNAME2 : (UOTGHS Offset: 0x0828) General Name Register 2 -------- */\r
+#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos 0\r
+#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Msk (0xffffffffu << UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos) /**< \brief (UOTGHS_IPNAME2) IP Name Part Two */\r
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */\r
+#define UOTGHS_FSM_DRDSTATE_Pos 0\r
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) Dual Role Device State */\r
+#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */\r
+#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */\r
+#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */\r
+#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */\r
+#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */\r
+#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */\r
+#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_UOTGHS_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_USART_COMPONENT_\r
+#define _SAM_USART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */\r
+ __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */\r
+ __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */\r
+ __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */\r
+ __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */\r
+ __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */\r
+ __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */\r
+ __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */\r
+ __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */\r
+ __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */\r
+ __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */\r
+ __I uint32_t Reserved1[5];\r
+ __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */\r
+ __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */\r
+ __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */\r
+ __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */\r
+ __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */\r
+ __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */\r
+ __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */\r
+ __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */\r
+ __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */\r
+ __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */\r
+ __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */\r
+ __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */\r
+ __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */\r
+ __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */\r
+ __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */\r
+ __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */\r
+ __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */\r
+ __I uint32_t Reserved3[22];\r
+ __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */\r
+ __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */\r
+} Usart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */\r
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */\r
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) master Clock MCK is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=DIV=8) is selected */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */\r
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */\r
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */\r
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */\r
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */\r
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */\r
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */\r
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */\r
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */\r
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */\r
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */\r
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */\r
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */\r
+#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */\r
+#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */\r
+#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */\r
+#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */\r
+#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */\r
+#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */\r
+#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */\r
+#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */\r
+#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */\r
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */\r
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */\r
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */\r
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */\r
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */\r
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */\r
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */\r
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */\r
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */\r
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */\r
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */\r
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */\r
+#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */\r
+#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */\r
+#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */\r
+#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */\r
+#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */\r
+#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */\r
+#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */\r
+#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */\r
+#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */\r
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */\r
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */\r
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */\r
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */\r
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */\r
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */\r
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */\r
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */\r
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */\r
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */\r
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */\r
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */\r
+#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */\r
+#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */\r
+#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */\r
+#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */\r
+#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */\r
+#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */\r
+#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */\r
+#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */\r
+#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */\r
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */\r
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */\r
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */\r
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */\r
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */\r
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */\r
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */\r
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */\r
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */\r
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */\r
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */\r
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */\r
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */\r
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */\r
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */\r
+#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error */\r
+#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error */\r
+#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error */\r
+#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error */\r
+#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag */\r
+#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag */\r
+#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination */\r
+#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag */\r
+#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error */\r
+/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */\r
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+#define US_TTGR_PCYCLE_Pos 0\r
+#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */\r
+#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))\r
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+#define US_FIDI_BETA2_Pos 0\r
+#define US_FIDI_BETA2_Msk (0xffffffu << US_FIDI_BETA2_Pos) /**< \brief (US_FIDI) LON BETA2 Length */\r
+#define US_FIDI_BETA2(value) ((US_FIDI_BETA2_Msk & ((value) << US_FIDI_BETA2_Pos)))\r
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */\r
+#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) Receiver Idle Value */\r
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */\r
+#define US_LINMR_NACT_Pos 0\r
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */\r
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */\r
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */\r
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */\r
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */\r
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */\r
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */\r
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */\r
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */\r
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */\r
+#define US_LINMR_DLC_Pos 8\r
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */\r
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))\r
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */\r
+#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */\r
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */\r
+#define US_LINIR_IDCHR_Pos 0\r
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */\r
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))\r
+/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */\r
+#define US_LINBRR_LINCD_Pos 0\r
+#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */\r
+#define US_LINBRR_LINFP_Pos 16\r
+#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */\r
+/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */\r
+#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */\r
+#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */\r
+#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */\r
+#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */\r
+#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */\r
+#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */\r
+#define US_LONMR_EOFS_Pos 16\r
+#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */\r
+#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))\r
+/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */\r
+#define US_LONPR_LONPL_Pos 0\r
+#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */\r
+#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))\r
+/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */\r
+#define US_LONDL_LONDL_Pos 0\r
+#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */\r
+#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))\r
+/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */\r
+#define US_LONL2HDR_BLI_Pos 0\r
+#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */\r
+#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))\r
+#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */\r
+#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */\r
+/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */\r
+#define US_LONBL_LONBL_Pos 0\r
+#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */\r
+/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */\r
+#define US_LONB1TX_BETA1TX_Pos 0\r
+#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */\r
+#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))\r
+/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */\r
+#define US_LONB1RX_BETA1RX_Pos 0\r
+#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */\r
+#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))\r
+/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */\r
+#define US_LONPRIO_PSNB_Pos 0\r
+#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */\r
+#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))\r
+#define US_LONPRIO_NPS_Pos 8\r
+#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */\r
+#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))\r
+/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */\r
+#define US_IDTTX_IDTTX_Pos 0\r
+#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */\r
+#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))\r
+/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */\r
+#define US_IDTRX_IDTRX_Pos 0\r
+#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */\r
+#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))\r
+/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */\r
+#define US_ICDIFF_ICDIFF_Pos 0\r
+#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */\r
+#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))\r
+/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */\r
+#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */\r
+/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */\r
+#define US_VERSION_VERSION_Pos 0\r
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */\r
+#define US_VERSION_MFN_Pos 16\r
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_USART_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_WDT_COMPONENT_\r
+#define _SAM_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password. */\r
+#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_WDT_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_XDMAC_COMPONENT_\r
+#define _SAM_XDMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM_XDMAC Extensible DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief XdmacChid hardware registers */\r
+typedef struct {\r
+ __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */\r
+ __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */\r
+ __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */\r
+ __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */\r
+ __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */\r
+ __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */\r
+ __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */\r
+ __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */\r
+ __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */\r
+ __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */\r
+ __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */\r
+ __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */\r
+ __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */\r
+ __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */\r
+ __I uint32_t Reserved1[2];\r
+} XdmacChid;\r
+/** \brief Xdmac hardware registers */\r
+#define XDMACCHID_NUMBER 24\r
+typedef struct {\r
+ __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */\r
+ __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */\r
+ __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */\r
+ __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */\r
+ __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */\r
+ __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */\r
+ __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */\r
+ __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */\r
+ __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */\r
+ __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */\r
+ __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */\r
+ __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */\r
+ __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */\r
+ __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */\r
+ __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */\r
+ __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */\r
+ __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */\r
+ __I uint32_t Reserved1[3];\r
+ XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */\r
+ __I uint32_t Reserved2[619];\r
+ __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */\r
+} Xdmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */\r
+#define XDMAC_GTYPE_NB_CH_Pos 0\r
+#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */\r
+#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))\r
+#define XDMAC_GTYPE_FIFO_SZ_Pos 5\r
+#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */\r
+#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))\r
+#define XDMAC_GTYPE_NB_REQ_Pos 16\r
+#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */\r
+#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))\r
+/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */\r
+#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */\r
+#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */\r
+/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */\r
+#define XDMAC_GWAC_PW0_Pos 0\r
+#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */\r
+#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))\r
+#define XDMAC_GWAC_PW1_Pos 4\r
+#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */\r
+#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))\r
+#define XDMAC_GWAC_PW2_Pos 8\r
+#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */\r
+#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))\r
+#define XDMAC_GWAC_PW3_Pos 12\r
+#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */\r
+#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))\r
+/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */\r
+#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */\r
+/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */\r
+#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */\r
+/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */\r
+#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */\r
+/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */\r
+#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */\r
+/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */\r
+#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */\r
+#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */\r
+#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */\r
+#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */\r
+#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */\r
+#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */\r
+#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */\r
+#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */\r
+#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */\r
+#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */\r
+#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */\r
+#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */\r
+#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */\r
+#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */\r
+#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */\r
+#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */\r
+#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */\r
+#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */\r
+#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */\r
+#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */\r
+#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */\r
+#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */\r
+#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */\r
+#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */\r
+/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */\r
+#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */\r
+#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */\r
+#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */\r
+#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */\r
+#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */\r
+#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */\r
+#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */\r
+#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */\r
+#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */\r
+#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */\r
+#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */\r
+#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */\r
+#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */\r
+#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */\r
+#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */\r
+#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */\r
+#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */\r
+#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */\r
+#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */\r
+#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */\r
+#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */\r
+#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */\r
+#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */\r
+#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */\r
+/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */\r
+#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */\r
+#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */\r
+#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */\r
+#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */\r
+#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */\r
+#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */\r
+#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */\r
+#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */\r
+#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */\r
+#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */\r
+#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */\r
+#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */\r
+#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */\r
+#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */\r
+#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */\r
+#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */\r
+#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */\r
+#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */\r
+#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */\r
+#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */\r
+#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */\r
+#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */\r
+#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */\r
+#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */\r
+/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */\r
+#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */\r
+#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */\r
+#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */\r
+#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */\r
+#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */\r
+#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */\r
+#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */\r
+#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */\r
+#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */\r
+#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */\r
+#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */\r
+#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */\r
+#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */\r
+#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */\r
+#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */\r
+#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */\r
+#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */\r
+#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */\r
+#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */\r
+#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */\r
+#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */\r
+#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */\r
+#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */\r
+#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */\r
+/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */\r
+#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */\r
+#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */\r
+#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */\r
+#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */\r
+#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */\r
+#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */\r
+#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */\r
+#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */\r
+#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */\r
+#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */\r
+#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */\r
+#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */\r
+#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */\r
+#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */\r
+#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */\r
+#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */\r
+#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */\r
+#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */\r
+#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */\r
+#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */\r
+#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */\r
+#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */\r
+#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */\r
+#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */\r
+/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */\r
+#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */\r
+/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */\r
+#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */\r
+/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */\r
+#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */\r
+/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */\r
+#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */\r
+/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */\r
+#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */\r
+/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */\r
+#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */\r
+#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */\r
+#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */\r
+#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */\r
+#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */\r
+#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */\r
+#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */\r
+/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */\r
+#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */\r
+#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */\r
+#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */\r
+#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */\r
+#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */\r
+#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */\r
+#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */\r
+/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */\r
+#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */\r
+#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */\r
+#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask bit */\r
+#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */\r
+#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */\r
+#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */\r
+#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */\r
+/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */\r
+#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */\r
+#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */\r
+#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */\r
+#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */\r
+#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */\r
+#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */\r
+#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */\r
+/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */\r
+#define XDMAC_CSA_SA_Pos 0\r
+#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */\r
+#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))\r
+/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */\r
+#define XDMAC_CDA_DA_Pos 0\r
+#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */\r
+#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))\r
+/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */\r
+#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */\r
+#define XDMAC_CNDA_NDA_Pos 2\r
+#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */\r
+#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))\r
+/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */\r
+#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */\r
+#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */\r
+#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */\r
+#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */\r
+#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */\r
+#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */\r
+#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */\r
+#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */\r
+#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */\r
+#define XDMAC_CNDC_NDVIEW_Pos 3\r
+#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */\r
+#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */\r
+#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */\r
+#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */\r
+#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */\r
+/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */\r
+#define XDMAC_CUBC_UBLEN_Pos 0\r
+#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */\r
+#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))\r
+/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */\r
+#define XDMAC_CBC_BLEN_Pos 0\r
+#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */\r
+#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))\r
+/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */\r
+#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */\r
+#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */\r
+#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */\r
+#define XDMAC_CC_MBSIZE_Pos 1\r
+#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */\r
+#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */\r
+#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */\r
+#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */\r
+#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */\r
+#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */\r
+#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */\r
+#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */\r
+#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */\r
+#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */\r
+#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */\r
+#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */\r
+#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */\r
+#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */\r
+#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */\r
+#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */\r
+#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */\r
+#define XDMAC_CC_CSIZE_Pos 8\r
+#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */\r
+#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */\r
+#define XDMAC_CC_DWIDTH_Pos 11\r
+#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */\r
+#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */\r
+#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */\r
+#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */\r
+#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */\r
+#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */\r
+#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */\r
+#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */\r
+#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */\r
+#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */\r
+#define XDMAC_CC_SAM_Pos 16\r
+#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */\r
+#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */\r
+#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */\r
+#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */\r
+#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */\r
+#define XDMAC_CC_DAM_Pos 18\r
+#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */\r
+#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */\r
+#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */\r
+#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */\r
+#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */\r
+#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read only) */\r
+#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */\r
+#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */\r
+#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read only) */\r
+#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */\r
+#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */\r
+#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read only) */\r
+#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */\r
+#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */\r
+#define XDMAC_CC_PERID_Pos 24\r
+#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */\r
+#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))\r
+/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */\r
+#define XDMAC_CDS_MSP_SDS_MSP_Pos 0\r
+#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */\r
+#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))\r
+#define XDMAC_CDS_MSP_DDS_MSP_Pos 16\r
+#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */\r
+#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))\r
+/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */\r
+#define XDMAC_CSUS_SUBS_Pos 0\r
+#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */\r
+#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))\r
+/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */\r
+#define XDMAC_CDUS_DUBS_Pos 0\r
+#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */\r
+#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))\r
+/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */\r
+#define XDMAC_VERSION_VERSION_Pos 0\r
+#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */\r
+#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos)))\r
+#define XDMAC_VERSION_MFN_Pos 16\r
+#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */\r
+#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM_XDMAC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ACC_INSTANCE_\r
+#define _SAM_ACC_INSTANCE_\r
+\r
+/* ========== Register definition for ACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */\r
+ #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */\r
+ #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */\r
+ #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */\r
+ #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */\r
+ #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */\r
+ #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */\r
+ #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */\r
+ #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */\r
+ #define REG_ACC_VER (0x400440FCU) /**< \brief (ACC) Version Register */\r
+#else\r
+ #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */\r
+ #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */\r
+ #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */\r
+ #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */\r
+ #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */\r
+ #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */\r
+ #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */\r
+ #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */\r
+ #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */\r
+ #define REG_ACC_VER (*(__I uint32_t*)0x400440FCU) /**< \brief (ACC) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_ACC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AES_INSTANCE_\r
+#define _SAM_AES_INSTANCE_\r
+\r
+/* ========== Register definition for AES peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */\r
+ #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */\r
+ #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */\r
+ #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */\r
+ #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */\r
+ #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */\r
+ #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */\r
+ #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */\r
+ #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */\r
+ #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */\r
+ #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */\r
+ #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */\r
+ #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */\r
+ #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */\r
+ #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */\r
+ #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H World Register */\r
+ #define REG_AES_VERSION (0x4006C0FCU) /**< \brief (AES) Version Register */\r
+#else\r
+ #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */\r
+ #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */\r
+ #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */\r
+ #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */\r
+ #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */\r
+ #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */\r
+ #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */\r
+ #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */\r
+ #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */\r
+ #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */\r
+ #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */\r
+ #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */\r
+ #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */\r
+ #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */\r
+ #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */\r
+ #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H World Register */\r
+ #define REG_AES_VERSION (*(__I uint32_t*)0x4006C0FCU) /**< \brief (AES) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_AES_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AFEC0_INSTANCE_\r
+#define _SAM_AFEC0_INSTANCE_\r
+\r
+/* ========== Register definition for AFEC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */\r
+ #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */\r
+ #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */\r
+ #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */\r
+ #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */\r
+ #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */\r
+ #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */\r
+ #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */\r
+ #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */\r
+ #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */\r
+ #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */\r
+ #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */\r
+ #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */\r
+ #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */\r
+ #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */\r
+ #define REG_AFEC0_CG1R (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain 1 Register */\r
+ #define REG_AFEC0_CG2R (0x4003C058U) /**< \brief (AFEC0) AFEC Channel Gain 2 Register */\r
+ #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */\r
+ #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Register Selection */\r
+ #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */\r
+ #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */\r
+ #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */\r
+ #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */\r
+ #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */\r
+ #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */\r
+ #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */\r
+ #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */\r
+ #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */\r
+ #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */\r
+ #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */\r
+ #define REG_AFEC0_VERSION (0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */\r
+#else\r
+ #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */\r
+ #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */\r
+ #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */\r
+ #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */\r
+ #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */\r
+ #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */\r
+ #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */\r
+ #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */\r
+ #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */\r
+ #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */\r
+ #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */\r
+ #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */\r
+ #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */\r
+ #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */\r
+ #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */\r
+ #define REG_AFEC0_CG1R (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain 1 Register */\r
+ #define REG_AFEC0_CG2R (*(__IO uint32_t*)0x4003C058U) /**< \brief (AFEC0) AFEC Channel Gain 2 Register */\r
+ #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */\r
+ #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Register Selection */\r
+ #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */\r
+ #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */\r
+ #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */\r
+ #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */\r
+ #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */\r
+ #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */\r
+ #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */\r
+ #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */\r
+ #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */\r
+ #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */\r
+ #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */\r
+ #define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_AFEC0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AFEC1_INSTANCE_\r
+#define _SAM_AFEC1_INSTANCE_\r
+\r
+/* ========== Register definition for AFEC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */\r
+ #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */\r
+ #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */\r
+ #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */\r
+ #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */\r
+ #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */\r
+ #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */\r
+ #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */\r
+ #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */\r
+ #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */\r
+ #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */\r
+ #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */\r
+ #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */\r
+ #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */\r
+ #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */\r
+ #define REG_AFEC1_CG1R (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain 1 Register */\r
+ #define REG_AFEC1_CG2R (0x40064058U) /**< \brief (AFEC1) AFEC Channel Gain 2 Register */\r
+ #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */\r
+ #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Register Selection */\r
+ #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */\r
+ #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */\r
+ #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */\r
+ #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */\r
+ #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */\r
+ #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */\r
+ #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */\r
+ #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */\r
+ #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */\r
+ #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */\r
+ #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */\r
+ #define REG_AFEC1_VERSION (0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */\r
+#else\r
+ #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */\r
+ #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */\r
+ #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */\r
+ #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */\r
+ #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */\r
+ #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */\r
+ #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */\r
+ #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */\r
+ #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */\r
+ #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */\r
+ #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */\r
+ #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */\r
+ #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */\r
+ #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */\r
+ #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */\r
+ #define REG_AFEC1_CG1R (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain 1 Register */\r
+ #define REG_AFEC1_CG2R (*(__IO uint32_t*)0x40064058U) /**< \brief (AFEC1) AFEC Channel Gain 2 Register */\r
+ #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */\r
+ #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Register Selection */\r
+ #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */\r
+ #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */\r
+ #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */\r
+ #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */\r
+ #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */\r
+ #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */\r
+ #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */\r
+ #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */\r
+ #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */\r
+ #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */\r
+ #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */\r
+ #define REG_AFEC1_VERSION (*(__I uint32_t*)0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_AFEC1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_CHIPID_INSTANCE_\r
+#define _SAM_CHIPID_INSTANCE_\r
+\r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */\r
+ #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#else\r
+ #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */\r
+ #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_CHIPID_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_DACC_INSTANCE_\r
+#define _SAM_DACC_INSTANCE_\r
+\r
+/* ========== Register definition for DACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */\r
+ #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */\r
+ #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */\r
+ #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */\r
+ #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */\r
+ #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */\r
+ #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */\r
+ #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */\r
+ #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */\r
+ #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */\r
+ #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */\r
+ #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */\r
+ #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */\r
+ #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */\r
+#else\r
+ #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */\r
+ #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */\r
+ #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */\r
+ #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */\r
+ #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */\r
+ #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */\r
+ #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */\r
+ #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */\r
+ #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */\r
+ #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */\r
+ #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */\r
+ #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */\r
+ #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */\r
+ #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_DACC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_EFC_INSTANCE_\r
+#define _SAM_EFC_INSTANCE_\r
+\r
+/* ========== Register definition for EFC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+ #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+ #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+ #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+ #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */\r
+#else\r
+ #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+ #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+ #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+ #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+ #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_EFC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_GMAC_INSTANCE_\r
+#define _SAM_GMAC_INSTANCE_\r
+\r
+/* ========== Register definition for GMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_GMAC_NCR (0x40050000U) /**< \brief (GMAC) Network Control Register */\r
+ #define REG_GMAC_NCFGR (0x40050004U) /**< \brief (GMAC) Network Configuration Register */\r
+ #define REG_GMAC_NSR (0x40050008U) /**< \brief (GMAC) Network Status Register */\r
+ #define REG_GMAC_UR (0x4005000CU) /**< \brief (GMAC) User Register */\r
+ #define REG_GMAC_DCFGR (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */\r
+ #define REG_GMAC_TSR (0x40050014U) /**< \brief (GMAC) Transmit Status Register */\r
+ #define REG_GMAC_RBQB (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */\r
+ #define REG_GMAC_TBQB (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */\r
+ #define REG_GMAC_RSR (0x40050020U) /**< \brief (GMAC) Receive Status Register */\r
+ #define REG_GMAC_ISR (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */\r
+ #define REG_GMAC_IER (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */\r
+ #define REG_GMAC_IDR (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */\r
+ #define REG_GMAC_IMR (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */\r
+ #define REG_GMAC_MAN (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */\r
+ #define REG_GMAC_RPQ (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */\r
+ #define REG_GMAC_TPQ (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */\r
+ #define REG_GMAC_HRB (0x40050080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */\r
+ #define REG_GMAC_HRT (0x40050084U) /**< \brief (GMAC) Hash Register Top [63:32] */\r
+ #define REG_GMAC_SAB1 (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT1 (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */\r
+ #define REG_GMAC_SAB2 (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT2 (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */\r
+ #define REG_GMAC_SAB3 (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT3 (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */\r
+ #define REG_GMAC_SAB4 (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT4 (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */\r
+ #define REG_GMAC_TIDM (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */\r
+ #define REG_GMAC_WOL (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */\r
+ #define REG_GMAC_IPGS (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */\r
+ #define REG_GMAC_SVLAN (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */\r
+ #define REG_GMAC_TPFCP (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */\r
+ #define REG_GMAC_SAMB1 (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */\r
+ #define REG_GMAC_SAMT1 (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */\r
+ #define REG_GMAC_MID (0x400500FCU) /**< \brief (GMAC) Module ID Register */\r
+ #define REG_GMAC_OTLO (0x40050100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */\r
+ #define REG_GMAC_OTHI (0x40050104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */\r
+ #define REG_GMAC_FT (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */\r
+ #define REG_GMAC_BCFT (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */\r
+ #define REG_GMAC_MFT (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */\r
+ #define REG_GMAC_PFT (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */\r
+ #define REG_GMAC_BFT64 (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT127 (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT255 (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT511 (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT1023 (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT1518 (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_GTBFT1518 (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TUR (0x40050134U) /**< \brief (GMAC) Transmit Under Runs Register */\r
+ #define REG_GMAC_SCF (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */\r
+ #define REG_GMAC_MCF (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */\r
+ #define REG_GMAC_EC (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */\r
+ #define REG_GMAC_LC (0x40050144U) /**< \brief (GMAC) Late Collisions Register */\r
+ #define REG_GMAC_DTF (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */\r
+ #define REG_GMAC_CSE (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */\r
+ #define REG_GMAC_ORLO (0x40050150U) /**< \brief (GMAC) Octets Received [31:0] Received */\r
+ #define REG_GMAC_ORHI (0x40050154U) /**< \brief (GMAC) Octets Received [47:32] Received */\r
+ #define REG_GMAC_FR (0x40050158U) /**< \brief (GMAC) Frames Received Register */\r
+ #define REG_GMAC_BCFR (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */\r
+ #define REG_GMAC_MFR (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */\r
+ #define REG_GMAC_PFR (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */\r
+ #define REG_GMAC_BFR64 (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR127 (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR255 (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR511 (0x40050174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR1023 (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR1518 (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */\r
+ #define REG_GMAC_TMXBFR (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */\r
+ #define REG_GMAC_UFR (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */\r
+ #define REG_GMAC_OFR (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */\r
+ #define REG_GMAC_JR (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */\r
+ #define REG_GMAC_FCSE (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */\r
+ #define REG_GMAC_LFFE (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */\r
+ #define REG_GMAC_RSE (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */\r
+ #define REG_GMAC_AE (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */\r
+ #define REG_GMAC_RRE (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */\r
+ #define REG_GMAC_ROE (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */\r
+ #define REG_GMAC_IHCE (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */\r
+ #define REG_GMAC_TCE (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */\r
+ #define REG_GMAC_UCE (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */\r
+ #define REG_GMAC_TSSS (0x400501C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */\r
+ #define REG_GMAC_TSSN (0x400501CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+ #define REG_GMAC_TS (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */\r
+ #define REG_GMAC_TN (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */\r
+ #define REG_GMAC_TA (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */\r
+ #define REG_GMAC_TI (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */\r
+ #define REG_GMAC_EFTS (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */\r
+ #define REG_GMAC_EFTN (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */\r
+ #define REG_GMAC_EFRS (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */\r
+ #define REG_GMAC_EFRN (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */\r
+ #define REG_GMAC_PEFTS (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */\r
+ #define REG_GMAC_PEFTN (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */\r
+ #define REG_GMAC_PEFRS (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */\r
+ #define REG_GMAC_PEFRN (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */\r
+ #define REG_GMAC_ISRPQ (0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */\r
+ #define REG_GMAC_TBQBAPQ (0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */\r
+ #define REG_GMAC_RBQBAPQ (0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */\r
+ #define REG_GMAC_RBSRPQ (0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */\r
+ #define REG_GMAC_ST1RPQ (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue */\r
+ #define REG_GMAC_ST2RPQ (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue */\r
+ #define REG_GMAC_IERPQ (0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */\r
+ #define REG_GMAC_IDRPQ (0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */\r
+ #define REG_GMAC_IMRPQ (0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */\r
+#else\r
+ #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */\r
+ #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */\r
+ #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */\r
+ #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */\r
+ #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */\r
+ #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */\r
+ #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */\r
+ #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */\r
+ #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */\r
+ #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */\r
+ #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */\r
+ #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */\r
+ #define REG_GMAC_IMR (*(__I uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */\r
+ #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */\r
+ #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */\r
+ #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */\r
+ #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */\r
+ #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top [63:32] */\r
+ #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */\r
+ #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */\r
+ #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */\r
+ #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */\r
+ #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */\r
+ #define REG_GMAC_TIDM (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */\r
+ #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */\r
+ #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */\r
+ #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */\r
+ #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */\r
+ #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */\r
+ #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */\r
+ #define REG_GMAC_MID (*(__I uint32_t*)0x400500FCU) /**< \brief (GMAC) Module ID Register */\r
+ #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */\r
+ #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */\r
+ #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */\r
+ #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */\r
+ #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */\r
+ #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */\r
+ #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */\r
+ #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Under Runs Register */\r
+ #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */\r
+ #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */\r
+ #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */\r
+ #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */\r
+ #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */\r
+ #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register */\r
+ #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received [31:0] Received */\r
+ #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received [47:32] Received */\r
+ #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */\r
+ #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */\r
+ #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */\r
+ #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */\r
+ #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */\r
+ #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */\r
+ #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */\r
+ #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */\r
+ #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */\r
+ #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */\r
+ #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */\r
+ #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */\r
+ #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */\r
+ #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */\r
+ #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */\r
+ #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */\r
+ #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */\r
+ #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */\r
+ #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */\r
+ #define REG_GMAC_TSSS (*(__IO uint32_t*)0x400501C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */\r
+ #define REG_GMAC_TSSN (*(__IO uint32_t*)0x400501CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */\r
+ #define REG_GMAC_TS (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */\r
+ #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */\r
+ #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */\r
+ #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */\r
+ #define REG_GMAC_EFTS (*(__I uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */\r
+ #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */\r
+ #define REG_GMAC_EFRS (*(__I uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */\r
+ #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */\r
+ #define REG_GMAC_PEFTS (*(__I uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */\r
+ #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */\r
+ #define REG_GMAC_PEFRS (*(__I uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */\r
+ #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */\r
+ #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */\r
+ #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */\r
+ #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */\r
+ #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */\r
+ #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue */\r
+ #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue */\r
+ #define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */\r
+ #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */\r
+ #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_GMAC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_GPBR_INSTANCE_\r
+#define _SAM_GPBR_INSTANCE_\r
+\r
+/* ========== Register definition for GPBR peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#else\r
+ #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_GPBR_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_HSMCI_INSTANCE_\r
+#define _SAM_HSMCI_INSTANCE_\r
+\r
+/* ========== Register definition for HSMCI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */\r
+ #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+ #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+ #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+ #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+ #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */\r
+ #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */\r
+ #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+ #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */\r
+ #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+ #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+ #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */\r
+ #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+ #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+ #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+ #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */\r
+ #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+ #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+ #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+ #define REG_HSMCI_VERSION (0x400000FCU) /**< \brief (HSMCI) Version Register */\r
+ #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#else\r
+ #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */\r
+ #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+ #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+ #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+ #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+ #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */\r
+ #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */\r
+ #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+ #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */\r
+ #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+ #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+ #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */\r
+ #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+ #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+ #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+ #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */\r
+ #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+ #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+ #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+ #define REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU) /**< \brief (HSMCI) Version Register */\r
+ #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_HSMCI_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ICM_INSTANCE_\r
+#define _SAM_ICM_INSTANCE_\r
+\r
+/* ========== Register definition for ICM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */\r
+ #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */\r
+ #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */\r
+ #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */\r
+ #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */\r
+ #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */\r
+ #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */\r
+ #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */\r
+ #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */\r
+ #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */\r
+ #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */\r
+ #define REG_ICM_ADDRSIZE (0x400480ECU) /**< \brief (ICM) Address Size Register */\r
+ #define REG_ICM_IPNAME (0x400480F0U) /**< \brief (ICM) IP Name 1 Register */\r
+ #define REG_ICM_FEATURES (0x400480F8U) /**< \brief (ICM) Feature Register */\r
+ #define REG_ICM_VERSION (0x400480FCU) /**< \brief (ICM) Version Register */\r
+#else\r
+ #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */\r
+ #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */\r
+ #define REG_ICM_SR (*(__O uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */\r
+ #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */\r
+ #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */\r
+ #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */\r
+ #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */\r
+ #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */\r
+ #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */\r
+ #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */\r
+ #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */\r
+ #define REG_ICM_ADDRSIZE (*(__I uint32_t*)0x400480ECU) /**< \brief (ICM) Address Size Register */\r
+ #define REG_ICM_IPNAME (*(__I uint32_t*)0x400480F0U) /**< \brief (ICM) IP Name 1 Register */\r
+ #define REG_ICM_FEATURES (*(__I uint32_t*)0x400480F8U) /**< \brief (ICM) Feature Register */\r
+ #define REG_ICM_VERSION (*(__I uint32_t*)0x400480FCU) /**< \brief (ICM) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_ICM_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_ISI_INSTANCE_\r
+#define _SAM_ISI_INSTANCE_\r
+\r
+/* ========== Register definition for ISI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */\r
+ #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */\r
+ #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */\r
+ #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */\r
+ #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */\r
+ #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */\r
+ #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */\r
+ #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */\r
+ #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */\r
+ #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */\r
+ #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */\r
+ #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */\r
+ #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */\r
+ #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */\r
+ #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */\r
+ #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */\r
+ #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */\r
+ #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */\r
+ #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */\r
+ #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */\r
+ #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */\r
+ #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */\r
+ #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */\r
+ #define REG_ISI_WPCR (0x4004C0E4U) /**< \brief (ISI) Write Protection Control Register */\r
+ #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */\r
+ #define REG_ISI_VERSION (0x4004C0FCU) /**< \brief (ISI) Version Register */\r
+#else\r
+ #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */\r
+ #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */\r
+ #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */\r
+ #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */\r
+ #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */\r
+ #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */\r
+ #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */\r
+ #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */\r
+ #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */\r
+ #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */\r
+ #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */\r
+ #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */\r
+ #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */\r
+ #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */\r
+ #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */\r
+ #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */\r
+ #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */\r
+ #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */\r
+ #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */\r
+ #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */\r
+ #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */\r
+ #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */\r
+ #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */\r
+ #define REG_ISI_WPCR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Control Register */\r
+ #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */\r
+ #define REG_ISI_VERSION (*(__I uint32_t*)0x4004C0FCU) /**< \brief (ISI) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_ISI_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_MATRIX_INSTANCE_\r
+#define _SAM_MATRIX_INSTANCE_\r
+\r
+/* ========== Register definition for MATRIX peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_MATRIX_MCFG (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */\r
+ #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */\r
+ #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+ #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */\r
+ #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+ #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */\r
+ #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+ #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */\r
+ #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+ #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */\r
+ #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+ #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */\r
+ #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+ #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */\r
+ #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */\r
+ #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */\r
+ #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */\r
+ #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */\r
+ #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */\r
+ #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */\r
+ #define REG_MATRIX_PRAS9 (0x400880C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */\r
+ #define REG_MATRIX_PRBS9 (0x400880CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */\r
+ #define REG_MATRIX_PRAS10 (0x400880D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */\r
+ #define REG_MATRIX_PRBS10 (0x400880D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */\r
+ #define REG_MATRIX_PRAS11 (0x400880D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */\r
+ #define REG_MATRIX_PRBS11 (0x400880DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */\r
+ #define REG_MATRIX_PRAS12 (0x400880E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */\r
+ #define REG_MATRIX_PRBS12 (0x400880E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */\r
+ #define REG_MATRIX_PRAS13 (0x400880E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */\r
+ #define REG_MATRIX_PRBS13 (0x400880ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */\r
+ #define REG_MATRIX_PRAS14 (0x400880F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */\r
+ #define REG_MATRIX_PRBS14 (0x400880F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */\r
+ #define REG_MATRIX_PRAS15 (0x400880F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */\r
+ #define REG_MATRIX_PRBS15 (0x400880FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */\r
+ #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */\r
+ #define REG_MATRIX_SFR (0x40088110U) /**< \brief (MATRIX) Special Function Register */\r
+ #define REG_MATRIX_MEIER (0x40088150U) /**< \brief (MATRIX) Master Error Interrupt Enable Register */\r
+ #define REG_MATRIX_MEIDR (0x40088154U) /**< \brief (MATRIX) Master Error Interrupt Disable Register */\r
+ #define REG_MATRIX_MEIMR (0x40088158U) /**< \brief (MATRIX) Master Error Interrupt Mask Register */\r
+ #define REG_MATRIX_MESR (0x4008815CU) /**< \brief (MATRIX) Master Error Status Register */\r
+ #define REG_MATRIX_MEAR (0x40088160U) /**< \brief (MATRIX) Master 0 Error Address Register */\r
+ #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+ #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+ #define REG_MATRIX_VERSION (0x400881FCU) /**< \brief (MATRIX) Version Register */\r
+ #define REG_MATRIX_SSR (0x40088200U) /**< \brief (MATRIX) Security Slave 0 Register */\r
+ #define REG_MATRIX_SASSR (0x40088240U) /**< \brief (MATRIX) Security Areas Split Slave 0 Register */\r
+ #define REG_MATRIX_SRTSR (0x40088280U) /**< \brief (MATRIX) Security Region Top Slave 0 Register */\r
+ #define REG_MATRIX_SPSELR (0x400882C0U) /**< \brief (MATRIX) Security Peripheral Select 1 Register */\r
+#else\r
+ #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */\r
+ #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */\r
+ #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+ #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */\r
+ #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+ #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */\r
+ #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+ #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */\r
+ #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+ #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */\r
+ #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+ #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */\r
+ #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+ #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */\r
+ #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */\r
+ #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */\r
+ #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */\r
+ #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */\r
+ #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */\r
+ #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */\r
+ #define REG_MATRIX_PRAS9 (*(__IO uint32_t*)0x400880C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */\r
+ #define REG_MATRIX_PRBS9 (*(__IO uint32_t*)0x400880CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */\r
+ #define REG_MATRIX_PRAS10 (*(__IO uint32_t*)0x400880D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */\r
+ #define REG_MATRIX_PRBS10 (*(__IO uint32_t*)0x400880D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */\r
+ #define REG_MATRIX_PRAS11 (*(__IO uint32_t*)0x400880D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */\r
+ #define REG_MATRIX_PRBS11 (*(__IO uint32_t*)0x400880DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */\r
+ #define REG_MATRIX_PRAS12 (*(__IO uint32_t*)0x400880E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */\r
+ #define REG_MATRIX_PRBS12 (*(__IO uint32_t*)0x400880E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */\r
+ #define REG_MATRIX_PRAS13 (*(__IO uint32_t*)0x400880E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */\r
+ #define REG_MATRIX_PRBS13 (*(__IO uint32_t*)0x400880ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */\r
+ #define REG_MATRIX_PRAS14 (*(__IO uint32_t*)0x400880F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */\r
+ #define REG_MATRIX_PRBS14 (*(__IO uint32_t*)0x400880F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */\r
+ #define REG_MATRIX_PRAS15 (*(__IO uint32_t*)0x400880F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */\r
+ #define REG_MATRIX_PRBS15 (*(__IO uint32_t*)0x400880FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */\r
+ #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */\r
+ #define REG_MATRIX_SFR (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) Special Function Register */\r
+ #define REG_MATRIX_MEIER (*(__O uint32_t*)0x40088150U) /**< \brief (MATRIX) Master Error Interrupt Enable Register */\r
+ #define REG_MATRIX_MEIDR (*(__O uint32_t*)0x40088154U) /**< \brief (MATRIX) Master Error Interrupt Disable Register */\r
+ #define REG_MATRIX_MEIMR (*(__I uint32_t*)0x40088158U) /**< \brief (MATRIX) Master Error Interrupt Mask Register */\r
+ #define REG_MATRIX_MESR (*(__I uint32_t*)0x4008815CU) /**< \brief (MATRIX) Master Error Status Register */\r
+ #define REG_MATRIX_MEAR (*(__I uint32_t*)0x40088160U) /**< \brief (MATRIX) Master 0 Error Address Register */\r
+ #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+ #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+ #define REG_MATRIX_VERSION (*(__I uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */\r
+ #define REG_MATRIX_SSR (*(__IO uint32_t*)0x40088200U) /**< \brief (MATRIX) Security Slave 0 Register */\r
+ #define REG_MATRIX_SASSR (*(__IO uint32_t*)0x40088240U) /**< \brief (MATRIX) Security Areas Split Slave 0 Register */\r
+ #define REG_MATRIX_SRTSR (*(__IO uint32_t*)0x40088280U) /**< \brief (MATRIX) Security Region Top Slave 0 Register */\r
+ #define REG_MATRIX_SPSELR (*(__IO uint32_t*)0x400882C0U) /**< \brief (MATRIX) Security Peripheral Select 1 Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_MATRIX_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIOA_INSTANCE_\r
+#define _SAM_PIOA_INSTANCE_\r
+\r
+/* ========== Register definition for PIOA peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+ #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+ #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+ #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+ #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+ #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+ #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+ #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+ #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+ #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+ #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+ #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+ #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+ #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+ #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+ #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+ #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+ #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+ #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+ #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+ #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+ #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+ #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+ #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+ #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+ #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+ #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+ #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+ #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+ #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+ #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+ #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+ #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+ #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+ #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */\r
+ #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */\r
+ #define REG_PIOA_VERSION (0x400E0EFCU) /**< \brief (PIOA) Version Register */\r
+ #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+ #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */\r
+ #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */\r
+ #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */\r
+ #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */\r
+ #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */\r
+ #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */\r
+ #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+ #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#else\r
+ #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+ #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+ #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+ #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+ #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+ #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+ #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+ #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+ #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+ #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+ #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+ #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+ #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+ #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+ #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+ #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+ #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+ #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+ #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+ #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+ #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+ #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+ #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+ #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+ #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+ #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+ #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+ #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+ #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+ #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+ #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+ #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+ #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+ #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+ #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */\r
+ #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */\r
+ #define REG_PIOA_VERSION (*(__I uint32_t*)0x400E0EFCU) /**< \brief (PIOA) Version Register */\r
+ #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+ #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */\r
+ #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */\r
+ #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */\r
+ #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */\r
+ #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */\r
+ #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */\r
+ #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+ #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PIOA_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIOB_INSTANCE_\r
+#define _SAM_PIOB_INSTANCE_\r
+\r
+/* ========== Register definition for PIOB peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+ #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+ #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+ #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+ #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+ #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+ #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+ #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+ #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+ #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+ #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+ #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+ #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+ #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+ #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+ #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+ #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+ #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+ #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+ #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+ #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+ #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+ #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+ #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+ #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+ #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+ #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+ #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+ #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+ #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+ #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+ #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+ #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+ #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+ #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */\r
+ #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */\r
+ #define REG_PIOB_VERSION (0x400E10FCU) /**< \brief (PIOB) Version Register */\r
+ #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+ #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */\r
+ #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */\r
+ #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */\r
+ #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */\r
+ #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */\r
+ #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */\r
+ #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+ #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#else\r
+ #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+ #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+ #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+ #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+ #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+ #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+ #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+ #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+ #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+ #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+ #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+ #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+ #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+ #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+ #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+ #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+ #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+ #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+ #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+ #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+ #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+ #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+ #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+ #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+ #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+ #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+ #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+ #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+ #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+ #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+ #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+ #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+ #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+ #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+ #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */\r
+ #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */\r
+ #define REG_PIOB_VERSION (*(__I uint32_t*)0x400E10FCU) /**< \brief (PIOB) Version Register */\r
+ #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+ #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */\r
+ #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */\r
+ #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */\r
+ #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */\r
+ #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */\r
+ #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */\r
+ #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+ #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PIOB_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIOC_INSTANCE_\r
+#define _SAM_PIOC_INSTANCE_\r
+\r
+/* ========== Register definition for PIOC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+ #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+ #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+ #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+ #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+ #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+ #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+ #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+ #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+ #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+ #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+ #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+ #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+ #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+ #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+ #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+ #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+ #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+ #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+ #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+ #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+ #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+ #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+ #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+ #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+ #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+ #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+ #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+ #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+ #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+ #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+ #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+ #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+ #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+ #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */\r
+ #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */\r
+ #define REG_PIOC_VERSION (0x400E12FCU) /**< \brief (PIOC) Version Register */\r
+ #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+ #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */\r
+ #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */\r
+ #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */\r
+ #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */\r
+ #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */\r
+ #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */\r
+ #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+ #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#else\r
+ #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+ #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+ #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+ #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+ #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+ #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+ #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+ #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+ #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+ #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+ #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+ #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+ #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+ #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+ #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+ #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+ #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+ #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+ #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+ #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+ #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+ #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+ #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+ #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+ #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+ #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+ #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+ #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+ #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+ #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+ #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+ #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+ #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+ #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+ #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */\r
+ #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */\r
+ #define REG_PIOC_VERSION (*(__I uint32_t*)0x400E12FCU) /**< \brief (PIOC) Version Register */\r
+ #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+ #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */\r
+ #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */\r
+ #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */\r
+ #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */\r
+ #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */\r
+ #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */\r
+ #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+ #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PIOC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIOD_INSTANCE_\r
+#define _SAM_PIOD_INSTANCE_\r
+\r
+/* ========== Register definition for PIOD peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+ #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+ #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+ #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+ #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+ #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+ #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+ #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+ #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+ #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+ #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+ #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+ #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+ #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+ #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+ #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+ #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+ #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+ #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+ #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+ #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+ #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+ #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+ #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */\r
+ #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */\r
+ #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */\r
+ #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */\r
+ #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+ #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+ #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+ #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+ #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+ #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+ #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+ #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */\r
+ #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */\r
+ #define REG_PIOD_VERSION (0x400E14FCU) /**< \brief (PIOD) Version Register */\r
+ #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */\r
+ #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */\r
+ #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */\r
+ #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */\r
+ #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */\r
+ #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */\r
+ #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */\r
+ #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */\r
+ #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */\r
+#else\r
+ #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+ #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+ #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+ #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+ #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+ #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+ #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+ #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+ #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+ #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+ #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+ #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+ #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+ #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+ #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+ #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+ #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+ #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+ #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+ #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+ #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+ #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+ #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+ #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */\r
+ #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */\r
+ #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */\r
+ #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */\r
+ #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+ #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+ #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+ #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+ #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+ #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+ #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+ #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */\r
+ #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */\r
+ #define REG_PIOD_VERSION (*(__I uint32_t*)0x400E14FCU) /**< \brief (PIOD) Version Register */\r
+ #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */\r
+ #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */\r
+ #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */\r
+ #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */\r
+ #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */\r
+ #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */\r
+ #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */\r
+ #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */\r
+ #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PIOD_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PIOE_INSTANCE_\r
+#define _SAM_PIOE_INSTANCE_\r
+\r
+/* ========== Register definition for PIOE peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+ #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+ #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+ #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+ #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+ #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+ #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+ #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+ #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+ #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+ #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+ #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+ #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+ #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+ #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+ #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+ #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+ #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+ #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+ #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+ #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+ #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+ #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+ #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */\r
+ #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */\r
+ #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */\r
+ #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */\r
+ #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+ #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+ #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+ #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+ #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+ #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+ #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+ #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */\r
+ #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */\r
+ #define REG_PIOE_VERSION (0x400E16FCU) /**< \brief (PIOE) Version Register */\r
+ #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */\r
+ #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */\r
+ #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */\r
+ #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */\r
+ #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */\r
+ #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */\r
+ #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */\r
+ #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */\r
+ #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */\r
+#else\r
+ #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+ #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+ #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+ #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+ #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+ #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+ #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+ #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+ #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+ #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+ #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+ #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+ #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+ #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+ #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+ #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+ #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+ #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+ #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+ #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+ #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+ #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+ #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+ #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */\r
+ #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */\r
+ #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */\r
+ #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */\r
+ #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+ #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */\r
+ #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */\r
+ #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */\r
+ #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+ #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+ #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+ #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+ #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */\r
+ #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+ #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+ #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+ #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+ #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */\r
+ #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High-Level Select Register */\r
+ #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+ #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+ #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */\r
+ #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */\r
+ #define REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) /**< \brief (PIOE) Version Register */\r
+ #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */\r
+ #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */\r
+ #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */\r
+ #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */\r
+ #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */\r
+ #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */\r
+ #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */\r
+ #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */\r
+ #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */\r
+ #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */\r
+ #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */\r
+ #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */\r
+ #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */\r
+ #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */\r
+ #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */\r
+ #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PIOE_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PMC_INSTANCE_\r
+#define _SAM_PMC_INSTANCE_\r
+\r
+/* ========== Register definition for PMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */\r
+ #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */\r
+ #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */\r
+ #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+ #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+ #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+ #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */\r
+ #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */\r
+ #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */\r
+ #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */\r
+ #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */\r
+ #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */\r
+ #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+ #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */\r
+ #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */\r
+ #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */\r
+ #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */\r
+ #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */\r
+ #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+ #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */\r
+ #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */\r
+ #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */\r
+ #define REG_PMC_ADDRSIZE (0x400E06ECU) /**< \brief (PMC) Address Size Register */\r
+ #define REG_PMC_IPNAME (0x400E06F0U) /**< \brief (PMC) IP Name1 Register */\r
+ #define REG_PMC_FEATURES (0x400E06F8U) /**< \brief (PMC) Features Register */\r
+ #define REG_PMC_VERSION (0x400E06FCU) /**< \brief (PMC) Version Register */\r
+ #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+ #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+ #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+ #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */\r
+ #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */\r
+ #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */\r
+ #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */\r
+ #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */\r
+ #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */\r
+ #define REG_PMC_PMMR (0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */\r
+ #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */\r
+ #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */\r
+ #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */\r
+ #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */\r
+ #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In ProgressRegister */\r
+#else\r
+ #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */\r
+ #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */\r
+ #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */\r
+ #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+ #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+ #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+ #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */\r
+ #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */\r
+ #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */\r
+ #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */\r
+ #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */\r
+ #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */\r
+ #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+ #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */\r
+ #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */\r
+ #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */\r
+ #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */\r
+ #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */\r
+ #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+ #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */\r
+ #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */\r
+ #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */\r
+ #define REG_PMC_ADDRSIZE (*(__I uint32_t*)0x400E06ECU) /**< \brief (PMC) Address Size Register */\r
+ #define REG_PMC_IPNAME (*(__I uint32_t*)0x400E06F0U) /**< \brief (PMC) IP Name1 Register */\r
+ #define REG_PMC_FEATURES (*(__I uint32_t*)0x400E06F8U) /**< \brief (PMC) Features Register */\r
+ #define REG_PMC_VERSION (*(__I uint32_t*)0x400E06FCU) /**< \brief (PMC) Version Register */\r
+ #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+ #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+ #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+ #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */\r
+ #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */\r
+ #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */\r
+ #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */\r
+ #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */\r
+ #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */\r
+ #define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */\r
+ #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */\r
+ #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */\r
+ #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */\r
+ #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */\r
+ #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In ProgressRegister */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PMC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PWM0_INSTANCE_\r
+#define _SAM_PWM0_INSTANCE_\r
+\r
+/* ========== Register definition for PWM0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */\r
+ #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */\r
+ #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */\r
+ #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */\r
+ #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */\r
+ #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */\r
+ #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */\r
+ #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */\r
+ #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */\r
+ #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */\r
+ #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */\r
+ #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */\r
+ #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */\r
+ #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */\r
+ #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */\r
+ #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */\r
+ #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */\r
+ #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */\r
+ #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */\r
+ #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */\r
+ #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */\r
+ #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */\r
+ #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */\r
+ #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */\r
+ #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */\r
+ #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */\r
+ #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */\r
+ #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */\r
+ #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */\r
+ #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */\r
+ #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */\r
+ #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */\r
+ #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */\r
+ #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */\r
+ #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */\r
+ #define REG_PWM0_VERSION (0x400200FCU) /**< \brief (PWM0) Version Register */\r
+ #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */\r
+ #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */\r
+ #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */\r
+ #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */\r
+ #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */\r
+ #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */\r
+ #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */\r
+ #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */\r
+ #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */\r
+ #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */\r
+ #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */\r
+ #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */\r
+ #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */\r
+ #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */\r
+ #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */\r
+ #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */\r
+ #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */\r
+ #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */\r
+ #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */\r
+ #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */\r
+ #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */\r
+ #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */\r
+ #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */\r
+ #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */\r
+ #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */\r
+ #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */\r
+ #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */\r
+ #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */\r
+ #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */\r
+ #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */\r
+ #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */\r
+ #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */\r
+ #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */\r
+ #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+ #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */\r
+ #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */\r
+ #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */\r
+ #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */\r
+ #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+ #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */\r
+ #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */\r
+ #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */\r
+ #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */\r
+ #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+ #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */\r
+ #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */\r
+ #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */\r
+ #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */\r
+ #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+ #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */\r
+ #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */\r
+ #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */\r
+ #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CAE0 (0x40020404U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 0) */\r
+ #define REG_PWM0_CAEUPD0 (0x40020408U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CAE1 (0x40020424U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 1) */\r
+ #define REG_PWM0_CAEUPD1 (0x40020428U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+ #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */\r
+ #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CAE2 (0x40020444U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 2) */\r
+ #define REG_PWM0_CAEUPD2 (0x40020448U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+ #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */\r
+ #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CAE3 (0x40020464U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 3) */\r
+ #define REG_PWM0_CAEUPD3 (0x40020468U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+ #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */\r
+ #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */\r
+#else\r
+ #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */\r
+ #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */\r
+ #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */\r
+ #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */\r
+ #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */\r
+ #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */\r
+ #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */\r
+ #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */\r
+ #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */\r
+ #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */\r
+ #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */\r
+ #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */\r
+ #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */\r
+ #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */\r
+ #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */\r
+ #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */\r
+ #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */\r
+ #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */\r
+ #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */\r
+ #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */\r
+ #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */\r
+ #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */\r
+ #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */\r
+ #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */\r
+ #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */\r
+ #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */\r
+ #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */\r
+ #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */\r
+ #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */\r
+ #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */\r
+ #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */\r
+ #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */\r
+ #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */\r
+ #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */\r
+ #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */\r
+ #define REG_PWM0_VERSION (*(__I uint32_t*)0x400200FCU) /**< \brief (PWM0) Version Register */\r
+ #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */\r
+ #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */\r
+ #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */\r
+ #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */\r
+ #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */\r
+ #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */\r
+ #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */\r
+ #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */\r
+ #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */\r
+ #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */\r
+ #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */\r
+ #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */\r
+ #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */\r
+ #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */\r
+ #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */\r
+ #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */\r
+ #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */\r
+ #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */\r
+ #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */\r
+ #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */\r
+ #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */\r
+ #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */\r
+ #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */\r
+ #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */\r
+ #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */\r
+ #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */\r
+ #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */\r
+ #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */\r
+ #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */\r
+ #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */\r
+ #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */\r
+ #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */\r
+ #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */\r
+ #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+ #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */\r
+ #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */\r
+ #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */\r
+ #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */\r
+ #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+ #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */\r
+ #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */\r
+ #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */\r
+ #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */\r
+ #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+ #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */\r
+ #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */\r
+ #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */\r
+ #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */\r
+ #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+ #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */\r
+ #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */\r
+ #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */\r
+ #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CAE0 (*(__IO uint32_t*)0x40020404U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 0) */\r
+ #define REG_PWM0_CAEUPD0 (*(__O uint32_t*)0x40020408U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+ #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */\r
+ #define REG_PWM0_CAE1 (*(__IO uint32_t*)0x40020424U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 1) */\r
+ #define REG_PWM0_CAEUPD1 (*(__O uint32_t*)0x40020428U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+ #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */\r
+ #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */\r
+ #define REG_PWM0_CAE2 (*(__IO uint32_t*)0x40020444U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 2) */\r
+ #define REG_PWM0_CAEUPD2 (*(__O uint32_t*)0x40020448U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+ #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */\r
+ #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */\r
+ #define REG_PWM0_CAE3 (*(__IO uint32_t*)0x40020464U) /**< \brief (PWM0) PWM Channel Additional Edge Register (ch_num = 3) */\r
+ #define REG_PWM0_CAEUPD3 (*(__O uint32_t*)0x40020468U) /**< \brief (PWM0) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+ #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */\r
+ #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PWM0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_PWM1_INSTANCE_\r
+#define _SAM_PWM1_INSTANCE_\r
+\r
+/* ========== Register definition for PWM1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */\r
+ #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */\r
+ #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */\r
+ #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */\r
+ #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */\r
+ #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */\r
+ #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */\r
+ #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */\r
+ #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */\r
+ #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */\r
+ #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */\r
+ #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */\r
+ #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */\r
+ #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */\r
+ #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */\r
+ #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */\r
+ #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */\r
+ #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */\r
+ #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */\r
+ #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */\r
+ #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */\r
+ #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */\r
+ #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */\r
+ #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */\r
+ #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */\r
+ #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */\r
+ #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */\r
+ #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */\r
+ #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */\r
+ #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */\r
+ #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */\r
+ #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */\r
+ #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */\r
+ #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */\r
+ #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */\r
+ #define REG_PWM1_VERSION (0x4005C0FCU) /**< \brief (PWM1) Version Register */\r
+ #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */\r
+ #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */\r
+ #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */\r
+ #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */\r
+ #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */\r
+ #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */\r
+ #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */\r
+ #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */\r
+ #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */\r
+ #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */\r
+ #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */\r
+ #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */\r
+ #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */\r
+ #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */\r
+ #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */\r
+ #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */\r
+ #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */\r
+ #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */\r
+ #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */\r
+ #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */\r
+ #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */\r
+ #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */\r
+ #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */\r
+ #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */\r
+ #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */\r
+ #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */\r
+ #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */\r
+ #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */\r
+ #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */\r
+ #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */\r
+ #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */\r
+ #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */\r
+ #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */\r
+ #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+ #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */\r
+ #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */\r
+ #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */\r
+ #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */\r
+ #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+ #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */\r
+ #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */\r
+ #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */\r
+ #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */\r
+ #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+ #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */\r
+ #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */\r
+ #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */\r
+ #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */\r
+ #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+ #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */\r
+ #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */\r
+ #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */\r
+ #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CAE0 (0x4005C404U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 0) */\r
+ #define REG_PWM1_CAEUPD0 (0x4005C408U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CAE1 (0x4005C424U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 1) */\r
+ #define REG_PWM1_CAEUPD1 (0x4005C428U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+ #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */\r
+ #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CAE2 (0x4005C444U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 2) */\r
+ #define REG_PWM1_CAEUPD2 (0x4005C448U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+ #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */\r
+ #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CAE3 (0x4005C464U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 3) */\r
+ #define REG_PWM1_CAEUPD3 (0x4005C468U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+ #define REG_PWM1_ETRG3 (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */\r
+ #define REG_PWM1_LEBR3 (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */\r
+#else\r
+ #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */\r
+ #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */\r
+ #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */\r
+ #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */\r
+ #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */\r
+ #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */\r
+ #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */\r
+ #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */\r
+ #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */\r
+ #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */\r
+ #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */\r
+ #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */\r
+ #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */\r
+ #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */\r
+ #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */\r
+ #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */\r
+ #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */\r
+ #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */\r
+ #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */\r
+ #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */\r
+ #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */\r
+ #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */\r
+ #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */\r
+ #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */\r
+ #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */\r
+ #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */\r
+ #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */\r
+ #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */\r
+ #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */\r
+ #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */\r
+ #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */\r
+ #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */\r
+ #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */\r
+ #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */\r
+ #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */\r
+ #define REG_PWM1_VERSION (*(__I uint32_t*)0x4005C0FCU) /**< \brief (PWM1) Version Register */\r
+ #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */\r
+ #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */\r
+ #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */\r
+ #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */\r
+ #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */\r
+ #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */\r
+ #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */\r
+ #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */\r
+ #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */\r
+ #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */\r
+ #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */\r
+ #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */\r
+ #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */\r
+ #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */\r
+ #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */\r
+ #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */\r
+ #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */\r
+ #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */\r
+ #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */\r
+ #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */\r
+ #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */\r
+ #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */\r
+ #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */\r
+ #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */\r
+ #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */\r
+ #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */\r
+ #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */\r
+ #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */\r
+ #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */\r
+ #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */\r
+ #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */\r
+ #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */\r
+ #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */\r
+ #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+ #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */\r
+ #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */\r
+ #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */\r
+ #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */\r
+ #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+ #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */\r
+ #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */\r
+ #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */\r
+ #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */\r
+ #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+ #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */\r
+ #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */\r
+ #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */\r
+ #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */\r
+ #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+ #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */\r
+ #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */\r
+ #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */\r
+ #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CAE0 (*(__IO uint32_t*)0x4005C404U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 0) */\r
+ #define REG_PWM1_CAEUPD0 (*(__O uint32_t*)0x4005C408U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 0) */\r
+ #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */\r
+ #define REG_PWM1_CAE1 (*(__IO uint32_t*)0x4005C424U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 1) */\r
+ #define REG_PWM1_CAEUPD1 (*(__O uint32_t*)0x4005C428U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 1) */\r
+ #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */\r
+ #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */\r
+ #define REG_PWM1_CAE2 (*(__IO uint32_t*)0x4005C444U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 2) */\r
+ #define REG_PWM1_CAEUPD2 (*(__O uint32_t*)0x4005C448U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 2) */\r
+ #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */\r
+ #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */\r
+ #define REG_PWM1_CAE3 (*(__IO uint32_t*)0x4005C464U) /**< \brief (PWM1) PWM Channel Additional Edge Register (ch_num = 3) */\r
+ #define REG_PWM1_CAEUPD3 (*(__O uint32_t*)0x4005C468U) /**< \brief (PWM1) PWM Channel Additional Edge Update Register (ch_num = 3) */\r
+ #define REG_PWM1_ETRG3 (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */\r
+ #define REG_PWM1_LEBR3 (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_PWM1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_QSPI_INSTANCE_\r
+#define _SAM_QSPI_INSTANCE_\r
+\r
+/* ========== Register definition for QSPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */\r
+ #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+ #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+ #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+ #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */\r
+ #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+ #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+ #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+ #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+ #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+ #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+ #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+ #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+ #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+ #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+ #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+ #define REG_QSPI_VERSION (0x4007C0FCU) /**< \brief (QSPI) Version Register */\r
+#else\r
+ #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */\r
+ #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+ #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+ #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+ #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */\r
+ #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+ #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+ #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+ #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+ #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+ #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+ #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+ #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+ #define REG_QSPI_SKR (*(__IO uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+ #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+ #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+ #define REG_QSPI_VERSION (*(__I uint32_t*)0x4007C0FCU) /**< \brief (QSPI) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_QSPI_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RSTC_INSTANCE_\r
+#define _SAM_RSTC_INSTANCE_\r
+\r
+/* ========== Register definition for RSTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */\r
+ #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */\r
+ #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */\r
+#else\r
+ #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */\r
+ #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */\r
+ #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_RSTC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RTC_INSTANCE_\r
+#define _SAM_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */\r
+ #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */\r
+ #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */\r
+ #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */\r
+ #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */\r
+ #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */\r
+ #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */\r
+ #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */\r
+ #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */\r
+ #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */\r
+ #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */\r
+ #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */\r
+ #define REG_RTC_TSTR0 (0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */\r
+ #define REG_RTC_TSDR0 (0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */\r
+ #define REG_RTC_TSSR0 (0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */\r
+ #define REG_RTC_TSTR1 (0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */\r
+ #define REG_RTC_TSDR1 (0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */\r
+ #define REG_RTC_TSSR1 (0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */\r
+ #define REG_RTC_WPMR (0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */\r
+ #define REG_RTC_VERSION (0x400E195CU) /**< \brief (RTC) Version Register */\r
+#else\r
+ #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */\r
+ #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */\r
+ #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */\r
+ #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */\r
+ #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */\r
+ #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */\r
+ #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */\r
+ #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */\r
+ #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */\r
+ #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */\r
+ #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */\r
+ #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */\r
+ #define REG_RTC_TSTR0 (*(__I uint32_t*)0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */\r
+ #define REG_RTC_TSDR0 (*(__I uint32_t*)0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */\r
+ #define REG_RTC_TSSR0 (*(__I uint32_t*)0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */\r
+ #define REG_RTC_TSTR1 (*(__I uint32_t*)0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */\r
+ #define REG_RTC_TSDR1 (*(__I uint32_t*)0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */\r
+ #define REG_RTC_TSSR1 (*(__I uint32_t*)0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */\r
+ #define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */\r
+ #define REG_RTC_VERSION (*(__I uint32_t*)0x400E195CU) /**< \brief (RTC) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_RTC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_RTT_INSTANCE_\r
+#define _SAM_RTT_INSTANCE_\r
+\r
+/* ========== Register definition for RTT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */\r
+ #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */\r
+ #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */\r
+ #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */\r
+#else\r
+ #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */\r
+ #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */\r
+ #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */\r
+ #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_RTT_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SDRAMC_INSTANCE_\r
+#define _SAM_SDRAMC_INSTANCE_\r
+\r
+/* ========== Register definition for SDRAMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+ #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+ #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+ #define REG_SDRAMC_HSR (0x4008400CU) /**< \brief (SDRAMC) SDRAMC High Speed Register */\r
+ #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+ #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+ #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+ #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+ #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+ #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+ #define REG_SDRAMC_CR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+ #define REG_SDRAMC_VERSION (0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */\r
+#else\r
+ #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+ #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+ #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+ #define REG_SDRAMC_HSR (*(__IO uint32_t*)0x4008400CU) /**< \brief (SDRAMC) SDRAMC High Speed Register */\r
+ #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+ #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+ #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+ #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+ #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+ #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+ #define REG_SDRAMC_CR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+ #define REG_SDRAMC_VERSION (*(__I uint32_t*)0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SDRAMC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SMC_INSTANCE_\r
+#define _SAM_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+ #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+ #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+ #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+ #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+ #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+ #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+ #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+ #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+ #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+ #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+ #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+ #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+ #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+ #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+ #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+ #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+ #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+ #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+ #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+ #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+ #define REG_SMC_ADDRSIZE (0x400800ECU) /**< \brief (SMC) SMC Address Size Register */\r
+ #define REG_SMC_IPNAME (0x400800F0U) /**< \brief (SMC) SMC IP Name 1 Register */\r
+ #define REG_SMC_FEATURES (0x400800F8U) /**< \brief (SMC) SMC Features Register */\r
+ #define REG_SMC_VERSION (0x400800FCU) /**< \brief (SMC) SMC Version Register */\r
+#else\r
+ #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+ #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+ #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+ #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+ #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+ #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+ #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+ #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+ #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+ #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+ #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+ #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+ #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+ #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+ #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+ #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+ #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+ #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+ #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+ #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+ #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+ #define REG_SMC_ADDRSIZE (*(__I uint32_t*)0x400800ECU) /**< \brief (SMC) SMC Address Size Register */\r
+ #define REG_SMC_IPNAME (*(__I uint32_t*)0x400800F0U) /**< \brief (SMC) SMC IP Name 1 Register */\r
+ #define REG_SMC_FEATURES (*(__I uint32_t*)0x400800F8U) /**< \brief (SMC) SMC Features Register */\r
+ #define REG_SMC_VERSION (*(__I uint32_t*)0x400800FCU) /**< \brief (SMC) SMC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SMC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SPI0_INSTANCE_\r
+#define _SAM_SPI0_INSTANCE_\r
+\r
+/* ========== Register definition for SPI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */\r
+ #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */\r
+ #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */\r
+ #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */\r
+ #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */\r
+ #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */\r
+ #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */\r
+ #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */\r
+ #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */\r
+ #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */\r
+ #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */\r
+ #define REG_SPI0_VERSION (0x400080FCU) /**< \brief (SPI0) Version Register */\r
+#else\r
+ #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */\r
+ #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */\r
+ #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */\r
+ #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */\r
+ #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */\r
+ #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */\r
+ #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */\r
+ #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */\r
+ #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */\r
+ #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */\r
+ #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */\r
+ #define REG_SPI0_VERSION (*(__I uint32_t*)0x400080FCU) /**< \brief (SPI0) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SPI0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SPI1_INSTANCE_\r
+#define _SAM_SPI1_INSTANCE_\r
+\r
+/* ========== Register definition for SPI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */\r
+ #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */\r
+ #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */\r
+ #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */\r
+ #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */\r
+ #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */\r
+ #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */\r
+ #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */\r
+ #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register */\r
+ #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Control Register */\r
+ #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */\r
+ #define REG_SPI1_VERSION (0x400580FCU) /**< \brief (SPI1) Version Register */\r
+#else\r
+ #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */\r
+ #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */\r
+ #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */\r
+ #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */\r
+ #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */\r
+ #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */\r
+ #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */\r
+ #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */\r
+ #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */\r
+ #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Control Register */\r
+ #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */\r
+ #define REG_SPI1_VERSION (*(__I uint32_t*)0x400580FCU) /**< \brief (SPI1) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SPI1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SSC_INSTANCE_\r
+#define _SAM_SSC_INSTANCE_\r
+\r
+/* ========== Register definition for SSC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */\r
+ #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+ #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+ #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+ #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+ #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+ #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+ #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+ #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+ #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+ #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+ #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+ #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */\r
+ #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+ #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+ #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+ #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+ #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+ #define REG_SSC_VERSION (0x400040FCU) /**< \brief (SSC) Version Register */\r
+#else\r
+ #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */\r
+ #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+ #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+ #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+ #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+ #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+ #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+ #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+ #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+ #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+ #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+ #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+ #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */\r
+ #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+ #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+ #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+ #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+ #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+ #define REG_SSC_VERSION (*(__I uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SSC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SUPC_INSTANCE_\r
+#define _SAM_SUPC_INSTANCE_\r
+\r
+/* ========== Register definition for SUPC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */\r
+ #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+ #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+ #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */\r
+ #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */\r
+ #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */\r
+ #define REG_SYSC_VERSION (0x400E190CU) /**< \brief (SUPC) Version Register */\r
+#else\r
+ #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */\r
+ #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+ #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+ #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */\r
+ #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */\r
+ #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */\r
+ #define REG_SYSC_VERSION (*(__I uint32_t*)0x400E190CU) /**< \brief (SUPC) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SUPC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TC0_INSTANCE_\r
+#define _SAM_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+ #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+ #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */\r
+ #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+ #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */\r
+ #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */\r
+ #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */\r
+ #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+ #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */\r
+ #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+ #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+ #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */\r
+ #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+ #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */\r
+ #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */\r
+ #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */\r
+ #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+ #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */\r
+ #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+ #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+ #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */\r
+ #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+ #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */\r
+ #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */\r
+ #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */\r
+ #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+ #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */\r
+ #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */\r
+ #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */\r
+ #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+ #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+ #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+ #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+ #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */\r
+ #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */\r
+ #define REG_TC0_VER (0x4000C0FCU) /**< \brief (TC0) Version Register */\r
+#else\r
+ #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+ #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+ #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */\r
+ #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+ #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */\r
+ #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */\r
+ #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */\r
+ #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+ #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */\r
+ #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+ #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+ #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */\r
+ #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+ #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */\r
+ #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */\r
+ #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */\r
+ #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+ #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */\r
+ #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+ #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+ #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */\r
+ #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+ #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */\r
+ #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */\r
+ #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */\r
+ #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+ #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */\r
+ #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */\r
+ #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */\r
+ #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+ #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+ #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+ #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+ #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */\r
+ #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */\r
+ #define REG_TC0_VER (*(__I uint32_t*)0x4000C0FCU) /**< \brief (TC0) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TC0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TC1_INSTANCE_\r
+#define _SAM_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+ #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+ #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */\r
+ #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+ #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */\r
+ #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */\r
+ #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */\r
+ #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+ #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */\r
+ #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+ #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+ #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */\r
+ #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+ #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */\r
+ #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */\r
+ #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */\r
+ #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+ #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */\r
+ #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+ #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+ #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */\r
+ #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+ #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */\r
+ #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */\r
+ #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */\r
+ #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+ #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */\r
+ #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */\r
+ #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */\r
+ #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+ #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+ #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+ #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+ #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */\r
+ #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */\r
+ #define REG_TC1_VER (0x400100FCU) /**< \brief (TC1) Version Register */\r
+#else\r
+ #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+ #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+ #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */\r
+ #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+ #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */\r
+ #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */\r
+ #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */\r
+ #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+ #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */\r
+ #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+ #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+ #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */\r
+ #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+ #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */\r
+ #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */\r
+ #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */\r
+ #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+ #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */\r
+ #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+ #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+ #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */\r
+ #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+ #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */\r
+ #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */\r
+ #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */\r
+ #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+ #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */\r
+ #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */\r
+ #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */\r
+ #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+ #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+ #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+ #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+ #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */\r
+ #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */\r
+ #define REG_TC1_VER (*(__I uint32_t*)0x400100FCU) /**< \brief (TC1) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TC1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TC2_INSTANCE_\r
+#define _SAM_TC2_INSTANCE_\r
+\r
+/* ========== Register definition for TC2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+ #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+ #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */\r
+ #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+ #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */\r
+ #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */\r
+ #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */\r
+ #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+ #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */\r
+ #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+ #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+ #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */\r
+ #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+ #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */\r
+ #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */\r
+ #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */\r
+ #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+ #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */\r
+ #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+ #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+ #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */\r
+ #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+ #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */\r
+ #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */\r
+ #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */\r
+ #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+ #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */\r
+ #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */\r
+ #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */\r
+ #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+ #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+ #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+ #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+ #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */\r
+ #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */\r
+ #define REG_TC2_VER (0x400140FCU) /**< \brief (TC2) Version Register */\r
+#else\r
+ #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+ #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+ #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */\r
+ #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+ #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */\r
+ #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */\r
+ #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */\r
+ #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+ #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */\r
+ #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+ #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+ #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */\r
+ #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+ #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */\r
+ #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */\r
+ #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */\r
+ #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+ #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */\r
+ #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+ #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+ #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */\r
+ #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+ #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */\r
+ #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */\r
+ #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */\r
+ #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+ #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */\r
+ #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */\r
+ #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */\r
+ #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+ #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+ #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+ #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+ #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */\r
+ #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */\r
+ #define REG_TC2_VER (*(__I uint32_t*)0x400140FCU) /**< \brief (TC2) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TC2_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TC3_INSTANCE_\r
+#define _SAM_TC3_INSTANCE_\r
+\r
+/* ========== Register definition for TC3 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */\r
+ #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */\r
+ #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */\r
+ #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */\r
+ #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */\r
+ #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */\r
+ #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */\r
+ #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */\r
+ #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */\r
+ #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */\r
+ #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */\r
+ #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */\r
+ #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */\r
+ #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */\r
+ #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */\r
+ #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */\r
+ #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */\r
+ #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */\r
+ #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */\r
+ #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */\r
+ #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */\r
+ #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */\r
+ #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */\r
+ #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */\r
+ #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */\r
+ #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */\r
+ #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */\r
+ #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */\r
+ #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */\r
+ #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */\r
+ #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */\r
+ #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */\r
+ #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */\r
+ #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */\r
+ #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */\r
+ #define REG_TC3_VER (0x400540FCU) /**< \brief (TC3) Version Register */\r
+#else\r
+ #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */\r
+ #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */\r
+ #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */\r
+ #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */\r
+ #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */\r
+ #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */\r
+ #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */\r
+ #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */\r
+ #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */\r
+ #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */\r
+ #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */\r
+ #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */\r
+ #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */\r
+ #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */\r
+ #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */\r
+ #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */\r
+ #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */\r
+ #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */\r
+ #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */\r
+ #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */\r
+ #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */\r
+ #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */\r
+ #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */\r
+ #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */\r
+ #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */\r
+ #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */\r
+ #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */\r
+ #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */\r
+ #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */\r
+ #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */\r
+ #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */\r
+ #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */\r
+ #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */\r
+ #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */\r
+ #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */\r
+ #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */\r
+ #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */\r
+ #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */\r
+ #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */\r
+ #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */\r
+ #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */\r
+ #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */\r
+ #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */\r
+ #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */\r
+ #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */\r
+ #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */\r
+ #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */\r
+ #define REG_TC3_VER (*(__I uint32_t*)0x400540FCU) /**< \brief (TC3) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TC3_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TRNG_INSTANCE_\r
+#define _SAM_TRNG_INSTANCE_\r
+\r
+/* ========== Register definition for TRNG peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */\r
+ #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */\r
+ #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */\r
+ #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */\r
+ #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */\r
+ #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */\r
+ #define REG_TRNG_VERSION (0x400700FCU) /**< \brief (TRNG) Version Register */\r
+#else\r
+ #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */\r
+ #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */\r
+ #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */\r
+ #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */\r
+ #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */\r
+ #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */\r
+ #define REG_TRNG_VERSION (*(__I uint32_t*)0x400700FCU) /**< \brief (TRNG) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TRNG_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TWI0_INSTANCE_\r
+#define _SAM_TWI0_INSTANCE_\r
+\r
+/* ========== Register definition for TWI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */\r
+ #define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+ #define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+ #define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+ #define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+ #define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */\r
+ #define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+ #define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+ #define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+ #define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+ #define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+ #define REG_TWI0_SMBTR (0x40018038U) /**< \brief (TWI0) SMBus Timing Register */\r
+ #define REG_TWI0_ACR (0x40018040U) /**< \brief (TWI0) Alternative Command Register */\r
+ #define REG_TWI0_FILTR (0x40018044U) /**< \brief (TWI0) Filter Register */\r
+ #define REG_TWI0_SWMR (0x4001804CU) /**< \brief (TWI0) SleepWalking Matching Register */\r
+ #define REG_TWI0_DR (0x400180D0U) /**< \brief (TWI0) Debug Register */\r
+ #define REG_TWI0_WPMR (0x400180E4U) /**< \brief (TWI0) Protection Mode Register */\r
+ #define REG_TWI0_WPSR (0x400180E8U) /**< \brief (TWI0) Protection Status Register */\r
+ #define REG_TWI0_VER (0x400180FCU) /**< \brief (TWI0) Version Register */\r
+#else\r
+ #define REG_TWI0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWI0) Control Register */\r
+ #define REG_TWI0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+ #define REG_TWI0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+ #define REG_TWI0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+ #define REG_TWI0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+ #define REG_TWI0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWI0) Status Register */\r
+ #define REG_TWI0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+ #define REG_TWI0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+ #define REG_TWI0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+ #define REG_TWI0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+ #define REG_TWI0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+ #define REG_TWI0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWI0) SMBus Timing Register */\r
+ #define REG_TWI0_ACR (*(__IO uint32_t*)0x40018040U) /**< \brief (TWI0) Alternative Command Register */\r
+ #define REG_TWI0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWI0) Filter Register */\r
+ #define REG_TWI0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWI0) SleepWalking Matching Register */\r
+ #define REG_TWI0_DR (*(__I uint32_t*)0x400180D0U) /**< \brief (TWI0) Debug Register */\r
+ #define REG_TWI0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWI0) Protection Mode Register */\r
+ #define REG_TWI0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWI0) Protection Status Register */\r
+ #define REG_TWI0_VER (*(__I uint32_t*)0x400180FCU) /**< \brief (TWI0) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TWI0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TWI1_INSTANCE_\r
+#define _SAM_TWI1_INSTANCE_\r
+\r
+/* ========== Register definition for TWI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */\r
+ #define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+ #define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+ #define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+ #define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+ #define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */\r
+ #define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+ #define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+ #define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+ #define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+ #define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+ #define REG_TWI1_WPMR (0x4001C0E4U) /**< \brief (TWI1) Write Protection Mode Register */\r
+ #define REG_TWI1_WPSR (0x4001C0E8U) /**< \brief (TWI1) Write Protection Status Register */\r
+#else\r
+ #define REG_TWI1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWI1) Control Register */\r
+ #define REG_TWI1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+ #define REG_TWI1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+ #define REG_TWI1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+ #define REG_TWI1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+ #define REG_TWI1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWI1) Status Register */\r
+ #define REG_TWI1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+ #define REG_TWI1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+ #define REG_TWI1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+ #define REG_TWI1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+ #define REG_TWI1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+ #define REG_TWI1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWI1) Write Protection Mode Register */\r
+ #define REG_TWI1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWI1) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TWI1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_TWI2_INSTANCE_\r
+#define _SAM_TWI2_INSTANCE_\r
+\r
+/* ========== Register definition for TWI2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_TWI2_CR (0x40060000U) /**< \brief (TWI2) Control Register */\r
+ #define REG_TWI2_MMR (0x40060004U) /**< \brief (TWI2) Master Mode Register */\r
+ #define REG_TWI2_SMR (0x40060008U) /**< \brief (TWI2) Slave Mode Register */\r
+ #define REG_TWI2_IADR (0x4006000CU) /**< \brief (TWI2) Internal Address Register */\r
+ #define REG_TWI2_CWGR (0x40060010U) /**< \brief (TWI2) Clock Waveform Generator Register */\r
+ #define REG_TWI2_SR (0x40060020U) /**< \brief (TWI2) Status Register */\r
+ #define REG_TWI2_IER (0x40060024U) /**< \brief (TWI2) Interrupt Enable Register */\r
+ #define REG_TWI2_IDR (0x40060028U) /**< \brief (TWI2) Interrupt Disable Register */\r
+ #define REG_TWI2_IMR (0x4006002CU) /**< \brief (TWI2) Interrupt Mask Register */\r
+ #define REG_TWI2_RHR (0x40060030U) /**< \brief (TWI2) Receive Holding Register */\r
+ #define REG_TWI2_THR (0x40060034U) /**< \brief (TWI2) Transmit Holding Register */\r
+ #define REG_TWI2_WPMR (0x400600E4U) /**< \brief (TWI2) Write Protection Mode Register */\r
+ #define REG_TWI2_WPSR (0x400600E8U) /**< \brief (TWI2) Write Protection Status Register */\r
+#else\r
+ #define REG_TWI2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWI2) Control Register */\r
+ #define REG_TWI2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWI2) Master Mode Register */\r
+ #define REG_TWI2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWI2) Slave Mode Register */\r
+ #define REG_TWI2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWI2) Internal Address Register */\r
+ #define REG_TWI2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWI2) Clock Waveform Generator Register */\r
+ #define REG_TWI2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWI2) Status Register */\r
+ #define REG_TWI2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWI2) Interrupt Enable Register */\r
+ #define REG_TWI2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWI2) Interrupt Disable Register */\r
+ #define REG_TWI2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWI2) Interrupt Mask Register */\r
+ #define REG_TWI2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWI2) Receive Holding Register */\r
+ #define REG_TWI2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWI2) Transmit Holding Register */\r
+ #define REG_TWI2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWI2) Write Protection Mode Register */\r
+ #define REG_TWI2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWI2) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_TWI2_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART0_INSTANCE_\r
+#define _SAM_UART0_INSTANCE_\r
+\r
+/* ========== Register definition for UART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */\r
+ #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */\r
+ #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */\r
+ #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */\r
+ #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */\r
+ #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */\r
+ #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */\r
+ #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */\r
+ #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */\r
+ #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */\r
+ #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */\r
+#else\r
+ #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */\r
+ #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */\r
+ #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */\r
+ #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */\r
+ #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */\r
+ #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */\r
+ #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */\r
+ #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */\r
+ #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */\r
+ #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */\r
+ #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_UART0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART1_INSTANCE_\r
+#define _SAM_UART1_INSTANCE_\r
+\r
+/* ========== Register definition for UART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */\r
+ #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */\r
+ #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */\r
+ #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */\r
+ #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */\r
+ #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */\r
+ #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */\r
+ #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */\r
+ #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */\r
+ #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */\r
+ #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */\r
+#else\r
+ #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */\r
+ #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */\r
+ #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */\r
+ #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */\r
+ #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */\r
+ #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */\r
+ #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */\r
+ #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */\r
+ #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */\r
+ #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */\r
+ #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_UART1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART2_INSTANCE_\r
+#define _SAM_UART2_INSTANCE_\r
+\r
+/* ========== Register definition for UART2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */\r
+ #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */\r
+ #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */\r
+ #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */\r
+ #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */\r
+ #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */\r
+ #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */\r
+ #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */\r
+ #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */\r
+ #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */\r
+ #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */\r
+#else\r
+ #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */\r
+ #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */\r
+ #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */\r
+ #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */\r
+ #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */\r
+ #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */\r
+ #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */\r
+ #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */\r
+ #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */\r
+ #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */\r
+ #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_UART2_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART3_INSTANCE_\r
+#define _SAM_UART3_INSTANCE_\r
+\r
+/* ========== Register definition for UART3 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */\r
+ #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */\r
+ #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */\r
+ #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */\r
+ #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */\r
+ #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */\r
+ #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */\r
+ #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */\r
+ #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */\r
+ #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */\r
+ #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */\r
+#else\r
+ #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */\r
+ #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */\r
+ #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */\r
+ #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */\r
+ #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */\r
+ #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */\r
+ #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */\r
+ #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */\r
+ #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */\r
+ #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */\r
+ #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_UART3_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_UART4_INSTANCE_\r
+#define _SAM_UART4_INSTANCE_\r
+\r
+/* ========== Register definition for UART4 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */\r
+ #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */\r
+ #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */\r
+ #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */\r
+ #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */\r
+ #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */\r
+ #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */\r
+ #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */\r
+ #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */\r
+ #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */\r
+ #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */\r
+#else\r
+ #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */\r
+ #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */\r
+ #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */\r
+ #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */\r
+ #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */\r
+ #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */\r
+ #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */\r
+ #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */\r
+ #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */\r
+ #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */\r
+ #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_UART4_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_USART0_INSTANCE_\r
+#define _SAM_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */\r
+ #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */\r
+ #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+ #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+ #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+ #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+ #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */\r
+ #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */\r
+ #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+ #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+ #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+ #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+ #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+ #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+ #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */\r
+ #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */\r
+ #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */\r
+ #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */\r
+ #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */\r
+ #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */\r
+ #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */\r
+ #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */\r
+ #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */\r
+ #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */\r
+ #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */\r
+ #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */\r
+ #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */\r
+ #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */\r
+ #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */\r
+ #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */\r
+ #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */\r
+ #define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */\r
+#else\r
+ #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */\r
+ #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */\r
+ #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+ #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+ #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+ #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+ #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */\r
+ #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */\r
+ #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+ #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+ #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+ #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+ #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+ #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+ #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */\r
+ #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */\r
+ #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */\r
+ #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */\r
+ #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */\r
+ #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */\r
+ #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */\r
+ #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */\r
+ #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */\r
+ #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */\r
+ #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */\r
+ #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */\r
+ #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */\r
+ #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */\r
+ #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */\r
+ #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */\r
+ #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */\r
+ #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_USART0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_USART1_INSTANCE_\r
+#define _SAM_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */\r
+ #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */\r
+ #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+ #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+ #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+ #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+ #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */\r
+ #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */\r
+ #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+ #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+ #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+ #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+ #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+ #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+ #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */\r
+ #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */\r
+ #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */\r
+ #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */\r
+ #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */\r
+ #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */\r
+ #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */\r
+ #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */\r
+ #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */\r
+ #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */\r
+ #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */\r
+ #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */\r
+ #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */\r
+ #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */\r
+ #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */\r
+ #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */\r
+ #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */\r
+ #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */\r
+#else\r
+ #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */\r
+ #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */\r
+ #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+ #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+ #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+ #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+ #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */\r
+ #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */\r
+ #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+ #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+ #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+ #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+ #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+ #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+ #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */\r
+ #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */\r
+ #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */\r
+ #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */\r
+ #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */\r
+ #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */\r
+ #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */\r
+ #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */\r
+ #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */\r
+ #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */\r
+ #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */\r
+ #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */\r
+ #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */\r
+ #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */\r
+ #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */\r
+ #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */\r
+ #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */\r
+ #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_USART1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_USART2_INSTANCE_\r
+#define _SAM_USART2_INSTANCE_\r
+\r
+/* ========== Register definition for USART2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */\r
+ #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */\r
+ #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */\r
+ #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */\r
+ #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */\r
+ #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */\r
+ #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */\r
+ #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */\r
+ #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+ #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */\r
+ #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+ #define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */\r
+ #define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */\r
+ #define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */\r
+ #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */\r
+ #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */\r
+ #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */\r
+ #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */\r
+ #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */\r
+ #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */\r
+ #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */\r
+ #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */\r
+ #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */\r
+ #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */\r
+ #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */\r
+ #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */\r
+ #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */\r
+ #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */\r
+ #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */\r
+ #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */\r
+ #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */\r
+ #define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */\r
+#else\r
+ #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */\r
+ #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */\r
+ #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */\r
+ #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */\r
+ #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */\r
+ #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */\r
+ #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */\r
+ #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */\r
+ #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+ #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */\r
+ #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+ #define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */\r
+ #define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */\r
+ #define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */\r
+ #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */\r
+ #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */\r
+ #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */\r
+ #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */\r
+ #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */\r
+ #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */\r
+ #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */\r
+ #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */\r
+ #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */\r
+ #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */\r
+ #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */\r
+ #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */\r
+ #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */\r
+ #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */\r
+ #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */\r
+ #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */\r
+ #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */\r
+ #define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_USART2_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_USBHS_INSTANCE_\r
+#define _SAM_USBHS_INSTANCE_\r
+\r
+/* ========== Register definition for USBHS peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */\r
+ #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */\r
+ #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */\r
+ #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */\r
+ #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */\r
+ #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */\r
+ #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */\r
+ #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */\r
+ #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */\r
+ #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */\r
+ #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */\r
+ #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */\r
+ #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */\r
+ #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */\r
+ #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */\r
+ #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */\r
+ #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */\r
+ #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */\r
+ #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */\r
+ #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */\r
+ #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */\r
+ #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */\r
+ #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */\r
+ #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */\r
+ #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */\r
+ #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */\r
+ #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */\r
+ #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */\r
+ #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */\r
+ #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */\r
+ #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */\r
+ #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */\r
+ #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */\r
+ #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */\r
+ #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */\r
+ #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */\r
+ #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */\r
+ #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */\r
+ #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */\r
+ #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */\r
+ #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */\r
+ #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */\r
+ #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */\r
+ #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */\r
+ #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */\r
+ #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */\r
+ #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */\r
+ #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */\r
+ #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */\r
+ #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */\r
+ #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */\r
+ #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */\r
+ #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */\r
+ #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */\r
+ #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */\r
+ #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */\r
+ #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */\r
+ #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */\r
+ #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */\r
+ #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */\r
+ #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */\r
+ #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */\r
+ #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */\r
+ #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */\r
+ #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */\r
+ #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */\r
+ #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */\r
+ #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */\r
+ #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */\r
+ #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */\r
+ #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */\r
+ #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */\r
+ #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */\r
+ #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */\r
+ #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */\r
+ #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */\r
+ #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */\r
+ #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */\r
+ #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */\r
+ #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */\r
+ #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */\r
+ #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */\r
+ #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */\r
+ #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */\r
+ #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */\r
+ #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */\r
+ #define REG_USBHS_FEATURES (0x4003881CU) /**< \brief (USBHS) General Features Register */\r
+ #define REG_USBHS_ADDRSIZE (0x40038820U) /**< \brief (USBHS) General APB Address Size Register */\r
+ #define REG_USBHS_IPNAME1 (0x40038824U) /**< \brief (USBHS) General Name Register 1 */\r
+ #define REG_USBHS_IPNAME2 (0x40038828U) /**< \brief (USBHS) General Name Register 2 */\r
+ #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */\r
+#else\r
+ #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */\r
+ #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */\r
+ #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */\r
+ #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */\r
+ #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */\r
+ #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */\r
+ #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */\r
+ #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */\r
+ #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */\r
+ #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */\r
+ #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */\r
+ #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */\r
+ #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */\r
+ #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */\r
+ #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */\r
+ #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */\r
+ #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */\r
+ #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */\r
+ #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */\r
+ #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */\r
+ #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */\r
+ #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */\r
+ #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */\r
+ #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */\r
+ #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */\r
+ #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */\r
+ #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */\r
+ #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */\r
+ #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */\r
+ #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */\r
+ #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */\r
+ #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */\r
+ #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */\r
+ #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */\r
+ #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */\r
+ #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */\r
+ #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */\r
+ #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */\r
+ #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */\r
+ #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */\r
+ #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */\r
+ #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */\r
+ #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */\r
+ #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */\r
+ #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */\r
+ #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */\r
+ #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */\r
+ #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */\r
+ #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */\r
+ #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */\r
+ #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */\r
+ #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */\r
+ #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */\r
+ #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */\r
+ #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */\r
+ #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */\r
+ #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */\r
+ #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */\r
+ #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */\r
+ #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */\r
+ #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */\r
+ #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */\r
+ #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */\r
+ #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */\r
+ #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */\r
+ #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */\r
+ #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */\r
+ #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */\r
+ #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */\r
+ #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */\r
+ #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */\r
+ #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */\r
+ #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */\r
+ #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */\r
+ #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */\r
+ #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */\r
+ #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */\r
+ #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */\r
+ #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */\r
+ #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */\r
+ #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */\r
+ #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */\r
+ #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */\r
+ #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */\r
+ #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */\r
+ #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */\r
+ #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */\r
+ #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */\r
+ #define REG_USBHS_FEATURES (*(__I uint32_t*)0x4003881CU) /**< \brief (USBHS) General Features Register */\r
+ #define REG_USBHS_ADDRSIZE (*(__I uint32_t*)0x40038820U) /**< \brief (USBHS) General APB Address Size Register */\r
+ #define REG_USBHS_IPNAME1 (*(__I uint32_t*)0x40038824U) /**< \brief (USBHS) General Name Register 1 */\r
+ #define REG_USBHS_IPNAME2 (*(__I uint32_t*)0x40038828U) /**< \brief (USBHS) General Name Register 2 */\r
+ #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_USBHS_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_WDT0_INSTANCE_\r
+#define _SAM_WDT0_INSTANCE_\r
+\r
+/* ========== Register definition for WDT0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_WDT0_CR (0x400E1850U) /**< \brief (WDT0) Control Register */\r
+ #define REG_WDT0_MR (0x400E1854U) /**< \brief (WDT0) Mode Register */\r
+ #define REG_WDT0_SR (0x400E1858U) /**< \brief (WDT0) Status Register */\r
+#else\r
+ #define REG_WDT0_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT0) Control Register */\r
+ #define REG_WDT0_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT0) Mode Register */\r
+ #define REG_WDT0_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT0) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_WDT0_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_WDT1_INSTANCE_\r
+#define _SAM_WDT1_INSTANCE_\r
+\r
+/* ========== Register definition for WDT1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_WDT1_CR (0x400E1900U) /**< \brief (WDT1) Control Register */\r
+ #define REG_WDT1_MR (0x400E1904U) /**< \brief (WDT1) Mode Register */\r
+ #define REG_WDT1_SR (0x400E1908U) /**< \brief (WDT1) Status Register */\r
+#else\r
+ #define REG_WDT1_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (WDT1) Control Register */\r
+ #define REG_WDT1_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (WDT1) Mode Register */\r
+ #define REG_WDT1_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (WDT1) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_WDT1_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_XDMAC_INSTANCE_\r
+#define _SAM_XDMAC_INSTANCE_\r
+\r
+/* ========== Register definition for XDMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+ #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */\r
+ #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */\r
+ #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */\r
+ #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */\r
+ #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */\r
+ #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */\r
+ #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */\r
+ #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */\r
+ #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */\r
+ #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */\r
+ #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */\r
+ #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */\r
+ #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */\r
+ #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */\r
+ #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */\r
+ #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */\r
+ #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */\r
+ #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */\r
+ #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */\r
+ #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */\r
+ #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */\r
+ #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */\r
+ #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */\r
+ #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */\r
+ #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */\r
+ #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */\r
+ #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */\r
+ #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */\r
+ #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */\r
+ #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */\r
+ #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */\r
+ #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */\r
+ #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */\r
+ #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */\r
+ #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */\r
+ #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */\r
+ #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */\r
+ #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */\r
+ #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */\r
+ #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */\r
+ #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */\r
+ #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */\r
+ #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */\r
+ #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */\r
+ #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */\r
+ #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */\r
+ #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */\r
+ #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */\r
+ #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */\r
+ #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */\r
+ #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */\r
+ #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */\r
+ #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */\r
+ #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */\r
+ #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */\r
+ #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */\r
+ #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */\r
+ #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */\r
+ #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */\r
+ #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */\r
+ #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */\r
+ #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */\r
+ #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */\r
+ #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */\r
+ #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */\r
+ #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */\r
+ #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */\r
+ #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */\r
+ #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */\r
+ #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */\r
+ #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */\r
+ #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */\r
+ #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */\r
+ #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */\r
+ #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */\r
+ #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */\r
+ #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */\r
+ #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */\r
+ #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */\r
+ #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */\r
+ #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */\r
+ #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */\r
+ #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */\r
+ #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */\r
+ #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */\r
+ #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */\r
+ #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */\r
+ #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */\r
+ #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */\r
+ #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */\r
+ #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */\r
+ #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */\r
+ #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */\r
+ #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */\r
+ #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */\r
+ #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */\r
+ #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */\r
+ #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */\r
+ #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */\r
+ #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */\r
+ #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */\r
+ #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */\r
+ #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */\r
+ #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */\r
+ #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */\r
+ #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */\r
+ #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */\r
+ #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */\r
+ #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */\r
+ #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */\r
+ #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */\r
+ #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */\r
+ #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */\r
+ #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */\r
+ #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */\r
+ #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */\r
+ #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */\r
+ #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */\r
+ #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */\r
+ #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */\r
+ #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */\r
+ #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */\r
+ #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */\r
+ #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */\r
+ #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */\r
+ #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */\r
+ #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */\r
+ #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */\r
+ #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */\r
+ #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */\r
+ #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */\r
+ #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */\r
+ #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */\r
+ #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */\r
+ #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */\r
+ #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */\r
+ #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */\r
+ #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */\r
+ #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */\r
+ #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */\r
+ #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */\r
+ #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */\r
+ #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */\r
+ #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */\r
+ #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */\r
+ #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */\r
+ #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */\r
+ #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */\r
+ #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */\r
+ #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */\r
+ #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */\r
+ #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */\r
+ #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */\r
+ #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */\r
+ #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */\r
+ #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */\r
+ #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */\r
+ #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */\r
+ #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */\r
+ #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */\r
+ #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */\r
+ #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */\r
+ #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */\r
+ #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */\r
+ #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */\r
+ #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */\r
+ #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */\r
+ #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */\r
+ #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */\r
+ #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */\r
+ #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */\r
+ #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */\r
+ #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */\r
+ #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */\r
+ #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */\r
+ #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */\r
+ #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */\r
+ #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */\r
+ #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */\r
+ #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */\r
+ #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */\r
+ #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */\r
+ #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */\r
+ #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */\r
+ #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */\r
+ #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */\r
+ #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */\r
+ #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */\r
+ #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */\r
+ #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */\r
+ #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */\r
+ #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */\r
+ #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */\r
+ #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */\r
+ #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */\r
+ #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */\r
+ #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */\r
+ #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */\r
+ #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */\r
+ #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */\r
+ #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */\r
+ #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */\r
+ #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */\r
+ #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */\r
+ #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */\r
+ #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */\r
+ #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */\r
+ #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */\r
+ #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */\r
+ #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */\r
+ #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */\r
+ #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */\r
+ #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */\r
+ #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */\r
+ #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */\r
+ #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */\r
+ #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */\r
+ #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */\r
+ #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */\r
+ #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */\r
+ #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */\r
+ #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */\r
+ #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */\r
+ #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */\r
+ #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */\r
+ #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */\r
+ #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */\r
+ #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */\r
+ #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */\r
+ #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */\r
+ #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */\r
+ #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */\r
+ #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */\r
+ #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */\r
+ #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */\r
+ #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */\r
+ #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */\r
+ #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */\r
+ #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */\r
+ #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */\r
+ #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */\r
+ #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */\r
+ #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */\r
+ #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */\r
+ #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */\r
+ #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */\r
+ #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */\r
+ #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */\r
+ #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */\r
+ #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */\r
+ #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */\r
+ #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */\r
+ #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */\r
+ #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */\r
+ #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */\r
+ #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */\r
+ #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */\r
+ #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */\r
+ #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */\r
+ #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */\r
+ #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */\r
+ #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */\r
+ #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */\r
+ #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */\r
+ #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */\r
+ #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */\r
+ #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */\r
+ #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */\r
+ #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */\r
+ #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */\r
+ #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */\r
+ #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */\r
+ #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */\r
+ #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */\r
+ #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */\r
+ #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */\r
+ #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */\r
+ #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */\r
+ #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */\r
+ #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */\r
+ #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */\r
+ #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */\r
+ #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */\r
+ #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */\r
+ #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */\r
+ #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */\r
+ #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */\r
+ #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */\r
+ #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */\r
+ #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */\r
+ #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */\r
+ #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */\r
+ #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */\r
+ #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */\r
+ #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */\r
+ #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */\r
+ #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */\r
+ #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */\r
+ #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */\r
+ #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */\r
+ #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */\r
+ #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */\r
+ #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */\r
+ #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */\r
+ #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */\r
+ #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */\r
+ #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */\r
+ #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */\r
+ #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */\r
+ #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */\r
+ #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */\r
+ #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */\r
+ #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */\r
+ #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */\r
+ #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */\r
+ #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */\r
+ #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */\r
+ #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */\r
+ #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */\r
+ #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */\r
+ #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */\r
+ #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */\r
+ #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */\r
+ #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */\r
+ #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */\r
+ #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */\r
+ #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */\r
+ #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */\r
+ #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */\r
+ #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */\r
+ #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */\r
+ #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */\r
+ #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */\r
+ #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */\r
+ #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */\r
+ #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */\r
+ #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */\r
+ #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */\r
+ #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */\r
+ #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */\r
+ #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */\r
+ #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */\r
+ #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */\r
+ #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */\r
+ #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */\r
+ #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */\r
+ #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */\r
+ #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */\r
+ #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */\r
+ #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */\r
+ #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */\r
+ #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */\r
+ #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */\r
+ #define REG_XDMAC_VERSION (0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */\r
+#else\r
+ #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */\r
+ #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */\r
+ #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */\r
+ #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */\r
+ #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */\r
+ #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */\r
+ #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */\r
+ #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */\r
+ #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */\r
+ #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */\r
+ #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */\r
+ #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */\r
+ #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */\r
+ #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */\r
+ #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */\r
+ #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */\r
+ #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */\r
+ #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */\r
+ #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */\r
+ #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */\r
+ #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */\r
+ #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */\r
+ #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */\r
+ #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */\r
+ #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */\r
+ #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */\r
+ #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */\r
+ #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */\r
+ #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */\r
+ #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */\r
+ #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */\r
+ #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */\r
+ #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */\r
+ #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */\r
+ #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */\r
+ #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */\r
+ #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */\r
+ #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */\r
+ #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */\r
+ #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */\r
+ #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */\r
+ #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */\r
+ #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */\r
+ #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */\r
+ #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */\r
+ #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */\r
+ #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */\r
+ #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */\r
+ #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */\r
+ #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */\r
+ #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */\r
+ #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */\r
+ #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */\r
+ #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */\r
+ #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */\r
+ #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */\r
+ #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */\r
+ #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */\r
+ #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */\r
+ #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */\r
+ #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */\r
+ #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */\r
+ #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */\r
+ #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */\r
+ #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */\r
+ #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */\r
+ #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */\r
+ #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */\r
+ #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */\r
+ #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */\r
+ #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */\r
+ #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */\r
+ #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */\r
+ #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */\r
+ #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */\r
+ #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */\r
+ #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */\r
+ #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */\r
+ #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */\r
+ #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */\r
+ #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */\r
+ #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */\r
+ #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */\r
+ #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */\r
+ #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */\r
+ #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */\r
+ #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */\r
+ #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */\r
+ #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */\r
+ #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */\r
+ #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */\r
+ #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */\r
+ #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */\r
+ #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */\r
+ #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */\r
+ #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */\r
+ #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */\r
+ #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */\r
+ #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */\r
+ #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */\r
+ #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */\r
+ #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */\r
+ #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */\r
+ #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */\r
+ #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */\r
+ #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */\r
+ #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */\r
+ #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */\r
+ #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */\r
+ #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */\r
+ #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */\r
+ #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */\r
+ #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */\r
+ #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */\r
+ #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */\r
+ #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */\r
+ #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */\r
+ #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */\r
+ #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */\r
+ #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */\r
+ #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */\r
+ #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */\r
+ #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */\r
+ #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */\r
+ #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */\r
+ #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */\r
+ #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */\r
+ #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */\r
+ #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */\r
+ #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */\r
+ #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */\r
+ #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */\r
+ #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */\r
+ #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */\r
+ #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */\r
+ #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */\r
+ #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */\r
+ #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */\r
+ #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */\r
+ #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */\r
+ #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */\r
+ #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */\r
+ #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */\r
+ #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */\r
+ #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */\r
+ #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */\r
+ #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */\r
+ #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */\r
+ #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */\r
+ #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */\r
+ #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */\r
+ #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */\r
+ #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */\r
+ #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */\r
+ #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */\r
+ #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */\r
+ #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */\r
+ #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */\r
+ #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */\r
+ #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */\r
+ #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */\r
+ #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */\r
+ #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */\r
+ #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */\r
+ #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */\r
+ #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */\r
+ #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */\r
+ #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */\r
+ #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */\r
+ #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */\r
+ #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */\r
+ #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */\r
+ #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */\r
+ #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */\r
+ #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */\r
+ #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */\r
+ #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */\r
+ #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */\r
+ #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */\r
+ #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */\r
+ #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */\r
+ #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */\r
+ #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */\r
+ #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */\r
+ #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */\r
+ #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */\r
+ #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */\r
+ #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */\r
+ #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */\r
+ #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */\r
+ #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */\r
+ #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */\r
+ #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */\r
+ #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */\r
+ #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */\r
+ #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */\r
+ #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */\r
+ #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */\r
+ #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */\r
+ #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */\r
+ #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */\r
+ #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */\r
+ #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */\r
+ #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */\r
+ #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */\r
+ #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */\r
+ #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */\r
+ #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */\r
+ #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */\r
+ #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */\r
+ #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */\r
+ #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */\r
+ #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */\r
+ #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */\r
+ #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */\r
+ #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */\r
+ #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */\r
+ #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */\r
+ #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */\r
+ #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */\r
+ #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */\r
+ #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */\r
+ #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */\r
+ #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */\r
+ #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */\r
+ #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */\r
+ #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */\r
+ #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */\r
+ #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */\r
+ #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */\r
+ #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */\r
+ #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */\r
+ #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */\r
+ #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */\r
+ #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */\r
+ #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */\r
+ #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */\r
+ #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */\r
+ #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */\r
+ #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */\r
+ #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */\r
+ #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */\r
+ #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */\r
+ #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */\r
+ #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */\r
+ #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */\r
+ #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */\r
+ #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */\r
+ #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */\r
+ #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */\r
+ #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */\r
+ #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */\r
+ #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */\r
+ #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */\r
+ #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */\r
+ #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */\r
+ #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */\r
+ #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */\r
+ #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */\r
+ #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */\r
+ #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */\r
+ #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */\r
+ #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */\r
+ #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */\r
+ #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */\r
+ #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */\r
+ #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */\r
+ #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */\r
+ #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */\r
+ #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */\r
+ #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */\r
+ #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */\r
+ #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */\r
+ #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */\r
+ #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */\r
+ #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */\r
+ #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */\r
+ #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */\r
+ #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */\r
+ #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */\r
+ #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */\r
+ #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */\r
+ #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */\r
+ #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */\r
+ #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */\r
+ #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */\r
+ #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */\r
+ #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */\r
+ #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */\r
+ #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */\r
+ #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */\r
+ #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */\r
+ #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */\r
+ #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */\r
+ #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */\r
+ #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */\r
+ #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */\r
+ #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */\r
+ #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */\r
+ #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */\r
+ #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */\r
+ #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */\r
+ #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */\r
+ #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */\r
+ #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */\r
+ #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */\r
+ #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */\r
+ #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */\r
+ #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */\r
+ #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */\r
+ #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */\r
+ #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */\r
+ #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */\r
+ #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */\r
+ #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */\r
+ #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */\r
+ #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */\r
+ #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */\r
+ #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */\r
+ #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */\r
+ #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */\r
+ #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */\r
+ #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */\r
+ #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */\r
+ #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */\r
+ #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */\r
+ #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */\r
+ #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */\r
+ #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */\r
+ #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */\r
+ #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */\r
+ #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */\r
+ #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */\r
+ #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */\r
+ #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */\r
+ #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */\r
+ #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */\r
+ #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */\r
+ #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */\r
+ #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */\r
+ #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */\r
+ #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */\r
+ #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */\r
+ #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */\r
+ #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */\r
+ #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */\r
+ #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */\r
+ #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */\r
+ #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */\r
+ #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */\r
+ #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */\r
+ #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */\r
+ #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */\r
+ #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU) /**< \brief (XDMAC) XDMAC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_XDMAC_INSTANCE_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70J19_PIO_\r
+#define _SAMV70J19_PIO_\r
+\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV70J19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70J20_PIO_\r
+#define _SAMV70J20_PIO_\r
+\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV70J20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70N19_PIO_\r
+#define _SAMV70N19_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV70N19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70N20_PIO_\r
+#define _SAMV70N20_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV70N20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70Q19_PIO_\r
+#define _SAMV70Q19_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA6 (1u << 28) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PA29 (1u << 31) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC27 (1u << 1) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC26 (1u << 2) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC31 (1u << 3) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PC30 (1u << 4) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC29 (1u << 5) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC12 (1u << 6) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC15 (1u << 7) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC13 (1u << 8) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC1 (1u << 9) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 10) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 11) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 12) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC7 (1u << 13) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC6 (1u << 14) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC5 (1u << 15) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC28 (1u << 16) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC8 (1u << 17) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 18) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 19) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 20) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC14 (1u << 21) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC16 (1u << 22) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 23) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 24) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 25) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 26) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 27) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 28) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 29) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 30) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 31) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD23 (1u << 7) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD29 (1u << 22) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */\r
+#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */\r
+#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */\r
+#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */\r
+#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */\r
+#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */\r
+#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA6_IDX 28\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PA29_IDX 31\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC27_IDX 65\r
+#define PIO_PC26_IDX 66\r
+#define PIO_PC31_IDX 67\r
+#define PIO_PC30_IDX 68\r
+#define PIO_PC29_IDX 69\r
+#define PIO_PC12_IDX 70\r
+#define PIO_PC15_IDX 71\r
+#define PIO_PC13_IDX 72\r
+#define PIO_PC1_IDX 73\r
+#define PIO_PC2_IDX 74\r
+#define PIO_PC3_IDX 75\r
+#define PIO_PC4_IDX 76\r
+#define PIO_PC7_IDX 77\r
+#define PIO_PC6_IDX 78\r
+#define PIO_PC5_IDX 79\r
+#define PIO_PC28_IDX 80\r
+#define PIO_PC8_IDX 81\r
+#define PIO_PC9_IDX 82\r
+#define PIO_PC10_IDX 83\r
+#define PIO_PC11_IDX 84\r
+#define PIO_PC14_IDX 85\r
+#define PIO_PC16_IDX 86\r
+#define PIO_PC17_IDX 87\r
+#define PIO_PC18_IDX 88\r
+#define PIO_PC19_IDX 89\r
+#define PIO_PC20_IDX 90\r
+#define PIO_PC21_IDX 91\r
+#define PIO_PC22_IDX 92\r
+#define PIO_PC23_IDX 93\r
+#define PIO_PC24_IDX 94\r
+#define PIO_PC25_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD23_IDX 103\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD29_IDX 118\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAMV70Q19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70Q20_PIO_\r
+#define _SAMV70Q20_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA6 (1u << 28) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PA29 (1u << 31) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC27 (1u << 1) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC26 (1u << 2) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC31 (1u << 3) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PC30 (1u << 4) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC29 (1u << 5) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC12 (1u << 6) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC15 (1u << 7) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC13 (1u << 8) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC1 (1u << 9) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 10) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 11) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 12) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC7 (1u << 13) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC6 (1u << 14) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC5 (1u << 15) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC28 (1u << 16) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC8 (1u << 17) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 18) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 19) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 20) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC14 (1u << 21) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC16 (1u << 22) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 23) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 24) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 25) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 26) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 27) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 28) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 29) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 30) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 31) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD23 (1u << 7) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD29 (1u << 22) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */\r
+#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */\r
+#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */\r
+#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */\r
+#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */\r
+#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */\r
+#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA6_IDX 28\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PA29_IDX 31\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC27_IDX 65\r
+#define PIO_PC26_IDX 66\r
+#define PIO_PC31_IDX 67\r
+#define PIO_PC30_IDX 68\r
+#define PIO_PC29_IDX 69\r
+#define PIO_PC12_IDX 70\r
+#define PIO_PC15_IDX 71\r
+#define PIO_PC13_IDX 72\r
+#define PIO_PC1_IDX 73\r
+#define PIO_PC2_IDX 74\r
+#define PIO_PC3_IDX 75\r
+#define PIO_PC4_IDX 76\r
+#define PIO_PC7_IDX 77\r
+#define PIO_PC6_IDX 78\r
+#define PIO_PC5_IDX 79\r
+#define PIO_PC28_IDX 80\r
+#define PIO_PC8_IDX 81\r
+#define PIO_PC9_IDX 82\r
+#define PIO_PC10_IDX 83\r
+#define PIO_PC11_IDX 84\r
+#define PIO_PC14_IDX 85\r
+#define PIO_PC16_IDX 86\r
+#define PIO_PC17_IDX 87\r
+#define PIO_PC18_IDX 88\r
+#define PIO_PC19_IDX 89\r
+#define PIO_PC20_IDX 90\r
+#define PIO_PC21_IDX 91\r
+#define PIO_PC22_IDX 92\r
+#define PIO_PC23_IDX 93\r
+#define PIO_PC24_IDX 94\r
+#define PIO_PC25_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD23_IDX 103\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD29_IDX 118\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAMV70Q20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J19_PIO_\r
+#define _SAMV71J19_PIO_\r
+\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71J19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J20_PIO_\r
+#define _SAMV71J20_PIO_\r
+\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71J20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J21_PIO_\r
+#define _SAMV71J21_PIO_\r
+\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71J21_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N19_PIO_\r
+#define _SAMV71N19_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71N19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N20_PIO_\r
+#define _SAMV71N20_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71N20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N21_PIO_\r
+#define _SAMV71N21_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+\r
+#endif /* _SAMV71N21_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q19_PIO_\r
+#define _SAMV71Q19_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA6 (1u << 28) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PA29 (1u << 31) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC27 (1u << 1) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC26 (1u << 2) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC31 (1u << 3) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PC30 (1u << 4) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC29 (1u << 5) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC12 (1u << 6) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC15 (1u << 7) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC13 (1u << 8) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC1 (1u << 9) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 10) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 11) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 12) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC7 (1u << 13) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC6 (1u << 14) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC5 (1u << 15) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC28 (1u << 16) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC8 (1u << 17) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 18) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 19) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 20) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC14 (1u << 21) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC16 (1u << 22) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 23) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 24) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 25) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 26) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 27) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 28) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 29) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 30) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 31) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD23 (1u << 7) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD29 (1u << 22) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */\r
+#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */\r
+#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */\r
+#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */\r
+#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */\r
+#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */\r
+#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA6_IDX 28\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PA29_IDX 31\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC27_IDX 65\r
+#define PIO_PC26_IDX 66\r
+#define PIO_PC31_IDX 67\r
+#define PIO_PC30_IDX 68\r
+#define PIO_PC29_IDX 69\r
+#define PIO_PC12_IDX 70\r
+#define PIO_PC15_IDX 71\r
+#define PIO_PC13_IDX 72\r
+#define PIO_PC1_IDX 73\r
+#define PIO_PC2_IDX 74\r
+#define PIO_PC3_IDX 75\r
+#define PIO_PC4_IDX 76\r
+#define PIO_PC7_IDX 77\r
+#define PIO_PC6_IDX 78\r
+#define PIO_PC5_IDX 79\r
+#define PIO_PC28_IDX 80\r
+#define PIO_PC8_IDX 81\r
+#define PIO_PC9_IDX 82\r
+#define PIO_PC10_IDX 83\r
+#define PIO_PC11_IDX 84\r
+#define PIO_PC14_IDX 85\r
+#define PIO_PC16_IDX 86\r
+#define PIO_PC17_IDX 87\r
+#define PIO_PC18_IDX 88\r
+#define PIO_PC19_IDX 89\r
+#define PIO_PC20_IDX 90\r
+#define PIO_PC21_IDX 91\r
+#define PIO_PC22_IDX 92\r
+#define PIO_PC23_IDX 93\r
+#define PIO_PC24_IDX 94\r
+#define PIO_PC25_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD23_IDX 103\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD29_IDX 118\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAMV71Q19_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q20_PIO_\r
+#define _SAMV71Q20_PIO_\r
+\r
+#define PIO_PA20 (1u << 0) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA19 (1u << 1) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA18 (1u << 2) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA17 (1u << 3) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA21 (1u << 4) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA7 (1u << 5) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 6) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA22 (1u << 7) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA13 (1u << 8) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA16 (1u << 9) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA23 (1u << 10) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA15 (1u << 11) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA14 (1u << 12) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA24 (1u << 13) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 14) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 15) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA11 (1u << 16) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA10 (1u << 17) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA12 (1u << 18) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA27 (1u << 19) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA5 (1u << 20) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA9 (1u << 21) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA4 (1u << 22) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA3 (1u << 23) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA2 (1u << 24) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA1 (1u << 25) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA0 (1u << 26) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA28 (1u << 27) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA6 (1u << 28) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA30 (1u << 29) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 30) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PA29 (1u << 31) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB1 (1u << 0) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB0 (1u << 1) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB6 (1u << 4) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB12 (1u << 5) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB7 (1u << 6) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB4 (1u << 7) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 8) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB8 (1u << 9) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 10) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB13 (1u << 11) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB10 (1u << 12) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 13) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC27 (1u << 1) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC26 (1u << 2) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC31 (1u << 3) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PC30 (1u << 4) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC29 (1u << 5) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC12 (1u << 6) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC15 (1u << 7) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC13 (1u << 8) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC1 (1u << 9) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 10) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 11) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 12) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC7 (1u << 13) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC6 (1u << 14) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC5 (1u << 15) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC28 (1u << 16) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC8 (1u << 17) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 18) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 19) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 20) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC14 (1u << 21) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC16 (1u << 22) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 23) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 24) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 25) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 26) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 27) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 28) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 29) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 30) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 31) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD31 (1u << 1) /**< \brief Pin Controlled by PD31 */\r
+#define PIO_PD30 (1u << 2) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD27 (1u << 3) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD25 (1u << 4) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 5) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD24 (1u << 6) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD23 (1u << 7) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD22 (1u << 8) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD21 (1u << 9) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD20 (1u << 10) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD19 (1u << 11) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD18 (1u << 12) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD28 (1u << 13) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD17 (1u << 14) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD16 (1u << 15) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD14 (1u << 16) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD13 (1u << 17) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD12 (1u << 18) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD11 (1u << 19) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD10 (1u << 20) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD15 (1u << 21) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD29 (1u << 22) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD9 (1u << 23) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD8 (1u << 24) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD7 (1u << 25) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD6 (1u << 26) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD5 (1u << 27) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD4 (1u << 28) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD3 (1u << 29) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD2 (1u << 30) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD1 (1u << 31) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */\r
+#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */\r
+#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */\r
+#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */\r
+#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */\r
+#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */\r
+#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA6_IDX 28\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PA29_IDX 31\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC27_IDX 65\r
+#define PIO_PC26_IDX 66\r
+#define PIO_PC31_IDX 67\r
+#define PIO_PC30_IDX 68\r
+#define PIO_PC29_IDX 69\r
+#define PIO_PC12_IDX 70\r
+#define PIO_PC15_IDX 71\r
+#define PIO_PC13_IDX 72\r
+#define PIO_PC1_IDX 73\r
+#define PIO_PC2_IDX 74\r
+#define PIO_PC3_IDX 75\r
+#define PIO_PC4_IDX 76\r
+#define PIO_PC7_IDX 77\r
+#define PIO_PC6_IDX 78\r
+#define PIO_PC5_IDX 79\r
+#define PIO_PC28_IDX 80\r
+#define PIO_PC8_IDX 81\r
+#define PIO_PC9_IDX 82\r
+#define PIO_PC10_IDX 83\r
+#define PIO_PC11_IDX 84\r
+#define PIO_PC14_IDX 85\r
+#define PIO_PC16_IDX 86\r
+#define PIO_PC17_IDX 87\r
+#define PIO_PC18_IDX 88\r
+#define PIO_PC19_IDX 89\r
+#define PIO_PC20_IDX 90\r
+#define PIO_PC21_IDX 91\r
+#define PIO_PC22_IDX 92\r
+#define PIO_PC23_IDX 93\r
+#define PIO_PC24_IDX 94\r
+#define PIO_PC25_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD23_IDX 103\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD29_IDX 118\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAMV71Q20_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q21_PIO_\r
+#define _SAMV71Q21_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20*/\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21*/\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22*/\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23*/\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24*/\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25*/\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26*/\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28*/\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10*/\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10*/\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11*/\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12*/\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13*/\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14*/\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15*/\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17*/\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18*/\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23*/\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24*/\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25*/\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26*/\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27*/\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28*/\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29*/\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30*/\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31*/\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+/* ========== Pio definition for AFEC0 peripheral ========== */\r
+#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */\r
+#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */\r
+#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */\r
+#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */\r
+#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */\r
+#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */\r
+#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */\r
+#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */\r
+#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */\r
+#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */\r
+/* ========== Pio definition for AFEC1 peripheral ========== */\r
+#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */\r
+#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */\r
+#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */\r
+#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */\r
+#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */\r
+#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */\r
+#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */\r
+#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */\r
+#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */\r
+#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */\r
+#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */\r
+#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */\r
+#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */\r
+#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */\r
+#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */\r
+#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */\r
+#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */\r
+#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */\r
+#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for ISI peripheral ========== */\r
+#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */\r
+#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */\r
+#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */\r
+#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */\r
+#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */\r
+#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */\r
+#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */\r
+#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */\r
+#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */\r
+#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */\r
+#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */\r
+#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */\r
+#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */\r
+#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */\r
+#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */\r
+#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */\r
+#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */\r
+#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */\r
+#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */\r
+#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM0 peripheral ========== */\r
+#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */\r
+#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */\r
+#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */\r
+#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */\r
+#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */\r
+#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */\r
+#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */\r
+#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */\r
+#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */\r
+#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */\r
+#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */\r
+#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */\r
+#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */\r
+/* ========== Pio definition for PWM1 peripheral ========== */\r
+#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */\r
+#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */\r
+#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */\r
+#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */\r
+#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */\r
+#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */\r
+#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */\r
+#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */\r
+#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */\r
+#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */\r
+#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */\r
+#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */\r
+#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */\r
+/* ========== Pio definition for QSPI peripheral ========== */\r
+#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */\r
+#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */\r
+#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */\r
+#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */\r
+#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */\r
+#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */\r
+#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */\r
+#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */\r
+#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */\r
+#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */\r
+#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */\r
+#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */\r
+#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TC3 peripheral ========== */\r
+#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */\r
+#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */\r
+#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */\r
+#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */\r
+#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */\r
+#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */\r
+#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */\r
+#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */\r
+#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for TWI2 peripheral ========== */\r
+#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twi2 signal: TWCK2 */\r
+#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twi2 signal: TWD2 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */\r
+#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */\r
+#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */\r
+#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */\r
+#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */\r
+#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */\r
+#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */\r
+#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */\r
+#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */\r
+#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA20_IDX 0\r
+#define PIO_PA19_IDX 1\r
+#define PIO_PA18_IDX 2\r
+#define PIO_PA17_IDX 3\r
+#define PIO_PA21_IDX 4\r
+#define PIO_PA7_IDX 5\r
+#define PIO_PA8_IDX 6\r
+#define PIO_PA22_IDX 7\r
+#define PIO_PA13_IDX 8\r
+#define PIO_PA16_IDX 9\r
+#define PIO_PA23_IDX 10\r
+#define PIO_PA15_IDX 11\r
+#define PIO_PA14_IDX 12\r
+#define PIO_PA24_IDX 13\r
+#define PIO_PA25_IDX 14\r
+#define PIO_PA26_IDX 15\r
+#define PIO_PA11_IDX 16\r
+#define PIO_PA10_IDX 17\r
+#define PIO_PA12_IDX 18\r
+#define PIO_PA27_IDX 19\r
+#define PIO_PA5_IDX 20\r
+#define PIO_PA9_IDX 21\r
+#define PIO_PA4_IDX 22\r
+#define PIO_PA3_IDX 23\r
+#define PIO_PA2_IDX 24\r
+#define PIO_PA1_IDX 25\r
+#define PIO_PA0_IDX 26\r
+#define PIO_PA28_IDX 27\r
+#define PIO_PA6_IDX 28\r
+#define PIO_PA30_IDX 29\r
+#define PIO_PA31_IDX 30\r
+#define PIO_PA29_IDX 31\r
+#define PIO_PB1_IDX 32\r
+#define PIO_PB0_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB6_IDX 36\r
+#define PIO_PB12_IDX 37\r
+#define PIO_PB7_IDX 38\r
+#define PIO_PB4_IDX 39\r
+#define PIO_PB5_IDX 40\r
+#define PIO_PB8_IDX 41\r
+#define PIO_PB9_IDX 42\r
+#define PIO_PB13_IDX 43\r
+#define PIO_PB10_IDX 44\r
+#define PIO_PB11_IDX 45\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC27_IDX 65\r
+#define PIO_PC26_IDX 66\r
+#define PIO_PC31_IDX 67\r
+#define PIO_PC30_IDX 68\r
+#define PIO_PC29_IDX 69\r
+#define PIO_PC12_IDX 70\r
+#define PIO_PC15_IDX 71\r
+#define PIO_PC13_IDX 72\r
+#define PIO_PC1_IDX 73\r
+#define PIO_PC2_IDX 74\r
+#define PIO_PC3_IDX 75\r
+#define PIO_PC4_IDX 76\r
+#define PIO_PC7_IDX 77\r
+#define PIO_PC6_IDX 78\r
+#define PIO_PC5_IDX 79\r
+#define PIO_PC28_IDX 80\r
+#define PIO_PC8_IDX 81\r
+#define PIO_PC9_IDX 82\r
+#define PIO_PC10_IDX 83\r
+#define PIO_PC11_IDX 84\r
+#define PIO_PC14_IDX 85\r
+#define PIO_PC16_IDX 86\r
+#define PIO_PC17_IDX 87\r
+#define PIO_PC18_IDX 88\r
+#define PIO_PC19_IDX 89\r
+#define PIO_PC20_IDX 90\r
+#define PIO_PC21_IDX 91\r
+#define PIO_PC22_IDX 92\r
+#define PIO_PC23_IDX 93\r
+#define PIO_PC24_IDX 94\r
+#define PIO_PC25_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD31_IDX 97\r
+#define PIO_PD30_IDX 98\r
+#define PIO_PD27_IDX 99\r
+#define PIO_PD25_IDX 100\r
+#define PIO_PD26_IDX 101\r
+#define PIO_PD24_IDX 102\r
+#define PIO_PD23_IDX 103\r
+#define PIO_PD22_IDX 104\r
+#define PIO_PD21_IDX 105\r
+#define PIO_PD20_IDX 106\r
+#define PIO_PD19_IDX 107\r
+#define PIO_PD18_IDX 108\r
+#define PIO_PD28_IDX 109\r
+#define PIO_PD17_IDX 110\r
+#define PIO_PD16_IDX 111\r
+#define PIO_PD14_IDX 112\r
+#define PIO_PD13_IDX 113\r
+#define PIO_PD12_IDX 114\r
+#define PIO_PD11_IDX 115\r
+#define PIO_PD10_IDX 116\r
+#define PIO_PD15_IDX 117\r
+#define PIO_PD29_IDX 118\r
+#define PIO_PD9_IDX 119\r
+#define PIO_PD8_IDX 120\r
+#define PIO_PD7_IDX 121\r
+#define PIO_PD6_IDX 122\r
+#define PIO_PD5_IDX 123\r
+#define PIO_PD4_IDX 124\r
+#define PIO_PD3_IDX 125\r
+#define PIO_PD2_IDX 126\r
+#define PIO_PD1_IDX 127\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+\r
+#endif /* _SAMV71Q21_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_\r
+#define _SAM_\r
+\r
+#if defined __SAME70J19__\r
+ #include "same70j19.h"\r
+#elif defined __SAME70J20__\r
+ #include "same70j20.h"\r
+#elif defined __SAME70J21__\r
+ #include "same70j21.h"\r
+#elif defined __SAME70N19__\r
+ #include "same70n19.h"\r
+#elif defined __SAME70N20__\r
+ #include "same70n20.h"\r
+#elif defined __SAME70N21__\r
+ #include "same70n21.h"\r
+#elif defined __SAME70Q19__\r
+ #include "same70q19.h"\r
+#elif defined __SAME70Q20__\r
+ #include "same70q20.h"\r
+#elif defined __SAME70Q21__\r
+ #include "same70q21.h"\r
+#elif defined __SAMS70J19__\r
+ #include "sams70j19.h"\r
+#elif defined __SAMS70J20__\r
+ #include "sams70j20.h"\r
+#elif defined __SAMS70J21__\r
+ #include "sams70j21.h"\r
+#elif defined __SAMS70N19__\r
+ #include "sams70n19.h"\r
+#elif defined __SAMS70N20__\r
+ #include "sams70n20.h"\r
+#elif defined __SAMS70N21__\r
+ #include "sams70n21.h"\r
+#elif defined __SAMS70Q19__\r
+ #include "sams70q19.h"\r
+#elif defined __SAMS70Q20__\r
+ #include "sams70q20.h"\r
+#elif defined __SAMS70Q21__\r
+ #include "sams70q21.h"\r
+#elif defined __SAMV70J19__\r
+ #include "samv70j19.h"\r
+#elif defined __SAMV70J20__\r
+ #include "samv70j20.h"\r
+#elif defined __SAMV70N19__\r
+ #include "samv70n19.h"\r
+#elif defined __SAMV70N20__\r
+ #include "samv70n20.h"\r
+#elif defined __SAMV70Q19__\r
+ #include "samv70q19.h"\r
+#elif defined __SAMV70Q20__\r
+ #include "samv70q20.h"\r
+#elif defined __SAMV71J19__\r
+ #include "samv71j19.h"\r
+#elif defined __SAMV71J20__\r
+ #include "samv71j20.h"\r
+#elif defined __SAMV71J21__\r
+ #include "samv71j21.h"\r
+#elif defined __SAMV71N19__\r
+ #include "samv71n19.h"\r
+#elif defined __SAMV71N20__\r
+ #include "samv71n20.h"\r
+#elif defined __SAMV71N21__\r
+ #include "samv71n21.h"\r
+#elif defined __SAMV71Q19__\r
+ #include "samv71q19.h"\r
+#elif defined __SAMV71Q20__\r
+ #include "samv71q20.h"\r
+#elif defined __SAMV71Q21__\r
+ #include "samv71q21.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAM_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70J19_\r
+#define _SAMV70J19_\r
+\r
+/** \addtogroup SAMV70J19_definitions SAMV70J19 definitions\r
+ This file defines all structures and symbols for SAMV70J19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70J19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70J19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70J19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70J19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70J19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70J19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70J19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70J19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70J19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70J19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70J19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70J19 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70J19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70J19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70J19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70J19 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70J19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70J19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70J19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70J19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70J19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70J19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70J19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70J19 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70J19 Analog Front End 0 (AFEC0) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70J19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70J19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70J19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70J19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70J19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70J19 Analog Front End 1 (AFEC1) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70J19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70J19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70J19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70J19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70J19 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70J19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70J19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70J19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70J19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70J19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70J19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70J19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70J19 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70J19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pvReserved30;\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pvReserved41;\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70J19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70J19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70J19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70J19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70j19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x200000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (32u)\r
+#define IRAM_SIZE (0x40000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA13D0A00UL)\r
+#define CHIP_EXID (0x00000000UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70J19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70J19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70J20_\r
+#define _SAMV70J20_\r
+\r
+/** \addtogroup SAMV70J20_definitions SAMV70J20 definitions\r
+ This file defines all structures and symbols for SAMV70J20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70J20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70J20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70J20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70J20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70J20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70J20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70J20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70J20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70J20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70J20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70J20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70J20 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70J20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70J20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70J20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70J20 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70J20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70J20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70J20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70J20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70J20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70J20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70J20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70J20 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70J20 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV70J20 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70J20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70J20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70J20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70J20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70J20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70J20 Analog Front End 1 (AFEC1) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70J20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70J20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70J20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70J20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70J20 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70J20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70J20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70J20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70J20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70J20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70J20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70J20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70J20 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70J20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pvReserved41;\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70J20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70J20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70J20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70J20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70J20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70j20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (64u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1320C00UL)\r
+#define CHIP_EXID (0x00000000UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70J20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70J20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70N19_\r
+#define _SAMV70N19_\r
+\r
+/** \addtogroup SAMV70N19_definitions SAMV70N19 definitions\r
+ This file defines all structures and symbols for SAMV70N19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70N19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70N19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70N19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70N19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70N19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70N19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70N19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70N19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70N19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70N19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70N19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70N19 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70N19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70N19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70N19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70N19 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70N19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70N19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70N19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70N19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70N19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70N19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70N19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70N19 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70N19 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV70N19 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70N19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70N19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70N19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70N19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70N19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70N19 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV70N19 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70N19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70N19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70N19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70N19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70N19 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70N19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70N19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70N19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70N19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70N19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70N19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70N19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70N19 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70N19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70N19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70N19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70N19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70N19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70n19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (32u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA13D0A00UL)\r
+#define CHIP_EXID (0x00000001UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70N19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70N19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70N20_\r
+#define _SAMV70N20_\r
+\r
+/** \addtogroup SAMV70N20_definitions SAMV70N20 definitions\r
+ This file defines all structures and symbols for SAMV70N20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70N20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70N20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70N20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70N20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70N20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70N20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70N20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70N20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70N20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70N20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70N20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70N20 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70N20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70N20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70N20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70N20 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70N20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70N20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70N20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70N20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70N20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70N20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70N20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70N20 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70N20 Analog Front End 0 (AFEC0) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70N20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70N20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70N20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70N20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70N20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70N20 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV70N20 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70N20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70N20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70N20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70N20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70N20 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70N20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70N20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70N20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70N20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70N20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70N20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70N20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70N20 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70N20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pvReserved30;\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70N20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70N20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70N20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70N20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70N20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70n20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x200000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (64u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1320C00UL)\r
+#define CHIP_EXID (0x00000001UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70N20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70N20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70Q19_\r
+#define _SAMV70Q19_\r
+\r
+/** \addtogroup SAMV70Q19_definitions SAMV70Q19 definitions\r
+ This file defines all structures and symbols for SAMV70Q19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70Q19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70Q19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70Q19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70Q19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70Q19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70Q19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70Q19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70Q19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70Q19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70Q19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70Q19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70Q19 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAMV70Q19 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70Q19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70Q19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70Q19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70Q19 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAMV70Q19 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70Q19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70Q19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70Q19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70Q19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70Q19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70Q19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70Q19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70Q19 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAMV70Q19 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAMV70Q19 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAMV70Q19 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70Q19 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV70Q19 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70Q19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70Q19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70Q19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70Q19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70Q19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70Q19 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV70Q19 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70Q19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70Q19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70Q19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70Q19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70Q19 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAMV70Q19 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAMV70Q19 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAMV70Q19 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70Q19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70Q19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70Q19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70Q19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70Q19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70Q19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70Q19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70Q19 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAMV70Q19 SDRAM Controller (SDRAMC) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70Q19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70Q19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70Q19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70Q19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70Q19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70q19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (32u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA13D0A00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70Q19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70Q19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV70Q20_\r
+#define _SAMV70Q20_\r
+\r
+/** \addtogroup SAMV70Q20_definitions SAMV70Q20 definitions\r
+ This file defines all structures and symbols for SAMV70Q20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV70Q20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV70Q20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV70Q20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV70Q20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV70Q20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV70Q20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV70Q20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV70Q20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV70Q20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV70Q20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV70Q20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV70Q20 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAMV70Q20 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAMV70Q20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV70Q20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV70Q20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV70Q20 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAMV70Q20 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV70Q20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV70Q20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV70Q20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV70Q20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV70Q20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV70Q20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV70Q20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV70Q20 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAMV70Q20 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAMV70Q20 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAMV70Q20 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV70Q20 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV70Q20 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV70Q20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV70Q20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV70Q20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV70Q20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV70Q20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV70Q20 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV70Q20 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV70Q20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV70Q20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV70Q20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV70Q20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV70Q20 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAMV70Q20 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAMV70Q20 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAMV70Q20 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAMV70Q20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV70Q20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV70Q20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV70Q20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV70Q20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV70Q20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV70Q20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV70Q20 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAMV70Q20 SDRAM Controller (SDRAMC) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV70Q20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV70Q20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV70Q20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV70Q20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV70Q20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV70Q20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv70q20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (64u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1320C00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV70Q20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV70Q20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J19_\r
+#define _SAMV71J19_\r
+\r
+/** \addtogroup SAMV71J19_definitions SAMV71J19 definitions\r
+ This file defines all structures and symbols for SAMV71J19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71J19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71J19 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71J19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pvReserved41;\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71j19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+\r
+#define IRAM_SIZE (0x40000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA12D0A00UL)\r
+#define CHIP_EXID (0x00000000UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71J19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71J19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J20_\r
+#define _SAMV71J20_\r
+\r
+/** \addtogroup SAMV71J20_definitions SAMV71J20 definitions\r
+ This file defines all structures and symbols for SAMV71J20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71J20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71J20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71J20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71J20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71J20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71J20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71J20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71J20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71J20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71J20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71J20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71J20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71J20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71J20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71J20 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71J20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71J20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71J20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pvReserved41;\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71J20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71J20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71J20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71j20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (64u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220C00UL)\r
+#define CHIP_EXID (0x00000000UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71J20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71J20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71J21_\r
+#define _SAMV71J21_\r
+\r
+/** \addtogroup SAMV71J21_definitions SAMV71J21 definitions\r
+ This file defines all structures and symbols for SAMV71J21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71J21 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71J21 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71J21 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71J21 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71J21 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71J21 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71J21 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71J21 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71J21 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71J21 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71J21 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71J21 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71J21 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71J21 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71J21 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71J21 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71J21 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71J21 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71J21 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71J21 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71J21 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71J21 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71J21 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71J21 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71J21 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71J21 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71J21 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71J21 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71J21 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71J21 Analog Front End 1 (AFEC1) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71J21 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71J21 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71J21 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71J21 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71J21 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71J21 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71J21 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71J21 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71J21 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71J21 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71J21 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71J21 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71J21 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71J21 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pvReserved41;\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71J21 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71J21 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71J21 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71J21 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71J21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71j21.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220E00UL)\r
+#define CHIP_EXID (0x00000000UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71J21 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71J21_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N19_\r
+#define _SAMV71N19_\r
+\r
+/** \addtogroup SAMV71N19_definitions SAMV71N19 definitions\r
+ This file defines all structures and symbols for SAMV71N19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71N19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71N19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71N19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71N19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71N19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71N19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71N19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71N19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71N19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71N19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71N19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71N19 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71N19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71N19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71N19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71N19 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71N19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71N19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71N19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71N19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71N19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71N19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71N19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71N19 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71N19 Analog Front End 0 (AFEC0) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71N19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71N19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71N19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71N19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71N19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71N19 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71N19 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71N19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71N19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71N19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71N19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71N19 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71N19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71N19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71N19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71N19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71N19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71N19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71N19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71N19 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71N19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pvReserved30;\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71N19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71N19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71N19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71N19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71n19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (1024u)\r
+#define IFLASH_NB_OF_LOCK_BITS (32u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA12D0A00UL)\r
+#define CHIP_EXID (0x00000001UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71N19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71N19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N20_\r
+#define _SAMV71N20_\r
+\r
+/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions\r
+ This file defines all structures and symbols for SAMV71N20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71N20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71N20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71N20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71N20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71N20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71N20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71N20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71N20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71N20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71N20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71N20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71N20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71N20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71N20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71N20 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71N20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71N20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71N20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pvReserved30;\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71N20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71N20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71N20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71n20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+\r
+#define IRAM_SIZE (0x40000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220C00UL)\r
+#define CHIP_EXID (0x00000001UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71N20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71N20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71N21_\r
+#define _SAMV71N21_\r
+\r
+/** \addtogroup SAMV71N21_definitions SAMV71N21 definitions\r
+ This file defines all structures and symbols for SAMV71N21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71N21 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71N21 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pvReserved12;\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pvReserved26;\r
+ void* pvReserved27;\r
+ void* pvReserved28;\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pvReserved30;\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pvReserved47;\r
+ void* pvReserved48;\r
+ void* pvReserved49;\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pvReserved62;\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71n21.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x80000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (4096u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x40000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220E00UL)\r
+#define CHIP_EXID (0x00000001UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71N21 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71N21_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q19_\r
+#define _SAMV71Q19_\r
+\r
+/** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions\r
+ This file defines all structures and symbols for SAMV71Q19:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71Q19 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71Q19 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71q19.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA12D0A00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71Q19_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q20_\r
+#define _SAMV71Q20_\r
+\r
+/** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions\r
+ This file defines all structures and symbols for SAMV71Q20:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71Q20 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71Q20 Watchdog Timer 1 (WDT1) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pvReserved35;\r
+ void* pvReserved36;\r
+ void* pvReserved37;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71q20.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (64u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220C00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71Q20_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMV71Q21_\r
+#define _SAMV71Q21_\r
+\r
+/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions\r
+ This file defines all structures and symbols for SAMV71Q21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAMV71Q21 specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */\r
+ WDT0_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer 0 (WDT0) */\r
+ PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWI1) */\r
+ SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */\r
+ GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */\r
+ TWI2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWI2) */\r
+ SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */\r
+ WDT1_IRQn = 63, /**< 63 SAMV71Q21 Watchdog Timer 1 (WDT1) */\r
+ CCW_IRQn = 64, /**< 64 SAMV71Q21 ARM Cache ECC Warning */\r
+ CCF_IRQn = 65, /**< 65 SAMV71Q21 ARM Cache ECC Fault */\r
+ GMACQ1_IRQn = 66, /**< 66 SAMV71Q21 GMAC Queue 1 Handler */\r
+ GMACQ2_IRQn = 67, /**< 67 SAMV71Q21 GMAC Queue 2 Handler */\r
+\r
+ PERIPH_COUNT_IRQn = 68 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pfnCAN0_Handler;\r
+ void* pvReserved36;\r
+ void* pfnCAN1_Handler;\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pfnMLB_Handler;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pfnFPU_Handler;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */\r
+ void* pfnCCW_Handler; /* 64 ARM Cache ECC Warning */\r
+ void* pfnCCF_Handler; /* 65 ARM Cache ECC Fault */\r
+ void* pfnGMACQ1_Handler; /* 66 GMAC Queue 1 Handler */\r
+ void* pfnGMACQ2_Handler; /* 67 GMAC Queue 2 Handler */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void CCF_Handler ( void );\r
+void CCW_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void FPU_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void GMACQ1_Handler ( void );\r
+void GMACQ2_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void MLB_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void TWI2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT0_Handler ( void );\r
+void WDT1_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */\r
+#define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm7.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_afec.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isi.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm0.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usbhs.h"\r
+#include "instance/instance_afec0.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_icm.h"\r
+#include "instance/instance_isi.h"\r
+#include "instance/instance_gmac.h"\r
+#include "instance/instance_tc3.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_pwm1.h"\r
+#include "instance/instance_twi2.h"\r
+#include "instance/instance_afec1.h"\r
+#include "instance/instance_aes.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_xdmac.h"\r
+#include "instance/instance_qspi.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt0.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+#include "instance/instance_wdt1.h"\r
+#include "instance/instance_uart2.h"\r
+#include "instance/instance_uart3.h"\r
+#include "instance/instance_uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */\r
+#define ID_CCW (64) /**< \brief ARM cache ECC Warning(CCW) */\r
+#define ID_CCF (65) /**< \brief ARM cache ECC Fault (CCF) */\r
+\r
+#define ID_PERIPH_COUNT (66) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define TWI1 ((Twihs *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWI2 ((Twihs *)0x40060000U) /**< \brief (TWI2 ) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_samv71q21.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x200000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (4096u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define USBHS_RAM_ADDR (0xA0100000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1220E00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMV71Q21_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef SYSTEM_SAM_H_INCLUDED\r
+#define SYSTEM_SAM_H_INCLUDED\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/**\r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t dw_clk);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* SYSTEM_SAM_H_INCLUDED */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+/**\r
+ * \file\r
+ *\r
+ * Definitions and function prototype for SDRAMC.\r
+ */\r
+\r
+// ----------------------------------------------------------------------------------------------------------\r
+// SDRAM\r
+// ----------------------------------------------------------------------------------------------------------\r
+/** SDRAMC Configuration */\r
+#define EBI_SDRAMC_ADDR (0x70000000u)\r
+\r
+/** SDRAM bus width */\r
+#define BOARD_SDRAM_BUSWIDTH 16\r
+\r
+\r
+typedef struct _SSdramc_config\r
+{\r
+ uint32_t dwColumnBits ; // Number of Column Bits\r
+ uint32_t dwRowBits ; // Number of Row Bits\r
+ uint32_t dwBanks ; // Number of Banks\r
+ uint32_t dwCAS ; // CAS Latency\r
+ uint32_t dwDataBusWidth ; // Data Bus Width\r
+ uint32_t dwWriteRecoveryDelay ; // Write Recovery Delay\r
+ uint32_t dwRowCycleDelay_RowRefreshCycle ; // Row Cycle Delay and Row Refresh Cycle\r
+ uint32_t dwRowPrechargeDelay ; // Row Precharge Delay\r
+ uint32_t dwRowColumnDelay ; // Row to Column Delay\r
+ uint32_t dwActivePrechargeDelay ; // Active to Precharge Delay\r
+ uint32_t dwExitSelfRefreshActiveDelay ; // Exit Self Refresh to Active Delay\r
+ uint32_t dwBK1 ; // bk1 addr\r
+\r
+} SSdramc_config ;\r
+\r
+typedef struct _SSdramc_Memory\r
+{\r
+ SSdramc_config cfg ;\r
+\r
+} SSdramc_Memory ;\r
+\r
+extern void SDRAMC_Configure( SSdramc_Memory* pMemory, uint32_t dwClockFrequency ) ;\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+/**\r
+* \file\r
+*\r
+* Definitions and function prototype for smc module\r
+*/\r
+\r
+#ifndef _SMC_\r
+#define _SMC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+typedef union _SmcStatus {\r
+ uint8_t BStatus;\r
+ struct _SmcStatusBits {\r
+ uint8_t smcSts:1, /**< NAND Flash Controller Status */\r
+ xfrDone:1, /**< NFC Data Transfer Terminated */\r
+ cmdDone:1, /**< Command Done */\r
+ rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/\r
+ hammingReady:1; /**< Hamming ecc ready */\r
+ } bStatus;\r
+} SmcStatus;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*\r
+ * NFC definitions\r
+ */\r
+\r
+/** Base address of NFC SRAM */\r
+#define NFC_SRAM_BASE_ADDRESS 0x200000\r
+/** Base address for NFC Address Command */\r
+#define NFC_CMD_BASE_ADDR 0x70000000\r
+\r
+\r
+/* -------- NFCADDR_CMD : NFC Address Command -------- */\r
+#define NFCADDR_CMD_CMD1 (0xFFu << 2) /* Command Register Value for Cycle 1 */\r
+#define NFCADDR_CMD_CMD2 (0xFFu << 10) /* Command Register Value for Cycle 2 */\r
+#define NFCADDR_CMD_VCMD2 (0x1u << 18) /* Valid Cycle 2 Command */\r
+#define NFCADDR_CMD_ACYCLE (0x7u << 19) /* Number of Address required for the current command */\r
+#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) /* No address cycle */\r
+#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) /* One address cycle */\r
+#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) /* Two address cycles */\r
+#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) /* Three address cycles */\r
+#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) /* Four address cycles */\r
+#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) /* Five address cycles */\r
+#define NFCADDR_CMD_CSID (0x7u << 22) /* Chip Select Identifier */\r
+#define NFCADDR_CMD_CSID_0 (0x0u << 22) /* CS0 */\r
+#define NFCADDR_CMD_CSID_1 (0x1u << 22) /* CS1 */\r
+#define NFCADDR_CMD_CSID_2 (0x2u << 22) /* CS2 */\r
+#define NFCADDR_CMD_CSID_3 (0x3u << 22) /* CS3 */\r
+#define NFCADDR_CMD_CSID_4 (0x4u << 22) /* CS4 */\r
+#define NFCADDR_CMD_CSID_5 (0x5u << 22) /* CS5 */\r
+#define NFCADDR_CMD_CSID_6 (0x6u << 22) /* CS6 */\r
+#define NFCADDR_CMD_CSID_7 (0x7u << 22) /* CS7 */\r
+#define NFCADDR_CMD_DATAEN (0x1u << 25) /* NFC Data Enable */\r
+#define NFCADDR_CMD_DATADIS (0x0u << 25) /* NFC Data disable */\r
+#define NFCADDR_CMD_NFCRD (0x0u << 26) /* NFC Read Enable */\r
+#define NFCADDR_CMD_NFCWR (0x1u << 26) /* NFC Write Enable */\r
+#define NFCADDR_CMD_NFCCMD (0x1u << 27) /* NFC Command Enable */\r
+\r
+/*\r
+ * ECC definitions (Hsiao Code Errors)\r
+ */\r
+\r
+/** A single bit was incorrect but has been recovered. */\r
+#define Hsiao_ERROR_SINGLEBIT 1\r
+\r
+/** The original code has been corrupted. */\r
+#define Hsiao_ERROR_ECC 2\r
+\r
+/** Multiple bits are incorrect in the data and they cannot be corrected. */\r
+#define Hsiao_ERROR_MULTIPLEBITS 3\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*\r
+ * NFC functions\r
+ */\r
+\r
+extern void SMC_NFC_Configure(uint32_t mode);\r
+extern void SMC_NFC_Reset(void);\r
+extern void SMC_NFC_EnableNfc(void);\r
+extern void SMC_NFC_EnableSpareRead(void);\r
+extern void SMC_NFC_DisableSpareRead(void);\r
+extern void SMC_NFC_EnableSpareWrite(void);\r
+extern void SMC_NFC_DisableSpareWrite(void);\r
+extern uint8_t SMC_NFC_isSpareRead(void);\r
+extern uint8_t SMC_NFC_isSpareWrite(void);\r
+extern uint8_t SMC_NFC_isTransferComplete(void);\r
+extern uint8_t SMC_NFC_isReadyBusy(void);\r
+extern uint8_t SMC_NFC_isNfcBusy(void);\r
+extern uint32_t SMC_NFC_GetStatus(void);\r
+\r
+extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, uint32_t cycle0);\r
+extern void SMC_NFC_Wait_CommandDone(void);\r
+extern void SMC_NFC_Wait_XfrDone(void);\r
+extern void SMC_NFC_Wait_RBbusy(void);\r
+extern void SMC_NFC_Wait_HammingReady(void);\r
+\r
+extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize);\r
+extern uint32_t SMC_ECC_GetCorrectoinType(void);\r
+extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber);\r
+\r
+extern void SMC_ECC_GetValue(uint32_t *ecc);\r
+extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, uint8_t busWidth);\r
+extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth);\r
+#endif /* #ifndef _SMC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Serial Peripheral Interface (SPI) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _SPI_\r
+#define _SPI_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ *\r
+ * Here are several macros which should be used when configuring a SPI\r
+ * peripheral.\r
+ *\r
+ * \section spi_configuration_macros SPI Configuration Macros\r
+ * - \ref SPI_PCS\r
+ * - \ref SPI_SCBR\r
+ * - \ref SPI_DLYBS\r
+ * - \ref SPI_DLYBCT\r
+ */\r
+\r
+/** Calculate the PCS field value given the chip select NPCS value */\r
+#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF))\r
+\r
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */\r
+#define SPI_SCBR(baudrate, masterClock) SPI_CSR_SCBR((uint32_t)(masterClock / baudrate))\r
+\r
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */\r
+#define SPI_DLYBS(delay, masterClock) SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1)\r
+\r
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */\r
+#define SPI_DLYBCT(delay, masterClock) SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1)\r
+\r
+/*------------------------------------------------------------------------------ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void SPI_Enable( Spi* spi ) ;\r
+extern void SPI_Disable( Spi* spi ) ;\r
+\r
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ;\r
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ;\r
+\r
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ;\r
+extern void SPI_SetMode( Spi* spi, uint32_t dwConfiguration );\r
+\r
+extern void SPI_ChipSelect( Spi* spi, uint8_t cS);\r
+extern void SPI_ReleaseCS( Spi* spi );\r
+\r
+extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ;\r
+extern void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast );\r
+\r
+extern uint32_t SPI_Read( Spi* spi ) ;\r
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ;\r
+extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData );\r
+\r
+extern uint32_t SPI_GetStatus( Spi* spi ) ;\r
+extern uint32_t SPI_IsFinished( Spi* pSpi ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _SPI_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of SPI driver, transfer data through DMA.\r
+ *\r
+ */\r
+\r
+#ifndef _SPI_DMA_\r
+#define _SPI_DMA_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** An unspecified error has occured.*/\r
+#define SPID_ERROR 1\r
+\r
+/** SPI driver is currently in use.*/\r
+#define SPID_ERROR_LOCK 2\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/\r
+#define SPID_CSR_SCBR(mck, spck) SPI_CSR_SCBR((mck) / (spck))\r
+\r
+/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/\r
+#define SPID_CSR_DLYBS(mck, delay) SPI_CSR_DLYBS((((delay) * ((mck) / 1000000)) / 1000) + 1)\r
+\r
+/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/\r
+#define SPID_CSR_DLYBCT(mck, delay) SPI_CSR_DLYBCT((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** SPI transfer complete callback. */\r
+typedef void (*SpidCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief Spi Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the SPI_SendCommand function to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct _SpidCmd\r
+{\r
+ /** Pointer to the Tx data. */\r
+ uint8_t *pTxBuff;\r
+ /** Tx size in bytes. */\r
+ uint8_t TxSize;\r
+ /** Pointer to the Rx data. */\r
+ uint8_t *pRxBuff;\r
+ /** Rx size in bytes. */\r
+ uint16_t RxSize;\r
+ /** SPI chip select. */\r
+ uint8_t spiCs;\r
+ /** Callback function invoked at the end of transfer. */\r
+ SpidCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+} SpidCmd ;\r
+\r
+/** Constant structure associated with SPI port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct _Spid\r
+{\r
+ /** Pointer to SPI Hardware registers */\r
+ Spi* pSpiHw ;\r
+ /** Current SpiCommand being processed */\r
+ SpidCmd *pCurrentCommand ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad;\r
+ /** SPI Id as defined in the product datasheet */\r
+ uint8_t spiId ;\r
+ /** Mutual exclusion semaphore. */\r
+ volatile int8_t semaphore ;\r
+} Spid ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t SPID_Configure( Spid* pSpid,\r
+ Spi* pSpiHw,\r
+ uint8_t spiId,\r
+ uint8_t SpiMode,\r
+ sXdmad* pXdmad ) ;\r
+\r
+extern void SPID_ConfigureCS( Spid* pSpid, uint32_t dwCS, uint32_t dwCsr ) ;\r
+\r
+extern uint32_t SPID_SendCommand( Spid* pSpid, SpidCmd* pCommand ) ;\r
+\r
+extern void SPID_Handler( Spid* pSpid ) ;\r
+\r
+extern void SPID_DmaHandler( Spid *pSpid );\r
+\r
+extern uint32_t SPID_IsBusy( const Spid* pSpid ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _SPI_DMA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Synchronous Serial (SSC) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _SSC_\r
+#define _SSC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock);\r
+extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr);\r
+extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr);\r
+extern void SSC_EnableTransmitter(Ssc *ssc);\r
+extern void SSC_DisableTransmitter(Ssc *ssc);\r
+extern void SSC_EnableReceiver(Ssc *ssc);\r
+extern void SSC_DisableReceiver(Ssc *ssc );\r
+extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources);\r
+extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources);\r
+extern void SSC_Write(Ssc *ssc, uint32_t frame);\r
+extern uint32_t SSC_Read(Ssc *ssc );\r
+extern uint8_t SSC_IsRxReady(Ssc *ssc);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _SSC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _SUPC_H_\r
+#define _SUPC_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <stdint.h>\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+\r
+extern void SUPC_SelectExtCrystal32K(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PMC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuring and using Timer Counter (TC) peripherals.\r
+ *\r
+ * \section Usage\r
+ * -# Optionally, use TC_FindMckDivisor() to let the program find the best\r
+ * TCCLKS field value automatically.\r
+ * -# Configure a Timer Counter in the desired mode using TC_Configure().\r
+ * -# Start or stop the timer clock using TC_Start() and TC_Stop().\r
+ */\r
+\r
+#ifndef _TC_\r
+#define _TC_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ;\r
+\r
+extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ;\r
+\r
+extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ;\r
+\r
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _TC_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ \r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Methods and definitions for Global time tick and wait functions.\r
+ *\r
+ * Defines a common and simpliest use of Time Tick, to increase tickCount\r
+ * every 1ms, the application can get this value through GetTickCount().\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Configure the System Tick with TimeTick_Configure() when MCK changed\r
+ * \note\r
+ * Must be done before any invoke of GetTickCount(), Wait() or Sleep().\r
+ * -# Uses GetTickCount to get current tick value.\r
+ * -# Uses Wait to wait several ms.\r
+ * -# Uses Sleep to enter wait for interrupt mode to wait several ms.\r
+ *\r
+ */\r
+\r
+#ifndef _TIMETICK_\r
+#define _TIMETICK_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;\r
+\r
+extern void TimeTick_Increment( uint32_t dwInc ) ;\r
+\r
+extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick);\r
+\r
+extern uint32_t GetTickCount( void ) ;\r
+\r
+extern void Wait( volatile uint32_t dwMs ) ;\r
+\r
+extern void Sleep( volatile uint32_t dwMs ) ;\r
+\r
+#endif /* _TIMETICK_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Standard output methods for reporting debug information, warnings and\r
+ * errors, which can be easily be turned on/off.\r
+ *\r
+ * \par Usage\r
+ * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually\r
+ * disable ALL traces; otherwise use DBGU_Configure().\r
+ * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR()\r
+ * TRACE_FATAL() macros to output traces throughout the program.\r
+ * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2\r
+ * and Fatal 1. Disable a group of traces by changing the value of\r
+ * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL\r
+ * are not generated. To generate no trace, use the reserved value 0.\r
+ * -# Trace disabling can be static or dynamic. If dynamic disabling is selected\r
+ * the trace level can be modified in runtime. If static disabling is selected\r
+ * the disabled traces are not compiled.\r
+ *\r
+ * \par traceLevels Trace level description\r
+ * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program,\r
+ * and which do not produce meaningful information otherwise.\r
+ * -# TRACE_INFO (4): Informational trace about the program execution. Should\r
+ * enable the user to see the execution flow.\r
+ * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case\r
+ * it can be discarded safely; it may even be expected.\r
+ * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution,\r
+ * but which indicates there is a problem with the code.\r
+ * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going\r
+ * any further.\r
+ */\r
+\r
+#ifndef _TRACE_\r
+#define _TRACE_\r
+\r
+/*\r
+ * Headers\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+#include <stdio.h>\r
+\r
+/*\r
+ * Global Definitions\r
+ */\r
+\r
+/** Softpack Version */\r
+#define SOFTPACK_VERSION "0.1"\r
+\r
+#define TRACE_LEVEL_DEBUG 5\r
+#define TRACE_LEVEL_INFO 4\r
+#define TRACE_LEVEL_WARNING 3\r
+#define TRACE_LEVEL_ERROR 2\r
+#define TRACE_LEVEL_FATAL 1\r
+#define TRACE_LEVEL_NO_TRACE 0\r
+\r
+/* By default, all traces are output except the debug one. */\r
+#if !defined(TRACE_LEVEL)\r
+#define TRACE_LEVEL TRACE_LEVEL_INFO\r
+#endif\r
+\r
+/* By default, trace level is static (not dynamic) */\r
+#if !defined(DYN_TRACES)\r
+#define DYN_TRACES 0\r
+#endif\r
+\r
+#if defined(NOTRACE)\r
+#error "Error: NOTRACE has to be not defined !"\r
+#endif\r
+\r
+#undef NOTRACE\r
+#if (DYN_TRACES==0)\r
+ #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE)\r
+ #define NOTRACE\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+/* ------------------------------------------------------------------------------\r
+ * Global Macros\r
+ * ------------------------------------------------------------------------------\r
+ */\r
+\r
+extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ;\r
+\r
+/**\r
+ * Initializes the DBGU for ISP project\r
+ *\r
+ * \param mode DBGU mode.\r
+ * \param baudrate DBGU baudrate.\r
+ * \param mck Master clock frequency.\r
+ */\r
+#ifndef DYNTRACE\r
+#define DYNTRACE 0\r
+#endif\r
+\r
+#if (TRACE_LEVEL==0) && (DYNTRACE==0)\r
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {}\r
+#else\r
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \\r
+ const Pin pinsUART0[] = {PINS_UART}; \\r
+ PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \\r
+ UART_Configure( baudrate, mck ) ; \\r
+ }\r
+#endif\r
+\r
+/**\r
+ * Outputs a formatted string using 'printf' if the log level is high\r
+ * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.\r
+ * \param ... Additional parameters depending on formatted string.\r
+ */\r
+#if defined(NOTRACE)\r
+\r
+/* Empty macro */\r
+#define TRACE_DEBUG(...) { }\r
+#define TRACE_INFO(...) { }\r
+#define TRACE_WARNING(...) { }\r
+#define TRACE_ERROR(...) { }\r
+#define TRACE_FATAL(...) { while(1); }\r
+\r
+#define TRACE_DEBUG_WP(...) { }\r
+#define TRACE_INFO_WP(...) { }\r
+#define TRACE_WARNING_WP(...) { }\r
+#define TRACE_ERROR_WP(...) { }\r
+#define TRACE_FATAL_WP(...) { while(1); }\r
+\r
+#elif (DYN_TRACES == 1)\r
+\r
+/* Trace output depends on dwTraceLevel value */\r
+#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } }\r
+#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } }\r
+#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }\r
+#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } }\r
+#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } }\r
+\r
+#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } }\r
+#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } }\r
+#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }\r
+#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } }\r
+#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } }\r
+\r
+#else\r
+\r
+/* Trace compilation depends on TRACE_LEVEL value */\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG)\r
+#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); }\r
+#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_DEBUG(...) { }\r
+#define TRACE_DEBUG_WP(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)\r
+#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); }\r
+#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_INFO(...) { }\r
+#define TRACE_INFO_WP(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING)\r
+#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); }\r
+#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_WARNING(...) { }\r
+#define TRACE_WARNING_WP(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR)\r
+#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); }\r
+#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); }\r
+#else\r
+#define TRACE_ERROR(...) { }\r
+#define TRACE_ERROR_WP(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL)\r
+#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); }\r
+#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); }\r
+#else\r
+#define TRACE_FATAL(...) { while(1); }\r
+#define TRACE_FATAL_WP(...) { while(1); }\r
+#endif\r
+\r
+#endif\r
+\r
+\r
+/**\r
+ * Exported variables\r
+ */\r
+/** Depending on DYN_TRACES, dwTraceLevel is a modifable runtime variable or a define */\r
+#if !defined(NOTRACE) && (DYN_TRACES == 1)\r
+ extern uint32_t dwTraceLevel ;\r
+#endif\r
+\r
+#endif //#ifndef TRACE_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _TRNG_\r
+#define _TRNG_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+void TRNG_Enable(void);\r
+void TRNG_Disable(void);\r
+void TRNG_EnableIt(void);\r
+void TRNG_DisableIt(void);\r
+uint32_t TRNG_GetStatus(void);\r
+uint32_t TRNG_GetRandData(void);\r
+\r
+#endif /* #ifndef _TRNG_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for configuration the Two Wire Interface (TWI) peripheral.\r
+ *\r
+ */\r
+\r
+#ifndef _TWI_\r
+#define _TWI_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/\r
+#define TWI_STATUS_TXRDY(status) ((status & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY)\r
+\r
+/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/\r
+#define TWI_STATUS_RXRDY(status) ((status & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY)\r
+\r
+/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/\r
+#define TWI_STATUS_TXCOMP(status) ((status & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * External function\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void TWI_ConfigureMaster(Twihs *pTwi, uint32_t twck, uint32_t mck);\r
+\r
+extern void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress);\r
+\r
+extern void TWI_Stop(Twihs *pTwi);\r
+\r
+extern void TWI_StartRead(\r
+ Twihs *pTwi,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize);\r
+\r
+extern uint8_t TWI_ReadByte(Twihs *pTwi);\r
+\r
+extern void TWI_WriteByte(Twihs *pTwi, uint8_t byte);\r
+\r
+extern void TWI_StartWrite(\r
+ Twihs *pTwi,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t byte);\r
+\r
+extern uint8_t TWI_ByteReceived(Twihs *pTwi);\r
+\r
+extern uint8_t TWI_ByteSent(Twihs *pTwi);\r
+\r
+extern uint8_t TWI_TransferComplete(Twihs *pTwi);\r
+\r
+extern void TWI_EnableIt(Twihs *pTwi, uint32_t sources);\r
+\r
+extern void TWI_DisableIt(Twihs *pTwi, uint32_t sources);\r
+\r
+extern uint32_t TWI_GetStatus(Twihs *pTwi);\r
+\r
+extern uint32_t TWI_GetMaskedStatus(Twihs *pTwi);\r
+\r
+extern void TWI_SendSTOPCondition(Twihs *pTwi);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _TWI_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _TWID_\r
+#define _TWID_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** TWI driver is currently busy. */\r
+#define TWID_ERROR_BUSY 1\r
+\r
+ /** Transfer is still pending.*/\r
+#define ASYNC_STATUS_PENDING 0xFF\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ /*----------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+/** \brief Asynchronous transfer descriptor. */\r
+typedef struct _Async\r
+{\r
+ /** Asynchronous transfer status.*/\r
+ volatile uint32_t status ;\r
+ /** Callback function to invoke when transfer completes or fails.*/\r
+ void *callback ;\r
+ /** Driver storage area; do not use.*/\r
+ uint8_t pStorage[9] ;\r
+} Async ;\r
+\r
+/** \brief TWI driver structure. Holds the internal state of the driver.*/\r
+typedef struct _Twid\r
+{\r
+ /** Pointer to the underlying TWI peripheral.*/\r
+ Twihs *pTwi ;\r
+ /** Current asynchronous transfer being processed.*/\r
+ Async *pTransfer ;\r
+} Twid;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void TWID_Initialize( Twid *pTwid, Twihs *pTwi ) ;\r
+extern void TWID_DmaInitialize(Twid *pTwid, Twihs *pTwi);\r
+\r
+extern void TWID_Handler( Twid *pTwid ) ;\r
+\r
+extern uint32_t ASYNC_IsFinished( Async* pAsync ) ;\r
+\r
+extern uint8_t TWID_Read(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync);\r
+\r
+extern uint8_t TWID_Write(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync);\r
+\r
+extern uint8_t TWID_DmaRead(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync,\r
+ uint8_t TWI_ID);\r
+\r
+extern uint8_t TWID_DmaWrite(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync,\r
+ uint8_t TWI_ID);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //#ifndef TWID_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifndef UART_H\r
+#define UART_H\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Global functions\r
+//------------------------------------------------------------------------------\r
+\r
+void UART_Configure(Uart *uart, uint32_t mode, uint32_t baudrate, uint32_t masterClock);\r
+\r
+void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled);\r
+\r
+void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled);\r
+\r
+void UART_PutChar( Uart *uart, uint8_t c);\r
+\r
+uint32_t UART_IsRxReady(Uart *uart);\r
+\r
+uint8_t UART_GetChar(Uart *uart);\r
+\r
+uint32_t UART_GetStatus(Uart *uart);\r
+\r
+void UART_EnableIt(Uart *uart,uint32_t mode);\r
+\r
+void UART_DisableIt(Uart *uart,uint32_t mode);\r
+\r
+uint32_t UART_GetItMask(Uart *uart);\r
+\r
+void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen);\r
+\r
+void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen);\r
+\r
+void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2);\r
+\r
+uint32_t UART_IsTxReady(Uart *uart);\r
+#endif //#ifndef UART_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of UART driver, transfer data through DMA.\r
+ *\r
+ */\r
+\r
+#ifndef _UART_DMA_\r
+#define _UART_DMA_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** An unspecified error has occured.*/\r
+#define UARTD_ERROR 1\r
+\r
+/** UART driver is currently in use.*/\r
+#define UARTD_ERROR_LOCK 2\r
+\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** UART transfer complete callback. */\r
+typedef void (*UartdCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief usart Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the UART_Send or UART_Rcv to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct\r
+{\r
+ /** Pointer to the Buffer. */\r
+ uint8_t *pBuff;\r
+ /** Buff size in bytes. */\r
+ uint8_t BuffSize;\r
+ /** Dma channel num. */\r
+ uint32_t ChNum;\r
+ /** Callback function invoked at the end of transfer. */\r
+ UartdCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+ /** flag to indicate the current transfer. */\r
+ volatile uint8_t sempaphore;\r
+} UartChannel ;\r
+\r
+/** Constant structure associated with UART port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct \r
+{\r
+ /** Pointer to UART Hardware registers */\r
+ Uart* pUartHw ;\r
+ /** Current Uart Rx channel */\r
+ UartChannel *pRxChannel ;\r
+ /** Current Uart Tx channel */\r
+ UartChannel *pTxChannel ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad;\r
+ /** USART Id as defined in the product datasheet */\r
+ uint8_t uartId ;\r
+} UartDma;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t UARTD_Configure( UartDma *pUartd ,\r
+ Uart *pUartHw ,\r
+ uint8_t uartId,\r
+ uint32_t UartMode,\r
+ sXdmad *pXdmad );\r
+\r
+extern uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh);\r
+\r
+extern uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh);\r
+\r
+extern uint32_t UARTD_SendData( UartDma* pUartd ) ;\r
+\r
+extern uint32_t UARTD_RcvData( UartDma *pUartd);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _UART_DMA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+#ifndef UDPHS_H\r
+#define UDPHS_H\r
+/** addtogroup usbd_hal\r
+ *@{\r
+ */\r
+\r
+/** Indicates chip has an UDP High Speed. */\r
+#define CHIP_USB_UDPHS\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 7\r
+\r
+/** Endpoints max paxcket size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \\r
+ ((i == 0) ? 64 : 1024)\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i) \\r
+ ((i == 0) ? 1 : ((i == 1) ? 3 : ((i == 2) ? 3 : 2)))\r
+\r
+/** Endpoints DMA support */\r
+#define CHIP_USB_ENDPOINTS_DMA(i) \\r
+ ((i == 0) ? 0 : 1)\r
+\r
+/**@}*/\r
+#endif /* #ifndef UDPHS_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This module provides several definitions and methods for using an USART\r
+ * peripheral.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Enable the USART peripheral clock in the PMC.\r
+ * -# Enable the required USART PIOs (see pio.h).\r
+ * -# Configure the UART by calling USART_Configure.\r
+ * -# Enable the transmitter and/or the receiver of the USART using\r
+ * USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+ * -# Send data through the USART using the USART_Write methods.\r
+ * -# Receive data from the USART using the USART_Read functions; the availability of data can be polled\r
+ * with USART_IsDataAvailable.\r
+ * -# Disable the transmitter and/or the receiver of the USART with\r
+ * USART_SetTransmitterEnabled and USART_SetReceiverEnabled.\r
+ */\r
+\r
+#ifndef _USART_\r
+#define _USART_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** \section USART_mode USART modes\r
+ * This section lists several common operating modes for an USART peripheral.\r
+ *\r
+ * \b Modes\r
+ * - USART_MODE_ASYNCHRONOUS\r
+ * - USART_MODE_IRDA\r
+ */\r
+\r
+/** Basic asynchronous mode, i.e. 8 bits no parity.*/\r
+#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO)\r
+\r
+/** IRDA mode*/\r
+#define USART_MODE_IRDA \\r
+ (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER)\r
+\r
+/** SPI mode*/\r
+#define AT91C_US_USMODE_SPIM 0xE\r
+#define US_SPI_CPOL_0 (0x0<<16)\r
+#define US_SPI_CPHA_0 (0x0<<8)\r
+#define US_SPI_CPOL_1 (0x1<<16)\r
+#define US_SPI_CPHA_1 (0x1<<8)\r
+#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1)\r
+#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0)\r
+#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1)\r
+#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0)\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void USART_Configure( Usart *pUsart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ;\r
+extern uint32_t USART_GetStatus( Usart *usart ) ;\r
+extern void USART_EnableIt( Usart *usart,uint32_t mode ) ;\r
+extern void USART_DisableIt( Usart *usart,uint32_t mode ) ;\r
+extern uint32_t USART_GetItMask( Usart * usart ) ;\r
+extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ;\r
+\r
+extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ;\r
+\r
+extern void USART_SetRTSEnabled(Usart *usart, uint8_t enabled);\r
+\r
+extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ;\r
+\r
+extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ;\r
+\r
+extern uint8_t USART_IsDataAvailable( Usart *usart ) ;\r
+\r
+extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);\r
+\r
+extern void USART_PutChar( Usart *usart, uint8_t c ) ;\r
+\r
+extern uint32_t USART_IsRxReady( Usart *usart ) ;\r
+\r
+extern uint8_t USART_GetChar( Usart *usart ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _USART_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2009, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of USART driver, transfer data through DMA.\r
+ *\r
+ */\r
+\r
+#ifndef _USART_DMA_H_\r
+#define _USART_DMA_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** An unspecified error has occured.*/\r
+#define USARTD_ERROR 1\r
+\r
+/** USART driver is currently in use.*/\r
+#define USARTD_ERROR_LOCK 2\r
+\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** USART transfer complete callback. */\r
+typedef void (*UsartdCallback)( uint8_t, void* ) ;\r
+\r
+/** \brief usart Transfer Request prepared by the application upper layer.\r
+ *\r
+ * This structure is sent to the USART_Send or USART_Rcv to start the transfer.\r
+ * At the end of the transfer, the callback is invoked by the interrupt handler.\r
+ */\r
+typedef struct\r
+{\r
+ /** Pointer to the Buffer. */\r
+ uint8_t *pBuff;\r
+ /** Buff size in bytes. */\r
+ uint8_t BuffSize;\r
+ /** Dma channel num. */\r
+ uint8_t ChNum;\r
+ /** Callback function invoked at the end of transfer. */\r
+ UsartdCallback callback;\r
+ /** Callback arguments. */\r
+ void *pArgument;\r
+ /** flag to indicate the current transfer. */\r
+ volatile uint8_t Done;\r
+} UsartChannel ;\r
+\r
+/** Constant structure associated with USART port. This structure prevents\r
+ client applications to have access in the same time. */\r
+typedef struct \r
+{\r
+ /** Pointer to USART Hardware registers */\r
+ Usart* pUsartHw ;\r
+ /** Current Usart Rx channel */\r
+ UsartChannel *pRxChannel ;\r
+ /** Current Usart Tx channel */\r
+ UsartChannel *pTxChannel ;\r
+ /** Pointer to DMA driver */\r
+ sXdmad* pXdmad;\r
+ /** USART Id as defined in the product datasheet */\r
+ uint8_t usartId ;\r
+} UsartDma;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t USARTD_Configure( UsartDma *pUsartd ,\r
+ Usart *pUsartHw ,\r
+ uint8_t USARTId,\r
+ uint32_t UsartMode,\r
+ uint32_t UsartClk,\r
+ sXdmad *pXdmad );\r
+\r
+extern uint32_t USARTD_EnableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh);\r
+\r
+extern uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh);\r
+\r
+extern uint32_t USARTD_SendData( UsartDma* pUsartd ) ;\r
+\r
+extern uint32_t USARTD_RcvData( UsartDma *pUsartd);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _USART_DMA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _VIDEO_H\r
+#define _VIDEO_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+/** Type of video is YUV */\r
+#define YUV 0\r
+/** Type of video is RGB */\r
+#define RGB 1\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+typedef struct _isi_Video\r
+{\r
+ /** LCD Vertical Size */\r
+ uint32_t lcd_vsize;\r
+ /** LCD Horizontal Size*/\r
+ uint32_t lcd_hsize;\r
+ /** LCD Number of Bit Per Pixel*/\r
+ uint32_t lcd_nbpp;\r
+ /** LCD Frame Buffer Address*/\r
+ uint32_t lcd_fb_addr;\r
+ /** Base address for the frame buffer descriptors list*/\r
+ uint32_t Isi_fbd_base;\r
+ /** Start of Line Delay*/\r
+ uint32_t Hblank;\r
+ /** Start of frame Delay */\r
+ uint32_t Vblank;\r
+ /** Vertical size of the Image sensor [0..2047]*/\r
+ uint32_t codec_vsize;\r
+ /** Horizontal size of the Image sensor [0..2047]*/\r
+ uint32_t codec_hsize;\r
+ /** Base address for codec DMA*/\r
+ uint32_t codec_fb_addr;\r
+ /** Base address for the frame buffer descriptors list*/\r
+ uint32_t codec_fbd_base;\r
+ /** Buffer index */\r
+ uint32_t IsiPrevBuffIndex;\r
+ /** Type of video */\r
+ uint8_t rgb_or_yuv;\r
+}isi_Video, *pIsi_Video;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len);\r
+\r
+#endif\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ * Interface for Watchdog Timer (WDT) controller.\r
+ *\r
+ * \section Usage\r
+ * -# Enable watchdog with given mode using \ref WDT_Enable().\r
+ * -# Disable watchdog using \ref WDT_Disable()\r
+ * -# Restart the watchdog using \ref WDT_Restart().\r
+ * -# Get watchdog status using \ref WDT_GetStatus().\r
+ * -# Caculate watchdog period value using \ref WDT_GetPeriod().\r
+ */\r
+\r
+#ifndef _WDT_\r
+#define _WDT_\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ;\r
+\r
+extern void WDT_Disable( Wdt* pWDT ) ;\r
+\r
+extern void WDT_Restart( Wdt* pWDT ) ;\r
+\r
+extern uint32_t WDT_GetStatus( Wdt* pWDT ) ;\r
+\r
+extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _WDT_ */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _XDMAD_IF_H\r
+#define _XDMAD_IF_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Includes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** DMA hardware interface */\r
+typedef struct _XdmaHardwareInterface {\r
+ uint8_t bXdmac; /**< DMA Controller number */\r
+ uint32_t bPeriphID; /**< Peripheral ID */\r
+ uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/\r
+ uint8_t bIfID; /**< DMA Interface ID */\r
+} XdmaHardwareInterface;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bPeriphID);\r
+extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, uint8_t bTransfer);\r
+\r
+#endif //#ifndef _XDMAD_IF_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup dmac_module Working with DMAC\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable or disable the a DMAC controller with DMAC_Enable() and or DMAC_Disable().</li>\r
+ * <li> Enable or disable %Dma interrupt using DMAC_EnableIt()or DMAC_DisableIt().</li>\r
+ * <li> Get %Dma interrupt status by DMAC_GetStatus() and DMAC_GetInterruptMask().</li>\r
+ * <li> Enable or disable specified %Dma channel with DMAC_EnableChannel() or DMAC_DisableChannel().</li>\r
+ * <li> Get %Dma channel status by DMAC_GetChannelStatus().</li>\r
+ * <li> ControlA and ControlB register is set by DMAC_SetControlA() and DMAC_SetControlB().</li>\r
+ * <li> Configure source and/or destination start address with DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().</li>\r
+ * <li> Set %Dma descriptor address using DMAC_SetDescriptorAddr().</li>\r
+ * <li> Set source transfer buffer size with DMAC_SetBufferSize().</li>\r
+ * <li> Configure source and/or destination Picture-In-Picutre mode with DMAC_SetSourcePip() and/or DMAC_SetDestPip().</li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the DMAC section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref dmad_module\r
+ *\r
+ * Related files :\n\r
+ * \ref dmac.c\n\r
+ * \ref dmac.h.\n\r
+ *\r
+ */\r
+\r
+#ifndef DMAC_H\r
+#define DMAC_H\r
+/**@{*/\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_defines DMAC Definitions\r
+ * @{\r
+ */\r
+/** Number of DMA channels */\r
+#define XDMAC_CONTROLLER_NUM 1\r
+/** Number of DMA channels */\r
+#define XDMAC_CHANNEL_NUM 24\r
+/** Max DMA single transfer size */\r
+#define XDMAC_MAX_BT_SIZE 0xFFFF\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macro\r
+ *----------------------------------------------------------------------------*/\r
+#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \\r
+ ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \\r
+ (XDMAC_CC_DWIDTH_WORD )))\r
+#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \\r
+ ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \\r
+ ((s==2)? XDMAC_CC_SAM_UBS_AM : XDMAC_CC_SAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \\r
+ ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \\r
+ ((d==2)? XDMAC_CC_DAM_UBS_AM : XDMAC_CC_DAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : XDMAC_CC_MEMSET_HW_MODE)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Data structs\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_struct DMAC Data Structs\r
+ * @{\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+/** \addtogroup dmac_functions\r
+ * @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern uint32_t XDMAC_GetType( Xdmac *pXdmac);\r
+extern uint32_t XDMAC_GetConfig( Xdmac *pXdmac);\r
+extern uint32_t XDMAC_GetArbiter( Xdmac *pXdmac);\r
+extern void XDMAC_EnableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask );\r
+extern void XDMAC_DisableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask );\r
+extern uint32_t XDMAC_GetGItMask( Xdmac *pXdmac );\r
+extern uint32_t XDMAC_GetGIsr( Xdmac *pXdmac );\r
+extern uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac );\r
+extern void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_EnableChannels( Xdmac *pXdmac, uint8_t bmChannels );\r
+extern void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_DisableChannels( Xdmac *pXdmac, uint8_t bmChannels );\r
+extern uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac);\r
+extern void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac);\r
+extern void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask );\r
+extern void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask );\r
+extern uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr);\r
+extern void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr);\r
+extern void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr, uint32_t ndaif);\r
+extern void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint32_t config);\r
+extern void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen);\r
+extern void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint32_t blen);\r
+extern void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config);\r
+extern uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, uint32_t dds_msp);\r
+extern void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t subs);\r
+extern void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t dubs);\r
+extern uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @}*/\r
+/**@}*/\r
+#endif //#ifndef DMAC_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _XDMAD_H\r
+#define _XDMAD_H\r
+\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Includes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include <assert.h>\r
+\r
+\r
+/** \addtogroup dmad_defines DMA Driver Defines\r
+ @{*/\r
+/*----------------------------------------------------------------------------\r
+ * Consts\r
+ *----------------------------------------------------------------------------*/\r
+#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */\r
+#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */\r
+\r
+#define XDMAD_TRANSFER_TX 0\r
+#define XDMAD_TRANSFER_RX 1\r
+\r
+/* XDMA_MBR_UBC */\r
+#define XDMA_UBC_NDE (0x1u << 24)\r
+#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)\r
+#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)\r
+#define XDMA_UBC_NSEN (0x1u << 25)\r
+#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)\r
+#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)\r
+#define XDMA_UBC_NDEN (0x1u << 26)\r
+#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)\r
+#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)\r
+#define XDMA_UBC_NVIEW_Pos 27\r
+#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * MACRO\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup dmad_structs DMA Driver Structs\r
+ @{*/\r
+\r
+/** DMA status or return code */\r
+typedef enum _XdmadStatus {\r
+ XDMAD_OK = 0, /**< Operation is sucessful */\r
+ XDMAD_PARTIAL_DONE,\r
+ XDMAD_DONE,\r
+ XDMAD_BUSY, /**< Channel occupied or transfer not finished */\r
+ XDMAD_ERROR, /**< Operation failed */\r
+ XDMAD_CANCELED /**< Operation canceled */\r
+} eXdmadStatus, eXdmadRC;\r
+\r
+/** DMA state for channel */\r
+typedef enum _XdmadState {\r
+ XDMAD_STATE_FREE = 0, /**< Free channel */\r
+ XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */\r
+ XDMAD_STATE_START, /**< DMA started */ \r
+ XDMAD_STATE_IN_XFR, /**< DMA in trasfering */\r
+ XDMAD_STATE_DONE, /**< DMA transfer done */\r
+} eXdmadState;\r
+\r
+/** DMA transfer callback */\r
+typedef void (*XdmadTransferCallback)(uint32_t status, void* pArg);\r
+\r
+/** DMA driver channel */\r
+typedef struct _XdmadChannel {\r
+ XdmadTransferCallback fCallback; /**< Callback */\r
+ void* pArg; /**< Callback argument */\r
+ uint8_t bIrqOwner; /**< Uses DMA handler or external one */\r
+ uint8_t bSrcPeriphID; /**< HW ID for source */\r
+ uint8_t bDstPeriphID; /**< HW ID for destination */\r
+ uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */\r
+ uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */\r
+ uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */\r
+ uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */\r
+ volatile uint8_t state; /**< DMA channel state */\r
+} sXdmadChannel;\r
+\r
+/** DMA driver instance */\r
+typedef struct _Xdmad {\r
+ Xdmac *pXdmacs;\r
+ sXdmadChannel XdmaChannels[XDMACCHID_NUMBER];\r
+ uint8_t numControllers;\r
+ uint8_t numChannels;\r
+ uint8_t pollingMode;\r
+ uint8_t pollingTimeout;\r
+} sXdmad;\r
+\r
+typedef struct _XdmadCfg {\r
+ /** Microblock Control Member. */\r
+ uint32_t mbr_ubc;\r
+ /** Source Address Member. */\r
+ uint32_t mbr_sa;\r
+ /** Destination Address Member. */\r
+ uint32_t mbr_da;\r
+ /** Configuration Register. */\r
+ uint32_t mbr_cfg;\r
+ /** Block Control Member. */\r
+ uint32_t mbr_bc;\r
+ /** Data Stride Member. */\r
+ uint32_t mbr_ds;\r
+ /** Source Microblock Stride Member. */\r
+ uint32_t mbr_sus;\r
+ /** Destination Microblock Stride Member. */\r
+ uint32_t mbr_dus;\r
+} sXdmadCfg;\r
+\r
+/** \brief Structure for storing parameters for DMA view0 that can be\r
+ * performed by the DMA Master transfer.*/\r
+typedef struct _LinkedListDescriporView0 \r
+{\r
+ /** Next Descriptor Address number. */\r
+ uint32_t mbr_nda;\r
+ /** Microblock Control Member. */\r
+ uint32_t mbr_ubc;\r
+ /** Transfer Address Member. */\r
+ uint32_t mbr_ta;\r
+}LinkedListDescriporView0;\r
+\r
+/** \brief Structure for storing parameters for DMA view1 that can be\r
+ * performed by the DMA Master transfer.*/\r
+typedef struct _LinkedListDescriporView1\r
+{\r
+ /** Next Descriptor Address number. */\r
+ uint32_t mbr_nda;\r
+ /** Microblock Control Member. */\r
+ uint32_t mbr_ubc;\r
+ /** Source Address Member. */\r
+ uint32_t mbr_sa;\r
+ /** Destination Address Member. */\r
+ uint32_t mbr_da;\r
+}LinkedListDescriporView1;\r
+\r
+/** \brief Structure for storing parameters for DMA view2 that can be\r
+ * performed by the DMA Master transfer.*/\r
+typedef struct _LinkedListDescriporView2\r
+{\r
+ /** Next Descriptor Address number. */\r
+ uint32_t mbr_nda;\r
+ /** Microblock Control Member. */\r
+ uint32_t mbr_ubc;\r
+ /** Source Address Member. */\r
+ uint32_t mbr_sa;\r
+ /** Destination Address Member. */\r
+ uint32_t mbr_da;\r
+ /** Configuration Register. */\r
+ uint32_t mbr_cfg;\r
+}LinkedListDescriporView2;\r
+\r
+/** \brief Structure for storing parameters for DMA view3 that can be\r
+ * performed by the DMA Master transfer.*/\r
+typedef struct _LinkedListDescriporView3\r
+{\r
+ /** Next Descriptor Address number. */\r
+ uint32_t mbr_nda;\r
+ /** Microblock Control Member. */\r
+ uint32_t mbr_ubc;\r
+ /** Source Address Member. */\r
+ uint32_t mbr_sa;\r
+ /** Destination Address Member. */\r
+ uint32_t mbr_da;\r
+ /** Configuration Register. */\r
+ uint32_t mbr_cfg;\r
+ /** Block Control Member. */\r
+ uint32_t mbr_bc;\r
+ /** Data Stride Member. */\r
+ uint32_t mbr_ds;\r
+ /** Source Microblock Stride Member. */\r
+ uint32_t mbr_sus;\r
+ /** Destination Microblock Stride Member. */\r
+ uint32_t mbr_dus;\r
+}LinkedListDescriporView3;\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup dmad_functions DMA Driver Functionos\r
+ @{*/\r
+extern void XDMAD_Initialize( sXdmad *pXdmad,\r
+ uint8_t bPollingMode );\r
+\r
+extern void XDMAD_Handler( sXdmad *pDmad);\r
+\r
+extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,\r
+ uint8_t bSrcID, uint8_t bDstID);\r
+extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel );\r
+\r
+extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,\r
+ uint32_t dwChannel,\r
+ sXdmadCfg *pXdmaParam,\r
+ uint32_t dwXdmaDescCfg,\r
+ uint32_t dwXdmaDescAddr);\r
+\r
+extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel);\r
+\r
+extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel );\r
+\r
+extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel );\r
+\r
+extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad, \r
+ uint32_t dwChannel,\r
+ XdmadTransferCallback fCallback, \r
+ void* pArg );\r
+\r
+extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel );\r
+/** @}*/\r
+/**@}*/\r
+#endif //#ifndef _XDMAD_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <USBD_Config.h>\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported function\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Invoked after the USB driver has been initialized. By default, configures\r
+ * the UDP/UDPHS interrupt.\r
+ */\r
+void USBDCallbacks_Initialized(void)\r
+{\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /** \file */\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "USBD_LEDs.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Invoked when the USB device leaves the Suspended state. By default,\r
+ * configures the LEDs.\r
+ */\r
+void USBDCallbacks_Resumed(void)\r
+{\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /** \file */\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "USBD_LEDs.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Invoked when the USB device gets suspended. By default, turns off all LEDs.\r
+ */\r
+void USBDCallbacks_Suspended(void)\r
+{\r
+ \r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+\r
+ \file\r
+\r
+ Implementation of USB device functions on a UDP controller.\r
+\r
+ See \ref usbd_api_method USBD API Methods.\r
+*/\r
+\r
+/** \addtogroup usbd_hal\r
+ *@{*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "USBD_HAL.h"\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Definitions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#define DMA\r
+\r
+/** Maximum number of endpoints interrupts. */\r
+#define NUM_IT_MAX \\r
+ ((UDPHS->UDPHS_IPFEATURES & UDPHS_IPFEATURES_EPT_NBR_MAX_Msk) ? \\r
+ (UDPHS->UDPHS_IPFEATURES & UDPHS_IPFEATURES_EPT_NBR_MAX_Msk) : 16)\r
+/** Maximum number of endpoint DMA interrupts */\r
+#define NUM_IT_MAX_DMA \\r
+ ((UDPHS->UDPHS_IPFEATURES \\r
+ & UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk) \\r
+ >>UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos)\r
+/** Bits that should be shifted to access DMA control bits. */\r
+#define SHIFT_DMA 24\r
+/** Bits that should be shifted to access interrupt bits. */\r
+#define SHIFT_INTERUPT 8\r
+\r
+/** Max size of the FMA FIFO */\r
+#define DMA_MAX_FIFO_SIZE (65536/1)\r
+/** fifo space size in DW */\r
+#define EPT_VIRTUAL_SIZE 16384\r
+\r
+/**\r
+ * \section endpoint_states_sec "UDP Endpoint states"\r
+ *\r
+ * This page lists the endpoint states.\r
+ *\r
+ * \subsection States\r
+ * - UDPHS_ENDPOINT_DISABLED\r
+ * - UDPHS_ENDPOINT_HALTED\r
+ * - UDPHS_ENDPOINT_IDLE\r
+ * - UDPHS_ENDPOINT_SENDING\r
+ * - UDPHS_ENDPOINT_RECEIVING\r
+ * - UDPHS_ENDPOINT_SENDINGM\r
+ * - UDPHS_ENDPOINT_RECEIVINGM\r
+ */\r
+\r
+/** Endpoint states: Endpoint is disabled */\r
+#define UDPHS_ENDPOINT_DISABLED 0\r
+/** Endpoint states: Endpoint is halted (i.e. STALLs every request) */\r
+#define UDPHS_ENDPOINT_HALTED 1\r
+/** Endpoint states: Endpoint is idle (i.e. ready for transmission) */\r
+#define UDPHS_ENDPOINT_IDLE 2\r
+/** Endpoint states: Endpoint is sending data */\r
+#define UDPHS_ENDPOINT_SENDING 3\r
+/** Endpoint states: Endpoint is receiving data */\r
+#define UDPHS_ENDPOINT_RECEIVING 4\r
+/** Endpoint states: Endpoint is sending MBL */\r
+#define UDPHS_ENDPOINT_SENDINGM 5\r
+/** Endpoint states: Endpoint is receiving MBL */\r
+#define UDPHS_ENDPOINT_RECEIVINGM 6\r
+\r
+/** Get Number of buffer in Multi-Buffer-List\r
+ * \param i input index\r
+ * \param o output index\r
+ * \param size list size\r
+ */\r
+#define MBL_NbBuffer(i, o, size) (((i)>(o))?((i)-(o)):((i)+(size)-(o)))\r
+\r
+/** Buffer list is full */\r
+#define MBL_FULL 1\r
+/** Buffer list is null */\r
+#define MBL_NULL 2\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** Describes header for UDP endpoint transfer. */\r
+typedef struct {\r
+ /** Optional callback to invoke when the transfer completes. */\r
+ void* fCallback;\r
+ /** Optional argument to the callback function. */\r
+ void* pArgument;\r
+ /** Transfer type */\r
+ uint8_t transType;\r
+ /* Reserved to 32-b aligned */\r
+ uint8_t reserved[3];\r
+} TransferHeader;\r
+\r
+/** Describes a transfer on a UDP endpoint. */\r
+typedef struct {\r
+\r
+ /** Optional callback to invoke when the transfer completes. */\r
+ TransferCallback fCallback;\r
+ /** Optional argument to the callback function. */\r
+ void *pArgument;\r
+ /** Transfer type */\r
+ uint8_t transType;\r
+ uint8_t reserved[3];\r
+ /** Number of bytes which have been written into the UDP internal FIFO\r
+ * buffers. */\r
+ int32_t buffered;\r
+ /** Pointer to a data buffer used for emission/reception. */\r
+ uint8_t *pData;\r
+ /** Number of bytes which have been sent/received. */\r
+ int32_t transferred;\r
+ /** Number of bytes which have not been buffered/transferred yet. */\r
+ int32_t remaining;\r
+} Transfer;\r
+\r
+/** Describes Multi Buffer List transfer on a UDP endpoint. */\r
+typedef struct {\r
+ /** Optional callback to invoke when the transfer completes. */\r
+ MblTransferCallback fCallback;\r
+ /** Optional argument to the callback function. */\r
+ void *pArgument;\r
+ /** Transfer type */\r
+ uint8_t transType;\r
+ /** List state (OK, FULL, NULL) (run time) */\r
+ uint8_t listState;\r
+ /** Multi-Buffer List size */\r
+ uint16_t listSize;\r
+ /** Pointer to multi-buffer list */\r
+ USBDTransferBuffer *pMbl;\r
+ /** Offset number of buffers to start transfer */\r
+ uint16_t offsetSize;\r
+ /** Current processing buffer index (run time) */\r
+ uint16_t outCurr;\r
+ /** Loast loaded buffer index (run time) */\r
+ uint16_t outLast;\r
+ /** Current buffer for input (run time) */\r
+ uint16_t inCurr;\r
+} MblTransfer;\r
+\r
+/**\r
+ * Describes the state of an endpoint of the UDP controller.\r
+ */\r
+typedef struct {\r
+\r
+ /* CSR */\r
+ /** Current endpoint state. */\r
+ volatile uint8_t state;\r
+ /** Current reception bank (0 or 1). */\r
+ volatile uint8_t bank;\r
+ /** Maximum packet size for the endpoint. */\r
+ volatile uint16_t size;\r
+ /** Describes an ongoing transfer (if current state is either\r
+ * UDPHS_ENDPOINT_SENDING or UDPHS_ENDPOINT_RECEIVING) */\r
+ union {\r
+ TransferHeader transHdr;\r
+ Transfer singleTransfer;\r
+ MblTransfer mblTransfer;\r
+ } transfer;\r
+ /** Special case for send a ZLP */\r
+ uint32_t sendZLP;\r
+} Endpoint;\r
+\r
+/**\r
+ * DMA Descriptor.\r
+ */\r
+typedef struct {\r
+ void *pNxtDesc;\r
+ void *pAddr;\r
+ uint32_t dwCtrl;\r
+ uint32_t dw;\r
+} UdphsDmaDescriptor;\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Internal variables\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** Holds the internal state for each endpoint of the UDP. */\r
+static Endpoint endpoints[CHIP_USB_NUMENDPOINTS];\r
+\r
+/** 7.1.20 Test Mode Support\r
+ * Test codes for the USB HS test mode. */\r
+static const char test_packet_buffer[] = {\r
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9\r
+ 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8\r
+ 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8\r
+ 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8\r
+ 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8\r
+ 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK\r
+};\r
+\r
+/** Force FS mode */\r
+static const uint8_t forceUsbFS = 0;\r
+\r
+/** DMA link list */\r
+static UdphsDmaDescriptor dmaLL[5];\r
+static UdphsDmaDescriptor *pDmaLL;\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Internal Functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Enables the clock of the UDP peripheral.\r
+ * \return 1 if peripheral status changed.\r
+ */\r
+static uint8_t UDPHS_EnablePeripheralClock(void)\r
+{\r
+ if (!PMC_IsPeriphEnabled(ID_UDPHS)) {\r
+ PMC_EnablePeripheral(ID_UDPHS);\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Disables the UDP peripheral clock.\r
+ */\r
+static inline void UDPHS_DisablePeripheralClock(void)\r
+{\r
+ PMC_DisablePeripheral(ID_UDPHS);\r
+}\r
+\r
+/**\r
+ * Enables the 480MHz USB clock.\r
+ */\r
+static inline void UDPHS_EnableUsbClock(void)\r
+{\r
+ Pmc *pPmc = PMC;\r
+ /* Enable 480Mhz UPLL */\r
+ pPmc->CKGR_UCKR |= CKGR_UCKR_UPLLEN\r
+ | CKGR_UCKR_UPLLCOUNT(0x3)\r
+ | CKGR_UCKR_BIASCOUNT(0x1);\r
+ /* Wait until UPLL is locked */\r
+ while((pPmc->PMC_SR & PMC_SR_LOCKU) == 0);\r
+}\r
+\r
+/**\r
+ * Disables the 480MHz USB clock.\r
+ */\r
+static inline void UDPHS_DisableUsbClock(void)\r
+{\r
+ Pmc *pPmc = PMC;\r
+ /* Disable System Clock */\r
+ //pPmc->PMC_SCDR = PMC_SCDR_UDP;\r
+ pPmc->CKGR_UCKR &= ~(uint32_t)CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+/**\r
+ * Enables the BIAS.\r
+ */\r
+static inline void UDPHS_EnableBIAS(void)\r
+{\r
+ Pmc *pPmc = PMC;\r
+ pPmc->CKGR_UCKR |= CKGR_UCKR_BIASEN;\r
+}\r
+\r
+/**\r
+ * Disables the BIAS.\r
+ */\r
+static inline void UDPHS_DisableBIAS(void)\r
+{\r
+ Pmc *pPmc = PMC;\r
+ pPmc->CKGR_UCKR &= ~(uint32_t)CKGR_UCKR_BIASEN;\r
+}\r
+\r
+/**\r
+ * Handles a completed transfer on the given endpoint, invoking the\r
+ * configured callback if any.\r
+ * \param bEndpoint Number of the endpoint for which the transfer has completed.\r
+ * \param bStatus Status code returned by the transfer operation\r
+ */\r
+static void UDPHS_EndOfTransfer(uint8_t bEndpoint, uint8_t bStatus)\r
+{\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+\r
+ /* Check that endpoint was sending or receiving data */\r
+ if ( (pEp->state == UDPHS_ENDPOINT_RECEIVING)\r
+ || (pEp->state == UDPHS_ENDPOINT_SENDING) )\r
+ {\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+ uint32_t transferred = pXfr->transferred;\r
+ uint32_t remaining = pXfr->remaining + pXfr->buffered;\r
+ \r
+ TRACE_DEBUG_WP("EoT ");\r
+ if (pEp->state == UDPHS_ENDPOINT_SENDING)\r
+ pEp->sendZLP = 0;\r
+ pEp->state = UDPHS_ENDPOINT_IDLE;\r
+ pXfr->pData = 0;\r
+ pXfr->transferred = -1;\r
+ pXfr->buffered = -1;\r
+ pXfr->remaining = -1;\r
+\r
+ /* Invoke callback */\r
+ if (pXfr->fCallback)\r
+ {\r
+ pXfr->fCallback(pXfr->pArgument, bStatus, transferred, remaining);\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG_WP("NoCB ");\r
+ }\r
+ }\r
+ else if ( (pEp->state == UDPHS_ENDPOINT_RECEIVINGM)\r
+ || (pEp->state == UDPHS_ENDPOINT_SENDINGM) )\r
+ {\r
+ MblTransfer *pXfr = (MblTransfer*)&(pEp->transfer);\r
+ TRACE_DEBUG_WP("EoMT ");\r
+\r
+ pEp->state = UDPHS_ENDPOINT_IDLE;\r
+ pXfr->listState = 0;\r
+ pXfr->outCurr = pXfr->inCurr = pXfr->outLast = 0;\r
+ /* Invoke callback */\r
+ if (pXfr->fCallback)\r
+ {\r
+ pXfr->fCallback(pXfr->pArgument, bStatus);\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG_WP("NoCB ");\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Update multi-buffer-transfer descriptors.\r
+ * \param pTransfer Pointer to instance MblTransfer.\r
+ * \param size Size of bytes that processed.\r
+ * \param forceEnd Force the buffer END.\r
+ * \return 1 if current buffer ended.\r
+ */\r
+static uint8_t UDPHS_MblUpdate(MblTransfer *pTransfer,\r
+ USBDTransferBuffer * pBi,\r
+ uint16_t size,\r
+ uint8_t forceEnd)\r
+{\r
+ /* Update transfer descriptor */\r
+ pBi->remaining -= size;\r
+ /* Check if list NULL */\r
+ if (pTransfer->listState == MBL_NULL) {\r
+ return 1;\r
+ }\r
+ /* Check if current buffer ended */\r
+ if (pBi->remaining == 0 || forceEnd || size == 0) {\r
+\r
+ /* Process to next buffer */\r
+ if ((++ pTransfer->outCurr) == pTransfer->listSize)\r
+ pTransfer->outCurr = 0;\r
+ /* Check buffer NULL case */\r
+ if (pTransfer->outCurr == pTransfer->inCurr)\r
+ pTransfer->listState = MBL_NULL;\r
+ else {\r
+ pTransfer->listState = 0;\r
+ /* Continue transfer, prepare for next operation */\r
+ pBi = &pTransfer->pMbl[pTransfer->outCurr];\r
+ pBi->buffered = 0;\r
+ pBi->transferred = 0;\r
+ pBi->remaining = pBi->size;\r
+ }\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Transfers a data payload from the current tranfer buffer to the endpoint\r
+ * FIFO\r
+ * \param bEndpoint Number of the endpoint which is sending data.\r
+ */\r
+static uint8_t UDPHS_MblWriteFifo(uint8_t bEndpoint)\r
+{\r
+ Endpoint *pEndpoint = &(endpoints[bEndpoint]);\r
+ MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer);\r
+ USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->outCurr]);\r
+ uint8_t *pFifo;\r
+ int32_t size;\r
+\r
+ volatile uint8_t * pBytes;\r
+ volatile uint8_t bufferEnd = 1;\r
+\r
+ /* Get the number of bytes to send */\r
+ size = pEndpoint->size;\r
+ if (size > pBi->remaining) size = pBi->remaining;\r
+\r
+ TRACE_DEBUG_WP("w%d.%d ", pTransfer->outCurr, size);\r
+\r
+ /* Record last accessed buffer */\r
+ pTransfer->outLast = pTransfer->outCurr;\r
+\r
+ pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]);\r
+ pBi->buffered += size;\r
+ bufferEnd = UDPHS_MblUpdate(pTransfer, pBi, size, 0);\r
+\r
+ /* Write packet in the FIFO buffer */\r
+ pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR\r
+ + (EPT_VIRTUAL_SIZE * bEndpoint));\r
+ if (size) {\r
+ int32_t c8 = size >> 3;\r
+ int32_t c1 = size & 0x7;\r
+ for (; c8; c8 --) {\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+ *(pFifo++) = *(pBytes ++);\r
+ }\r
+ for (; c1; c1 --) {\r
+ *(pFifo++) = *(pBytes ++);\r
+ }\r
+ }\r
+ return bufferEnd;\r
+}\r
+\r
+#if 0\r
+/**\r
+ * Transfers a data payload from an endpoint FIFO to the current transfer\r
+ * buffer, if NULL packet received, the current buffer is ENDed.\r
+ * \param bEndpoint Endpoint number.\r
+ * \param wPacketSize Size of received data packet */\r
+ * \return 1 if the buffer ENDed. */\r
+ */\r
+static uint8_t UDPHS_MblReadFifo(uint8_t bEndpoint, uint16_t wPacketSize)\r
+{\r
+ \r
+ return 0;\r
+}\r
+*/\r
+#endif\r
+/**\r
+ * Transfers a data payload from the current tranfer buffer to the endpoint\r
+ * FIFO\r
+ * \param bEndpoint Number of the endpoint which is sending data.\r
+ */\r
+static void UDPHS_WritePayload(uint8_t bEndpoint, int32_t size)\r
+{\r
+ Endpoint *pEndpoint = &(endpoints[bEndpoint]);\r
+ Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer);\r
+ uint8_t *pFifo;\r
+\r
+ /* Get the number of bytes to send */\r
+ if (size > pTransfer->remaining)\r
+ {\r
+ size = pTransfer->remaining;\r
+ }\r
+\r
+ /* Update transfer descriptor information */\r
+ pTransfer->buffered += size;\r
+ pTransfer->remaining -= size;\r
+\r
+ /* Write packet in the FIFO buffer */\r
+ pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR\r
+ + (EPT_VIRTUAL_SIZE * bEndpoint));\r
+ for (; size; size --)\r
+ {\r
+ *(pFifo ++) = *(pTransfer->pData ++);\r
+ }\r
+}\r
+\r
+/**\r
+ * Transfers a data payload from an endpoint FIFO to the current transfer buffer\r
+ * \param bEndpoint Endpoint number.\r
+ * \param wPacketSize Size of received data packet\r
+ */\r
+static void UDPHS_ReadPayload(uint8_t bEndpoint, int32_t wPacketSize)\r
+{\r
+ Endpoint *pEndpoint = &(endpoints[bEndpoint]);\r
+ Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer);\r
+ uint8_t *pFifo;\r
+ /* Check that the requested size is not bigger than the remaining transfer */\r
+ if (wPacketSize > pTransfer->remaining) {\r
+\r
+ pTransfer->buffered += wPacketSize - pTransfer->remaining;\r
+ wPacketSize = pTransfer->remaining;\r
+ }\r
+\r
+ /* Update transfer descriptor information */\r
+ pTransfer->remaining -= wPacketSize;\r
+ pTransfer->transferred += wPacketSize;\r
+\r
+ /* Retrieve packet */\r
+ pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR\r
+ + (EPT_VIRTUAL_SIZE * bEndpoint));\r
+ while (wPacketSize > 0)\r
+ {\r
+ *(pTransfer->pData ++) = *(pFifo ++);\r
+ wPacketSize--;\r
+ }\r
+}\r
+\r
+/**\r
+ * Received SETUP packet from endpoint 0 FIFO\r
+ * \param pRequest Generic USB SETUP request sent over Control endpoints\r
+ */\r
+static void UDPHS_ReadRequest(USBGenericRequest *pRequest)\r
+{\r
+ uint32_t *pData = (uint32_t *)(void*)pRequest;\r
+ volatile uint32_t *pFifo;\r
+ pFifo = (volatile uint32_t*)UDPHS_RAM_ADDR;\r
+ *pData ++ = *pFifo;\r
+ pFifo = (volatile uint32_t*)UDPHS_RAM_ADDR;\r
+ *pData = *pFifo;\r
+}\r
+\r
+/**\r
+ * Endpoint interrupt handler.\r
+ * Handle IN/OUT transfers, received SETUP packets and STALLing\r
+ * \param bEndpoint Index of endpoint\r
+ */\r
+static void UDPHS_EndpointHandler(uint8_t bEndpoint)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEndpoint];\r
+ //UdphsDma *pDma = &pUdp->UDPHS_DMA[bEndpoint];\r
+\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+ //MblTransfer *pMblt = (MblTransfer*)&(pEp->transfer);\r
+ uint32_t status = pEpt->UDPHS_EPTSTA;\r
+ uint32_t type = pEpt->UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_TYPE_Msk;\r
+ uint32_t reqBuf[2];\r
+ USBGenericRequest *pReq = (USBGenericRequest *)reqBuf;\r
+ uint16_t wPktSize;\r
+\r
+ TRACE_DEBUG_WP("Ep%d ", bEndpoint);\r
+ //TRACE_DEBUG_WP("St:%x ", status);\r
+ /* IN packet sent */\r
+ if ( (pEpt->UDPHS_EPTCTL & UDPHS_EPTCTL_TX_PK_RDY)\r
+ && (0 == (status & UDPHS_EPTSTA_TX_PK_RDY)) )\r
+ {\r
+ TRACE_DEBUG_WP("Wr ");\r
+\r
+ /* Multi-buffer-list transfer state */\r
+ if ( pEp->state == UDPHS_ENDPOINT_SENDINGM )\r
+ {\r
+ }\r
+ /* Sending state */\r
+ else if ( pEp->state == UDPHS_ENDPOINT_SENDING )\r
+ {\r
+ if (pXfr->buffered)\r
+ {\r
+ pXfr->transferred += pXfr->buffered;\r
+ pXfr->buffered = 0;\r
+ }\r
+ if ( pXfr->buffered == 0\r
+ && pXfr->transferred == 0\r
+ && pXfr->remaining == 0\r
+ && pEp->sendZLP == 0 )\r
+ {\r
+ pEp->sendZLP = 1;\r
+ }\r
+\r
+ /* End of Xfr ? */\r
+ if ( pXfr->remaining\r
+ || pEp->sendZLP == 1)\r
+ {\r
+ pEp->sendZLP = 2;\r
+\r
+ /* Transfer remaining */\r
+ TRACE_DEBUG_WP("%d ", pEp->size);\r
+ /* Send next packet */\r
+ UDPHS_WritePayload(bEndpoint, pEp->size);\r
+ pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY;\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG_WP("l%d ", pXfr->transferred);\r
+ /* Disable interrupt on none-control EP */\r
+ if (type != UDPHS_EPTCFG_EPT_TYPE_CTRL8)\r
+ {\r
+ pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint);\r
+ }\r
+ pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_TX_PK_RDY;\r
+\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);\r
+ pEp->sendZLP = 0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG("Err Wr %d\n\r", pEp->sendZLP);\r
+ }\r
+ }\r
+ /* OUT packet received */\r
+ if ( UDPHS_EPTSTA_RX_BK_RDY & status )\r
+ {\r
+ TRACE_DEBUG_WP("Rd ");\r
+\r
+ /* NOT in receiving state */\r
+ if (pEp->state != UDPHS_ENDPOINT_RECEIVING)\r
+ {\r
+ /* Check if ACK received on a Control EP */\r
+ if ( (UDPHS_EPTCFG_EPT_TYPE_CTRL8 == type)\r
+ && (0 == (status & UDPHS_EPTSTA_BYTE_COUNT_Msk)) )\r
+ {\r
+ TRACE_DEBUG_WP("Ack ");\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY;\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);\r
+ }\r
+ /* data has been STALLed */\r
+ else if (UDPHS_EPTSTA_FRCESTALL & status)\r
+ {\r
+ TRACE_DEBUG_WP("Discard ");\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY;\r
+ }\r
+ /* NAK the data */\r
+ else\r
+ {\r
+ TRACE_DEBUG_WP("Nak ");\r
+ pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint);\r
+ }\r
+ }\r
+ /* In read state */\r
+ else\r
+ {\r
+ wPktSize = (uint16_t)((status & UDPHS_EPTSTA_BYTE_COUNT_Msk) >> UDPHS_EPTSTA_BYTE_COUNT_Pos);\r
+\r
+ TRACE_DEBUG_WP("%d ", wPktSize);\r
+ UDPHS_ReadPayload(bEndpoint, wPktSize);\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY;\r
+ /* Check if transfer is finished */\r
+ if (pXfr->remaining == 0 || wPktSize < pEp->size)\r
+ {\r
+ pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_RX_BK_RDY;\r
+\r
+ /* Disable interrupt if not control EP */\r
+ if (UDPHS_EPTCFG_EPT_TYPE_CTRL8 != type)\r
+ {\r
+ pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint);\r
+ }\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);\r
+ }\r
+ }\r
+ }\r
+ /* STALL sent */\r
+ if ( UDPHS_EPTSTA_STALL_SNT & status )\r
+ {\r
+ /* Acknowledge */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_STALL_SNT;\r
+\r
+ /* ISO error */\r
+ if (type == UDPHS_EPTCFG_EPT_TYPE_ISO)\r
+ {\r
+ TRACE_WARNING("IsoE[%d]\n\r", bEndpoint);\r
+\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED);\r
+ }\r
+ /* If EP is not halted, clear STALL */\r
+ else\r
+ {\r
+ TRACE_WARNING("Stall[%d]\n\r", bEndpoint);\r
+\r
+ if (pEp->state != UDPHS_ENDPOINT_HALTED)\r
+ {\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_FRCESTALL;\r
+ }\r
+ }\r
+ }\r
+ /* SETUP packet received */\r
+ if ( UDPHS_EPTSTA_RX_SETUP & status )\r
+ {\r
+ /* If a transfer was pending, complete it\r
+ Handles the case where during the status phase of a control write\r
+ transfer, the host receives the device ZLP and ack it, but the ack\r
+ is not received by the device */\r
+ if (pEp->state == UDPHS_ENDPOINT_RECEIVING\r
+ || pEp->state == UDPHS_ENDPOINT_RECEIVINGM\r
+ || pEp->state == UDPHS_ENDPOINT_SENDING\r
+ || pEp->state == UDPHS_ENDPOINT_SENDINGM)\r
+ {\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS);\r
+ }\r
+\r
+ /* ISO Err Flow */\r
+ if (type == UDPHS_EPTCFG_EPT_TYPE_ISO)\r
+ {\r
+ TRACE_WARNING("IsoFE[%d]\n\r", bEndpoint);\r
+ /* Acknowledge setup packet */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_SETUP;\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG_WP("Stup ");\r
+ \r
+ /* Copy setup */\r
+ UDPHS_ReadRequest(pReq);\r
+ /* Acknowledge setup packet */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_SETUP;\r
+ /* Handler */\r
+ USBD_RequestHandler(bEndpoint, pReq);\r
+ }\r
+ }\r
+}\r
+#ifdef DMA\r
+/**\r
+ * DMA Single transfer\r
+ * \param bEndpoint EP number.\r
+ * \pXfr Pointer to transfer instance.\r
+ * \dwCfg DMA Control configuration (excluding length).\r
+ */\r
+static inline void UDPHS_DmaSingle(uint8_t bEndpoint, Transfer *pXfr, uint32_t dwCfg)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ /* Single transfer */\r
+ CP15_coherent_dcache_for_dma ((uint32_t)&pXfr->pData[pXfr->transferred], ((uint32_t)&pXfr->pData[pXfr->transferred]) + pXfr->buffered);\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS =\r
+ (uint32_t)&pXfr->pData[pXfr->transferred];\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;\r
+ /* Interrupt enable */\r
+ pUdp->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint);\r
+ \r
+ TRACE_DEBUG_WP("Dma[B%d:T%d] ", pXfr->buffered, pXfr->transferred);\r
+ /* DMA Configure */\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0;\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(pXfr->buffered)\r
+ | dwCfg;\r
+}\r
+/**\r
+ * Endpoint DMA interrupt handler.\r
+ * This function handles DMA interrupts.\r
+ * \param bEndpoint Index of endpoint\r
+ */\r
+static void UDPHS_DmaHandler(uint8_t bEndpoint)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ //UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint];\r
+\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+\r
+ uint32_t dwDmaSr;\r
+ int32_t iRemain, iXfred;\r
+ uint8_t bRc = USBD_STATUS_SUCCESS;\r
+\r
+ CP15_flush_dcache_for_dma ((uint32_t)&pXfr->pData[pXfr->transferred], ((uint32_t)&pXfr->pData[pXfr->transferred]) + pXfr->buffered);\r
+ dwDmaSr = pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;\r
+ TRACE_DEBUG_WP("iDma%d,%x ", bEndpoint, dwDmaSr);\r
+ /* Mbl transfer */\r
+ if (pEp->state == UDPHS_ENDPOINT_SENDINGM)\r
+ {\r
+ /* Not implemented */\r
+ return;\r
+ }\r
+ else if (pEp->state == UDPHS_ENDPOINT_RECEIVINGM)\r
+ {\r
+ /* Not implemented */\r
+ return;\r
+ }\r
+\r
+ /* Disable DMA interrupt to avoid receiving 2 (B_EN and TR_EN) */\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL &= ~(UDPHS_DMACONTROL_END_TR_EN\r
+ |UDPHS_DMACONTROL_END_B_EN);\r
+ if (UDPHS_DMASTATUS_END_BF_ST & dwDmaSr)\r
+ {\r
+ TRACE_DEBUG_WP("EoDmaB ");\r
+ /* BUFF_COUNT holds the number of untransmitted bytes.\r
+ BUFF_COUNT is equal to zero in case of good transfer */\r
+ iRemain = (dwDmaSr & UDPHS_DMASTATUS_BUFF_COUNT_Msk)\r
+ >> UDPHS_DMASTATUS_BUFF_COUNT_Pos;\r
+ TRACE_DEBUG_WP("C%d ", iRemain);\r
+ iXfred = pXfr->buffered - iRemain;\r
+\r
+ pXfr->transferred += iXfred;\r
+ pXfr->buffered = iRemain;\r
+ pXfr->remaining -= iXfred;\r
+ TRACE_DEBUG_WP("[B%d:T%d:R%d] ", pXfr->buffered, pXfr->transferred, pXfr->remaining);\r
+ /* There is still data */\r
+ if (pXfr->remaining + pXfr->buffered > 0)\r
+ { \r
+ if (pXfr->remaining > DMA_MAX_FIFO_SIZE)\r
+ {\r
+ pXfr->buffered = DMA_MAX_FIFO_SIZE;\r
+ }\r
+ else\r
+ {\r
+ pXfr->buffered = pXfr->remaining;\r
+ }\r
+ /* Single transfer again */\r
+ UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_TR_EN\r
+ | UDPHS_DMACONTROL_END_TR_IT\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT\r
+ | UDPHS_DMACONTROL_CHANN_ENB);\r
+ }\r
+ }\r
+ else if (UDPHS_DMASTATUS_END_TR_ST & dwDmaSr)\r
+ {\r
+ TRACE_DEBUG_WP("EoDmaT ");\r
+ pXfr->transferred = pXfr->buffered -\r
+ ((dwDmaSr & UDPHS_DMASTATUS_BUFF_COUNT_Msk)\r
+ >> UDPHS_DMASTATUS_BUFF_COUNT_Pos);\r
+ pXfr->remaining = 0;\r
+\r
+ TRACE_DEBUG_WP("[B%d:T%d] ", pXfr->buffered, pXfr->transferred);\r
+ }\r
+ else\r
+ {\r
+ TRACE_ERROR("UDPHS_DmaHandler: ST 0x%X\n\r", (unsigned int)dwDmaSr);\r
+ bRc = USBD_STATUS_ABORTED;\r
+ }\r
+ /* Callback */\r
+ if (pXfr->remaining == 0)\r
+ {\r
+ UDPHS_EndOfTransfer(bEndpoint, bRc);\r
+ \r
+ }\r
+ \r
+}\r
+#endif\r
+/**\r
+ * Sends data through a USB endpoint. Sets up the transfer descriptor,\r
+ * writes one or two data payloads (depending on the number of FIFO bank\r
+ * for the endpoint) and then starts the actual transfer. The operation is\r
+ * complete when all the data has been sent.\r
+ *\r
+ * *If the size of the buffer is greater than the size of the endpoint\r
+ * (or twice the size if the endpoint has two FIFO banks), then the buffer\r
+ * must be kept allocated until the transfer is finished*. This means that\r
+ * it is not possible to declare it on the stack (i.e. as a local variable\r
+ * of a function which returns after starting a transfer).\r
+ *\r
+ * \param pEndpoint Pointer to Endpoint struct.\r
+ * \param pData Pointer to a buffer with the data to send.\r
+ * \param dLength Size of the data buffer.\r
+ * \return USBD_STATUS_SUCCESS if the transfer has been started;\r
+ * otherwise, the corresponding error status code.\r
+ */\r
+static inline uint8_t UDPHS_Write(uint8_t bEndpoint,\r
+ const void *pData,\r
+ uint32_t dLength)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint];\r
+ \r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+ /* Return if busy */\r
+ if (pEp->state != UDPHS_ENDPOINT_IDLE)\r
+ {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ /* Sending state */\r
+ pEp->state = UDPHS_ENDPOINT_SENDING;\r
+ TRACE_DEBUG_WP("Wr%d(%d) ", bEndpoint, dLength);\r
+ pEp->sendZLP = 0;\r
+ /* Setup transfer descriptor */\r
+ pXfr->pData = (void*) pData;\r
+ pXfr->remaining = dLength;\r
+ pXfr->buffered = 0;\r
+ pXfr->transferred = 0;\r
+ #ifdef DMA\r
+ /* 1. DMA supported, 2. Not ZLP */\r
+ if (CHIP_USB_ENDPOINTS_DMA(bEndpoint)\r
+ && pXfr->remaining > 0)\r
+ {\r
+ if (pXfr->remaining > DMA_MAX_FIFO_SIZE)\r
+ {\r
+ /* Transfer the max */\r
+ pXfr->buffered = DMA_MAX_FIFO_SIZE;\r
+ }\r
+ else\r
+ {\r
+ /* Good size */\r
+ pXfr->buffered = pXfr->remaining;\r
+ }\r
+ /* Single transfer */\r
+ UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT\r
+ | UDPHS_DMACONTROL_CHANN_ENB);\r
+ return USBD_STATUS_SUCCESS;\r
+ }\r
+ #endif\r
+\r
+ /* Enable IT */\r
+ pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint );\r
+ pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY;\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Sends data through a USB endpoint. Sets up the transfer descriptor list,\r
+ * writes one or two data payloads (depending on the number of FIFO bank\r
+ * for the endpoint) and then starts the actual transfer. The operation is\r
+ * complete when all the transfer buffer in the list has been sent.\r
+ *\r
+ * *If the size of the buffer is greater than the size of the endpoint\r
+ * (or twice the size if the endpoint has two FIFO banks), then the buffer\r
+ * must be kept allocated until the transfer is finished*. This means that\r
+ * it is not possible to declare it on the stack (i.e. as a local variable\r
+ * of a function which returns after starting a transfer).\r
+ *\r
+ * \param pEndpoint Pointer to Endpoint struct.\r
+ * \param pData Pointer to a buffer with the data to send.\r
+ * \param dLength Size of the data buffer.\r
+ * \return USBD_STATUS_SUCCESS if the transfer has been started;\r
+ * otherwise, the corresponding error status code.\r
+ */\r
+static inline uint8_t UDPHS_AddWr(uint8_t bEndpoint,\r
+ const void *pData,\r
+ uint32_t dLength)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint];\r
+\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ MblTransfer *pMbl = (MblTransfer*)&(pEp->transfer);\r
+ USBDTransferBuffer *pTx;\r
+ /* Check parameter */\r
+ if (dLength >= 0x10000)\r
+ {\r
+ return USBD_STATUS_INVALID_PARAMETER;\r
+ }\r
+ /* Data in process */\r
+ if (pEp->state > UDPHS_ENDPOINT_IDLE)\r
+ { /* MBL transfer */\r
+ if (pMbl->transType)\r
+ {\r
+ if (pMbl->listState == MBL_FULL)\r
+ {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ }\r
+\r
+ TRACE_DEBUG_WP("AddW%d(%d) ", bEndpoint, dLength);\r
+ /* Add buffer to buffer list and update index */\r
+ pTx = &(pMbl->pMbl[pMbl->inCurr]);\r
+ pTx->pBuffer = (uint8_t*)pData;\r
+ pTx->size = pTx->remaining = dLength;\r
+ pTx->transferred = pTx->buffered = 0;\r
+ /* Update input index */\r
+ if (pMbl->inCurr >= (pMbl->listSize-1)) pMbl->inCurr = 0;\r
+ else pMbl->inCurr ++;\r
+ if (pMbl->inCurr == pMbl->outCurr) pMbl->listState = MBL_FULL;\r
+ else pMbl->listState = 0;\r
+ /* Start sending when offset achieved */\r
+ if (MBL_NbBuffer(pMbl->inCurr, pMbl->outCurr, pMbl->listSize)\r
+ >= pMbl->offsetSize\r
+ && pEp->state == UDPHS_ENDPOINT_IDLE)\r
+ {\r
+ uint8_t nbBanks = CHIP_USB_ENDPOINTS_BANKS(bEndpoint);\r
+\r
+ /* Change state */\r
+ pEp->state = UDPHS_ENDPOINT_SENDINGM;\r
+\r
+ TRACE_DEBUG_WP("StartM ");\r
+\r
+ /* Fill data into FIFO */\r
+ for (;\r
+ nbBanks && pMbl->pMbl[pMbl->inCurr].remaining;\r
+ nbBanks --)\r
+ {\r
+ UDPHS_MblWriteFifo(bEndpoint);\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY;\r
+ }\r
+\r
+ /* Enable interrupt */\r
+ pUdp->UDPHS_IEN |= (UDPHS_IEN_EPT_0 << bEndpoint);\r
+ pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY;\r
+\r
+ }\r
+\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Reads incoming data on an USB endpoint This methods sets the transfer\r
+ * descriptor and activate the endpoint interrupt. The actual transfer is\r
+ * then carried out by the endpoint interrupt handler. The Read operation\r
+ * finishes either when the buffer is full, or a short packet (inferior to\r
+ * endpoint maximum size) is received.\r
+ *\r
+ * *The buffer must be kept allocated until the transfer is finished*.\r
+ * \param bEndpoint Endpoint number.\r
+ * \param pData Pointer to a data buffer.\r
+ * \param dLength Size of the data buffer in bytes.\r
+ * \return USBD_STATUS_SUCCESS if the read operation has been started;\r
+ * otherwise, the corresponding error code.\r
+ */\r
+static inline uint8_t UDPHS_Read(uint8_t bEndpoint,\r
+ void *pData,\r
+ uint32_t dLength)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint];\r
+\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+ /* Return if busy */\r
+ if (pEp->state != UDPHS_ENDPOINT_IDLE)\r
+ {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ /* Receiving state */\r
+ pEp->state = UDPHS_ENDPOINT_RECEIVING;\r
+\r
+ TRACE_DEBUG_WP("Rd%d(%d) ", bEndpoint, dLength);\r
+ /* Setup transfer descriptor */\r
+ pXfr->pData = (void*) pData;\r
+ pXfr->remaining = dLength;\r
+ pXfr->buffered = 0;\r
+ pXfr->transferred = 0;\r
+\r
+ #ifdef DMA\r
+ /* If: 1. DMA supported, 2. Has data */\r
+ if (CHIP_USB_ENDPOINTS_DMA(bEndpoint)\r
+ && pXfr->remaining > 0)\r
+ {\r
+ /* DMA XFR size adjust */\r
+ if (pXfr->remaining > DMA_MAX_FIFO_SIZE)\r
+ pXfr->buffered = DMA_MAX_FIFO_SIZE;\r
+ else\r
+ pXfr->buffered = pXfr->remaining;\r
+ /* Single transfer */\r
+ UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_TR_EN\r
+ | UDPHS_DMACONTROL_END_TR_IT\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT\r
+ | UDPHS_DMACONTROL_CHANN_ENB);\r
+ return USBD_STATUS_SUCCESS;\r
+ }\r
+ #endif\r
+\r
+ /* Enable IT */\r
+ pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint );\r
+ pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY;\r
+ \r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+#if 0\r
+/**\r
+ * Reads incoming data on an USB endpoint This methods sets the transfer\r
+ * descriptor and activate the endpoint interrupt. The actual transfer is\r
+ * then carried out by the endpoint interrupt handler. The Read operation\r
+ * finishes either when the buffer is full, or a short packet (inferior to\r
+ * endpoint maximum size) is received.\r
+ *\r
+ * *The buffer must be kept allocated until the transfer is finished*.\r
+ * \param bEndpoint Endpoint number.\r
+ * \param pData Pointer to a data buffer.\r
+ * \param dLength Size of the data buffer in bytes.\r
+ * \return USBD_STATUS_SUCCESS if the read operation has been started;\r
+ * otherwise, the corresponding error code.\r
+ */\r
+static inline uint8_t UDPHS_AddRd(uint8_t bEndpoint,\r
+ void *pData,\r
+ uint32_t dLength)\r
+{\r
+ return USBD_STATUS_SW_NOT_SUPPORTED;\r
+}\r
+#endif\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+extern void USBD_IrqHandler(void);\r
+/**\r
+ * USBD (UDP) interrupt handler\r
+ * Manages device resume, suspend, end of bus reset.\r
+ * Forwards endpoint events to the appropriate handler.\r
+ */\r
+void USBD_IrqHandler(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ uint32_t status;\r
+ uint8_t numIt;\r
+\r
+ status = pUdp->UDPHS_INTSTA;\r
+ status &= pUdp->UDPHS_IEN;\r
+\r
+ /* Handle all UDPHS interrupts */\r
+ TRACE_DEBUG_WP("\n\r%c ", USBD_HAL_IsHighSpeed() ? 'H' : 'F');\r
+ while( status )\r
+ {\r
+ /* SOF */\r
+ if (status & UDPHS_INTSTA_INT_SOF)\r
+ {\r
+ TRACE_DEBUG_WP("SOF ");\r
+ /* SOF handler */\r
+ //USBD_SofHandler();\r
+\r
+ /* Acknowledge interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;\r
+ status &= ~(uint32_t)UDPHS_INTSTA_INT_SOF;\r
+ }\r
+ /* Suspend, treated last */\r
+ else if (status == UDPHS_INTSTA_DET_SUSPD)\r
+ {\r
+ TRACE_WARNING_WP("Susp ");\r
+ /* Enable wakeup */\r
+ pUdp->UDPHS_IEN |= (UDPHS_IEN_WAKE_UP | UDPHS_IEN_ENDOFRSM);\r
+ pUdp->UDPHS_IEN &= ~(uint32_t)UDPHS_IEN_DET_SUSPD;\r
+\r
+ /* Acknowledge interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD | UDPHS_CLRINT_WAKE_UP;\r
+\r
+ USBD_SuspendHandler();\r
+ }\r
+ /* Resume */\r
+ else if ( (status & UDPHS_INTSTA_WAKE_UP)\r
+ || (status & UDPHS_INTSTA_ENDOFRSM) )\r
+ {\r
+ USBD_ResumeHandler();\r
+\r
+ TRACE_INFO_WP("Rsm ");\r
+\r
+ /* Acknowledge interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP\r
+ | UDPHS_CLRINT_ENDOFRSM\r
+ | UDPHS_CLRINT_DET_SUSPD;\r
+\r
+ pUdp->UDPHS_IEN |= UDPHS_IEN_ENDOFRSM | UDPHS_IEN_DET_SUSPD;\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM;\r
+ pUdp->UDPHS_IEN &= ~(uint32_t)UDPHS_IEN_WAKE_UP;\r
+ }\r
+ /* Bus reset */\r
+ else if (status & UDPHS_INTSTA_ENDRESET)\r
+ {\r
+ TRACE_DEBUG_WP("EoB ");\r
+ /* Flush and enable the suspend interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_DET_SUSPD;\r
+ pUdp->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD;\r
+\r
+ /* Reset handler */\r
+ USBD_ResetHandler();\r
+\r
+ /* Acknowledge interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;\r
+ }\r
+ /* Upstream resume */\r
+ else if (status & UDPHS_INTSTA_UPSTR_RES)\r
+ {\r
+ TRACE_DEBUG_WP("ExtRes ");\r
+ /* Acknowledge interrupt */\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES;\r
+ }\r
+ /* Endpoints */\r
+ else\r
+ {\r
+ #ifdef DMA\r
+ for (numIt = 0; numIt < NUM_IT_MAX; numIt ++)\r
+ {\r
+ if (status & (1 << SHIFT_DMA << numIt))\r
+ {\r
+ UDPHS_DmaHandler(numIt);\r
+ }\r
+ else if (status & (UDPHS_INTSTA_EPT_0 << numIt))\r
+ {\r
+ UDPHS_EndpointHandler(numIt);\r
+ }\r
+ }\r
+ #else\r
+ for (numIt = 0; numIt < NUM_IT_MAX; numIt ++)\r
+ {\r
+ if (status & (UDPHS_INTSTA_EPT_0 << numIt))\r
+ {\r
+ UDPHS_EndpointHandler(numIt);\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+\r
+ /* Update interrupt status */\r
+ status = pUdp->UDPHS_INTSTA;\r
+ status &= pUdp->UDPHS_IEN;\r
+\r
+ TRACE_DEBUG_WP("\n\r");\r
+ if (status)\r
+ {\r
+ TRACE_DEBUG_WP(" - ");\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reset endpoints and disable them.\r
+ * -# Terminate transfer if there is any, with given status;\r
+ * -# Reset the endpoint & disable it.\r
+ * \param bmEPs Bitmap for endpoints to reset.\r
+ * \param bStatus Status passed to terminate transfer on endpoint.\r
+ * \param bKeepCfg 1 to keep old endpoint configuration.\r
+ * \note Use USBD_HAL_ConfigureEP() to configure and enable endpoint\r
+ if not keeping old configuration.\r
+ * \sa USBD_HAL_ConfigureEP().\r
+ */\r
+void USBD_HAL_ResetEPs(uint32_t bmEPs, uint8_t bStatus, uint8_t bKeepCfg)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pHwEp;\r
+\r
+ Endpoint *pEndpoint;\r
+ uint32_t tmp = bmEPs & ((1<<CHIP_USB_NUMENDPOINTS)-1);\r
+ uint8_t ep;\r
+ uint32_t epBit, epCfg;\r
+\r
+ for (ep = 0, epBit = 1; ep < CHIP_USB_NUMENDPOINTS; ep ++)\r
+ {\r
+ if (tmp & epBit)\r
+ {\r
+ pHwEp = &pUdp->UDPHS_EPT[ep];\r
+\r
+ /* Disable ISR */\r
+ pUdp->UDPHS_IEN &= ~(epBit << SHIFT_INTERUPT);\r
+ /* Kill pending Banks ?? */\r
+ #if 0\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ #endif\r
+ \r
+ /* Reset transfer information */\r
+ pEndpoint = &(endpoints[ep]);\r
+ /* Reset endpoint state */\r
+ pEndpoint->bank = 0;\r
+ /* Endpoint configure */\r
+ epCfg = pHwEp->UDPHS_EPTCFG;\r
+ /* Reset endpoint */\r
+ pUdp->UDPHS_EPTRST = epBit;\r
+ /* Restore configure */\r
+ if (bKeepCfg)\r
+ {\r
+ pHwEp->UDPHS_EPTCFG = epCfg;\r
+ }\r
+ else\r
+ {\r
+ pEndpoint->state = UDPHS_ENDPOINT_DISABLED;\r
+ }\r
+\r
+ /* Terminate transfer on this EP */\r
+ UDPHS_EndOfTransfer(ep, bStatus);\r
+ }\r
+ epBit <<= 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * Cancel pending READ/WRITE\r
+ * \param bmEPs Bitmap for endpoints to reset.\r
+ * \note EP callback is invoked with USBD_STATUS_CANCELED.\r
+ */\r
+void USBD_HAL_CancelIo(uint32_t bmEPs)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ //UdphsEpt *pHwEp = NULL;\r
+\r
+ uint32_t tmp = bmEPs & ((1<<CHIP_USB_NUMENDPOINTS)-1);\r
+ uint8_t ep;\r
+ uint32_t epBit;\r
+ for (ep = 0, epBit = 1; ep < CHIP_USB_NUMENDPOINTS; ep ++)\r
+ {\r
+ if (tmp & epBit)\r
+ {\r
+ //pHwEp = &pUdp->UDPHS_EPT[ep];\r
+\r
+ /* Disable ISR */\r
+ pUdp->UDPHS_IEN &= ~(epBit << SHIFT_INTERUPT);\r
+ /* Kill pending Banks ?? */\r
+ #if 0\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK;\r
+ #endif\r
+\r
+ /* Terminate transfer on this EP */\r
+ UDPHS_EndOfTransfer(ep, USBD_STATUS_CANCELED);\r
+ }\r
+ epBit <<= 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * Configures an endpoint according to its endpoint Descriptor.\r
+ * \param pDescriptor Pointer to an endpoint descriptor.\r
+ * \return The endpoint address.\r
+ */\r
+uint8_t USBD_HAL_ConfigureEP(const USBEndpointDescriptor *pDescriptor)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pEpt;\r
+ //UdphsDma *pDma;\r
+\r
+ Endpoint *pEndpoint;\r
+ uint8_t bEndpoint;\r
+ uint8_t bType;\r
+ uint8_t bEndpointDir;\r
+ //uint8_t bInterval = 0;\r
+ uint8_t bNbTrans = 1;\r
+ uint8_t bSizeEpt = 0;\r
+ uint8_t bHs = ((pUdp->UDPHS_INTSTA & UDPHS_INTSTA_SPEED) > 0);\r
+\r
+ /* NULL descriptor -> Control endpoint 0 */\r
+ if (pDescriptor == 0)\r
+ {\r
+\r
+ bEndpoint = 0;\r
+ pEndpoint = &(endpoints[bEndpoint]);\r
+ pEpt = &(pUdp->UDPHS_EPT[0]);\r
+ bType = USBEndpointDescriptor_CONTROL;\r
+ bEndpointDir = 0;\r
+ pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0);\r
+ pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0);\r
+ }\r
+ /* Device descriptor -> Control endpoint 0 */\r
+ else if (pDescriptor->bDescriptorType == USBGenericDescriptor_DEVICE)\r
+ {\r
+ USBDeviceDescriptor *pDevDesc = (USBDeviceDescriptor*)pDescriptor;\r
+ bEndpoint = 0;\r
+ pEndpoint = &(endpoints[bEndpoint]);\r
+ pEpt = &(pUdp->UDPHS_EPT[0]);\r
+ bType = USBEndpointDescriptor_CONTROL;\r
+ bEndpointDir = 0;\r
+ pEndpoint->size =pDevDesc->bMaxPacketSize0;\r
+ pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0);\r
+ }\r
+ /* Endpoint descriptor */\r
+ else\r
+ {\r
+ /* The endpoint number */\r
+ bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor);\r
+ pEndpoint = &(endpoints[bEndpoint]);\r
+ pEpt = &(pUdp->UDPHS_EPT[bEndpoint]);\r
+ /* Transfer type: Control, Isochronous, Bulk, Interrupt */\r
+ bType = USBEndpointDescriptor_GetType(pDescriptor);\r
+ /* interval */\r
+ //bInterval = USBEndpointDescriptor_GetInterval(pDescriptor);\r
+ /* Direction, ignored for control endpoints */\r
+ bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor);\r
+ pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor);\r
+ pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(bEndpoint);\r
+\r
+ /* Convert descriptor value to EP configuration */\r
+ if (bHs) { /* HS Interval, *125us */\r
+\r
+ /* MPS: Bit12,11 specify NB_TRANS, as USB 2.0 Spec. */\r
+ bNbTrans = ((pEndpoint->size >> 11) & 0x3);\r
+ if (bNbTrans == 3)\r
+ bNbTrans = 1;\r
+ else\r
+ bNbTrans ++;\r
+\r
+ /* Mask, bit 10..0 is the size */\r
+ pEndpoint->size &= 0x7FF;\r
+ }\r
+ }\r
+\r
+ //TRACE_DEBUG_WP("CfgE%d ", bEndpoint);\r
+\r
+ /* Abort the current transfer is the endpoint was configured and in\r
+ Write or Read state */\r
+ if( (pEndpoint->state == UDPHS_ENDPOINT_RECEIVING)\r
+ || (pEndpoint->state == UDPHS_ENDPOINT_SENDING)\r
+ || (pEndpoint->state == UDPHS_ENDPOINT_RECEIVINGM)\r
+ || (pEndpoint->state == UDPHS_ENDPOINT_SENDINGM) ) {\r
+\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET);\r
+ }\r
+ pEndpoint->state = UDPHS_ENDPOINT_IDLE;\r
+\r
+ /* Disable endpoint */\r
+ pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_SHRT_PCKT\r
+ | UDPHS_EPTCTLDIS_BUSY_BANK\r
+ | UDPHS_EPTCTLDIS_NAK_OUT\r
+ | UDPHS_EPTCTLDIS_NAK_IN\r
+ | UDPHS_EPTCTLDIS_STALL_SNT\r
+ | UDPHS_EPTCTLDIS_RX_SETUP\r
+ | UDPHS_EPTCTLDIS_TX_PK_RDY\r
+ | UDPHS_EPTCTLDIS_RX_BK_RDY\r
+ | UDPHS_EPTCTLDIS_ERR_OVFLW\r
+ | UDPHS_EPTCTLDIS_MDATA_RX\r
+ | UDPHS_EPTCTLDIS_DATAX_RX\r
+ | UDPHS_EPTCTLDIS_NYET_DIS\r
+ | UDPHS_EPTCTLDIS_INTDIS_DMA\r
+ | UDPHS_EPTCTLDIS_AUTO_VALID\r
+ | UDPHS_EPTCTLDIS_EPT_DISABL\r
+ ;\r
+ /* Reset Endpoint Fifos */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL;\r
+ pUdp->UDPHS_EPTRST = 1 << bEndpoint;\r
+ /* Configure endpoint size */\r
+ if( pEndpoint->size <= 8 )\r
+ bSizeEpt = 0;\r
+ else if ( pEndpoint->size <= 16 )\r
+ bSizeEpt = 1;\r
+ else if ( pEndpoint->size <= 32 )\r
+ bSizeEpt = 2;\r
+ else if ( pEndpoint->size <= 64 )\r
+ bSizeEpt = 3;\r
+ else if ( pEndpoint->size <= 128 )\r
+ bSizeEpt = 4;\r
+ else if ( pEndpoint->size <= 256 )\r
+ bSizeEpt = 5;\r
+ else if ( pEndpoint->size <= 512 )\r
+ bSizeEpt = 6;\r
+ else if ( pEndpoint->size <= 1024 )\r
+ bSizeEpt = 7;\r
+\r
+ /* Configure endpoint */\r
+ if (bType == USBEndpointDescriptor_CONTROL)\r
+ {\r
+ pUdp->UDPHS_IEN |= (UDPHS_IEN_EPT_0 << bEndpoint);\r
+ }\r
+\r
+ pEpt->UDPHS_EPTCFG = bSizeEpt \r
+ | ( bEndpointDir << 3) \r
+ | ( bType << 4) \r
+ | ((pEndpoint->bank) << 6)\r
+ | ( bNbTrans << 8)\r
+ ;\r
+ while( (UDPHS_EPTCFG_EPT_MAPD & pEpt->UDPHS_EPTCFG) == 0 ) {\r
+\r
+ /* resolved by clearing the reset IT in good place */\r
+ TRACE_ERROR("PB bEndpoint: 0x%X\n\r", bEndpoint);\r
+ TRACE_ERROR("PB bSizeEpt: 0x%X\n\r", bSizeEpt);\r
+ TRACE_ERROR("PB bEndpointDir: 0x%X\n\r", bEndpointDir);\r
+ TRACE_ERROR("PB bType: 0x%X\n\r", bType);\r
+ TRACE_ERROR("PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank);\r
+ TRACE_ERROR("PB UDPHS_EPTCFG: 0x%X\n\r", (unsigned int)pEpt->UDPHS_EPTCFG);\r
+ for(;;);\r
+ }\r
+\r
+ if (bType == USBEndpointDescriptor_CONTROL)\r
+ {\r
+ pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY \r
+ | UDPHS_EPTCTLENB_RX_SETUP\r
+ | UDPHS_EPTCTLENB_EPT_ENABL;\r
+ }\r
+ else\r
+ {\r
+#ifndef DMA\r
+ pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL;\r
+#else\r
+ pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_AUTO_VALID | UDPHS_EPTCTLENB_EPT_ENABL;\r
+#endif\r
+ }\r
+\r
+ //TRACE_DEBUG_WP("<%x,%x,%x> ", pEpt->UDPHS_EPTCFG, pEpt->UDPHS_EPTCTL, pEpt->UDPHS_EPTSTA);\r
+ return bEndpoint;\r
+}\r
+\r
+/**\r
+ * Set callback for a USB endpoint for transfer (read/write).\r
+ *\r
+ * \param bEP Endpoint number.\r
+ * \param fCallback Optional callback function to invoke when the transfer is\r
+ * complete.\r
+ * \param pCbData Optional pointer to data to the callback function.\r
+ * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED if endpoint is busy.\r
+ */\r
+uint8_t USBD_HAL_SetTransferCallback(uint8_t bEP,\r
+ TransferCallback fCallback,\r
+ void *pCbData)\r
+{\r
+ Endpoint *pEndpoint = &(endpoints[bEP]);\r
+ TransferHeader *pTransfer = (TransferHeader*)&(pEndpoint->transfer);\r
+ /* Check that the endpoint is not transferring */\r
+ if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ TRACE_DEBUG_WP("sXfrCb ");\r
+ /* Setup the transfer callback and extension data */\r
+ pTransfer->fCallback = (void*)fCallback;\r
+ pTransfer->pArgument = pCbData;\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Configure an endpoint to use multi-buffer-list transfer mode.\r
+ * The buffers can be added by _Read/_Write function.\r
+ * \param pMbList Pointer to a multi-buffer list used, NULL to disable MBL.\r
+ * \param mblSize Multi-buffer list size (number of buffers can be queued)\r
+ * \param startOffset When number of buffer achieve this offset transfer start\r
+ */\r
+uint8_t USBD_HAL_SetupMblTransfer( uint8_t bEndpoint,\r
+ USBDTransferBuffer* pMbList,\r
+ uint16_t mblSize,\r
+ uint16_t startOffset)\r
+{\r
+ Endpoint *pEndpoint = &(endpoints[bEndpoint]);\r
+ MblTransfer *pXfr = (MblTransfer*)&(pEndpoint->transfer);\r
+ uint16_t i;\r
+ /* Check that the endpoint is not transferring */\r
+ if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ TRACE_DEBUG_WP("sMblXfr ");\r
+ /* Enable Multi-Buffer Transfer List */\r
+ if (pMbList) {\r
+ /* Reset list items */\r
+ for (i = 0; i < mblSize; i --) {\r
+ pMbList[i].pBuffer = NULL;\r
+ pMbList[i].size = 0;\r
+ pMbList[i].transferred = 0;\r
+ pMbList[i].buffered = 0;\r
+ pMbList[i].remaining = 0;\r
+ }\r
+ /* Setup transfer */\r
+ pXfr->transType = 1;\r
+ pXfr->listState = 0; /* OK */\r
+ pXfr->listSize = mblSize;\r
+ pXfr->pMbl = pMbList;\r
+ pXfr->outCurr = pXfr->outLast = 0;\r
+ pXfr->inCurr = 0;\r
+ pXfr->offsetSize = startOffset;\r
+ }\r
+ /* Disable Multi-Buffer Transfer */\r
+ else {\r
+ pXfr->transType = 0;\r
+ pXfr->pMbl = NULL;\r
+ pXfr->listSize = 0;\r
+ pXfr->offsetSize = 1;\r
+ }\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Sends data through a USB endpoint. Sets up the transfer descriptor,\r
+ * writes one or two data payloads (depending on the number of FIFO bank\r
+ * for the endpoint) and then starts the actual transfer. The operation is\r
+ * complete when all the data has been sent.\r
+ *\r
+ * *If the size of the buffer is greater than the size of the endpoint\r
+ * (or twice the size if the endpoint has two FIFO banks), then the buffer\r
+ * must be kept allocated until the transfer is finished*. This means that\r
+ * it is not possible to declare it on the stack (i.e. as a local variable\r
+ * of a function which returns after starting a transfer).\r
+ *\r
+ * \param bEndpoint Endpoint number.\r
+ * \param pData Pointer to a buffer with the data to send.\r
+ * \param dLength Size of the data buffer.\r
+ * \return USBD_STATUS_SUCCESS if the transfer has been started;\r
+ * otherwise, the corresponding error status code.\r
+ */\r
+uint8_t USBD_HAL_Write( uint8_t bEndpoint,\r
+ const void *pData,\r
+ uint32_t dLength)\r
+{\r
+ if (endpoints[bEndpoint].transfer.transHdr.transType)\r
+ return UDPHS_AddWr(bEndpoint, pData, dLength);\r
+ else\r
+ return UDPHS_Write(bEndpoint, pData, dLength);\r
+}\r
+\r
+/**\r
+ * Special write function.\r
+ * Sends data through a USB endpoint. Sets up the transfer descriptor,\r
+ * writes header and one or two data payloads (depending on the number of\r
+ * FIFO bank for the endpoint) and then starts the actual transfer. The\r
+ * operation is complete when all the data has been sent.\r
+ *\r
+ * *If the size of the buffer is greater than the size of the endpoint\r
+ * (or twice the size if the endpoint has two FIFO banks), then the buffer\r
+ * must be kept allocated until the transfer is finished*. This means that\r
+ * it is not possible to declare it on the stack (i.e. as a local variable\r
+ * of a function which returns after starting a transfer).\r
+ *\r
+ * \param bEndpoint Endpoint number.\r
+ * \param pData Pointer to a buffer with the data to send.\r
+ * \param dLength Size of the data buffer.\r
+ * \return USBD_STATUS_SUCCESS if the transfer has been started;\r
+ * otherwise, the corresponding error status code.\r
+ */\r
+uint8_t USBD_HAL_WrWithHdr(uint8_t bEndpoint,\r
+ const void * pHdr, uint8_t bHdrLen,\r
+ const void * pData,uint32_t dLength)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint];\r
+ Endpoint *pEp = &(endpoints[bEndpoint]);\r
+ Transfer *pXfr = (Transfer*)&(pEp->transfer);\r
+ /* Return if DMA is not supported */\r
+ if (!CHIP_USB_ENDPOINTS_DMA(bEndpoint))\r
+ {\r
+ return USBD_STATUS_HW_NOT_SUPPORTED;\r
+ }\r
+\r
+#ifdef DMA\r
+ /* Return if busy */\r
+ if (pEp->state != UDPHS_ENDPOINT_IDLE)\r
+ {\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ /* Sending state */\r
+ pEp->state = UDPHS_ENDPOINT_SENDING;\r
+ TRACE_DEBUG_WP("Wr%d(%d+%d) ", bEndpoint, bHdrLen, dLength);\r
+\r
+ pEp->sendZLP = 0;\r
+\r
+ /* Setup transfer descriptor */\r
+ pXfr->pData = (void*) pData;\r
+ pXfr->remaining = bHdrLen + dLength;\r
+ pXfr->buffered = 0;\r
+ pXfr->transferred = 0;\r
+\r
+ /* 1. DMA supported always, 2. Not ZLP */\r
+ if (bHdrLen + dLength > 0)\r
+ {\r
+ uint8_t bNbTrans = (pHwEp->UDPHS_EPTCFG & UDPHS_EPTCFG_NB_TRANS_Msk)\r
+ >> UDPHS_EPTCFG_NB_TRANS_Pos;\r
+ if (pXfr->remaining > DMA_MAX_FIFO_SIZE)\r
+ {\r
+ /* Transfer the max */\r
+ pXfr->buffered = DMA_MAX_FIFO_SIZE;\r
+ }\r
+ else\r
+ {\r
+ /* Good size, total size */\r
+ pXfr->buffered = pXfr->remaining;\r
+ }\r
+\r
+ /* LD1: header - load to fifo without interrupt */\r
+ /* Header discarded if exceed the DMA FIFO length */\r
+ //if (bHdrLen > DMA_MAX_FIFO_SIZE) bHdrLen = DMA_MAX_FIFO_SIZE;\r
+ pDmaLL[0].pNxtDesc = (void*)&pDmaLL[1];\r
+ pDmaLL[0].pAddr = (void*)pHdr;\r
+ pDmaLL[0].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(bHdrLen)\r
+ | UDPHS_DMACONTROL_LDNXT_DSC;\r
+ /* High bandwidth ISO EP, max size n*ep_size */\r
+ if (bNbTrans > 1) {\r
+ uint8_t* pU8 = (uint8_t*)pData;\r
+ uint32_t maxSize = bNbTrans * pEp->size;\r
+ dLength = pXfr->buffered - bHdrLen;\r
+ if (dLength > maxSize) dLength = maxSize;\r
+ #if 0 /* Prepare banks by 1 DMA descriptor -- NK if not standard EP size, works! */\r
+ /* LD2: data - load to fifo with interrupt */\r
+ pDmaLL[1].pNxtDesc = (void*)NULL;\r
+ pDmaLL[1].pAddr = (void*)pU8;\r
+ pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(dLength)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT;\r
+ #else\r
+ uint32_t pktLen, ndxData = 0;\r
+ /* LD2: data - bank 0 */\r
+ pktLen = pEp->size - bHdrLen;\r
+ if (pktLen >= dLength) { /* It's the last DMA LLI */\r
+ pDmaLL[1].pNxtDesc = (void*)NULL;\r
+ pDmaLL[1].pAddr = (void*)pU8;\r
+ pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(dLength)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT;\r
+ }\r
+ else {\r
+ pDmaLL[1].pNxtDesc = (void*)&pDmaLL[2];\r
+ pDmaLL[1].pAddr = (void*)pU8;\r
+ pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(pktLen)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_LDNXT_DSC;\r
+ dLength -= pktLen; ndxData += pktLen;\r
+ /* LD3: data - bank 1 */\r
+ pktLen = pEp->size;\r
+ if (pktLen >= dLength) { /* It's the last */\r
+ pDmaLL[1].pNxtDesc = (void*) NULL;\r
+ pDmaLL[1].pAddr = (void*)&pU8[ndxData];\r
+ pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(dLength)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT;\r
+ }\r
+ else {\r
+ pDmaLL[2].pNxtDesc = (void*)&pDmaLL[3];\r
+ pDmaLL[2].pAddr = (void*)&pU8[ndxData];\r
+ pDmaLL[2].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(pktLen)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_LDNXT_DSC;\r
+ dLength -= pktLen; ndxData += pktLen;\r
+ /* LD4: data - bank 2 */\r
+ pDmaLL[3].pNxtDesc = (void*) NULL;\r
+ pDmaLL[3].pAddr = (void*)&pU8[ndxData];\r
+ pDmaLL[3].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(dLength)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT;\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ else { /* Normal, fill all data */\r
+ /* LD2: data - load to fifo with interrupt */\r
+ dLength = pXfr->buffered - bHdrLen;\r
+ pDmaLL[1].pNxtDesc = (void*)NULL;\r
+ pDmaLL[1].pAddr = (void*)pData;\r
+ pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB\r
+ | UDPHS_DMACONTROL_BUFF_LENGTH(dLength)\r
+ | UDPHS_DMACONTROL_END_B_EN\r
+ | UDPHS_DMACONTROL_END_BUFFIT;\r
+ }\r
+ /* Interrupt enable */\r
+ pUdp->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint);\r
+ /* Start transfer with LLI */\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMANXTDSC = (uint32_t)pDmaLL;\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0;\r
+ pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = UDPHS_DMACONTROL_LDNXT_DSC;\r
+ return USBD_STATUS_SUCCESS;\r
+ }\r
+#endif\r
+ \r
+ /* Enable IT */\r
+ pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint );\r
+ pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY;\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Reads incoming data on an USB endpoint This methods sets the transfer\r
+ * descriptor and activate the endpoint interrupt. The actual transfer is\r
+ * then carried out by the endpoint interrupt handler. The Read operation\r
+ * finishes either when the buffer is full, or a short packet (inferior to\r
+ * endpoint maximum size) is received.\r
+ *\r
+ * *The buffer must be kept allocated until the transfer is finished*.\r
+ * \param bEndpoint Endpoint number.\r
+ * \param pData Pointer to a data buffer.\r
+ * \param dLength Size of the data buffer in bytes.\r
+ * \return USBD_STATUS_SUCCESS if the read operation has been started;\r
+ * otherwise, the corresponding error code.\r
+ */\r
+uint8_t USBD_HAL_Read(uint8_t bEndpoint,\r
+ void *pData,\r
+ uint32_t dLength)\r
+{\r
+ if (endpoints[bEndpoint].transfer.transHdr.transType)\r
+ return USBD_STATUS_SW_NOT_SUPPORTED;\r
+ else\r
+ return UDPHS_Read(bEndpoint, pData, dLength);\r
+}\r
+\r
+/**\r
+ * \brief Enable Pull-up, connect.\r
+ *\r
+ * -# Enable HW access if needed\r
+ * -# Enable Pull-Up\r
+ * -# Disable HW access if needed\r
+ */\r
+void USBD_HAL_Connect(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ uint8_t dis = UDPHS_EnablePeripheralClock();\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS;\r
+ pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_DETACH;\r
+ if (dis) UDPHS_DisablePeripheralClock();\r
+}\r
+\r
+/**\r
+ * \brief Disable Pull-up, disconnect.\r
+ *\r
+ * -# Enable HW access if needed\r
+ * -# Disable PULL-Up\r
+ * -# Disable HW access if needed\r
+ */\r
+void USBD_HAL_Disconnect(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ uint8_t dis = UDPHS_EnablePeripheralClock();\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_DETACH;\r
+ pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_PULLD_DIS;\r
+ if (dis) UDPHS_DisablePeripheralClock();\r
+}\r
+\r
+/**\r
+ * Starts a remote wake-up procedure.\r
+ */\r
+void USBD_HAL_RemoteWakeUp(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ UDPHS_EnablePeripheralClock();\r
+ UDPHS_EnableUsbClock();\r
+\r
+ TRACE_INFO_WP("RWUp ");\r
+\r
+ /* Activates a remote wakeup (edge on ESR), then clear ESR */\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_REWAKEUP;\r
+ while(pUdp->UDPHS_CTRL & UDPHS_CTRL_REWAKEUP)\r
+ {\r
+ TRACE_DEBUG_WP("w");\r
+ }\r
+ UDPHS_EnableBIAS();\r
+}\r
+\r
+/**\r
+ * Sets the device address to the given value.\r
+ * \param address New device address.\r
+ */\r
+void USBD_HAL_SetAddress(uint8_t address)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+\r
+ if (address)\r
+ {\r
+ pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_DEV_ADDR_Msk;\r
+ pUdp->UDPHS_CTRL |= address | UDPHS_CTRL_FADDR_EN;\r
+ }\r
+ else\r
+ {\r
+ pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_FADDR_EN;\r
+ }\r
+}\r
+\r
+/**\r
+ * Sets the current device configuration.\r
+ * \param cfgnum - Configuration number to set.\r
+ */\r
+void USBD_HAL_SetConfiguration(uint8_t cfgnum)\r
+{\r
+ /* Nothing to do now */\r
+ cfgnum = cfgnum;\r
+}\r
+\r
+/**\r
+ * Initializes the USB HW Access driver.\r
+ */\r
+void USBD_HAL_Init(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pEpt;\r
+ UdphsDma *pDma;\r
+ uint32_t i;\r
+#ifdef DMA\r
+ /* DMA Link list should be 16-bytes aligned */\r
+ if ((uint32_t)dmaLL & 0xFFFFFFF0)\r
+ pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[1] & 0xFFFFFFF0);\r
+ else\r
+ pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[0]);\r
+#endif\r
+ /* Must before USB & TXVC access! */\r
+ UDPHS_EnablePeripheralClock();\r
+\r
+ /* Reset & disable endpoints */\r
+ USBD_HAL_ResetEPs(0xFFFFFFFF, USBD_STATUS_RESET, 0);\r
+\r
+ /* Configure the pull-up on D+ and disconnect it */\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_DETACH;\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS;\r
+\r
+ /* Reset IP */\r
+ pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_EN_UDPHS;\r
+ pUdp->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS;\r
+\r
+ /* (XCHQ[2010.1.21], IP recomendation, setup clock after reset IP) */\r
+ UDPHS_EnableUsbClock();\r
+\r
+ /* Initialize DMA */\r
+ for (i = 1;\r
+ i < ((pUdp->UDPHS_IPFEATURES & UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk) >> 4);\r
+ i ++)\r
+ {\r
+ pEpt = &pUdp->UDPHS_EPT[i];\r
+ pDma = &pUdp->UDPHS_DMA[i];\r
+ /* DMA stop */\r
+ pDma->UDPHS_DMACONTROL = 0;\r
+ /* Disable endpoint */\r
+ pEpt->UDPHS_EPTCTLDIS = (uint32_t)UDPHS_EPTCTLDIS_SHRT_PCKT\r
+ | UDPHS_EPTCTLDIS_BUSY_BANK\r
+ | UDPHS_EPTCTLDIS_NAK_OUT\r
+ | UDPHS_EPTCTLDIS_NAK_IN\r
+ | UDPHS_EPTCTLDIS_STALL_SNT\r
+ | UDPHS_EPTCTLDIS_RX_SETUP\r
+ | UDPHS_EPTCTLDIS_TX_PK_RDY\r
+ | UDPHS_EPTCTLDIS_TX_COMPLT\r
+ | UDPHS_EPTCTLDIS_RX_BK_RDY\r
+ | UDPHS_EPTCTLDIS_ERR_OVFLW\r
+ | UDPHS_EPTCTLDIS_MDATA_RX\r
+ | UDPHS_EPTCTLDIS_DATAX_RX\r
+ | UDPHS_EPTCTLDIS_NYET_DIS\r
+ | UDPHS_EPTCTLDIS_INTDIS_DMA\r
+ | UDPHS_EPTCTLDIS_AUTO_VALID\r
+ | UDPHS_EPTCTLDIS_EPT_DISABL\r
+ ;\r
+ /* Clear status endpoint */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ\r
+ | UDPHS_EPTCLRSTA_FRCESTALL\r
+ | UDPHS_EPTCLRSTA_RX_BK_RDY\r
+ | UDPHS_EPTCLRSTA_TX_COMPLT\r
+ | UDPHS_EPTCLRSTA_RX_SETUP\r
+ | UDPHS_EPTCLRSTA_STALL_SNT\r
+ | UDPHS_EPTCLRSTA_NAK_IN\r
+ | UDPHS_EPTCLRSTA_NAK_OUT\r
+ ;\r
+ /* Reset endpoint config */\r
+ pEpt->UDPHS_EPTCTLENB = 0;\r
+ /* Reset DMA channel (Buffer count and Control field) */\r
+ pDma->UDPHS_DMACONTROL = UDPHS_DMACONTROL_LDNXT_DSC;\r
+ /* Reset DMA channel */\r
+ pDma->UDPHS_DMACONTROL = 0;\r
+ /* Clear DMA channel status (read to clear) */\r
+ pDma->UDPHS_DMASTATUS = pDma->UDPHS_DMASTATUS;\r
+ }\r
+\r
+ /* Force Full-Speed */\r
+ pUdp->UDPHS_TST = forceUsbFS ? UDPHS_TST_SPEED_CFG_FULL_SPEED : 0;\r
+\r
+ pUdp->UDPHS_IEN = 0;\r
+ pUdp->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES\r
+ | UDPHS_CLRINT_ENDOFRSM\r
+ | UDPHS_CLRINT_WAKE_UP\r
+ | UDPHS_CLRINT_ENDRESET\r
+ | UDPHS_CLRINT_INT_SOF\r
+ | UDPHS_CLRINT_MICRO_SOF\r
+ | UDPHS_CLRINT_DET_SUSPD\r
+ ;\r
+\r
+ /* Enable interrupts */\r
+ pUdp->UDPHS_IEN = UDPHS_IEN_ENDOFRSM\r
+ | UDPHS_IEN_WAKE_UP\r
+ | UDPHS_IEN_DET_SUSPD;\r
+\r
+ /* Disable USB clocks */\r
+ UDPHS_DisableUsbClock();\r
+}\r
+\r
+/**\r
+ * Causes the given endpoint to acknowledge the next packet it receives\r
+ * with a STALL handshake except setup request.\r
+ * \param bEP Endpoint number.\r
+ * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED.\r
+ */\r
+uint8_t USBD_HAL_Stall(uint8_t bEP)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEP];\r
+\r
+ Endpoint *pEndpoint = &(endpoints[bEP]);\r
+\r
+ /* Check that endpoint is in Idle state */\r
+ if (pEndpoint->state != UDPHS_ENDPOINT_IDLE)\r
+ {\r
+ TRACE_WARNING("UDP_Stall: EP%d locked\n\r", bEP);\r
+ return USBD_STATUS_LOCKED;\r
+ }\r
+ /* STALL endpoint */\r
+ pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL;\r
+\r
+ TRACE_DEBUG_WP("Stall%d ", bEP);\r
+ return USBD_STATUS_SUCCESS;\r
+}\r
+\r
+/**\r
+ * Sets/Clear/Get the HALT state on the endpoint.\r
+ * In HALT state, the endpoint should keep stalling any packet.\r
+ * \param bEndpoint Endpoint number.\r
+ * \param ctl Control code CLR/HALT/READ.\r
+ * 0: Clear HALT state;\r
+ * 1: Set HALT state;\r
+ * .: Return HALT status.\r
+ * \return USBD_STATUS_INVALID_PARAMETER if endpoint not exist,\r
+ * otherwise endpoint halt status.\r
+ */\r
+uint8_t USBD_HAL_Halt(uint8_t bEndpoint, uint8_t ctl)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEndpoint];\r
+\r
+ Endpoint *pEndpoint = &(endpoints[bEndpoint]);\r
+ uint8_t status = 0;\r
+\r
+ /* SET Halt */\r
+ if (ctl == 1)\r
+ {\r
+ /* Check that endpoint is enabled and not already in Halt state */\r
+ if ((pEndpoint->state != UDPHS_ENDPOINT_DISABLED)\r
+ && (pEndpoint->state != UDPHS_ENDPOINT_HALTED))\r
+ {\r
+\r
+ TRACE_DEBUG_WP("Halt%d ", bEndpoint);\r
+\r
+ /* Abort the current transfer if necessary */\r
+ UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED);\r
+\r
+ /* Put endpoint into Halt state */\r
+ pEndpoint->state = UDPHS_ENDPOINT_HALTED;\r
+ pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL;\r
+\r
+ #ifdef DMA\r
+ if (CHIP_USB_ENDPOINTS_DMA(bEndpoint))\r
+ {\r
+ /* Enable the endpoint DMA interrupt */\r
+ pUdp->UDPHS_IEN |= ( 1 << SHIFT_DMA << bEndpoint );\r
+ }\r
+ else\r
+ {\r
+ /* Enable the endpoint interrupt */\r
+ pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint );\r
+ }\r
+ #else\r
+ /* Enable the endpoint interrupt */\r
+ pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint );\r
+ #endif\r
+ }\r
+ }\r
+ /* CLEAR Halt */\r
+ else if (ctl == 0)\r
+ {\r
+ /* Check if the endpoint is halted */\r
+ if (pEndpoint->state == UDPHS_ENDPOINT_HALTED)\r
+ {\r
+\r
+ TRACE_DEBUG_WP("Unhalt%d ", bEndpoint);\r
+\r
+ /* Return endpoint to Idle state */\r
+ pEndpoint->state = UDPHS_ENDPOINT_IDLE;\r
+\r
+ /* Clear FORCESTALL flag */\r
+ pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ\r
+ | UDPHS_EPTCLRSTA_FRCESTALL;\r
+\r
+ /* Reset Endpoint Fifos */\r
+ pUdp->UDPHS_EPTRST = (1 << bEndpoint);\r
+ }\r
+ }\r
+\r
+ /* Return Halt status */\r
+ if (pEndpoint->state == UDPHS_ENDPOINT_HALTED)\r
+ {\r
+ status = 1;\r
+ }\r
+ return( status );\r
+}\r
+\r
+/**\r
+ * Indicates if the device is running in high or full-speed. Always returns 0\r
+ * since UDP does not support high-speed mode.\r
+ */\r
+uint8_t USBD_HAL_IsHighSpeed(void)\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ return (pUdp->UDPHS_INTSTA & UDPHS_INTSTA_SPEED);\r
+}\r
+\r
+/**\r
+ * Suspend USB Device HW Interface\r
+ *\r
+ * -# Disable transceiver\r
+ * -# Disable USB Clock\r
+ * -# Disable USB Peripheral\r
+ */\r
+void USBD_HAL_Suspend(void)\r
+{\r
+ /* The device enters the Suspended state */\r
+ UDPHS_DisableBIAS();\r
+ UDPHS_DisableUsbClock();\r
+ UDPHS_DisablePeripheralClock();\r
+}\r
+\r
+/**\r
+ * Activate USB Device HW Interface\r
+ * -# Enable USB Peripheral\r
+ * -# Enable USB Clock\r
+ * -# Enable transceiver\r
+ */\r
+void USBD_HAL_Activate(void)\r
+{\r
+ UDPHS_EnablePeripheralClock();\r
+ UDPHS_EnableUsbClock();\r
+ UDPHS_EnableBIAS();\r
+}\r
+\r
+/**\r
+ * Certification test for High Speed device.\r
+ * \param bIndex Test to be done\r
+ */\r
+void USBD_HAL_Test( uint8_t bIndex )\r
+{\r
+ Udphs *pUdp = UDPHS;\r
+ uint8_t *pFifo;\r
+ uint32_t i;\r
+\r
+ /* remove suspend for TEST */\r
+ pUdp->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD;\r
+ /* force High Speed (remove suspend) */\r
+ pUdp->UDPHS_TST |= UDPHS_TST_SPEED_CFG_HIGH_SPEED;\r
+\r
+ switch( bIndex ) {\r
+\r
+ case USBFeatureRequest_TESTPACKET:\r
+ TRACE_DEBUG_WP("TEST_PACKET ");\r
+\r
+ pUdp->UDPHS_DMA[1].UDPHS_DMACONTROL = 0;\r
+ pUdp->UDPHS_DMA[2].UDPHS_DMACONTROL = 0;\r
+\r
+ /* Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank */\r
+ pUdp->UDPHS_EPT[2].UDPHS_EPTCFG = UDPHS_EPTCFG_EPT_SIZE_64\r
+ | UDPHS_EPTCFG_EPT_DIR\r
+ | UDPHS_EPTCFG_EPT_TYPE_BULK\r
+ | UDPHS_EPTCFG_BK_NUMBER_1;\r
+ while( (pUdp->UDPHS_EPT[2].UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_MAPD) != UDPHS_EPTCFG_EPT_MAPD );\r
+ pUdp->UDPHS_EPT[2].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL;\r
+\r
+ /* Write FIFO */\r
+ pFifo = (uint8_t*)((uint32_t *)(UDPHS_RAM_ADDR) + (EPT_VIRTUAL_SIZE * 2));\r
+ for( i=0; i<sizeof(test_packet_buffer); i++) {\r
+ pFifo[i] = test_packet_buffer[i];\r
+ }\r
+ /* Tst PACKET */\r
+ pUdp->UDPHS_TST |= UDPHS_TST_TST_PKT;\r
+ /* Send packet */\r
+ pUdp->UDPHS_EPT[2].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY;\r
+ break;\r
+\r
+ case USBFeatureRequest_TESTJ:\r
+ TRACE_DEBUG_WP("TEST_J ");\r
+ pUdp->UDPHS_TST = UDPHS_TST_TST_J;\r
+ break;\r
+\r
+ case USBFeatureRequest_TESTK:\r
+ TRACE_DEBUG_WP("TEST_K ");\r
+ pUdp->UDPHS_TST = UDPHS_TST_TST_K;\r
+ break;\r
+\r
+ case USBFeatureRequest_TESTSE0NAK:\r
+ TRACE_DEBUG_WP("TEST_SEO_NAK ");\r
+ pUdp->UDPHS_IEN = 0; // for test\r
+ break;\r
+\r
+ case USBFeatureRequest_TESTSENDZLP:\r
+ //while( 0 != (pUdp->UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSETSTA_TX_PK_RDY ) ) {}\r
+ pUdp->UDPHS_EPT[0].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY;\r
+ //while( 0 != (pUdp->UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSETSTA_TX_PK_RDY ) ) {}\r
+ TRACE_DEBUG_WP("SEND_ZLP ");\r
+ break;\r
+ }\r
+ TRACE_DEBUG_WP("\n\r");\r
+}\r
+\r
+/**@}*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup acc_module Working with ACC\r
+ * \ingroup peripherals_module\r
+ * The ACC driver provides the interface to configure and use the ACC peripheral.\n\r
+ *\r
+ * It applies comparison on two inputs and gives a compare output.\r
+ *\r
+ * To Enable a ACC Comparison,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Enable ACC peripheral clock by setting the corresponding bit in PMC_PCER1\r
+ * (PMC Peripheral Clock Enable Register 1)\r
+ * </li>\r
+ * <li> Reset the controller by asserting ACC_CR_SWRST in ACC_CR(ACC Control Register)\r
+ </li>\r
+ * <li> Configure the mode as following steps: </li>\r
+ * -# Select inputs for SELMINUS and SELPLUS in ACC_MR (ACC Mode Register).\r
+ * -# Enable Analog Comparator by setting ACEN in ACC_MR.\r
+ * -# Configure Edge Type to detect different compare output.\r
+ * </li>\r
+ * <li> Wait until the automatic mask period expires by polling MASK bit in\r
+ * ACC_ISR.\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the ACC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref acc.c\n\r
+ * \ref acc.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Analog Comparator Controller (ACC).\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize the ACC controller\r
+ *\r
+ * \param pAcc Pointer to an Acc instance.\r
+ * \param idAcc ACC identifier\r
+ * \param ucSelplus input connected to inp, 0~7\r
+ * \param ucSelminus input connected to inm,0~7\r
+ * \param wAc_en Analog comprator enabled/disabled\r
+ * \param wEdge CF flag triggering mode\r
+ * \param wInvert INVert comparator output,use pattern defined in the device header file\r
+ */\r
+extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, uint8_t ucSelminus,\r
+ uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert )\r
+{\r
+ /* Enable peripheral clock*/\r
+ PMC->PMC_PCER1 = 1 << (idAcc - 32) ;\r
+\r
+ /* Reset the controller */\r
+ pAcc->ACC_CR |= ACC_CR_SWRST ;\r
+\r
+ /* Write to the MR register */\r
+ ACC_CfgModeReg( pAcc,\r
+ ( (ucSelplus<<ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk ) |\r
+ ( (ucSelminus<<ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk ) |\r
+ ( (wAc_en<<8) & ACC_MR_ACEN ) |\r
+ ( (wEdge<<ACC_MR_EDGETYP_Pos) & ACC_MR_EDGETYP_Msk ) |\r
+ ( (wInvert<<12) & ACC_MR_INV ) ) ;\r
+ /* set hysteresis and current option*/\r
+ pAcc->ACC_ACR = (ACC_ACR_ISEL_HISP | ((0x01 << ACC_ACR_HYST_Pos) & ACC_ACR_HYST_Msk));\r
+\r
+ /* Automatic Output Masking Period*/\r
+ while ( pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK ) ;\r
+}\r
+\r
+/**\r
+ * Return the Channel Converted Data\r
+ * \param pAcc Pointer to an Acc instance.\r
+ * \param selplus input applied on ACC SELPLUS\r
+ * \param selminus input applied on ACC SELMINUS\r
+ */\r
+extern void ACC_SetComparisonPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus )\r
+{\r
+ uint32_t dwTemp ;\r
+\r
+ assert( ucSelplus < 8 && ucSelminus < 8 ) ;\r
+\r
+ dwTemp = pAcc->ACC_MR ;\r
+\r
+ pAcc->ACC_MR = dwTemp & (uint32_t) ((~ACC_MR_SELMINUS_Msk) & (~ACC_MR_SELPLUS_Msk));\r
+\r
+ pAcc->ACC_MR |= ( ((ucSelplus << ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk) |\r
+ ((ucSelminus << ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk) ) ;\r
+\r
+}\r
+/**\r
+ * Return Comparison Result\r
+ * \param pAcc Pointer to an Acc instance.\r
+ * \param status value of ACC_ISR\r
+ */\r
+extern uint32_t ACC_GetComparisonResult( Acc *pAcc, uint32_t dwStatus )\r
+{\r
+ uint32_t dwTemp = pAcc->ACC_MR ;\r
+\r
+ if ( (dwTemp & ACC_MR_INV) == ACC_MR_INV )\r
+ {\r
+ if ( dwStatus & ACC_ISR_SCO )\r
+ {\r
+ return 0 ; /* inn>inp*/\r
+ }\r
+ else\r
+ {\r
+ return 1 ;/* inp>inn*/\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ( dwStatus & ACC_ISR_SCO )\r
+ {\r
+ return 1 ; /* inp>inn*/\r
+ }\r
+ else\r
+ {\r
+ return 0 ;/* inn>inp*/\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup aes_module Working with AES\r
+ * \ingroup peripherals_module\r
+ * The AES driver provides the interface to configure and use the AES peripheral.\r
+ * \n\r
+ *\r
+ * The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm\r
+ * that can be used to protect electronic data. The AES algorithm is a symmetric block \r
+ * cipher that can encrypt (encipher) and decrypt (decipher) information.\r
+ * Encryption converts data to an unintelligible form called ciphertext. \r
+ * Decrypting the ciphertext converts the data back into its original form, \r
+ * called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection \r
+ * between the encryption and the decryption processes. The AES is capable of using cryptographic \r
+ * keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. \r
+ * This 128-bit/192-bit/256-bit key is defined in the Key Registers (AES_KEYWRx) and set by \r
+ * AES_WriteKey(). The input to the encryption processes of the CBC, CFB, and OFB modes includes,\r
+ * in addition to the plaintext, a 128-bit data block called the initialization vector (IV), \r
+ * which must be set with AES_SetVector(). \r
+ * The initialization vector is used in an initial step in the encryption of a message and \r
+ * in the corresponding decryption of the message. The Initialization Vector Registers are \r
+ * also used by the CTR mode to set the counter value.\r
+ *\r
+ * To Enable a AES encryption and decryption,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> A software triggered hardware reset of the AES interface is performed by AES_SoftReset().</li>\r
+ * <li> Configure AES algorithm mode, key mode, start mode and operation mode by AES_Configure(). </li>\r
+ * <li> Input AES data for encryption and decryption with function AES_SetInput() </li>\r
+ * <li> Set AES key with fucntion AES_WriteKey(). </li>\r
+ * <li> To start the encryption or the decryption process with AES_Start()</li>\r
+ * <li> To get the encryption or decryption reslut by AES_GetOutput() </li>\r
+ * </ul>\r
+ *\r
+ *\r
+ * For more accurate information, please look at the AES section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref aes.c\n\r
+ * \ref aes.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Advanced Encryption Standard (AES)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Starts Manual encryption/decryption process.\r
+ */\r
+void AES_Start(void)\r
+{\r
+ AES->AES_CR = AES_CR_START;\r
+}\r
+\r
+/**\r
+ * \brief Resets the AES. A software triggered hardware reset of the AES interface is performed.\r
+ */\r
+void AES_SoftReset(void)\r
+{\r
+ AES->AES_CR = AES_CR_SWRST;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configures an AES peripheral with the specified parameters.\r
+ * \param mode Desired value for the AES mode register (see the datasheet).\r
+ */\r
+void AES_Configure(uint32_t mode)\r
+{\r
+ AES->AES_MR = mode; \r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a AES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void AES_EnableIt(uint32_t sources)\r
+{\r
+ AES->AES_IER = sources;\r
+}\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a AES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void AES_DisableIt(uint32_t sources)\r
+{\r
+ AES->AES_IDR = sources;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given AES peripheral.\r
+ * \return AES status register.\r
+ */\r
+uint32_t AES_GetStatus(void)\r
+{\r
+ return AES->AES_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption.\r
+ * \param pKey Pointer to a 16/24/32 bytes cipher key.\r
+ * \param keyLength length of key\r
+ */\r
+void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength)\r
+{\r
+ AES->AES_KEYWR[0] = pKey[0];\r
+ AES->AES_KEYWR[1] = pKey[1];\r
+ AES->AES_KEYWR[2] = pKey[2];\r
+ AES->AES_KEYWR[3] = pKey[3];\r
+\r
+ if( keyLength >= 24 ) {\r
+ AES->AES_KEYWR[4] = pKey[4];\r
+ AES->AES_KEYWR[5] = pKey[5];\r
+ }\r
+ if( keyLength == 32 ) {\r
+ AES->AES_KEYWR[6] = pKey[6];\r
+ AES->AES_KEYWR[7] = pKey[7];\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set the for 32-bit input Data allow to set the 128-bit data block used for encryption/decryption.\r
+ * \param data Pointer to the 16-bytes data to cipher/decipher.\r
+ */\r
+void AES_SetInput(uint32_t *data)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i< 4; i++)\r
+ AES->AES_IDATAR[i] = data[i];\r
+}\r
+\r
+/**\r
+ * \brief Get the four 32-bit data contain the 128-bit data block which has been encrypted/decrypted.\r
+ * \param data pointer to the word that has been encrypted/decrypted..\r
+ */\r
+void AES_GetOutput(uint32_t *data)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i< 4; i++) \r
+ data[i] = AES->AES_ODATAR[i];\r
+}\r
+\r
+/**\r
+ * \brief Set four 64-bit initialization vector data block, which is used by some\r
+ * modes of operation as an additional initial input.\r
+ * \param pVector point to the word of the initialization vector.\r
+ */\r
+void AES_SetVector(const uint32_t *pVector)\r
+{\r
+ AES->AES_IVR[0] = pVector[0];\r
+ AES->AES_IVR[1] = pVector[1];\r
+ AES->AES_IVR[2] = pVector[2];\r
+ AES->AES_IVR[3] = pVector[3];\r
+}\r
+\r
+\r
+/**\r
+ * \brief Set Length in bytes of the AAD data that is to be processed.\r
+ * \param len Length.\r
+ */\r
+void AES_SetAadLen(uint32_t len)\r
+{\r
+ AES->AES_AADLENR = len;\r
+}\r
+\r
+/**\r
+ * \brief Set Length in bytes of the Length in bytes of the \r
+ * plaintext/ciphertext (C) data that is to be processed..\r
+ * \param len Length.\r
+ */\r
+void AES_SetDataLen(uint32_t len)\r
+{\r
+ AES->AES_CLENR = len;\r
+}\r
+\r
+/**\r
+ * \brief Set The four 32-bit Hash Word registers expose the intermediate GHASH value. \r
+ * May be read to save the current GHASH value so processing can later be resumed, \r
+ * presumably on a later message fragment. modes of operation as an additional initial input.\r
+ * \param hash point to the word of the hash.\r
+ */\r
+void AES_SetGcmHash(uint32_t * hash)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i< 4; i++) \r
+ AES->AES_GHASHR[i] = hash[i];\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get The four 32-bit Tag which contain the final 128-bit GCM Authentication tag \r
+ * ¡°T¡± when GCM processing is complete.\r
+ * \param tag point to the word of the tag.\r
+ */\r
+void AES_GetGcmTag(uint32_t * tag)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i< 4; i++) \r
+ tag[i] = AES->AES_TAGR[i] ;\r
+}\r
+\r
+/**\r
+ * \brief Reports the current value of the 32-bit GCM counter\r
+ * \param counter Point to value of GCM counter.\r
+ */\r
+void AES_GetGcmCounter(uint32_t * counter)\r
+{\r
+ *counter = AES->AES_CTRR;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get the four 32-bit data contain the 128-bit H value computed from the KEYW value\r
+ * \param data point to the word that has been encrypted/decrypted..\r
+ */\r
+void AES_GetGcmH(uint32_t *h)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i< 4; i++) \r
+ h[i] = AES->AES_GCMHR[i];\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup afecc_module Working with afecC\r
+ * \ingroup peripherals_module\r
+ * The afecC driver provides the interface to configure and use the afecC peripheral.\n\r
+ *\r
+ * The afecC(Digital-to-Analog Converter Controller) converts digital code to analog output.\r
+ * The data to be converted are sent in a common register for all channels. It offers up to 2\r
+ * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.\r
+ *\r
+ * To Enable a afecC conversion,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Select an appropriate reference voltage on ADVREF </li>\r
+ * <li> Configure the afecC according to its requirements and special needs,which could be\r
+ broken down into several parts:\r
+ * -# Enable afecC in free running mode by clearing TRGEN in afecC_MR;\r
+ * -# Configure Refresh Period through setting REFRESH fields\r
+ * in afecC_MR; The refresh mechanism is used to protect the output analog value from\r
+ * decreasing.\r
+ * -# Enable channels and write digital code to afecC_CDR,in free running mode, the conversion\r
+ * is started right after at least one channel is enabled and data is written .\r
+ </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the afecC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref afecC.c\n\r
+ * \ref afecC.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Digital-to-Analog Converter Controller (afecC).\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/* DMA driver instance */\r
+static uint32_t afeDmaRxChannel;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief AFE xDMA Rx callback\r
+ * Invoked on AFE DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to AfeDma instance.\r
+ */ \r
+static void Afe_Rx_Cb(uint32_t channel, AfeDma* pArg)\r
+{\r
+ AfeCmd *pAfedCmd = pArg->pCurrentCommand;\r
+ if (channel != afeDmaRxChannel)\r
+ return;\r
+\r
+ /* Configure and enable interrupt on RC compare */\r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_DisableIRQ(XDMAC_IRQn);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, afeDmaRxChannel);\r
+\r
+ /* Release the dataflash semaphore */\r
+ pArg->semaphore++;\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pAfedCmd && pAfedCmd->callback) {\r
+ pAfedCmd->callback(0, pAfedCmd->pArgument);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA Channels: 0 RX.\r
+ * Channels are disabled after configure.\r
+ * \returns 0 if the dma channel configuration successfully; otherwise returns\r
+ * AFE_ERROR_XXX.\r
+ */\r
+static uint8_t _AfeConfigureDmaChannels( AfeDma* pAfed )\r
+{\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pAfed->pXdmad, 0 );\r
+\r
+ XDMAD_FreeChannel( pAfed->pXdmad, afeDmaRxChannel);\r
+\r
+ /* Allocate a DMA channel for AFE0/1 RX. */\r
+ afeDmaRxChannel = XDMAD_AllocateChannel( pAfed->pXdmad, pAfed->afeId, XDMAD_TRANSFER_MEMORY);\r
+ {\r
+ if ( afeDmaRxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return AFE_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Setup callbacks for AFE0/1 RX */\r
+ XDMAD_SetCallback(pAfed->pXdmad, afeDmaRxChannel, (XdmadTransferCallback)Afe_Rx_Cb, pAfed);\r
+ if (XDMAD_PrepareChannel( pAfed->pXdmad, afeDmaRxChannel ))\r
+ return AFE_ERROR;\r
+ return AFE_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the DMA source and destination with Linker List mode.\r
+ *\r
+ * \param pBuffer Pointer to afec buffer\r
+ * \param size length of buffer\r
+ */\r
+\r
+static uint8_t _Afe_configureLinkList(Afec *pAfeHw, void *pXdmad, AfeCmd *pCommand)\r
+{\r
+ uint32_t xdmaCndc;\r
+ sXdmadCfg xdmadRxCfg;\r
+ uint32_t afeId;\r
+ if ((unsigned int)pAfeHw == (unsigned int)AFEC0 ) afeId = ID_AFEC0;\r
+ if ((unsigned int)pAfeHw == (unsigned int)AFEC1 ) afeId = ID_AFEC1;\r
+ /* Setup RX Link List */\r
+ xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_EN|\r
+ XDMA_UBC_NDEN_UPDATED |\r
+ pCommand->RxSize;;\r
+ xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;\r
+ xdmadRxCfg.mbr_sa = (uint32_t)&(pAfeHw->AFEC_LCDR);\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_PER2MEM |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_WORD|\r
+ XDMAC_CC_SIF_AHB_IF1 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_FIXED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( afeId, XDMAD_TRANSFER_RX ));\r
+\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ xdmadRxCfg.mbr_sus = 0;\r
+ xdmadRxCfg.mbr_dus =0;\r
+\r
+ xdmaCndc = 0;\r
+ if (XDMAD_ConfigureTransfer( pXdmad, afeDmaRxChannel, &xdmadRxCfg, xdmaCndc, 0))\r
+ return AFE_ERROR;\r
+\r
+ return AFE_OK;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Initializes the AfeDma structure and the corresponding AFE & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX .\r
+ * The DMA channels are freed automatically when no DMA command processing.\r
+ *\r
+ * \param pAfed Pointer to a AfeDma instance.\r
+ * \param pAfeHw Associated Afe peripheral.\r
+ * \param AfeId Afe peripheral identifier.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t Afe_ConfigureDma( AfeDma *pAfed ,\r
+ Afec *pAfeHw ,\r
+ uint8_t AfeId,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the Afe structure */\r
+ pAfed->pAfeHw = pAfeHw;\r
+ pAfed->afeId = AfeId;\r
+ pAfed->semaphore = 1;\r
+ pAfed->pCurrentCommand = 0;\r
+ pAfed->pXdmad = pXdmad;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a AFE transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pAfed Pointer to a AfeDma instance.\r
+ * \param pCommand Pointer to the Afe command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * AFE_ERROR_LOCK is the driver is in use, or AFE_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand)\r
+{\r
+ Afec *pAfeHw = pAfed->pAfeHw;\r
+\r
+ /* Try to get the dataflash semaphore */\r
+ if (pAfed->semaphore == 0) {\r
+\r
+ return AFE_ERROR_LOCK;\r
+ }\r
+ pAfed->semaphore--;\r
+\r
+ // Initialize the callback\r
+ pAfed->pCurrentCommand = pCommand;\r
+\r
+ /* Initialize DMA controller using channel 0 for RX. */\r
+ if (_AfeConfigureDmaChannels(pAfed) )\r
+ return AFE_ERROR_LOCK;\r
+\r
+ /* Configure and enable interrupt on RC compare */\r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_SetPriority( XDMAC_IRQn ,1);\r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+ if (_Afe_configureLinkList(pAfeHw, pAfed->pXdmad, pCommand))\r
+ return AFE_ERROR_LOCK;\r
+\r
+ AFEC_StartConversion(pAfeHw);\r
+ /* Start DMA 0(RX) */\r
+ if (XDMAD_StartTransfer( pAfed->pXdmad, afeDmaRxChannel )) \r
+ return AFE_ERROR_LOCK;\r
+\r
+ return AFE_OK;;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup AFEC_module Working with AFE\r
+ * \ingroup peripherals_module\r
+ * The AFE driver provides the interface to configure and use the AFE peripheral.\r
+ * \n\r
+ *\r
+ * It converts the analog input to digital format. The converted result could be\r
+ * 12bit or 10bit. The AFE supports up to 16 analog lines.\r
+ *\r
+ * To Enable a AFE conversion,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Select an appropriate reference voltage on ADVREF </li>\r
+ * <li> Configure the AFE according to its requirements and special needs,which\r
+ * could be broken down into several parts:\r
+ * -# Select the resolution by setting or clearing AFEC_MR_LOWRES bit in\r
+ * AFEC_MR (Mode Register)\r
+ * -# Set AFE clock by setting AFEC_MR_PRESCAL bits in AFEC_MR, the clock is\r
+ * calculated with AFEClock = MCK / ( (PRESCAL+1) * 2 )\r
+ * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively\r
+ * in AFEC_MR.\r
+ </li>\r
+ * <li> Start conversion by setting AFEC_CR_START in AFEC_CR. </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the AFE section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref AFE.c\n\r
+ * \ref AFE.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Analog-to-Digital Converter (AFE).\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Current working clock */\r
+static uint32_t dwAFEClock = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize the AFE controller\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwID AFE Index\r
+ */\r
+extern void AFEC_Initialize( Afec* pAFE, uint32_t dwID )\r
+{\r
+ /* Enable peripheral clock*/\r
+ PMC_EnablePeripheral(dwID);\r
+\r
+ /* Reset the controller */\r
+ pAFE->AFEC_CR = AFEC_CR_SWRST;\r
+\r
+ /* Reset Mode Register */\r
+ pAFE->AFEC_MR = 0;\r
+}\r
+\r
+/**\r
+ * \brief Set AFE clock.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwPres prescal value\r
+ * \param dwMck Board MCK (Hz)\r
+ *\r
+ * \return AFE clock\r
+ */\r
+\r
+extern uint32_t AFEC_SetClock( Afec* pAFE, uint32_t dwClk, uint32_t dwMck )\r
+{ \r
+ uint32_t dwPres, dwMr;\r
+ /* Formula for PRESCAL is:\r
+ PRESCAL = peripheral clock/ fAFE Clock - 1 */\r
+\r
+ dwPres = (dwMck) / (dwClk ) - 1;\r
+ dwMr = AFEC_MR_PRESCAL(dwPres);\r
+ if (dwMr == 0) return 0;\r
+\r
+ dwMr |= (pAFE->AFEC_MR & ~AFEC_MR_PRESCAL_Msk);\r
+ pAFE->AFEC_MR = dwMr;\r
+ dwAFEClock = dwMck / (dwPres + 1);\r
+ return dwAFEClock;\r
+}\r
+\r
+/**\r
+ * \brief Set AFE timing.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwStartup startup value\r
+ * \param dwTracking tracking value\r
+ * \param dwSettling settling value\r
+ */\r
+extern void AFEC_SetTiming( Afec* pAFE, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling )\r
+{\r
+ uint32_t dwMr;\r
+\r
+ dwMr = pAFE->AFEC_MR;\r
+ dwMr &= (~AFEC_MR_STARTUP_Msk) & (~AFEC_MR_TRACKTIM_Msk) & (~AFEC_MR_SETTLING_Msk);\r
+\r
+ /* Formula:\r
+ * Startup Time = startup value / AFEClock\r
+ * Transfer Time = (TRANSFER * 2 + 3) / AFEClock\r
+ * Tracking Time = (TRACKTIM + 1) / AFEClock\r
+ * Settling Time = settling value / AFEClock\r
+ */\r
+ dwMr |= dwStartup | dwTracking | dwSettling;\r
+ pAFE->AFEC_MR |= dwMr;\r
+}\r
+\r
+/**\r
+ * \brief Set AFE trigger.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwTrgSel Trigger selection\r
+ */\r
+extern void AFEC_SetTrigger( Afec* pAFE, uint32_t dwTrgSel )\r
+{\r
+ uint32_t dwMr;\r
+\r
+ dwMr = pAFE->AFEC_MR;\r
+ dwMr &= ~AFEC_MR_TRGSEL_Msk;\r
+ dwMr |= dwTrgSel;\r
+ pAFE->AFEC_MR |= dwMr;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable/Disable sleep mode.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param bEnDis Enable/Disable sleep mode.\r
+ */\r
+extern void AFEC_SetSleepMode( Afec *pAFE, uint8_t bEnDis )\r
+{\r
+ if ( bEnDis )\r
+ {\r
+ pAFE->AFEC_MR |= AFEC_MR_SLEEP;\r
+ }\r
+ else\r
+ {\r
+ pAFE->AFEC_MR &= ~AFEC_MR_SLEEP;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable fast wake up.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param bEnDis Enable/Disable fast wake up in sleep mode.\r
+ */\r
+extern void AFEC_SetFastWakeup( Afec *pAFE, uint8_t bEnDis )\r
+{\r
+ if ( bEnDis )\r
+ {\r
+ pAFE->AFEC_MR |= AFEC_MR_FWUP;\r
+ }\r
+ else\r
+ {\r
+ pAFE->AFEC_MR &= ~AFEC_MR_FWUP;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable seqnence mode.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param bEnDis Enable/Disable seqnence mode.\r
+ */\r
+extern void AFEC_SetSequenceMode( Afec *pAFE, uint8_t bEnDis )\r
+{\r
+ if ( bEnDis )\r
+ {\r
+ /* User Sequence Mode: The sequence respects what is defined in\r
+ AFEC_SEQR1 and AFEC_SEQR2 */\r
+ pAFE->AFEC_MR |= AFEC_MR_USEQ;\r
+ }\r
+ else\r
+ {\r
+ /* Normal Mode: The controller converts channels in a simple numeric order. */\r
+ pAFE->AFEC_MR &= ~AFEC_MR_USEQ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set channel sequence.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwSEQ1 Sequence 1 ~ 8 channel number.\r
+ * \param dwSEQ2 Sequence 9 ~ 16 channel number.\r
+ */\r
+extern void AFEC_SetSequence( Afec *pAFE, uint32_t dwSEQ1, uint32_t dwSEQ2 )\r
+{\r
+ pAFE->AFEC_SEQ1R = dwSEQ1;\r
+ pAFE->AFEC_SEQ2R = dwSEQ2;\r
+}\r
+\r
+/**\r
+ * \brief Set channel sequence by given channel list.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param ucChList Channel list.\r
+ * \param ucNumCh Number of channels in list.\r
+ */\r
+extern void AFEC_SetSequenceByList( Afec *pAFE, uint8_t ucChList[], uint8_t ucNumCh )\r
+{\r
+ uint8_t i;\r
+ uint8_t ucShift;\r
+\r
+ pAFE->AFEC_SEQ1R = 0;\r
+ for (i = 0, ucShift = 0; i < 8; i ++, ucShift += 4)\r
+ {\r
+ if (i >= ucNumCh) return;\r
+ pAFE->AFEC_SEQ1R |= ucChList[i] << ucShift;\r
+\r
+ }\r
+ pAFE->AFEC_SEQ2R = 0;\r
+ for (ucShift = 0; i < 16; i ++, ucShift += 4)\r
+ {\r
+ if (i >= ucNumCh) return;\r
+ pAFE->AFEC_SEQ2R |= ucChList[i] << ucShift;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set analog change.\r
+ * IF enabled, it allows different analog settings for each channel,\r
+ * otherwise, DIFF0, GAIN0 and OFF0 are used for all channels.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param bEnDis Enable/Disable.\r
+ */\r
+extern void AFEC_SetAnalogChange( Afec* pAFE, uint8_t bEnDis )\r
+{\r
+ if ( bEnDis )\r
+ {\r
+ pAFE->AFEC_MR |= AFEC_MR_ANACH;\r
+ }\r
+ else\r
+ {\r
+ pAFE->AFEC_MR &= ~AFEC_MR_ANACH;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set "TAG" mode, show channel number in last data or not.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param bEnDis Enable/Disable TAG value.\r
+ */\r
+extern void AFEC_SetTagEnable( Afec *pAFE, uint8_t bEnDis )\r
+{\r
+ if ( bEnDis )\r
+ {\r
+ pAFE->AFEC_EMR |= AFEC_EMR_TAG;\r
+ }\r
+ else\r
+ {\r
+ pAFE->AFEC_EMR &= ~AFEC_EMR_TAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set compare channel.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwChannel channel number to be set,16 for all channels\r
+ */\r
+extern void AFEC_SetCompareChannel( Afec* pAFE, uint32_t dwChannel )\r
+{\r
+ assert( dwChannel <= 16 ) ;\r
+\r
+ if ( dwChannel < 16 )\r
+ {\r
+ pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPALL);\r
+ pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPSEL_Msk);\r
+ pAFE->AFEC_EMR |= (dwChannel << AFEC_EMR_CMPSEL_Pos);\r
+ }\r
+ else\r
+ {\r
+ pAFE->AFEC_EMR |= AFEC_EMR_CMPALL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set compare mode.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwMode compare mode\r
+ */\r
+extern void AFEC_SetCompareMode( Afec* pAFE, uint32_t dwMode )\r
+{\r
+ pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPMODE_Msk);\r
+ pAFE->AFEC_EMR |= (dwMode & AFEC_EMR_CMPMODE_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Set comparsion window.\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwHi_Lo Comparison Window\r
+ */\r
+extern void AFEC_SetComparisonWindow( Afec* pAFE, uint32_t dwHi_Lo )\r
+{\r
+ pAFE->AFEC_CWR = dwHi_Lo ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return the Channel Converted Data\r
+ *\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwChannel channel to get converted value\r
+ */\r
+extern uint32_t AFEC_GetConvertedData( Afec* pAFE, uint32_t dwChannel )\r
+{\r
+ uint32_t dwData = 0;\r
+ assert( dwChannel < 12 ) ;\r
+ pAFE->AFEC_CSELR = dwChannel;\r
+ dwData = pAFE->AFEC_CDR;\r
+\r
+ return dwData ;\r
+}\r
+\r
+\r
+/**\r
+ * Sets the AFE startup time.\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwUs Startup time in uS.\r
+ */\r
+void AFEC_SetStartupTime( Afec *pAFE, uint32_t dwUs )\r
+{\r
+ uint32_t dwStart;\r
+ uint32_t dwMr;\r
+\r
+ if (dwAFEClock == 0) return;\r
+ /* Formula for STARTUP is:\r
+ STARTUP = (time x AFECLK) / (1000000) - 1\r
+ Division multiplied by 10 for higher precision */\r
+\r
+ dwStart = (dwUs * dwAFEClock) / (100000);\r
+ if (dwStart % 10) dwStart /= 10;\r
+ else\r
+ {\r
+ dwStart /= 10;\r
+ if (dwStart) dwStart --;\r
+ }\r
+ if (dwStart > 896) dwMr = AFEC_MR_STARTUP_SUT960;\r
+ else if (dwStart > 832) dwMr = AFEC_MR_STARTUP_SUT896;\r
+ else if (dwStart > 768) dwMr = AFEC_MR_STARTUP_SUT832;\r
+ else if (dwStart > 704) dwMr = AFEC_MR_STARTUP_SUT768;\r
+ else if (dwStart > 640) dwMr = AFEC_MR_STARTUP_SUT704;\r
+ else if (dwStart > 576) dwMr = AFEC_MR_STARTUP_SUT640;\r
+ else if (dwStart > 512) dwMr = AFEC_MR_STARTUP_SUT576;\r
+ else if (dwStart > 112) dwMr = AFEC_MR_STARTUP_SUT512;\r
+ else if (dwStart > 96) dwMr = AFEC_MR_STARTUP_SUT112;\r
+ else if (dwStart > 80) dwMr = AFEC_MR_STARTUP_SUT96;\r
+ else if (dwStart > 64) dwMr = AFEC_MR_STARTUP_SUT80;\r
+ else if (dwStart > 24) dwMr = AFEC_MR_STARTUP_SUT64;\r
+ else if (dwStart > 16) dwMr = AFEC_MR_STARTUP_SUT24;\r
+ else if (dwStart > 8) dwMr = AFEC_MR_STARTUP_SUT16;\r
+ else if (dwStart > 0) dwMr = AFEC_MR_STARTUP_SUT8;\r
+ else dwMr = AFEC_MR_STARTUP_SUT0;\r
+\r
+ dwMr |= pAFE->AFEC_MR & ~AFEC_MR_STARTUP_Msk;\r
+ pAFE->AFEC_MR = dwMr;\r
+}\r
+\r
+\r
+/**\r
+ * Set AFE tracking time\r
+ * \param pAFE Pointer to an AFE instance.\r
+ * \param dwNs Tracking time in nS.\r
+ */\r
+void AFEC_SetTrackingTime( Afec *pAFE, uint32_t dwNs )\r
+{\r
+ uint32_t dwShtim;\r
+ uint32_t dwMr;\r
+\r
+ if (dwAFEClock == 0) return;\r
+ /* Formula for SHTIM is:\r
+ SHTIM = (time x AFECLK) / (1000000000) - 1\r
+ Since 1 billion is close to the maximum value for an integer, we first\r
+ divide AFECLK by 1000 to avoid an overflow */\r
+ dwShtim = (dwNs * (dwAFEClock / 1000)) / 100000;\r
+ if (dwShtim % 10) dwShtim /= 10;\r
+ else\r
+ {\r
+ dwShtim /= 10;\r
+ if (dwShtim) dwShtim --;\r
+ }\r
+ dwMr = AFEC_MR_TRACKTIM(dwShtim);\r
+ dwMr |= pAFE->AFEC_MR & ~AFEC_MR_TRACKTIM_Msk;\r
+ pAFE->AFEC_MR = dwMr;\r
+}\r
+\r
+/**\r
+ * \brief Set analog offset to be used for channel CSEL.\r
+ *\r
+ * \param afec Base address of the AFEC.\r
+ * \param dwChannel AFEC channel number.\r
+ * \param aoffset Analog offset value.\r
+ */\r
+void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset )\r
+{\r
+ assert( dwChannel < 12 ) ;\r
+ pAFE->AFEC_CSELR = dwChannel;\r
+ pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);;\r
+}\r
+\r
+/**\r
+ * \brief Set analog offset to be used for channel CSEL.\r
+ *\r
+ * \param afec Base address of the AFEC.\r
+ * \param control Analog control value.\r
+ */\r
+void AFEC_SetAnalogControl( Afec *pAFE, uint32_t control)\r
+{\r
+ pAFE->AFEC_ACR = control;\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ * Implements functions for Controller Area Network (CAN)\r
+ * peripheral operations.\r
+ */\r
+/** \addtogroup can_module\r
+ *@{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+#if defined(REG_CAN0_MR) || defined(REG_CAN_MR)\r
+\r
+/* ----------- CAN_MR Operations --------------- */\r
+/**\r
+ * \brief Set CAN Mode Register (CAN_MR)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwMr Mode register settings.\r
+ */\r
+void CAN_ConfigureMode(Can *pCan, uint32_t dwMr)\r
+{\r
+ pCan->CAN_MR = dwMr;\r
+}\r
+\r
+/**\r
+ * \brief CAN Controller Enable/Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis 1 to enable and 0 to disable.\r
+ */\r
+void CAN_Enable(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_CANEN;\r
+ else pCan->CAN_MR &= ~CAN_MR_CANEN;\r
+}\r
+\r
+/**\r
+ * \brief CAN Low Power Mode Enable/Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis 1 to enable and 0 to disable.\r
+ */\r
+void CAN_EnableLowPower(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_LPM;\r
+ else pCan->CAN_MR &= ~CAN_MR_LPM;\r
+}\r
+\r
+/**\r
+ * \brief CAN Autobaud/Listen mode\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis 1 to enable and 0 to disable.\r
+ */\r
+void CAN_EnableAutobaud(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_ABM;\r
+ else pCan->CAN_MR &= ~CAN_MR_ABM;\r
+}\r
+\r
+/**\r
+ * \brief CAN Overload Frame Enable/Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis 1 to enable and 0 to disable.\r
+ */\r
+void CAN_EnableOverloadFrame(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_OVL;\r
+ else pCan->CAN_MR &= ~CAN_MR_OVL;\r
+}\r
+\r
+/**\r
+ * \brief CAN Timestamp capture mode (@EOF/@SOF).\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEofSof 1 for EOF/0 for SOF.\r
+ */\r
+void CAN_EnableTimeStampEof(Can *pCan, uint8_t bEofSof)\r
+{\r
+ if (bEofSof) pCan->CAN_MR |= CAN_MR_TEOF;\r
+ else pCan->CAN_MR &= ~CAN_MR_TEOF;\r
+}\r
+\r
+/**\r
+ * \brief CAN Time Triggered Mode Enable/Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis Enable/Disable Time Trigger Mode.\r
+ */\r
+void CAN_EnableTimeTriggerMode(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_TTM;\r
+ else pCan->CAN_MR &= ~CAN_MR_TTM;\r
+}\r
+\r
+/**\r
+ * \brief CAN Timer Freeze Enable/Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis Enable/Disable Timer Freeze.\r
+ */\r
+void CAN_EnableTimerFreeze(Can *pCan, uint8_t bEnDis)\r
+{\r
+ if (bEnDis) pCan->CAN_MR |= CAN_MR_TIMFRZ;\r
+ else pCan->CAN_MR &= ~CAN_MR_TIMFRZ;\r
+}\r
+\r
+/**\r
+ * \brief CAN Repeat Disable/Enable.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bEnDis Disable/Enable Repeat.\r
+ */\r
+void CAN_DisableRepeat(Can *pCan, uint8_t bDisEn)\r
+{\r
+ if (bDisEn) pCan->CAN_MR |= CAN_MR_DRPT;\r
+ else pCan->CAN_MR &= ~CAN_MR_DRPT;\r
+}\r
+\r
+/* ---------- Interrupt settings ------------- */\r
+\r
+/**\r
+ * \brief CAN Interrupts Enable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwSources Interrupt sources bits.\r
+ */\r
+void CAN_EnableIt(Can *pCan, uint32_t dwSources)\r
+{\r
+ pCan->CAN_IER = dwSources;\r
+}\r
+\r
+/**\r
+ * \brief CAN Interrupts Disable\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwSources Interrupt sources bits.\r
+ */\r
+void CAN_DisableIt(Can *pCan, uint32_t dwSources)\r
+{\r
+ pCan->CAN_IDR = dwSources;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Interrupts Masks\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetItMask(Can *pCan)\r
+{\r
+ return pCan->CAN_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Statuses\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetStatus(Can *pCan)\r
+{\r
+ return pCan->CAN_SR;\r
+}\r
+\r
+/**\r
+ * \brief Calculate and configure the baudrate\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwBaudrate Baudrate value (kB/s)\r
+ * allowed: 100, 800, 500, 250, 125, 50, 25, 10\r
+ * \param dwMck MCK.\r
+ * \return 1 in success, otherwise return 0.\r
+ */\r
+uint8_t CAN_CalcBaudrate(Can *pCan, uint32_t dwBaudrate, uint32_t dwMck)\r
+{\r
+ uint32_t BRP, PROPAG, PHASE1, PHASE2, SJW;\r
+ uint8_t TQ;\r
+ uint32_t t1t2;\r
+ uint32_t maxClock;\r
+ uint32_t id = ID_CAN0;\r
+\r
+ if ((uint32_t)pCan == (uint32_t)CAN0) id = ID_CAN0;\r
+ else if ((uint32_t)pCan == (uint32_t)CAN1) id = ID_CAN1;\r
+ maxClock = PMC_SetPeriMaxClock(id, dwMck);\r
+\r
+ if (dwBaudrate >= 1000) TQ = 8;\r
+ else TQ = 16;\r
+ BRP = (maxClock / (dwBaudrate * 1000 * TQ)) - 1;\r
+ if (BRP == 0) {\r
+ return 0;\r
+ }\r
+\r
+ /* Timing delay:\r
+ Delay Bus Driver - 50ns\r
+ Delay Receiver - 30ns\r
+ Delay Bus Line (20m) - 110ns */\r
+ if ( (TQ * dwBaudrate * 2 * (50+30+110)/1000000) >= 1 )\r
+ PROPAG = (TQ * dwBaudrate * 2 * (50+30+110)/1000000) - 1;\r
+ else\r
+ PROPAG = 0;\r
+ t1t2 = TQ - 1 - (PROPAG + 1);\r
+\r
+ if ( (t1t2 & 0x01) == 0x01 ) {\r
+ PHASE1 = ((t1t2 - 1) / 2) - 1;\r
+ PHASE2 = PHASE1 + 1;\r
+ }\r
+ else {\r
+ PHASE1 = ((t1t2) / 2) - 1;\r
+ PHASE2 = PHASE1;\r
+ }\r
+\r
+ if ( 1 > (4/(PHASE1 + 1)) ) SJW = 3;\r
+ else SJW = PHASE1;\r
+\r
+ if ( (PROPAG + PHASE1 + PHASE2) != (uint32_t)(TQ - 4) ) {\r
+ return 0;\r
+ }\r
+\r
+ pCan->CAN_BR = CAN_BR_PHASE2(PHASE2)\r
+ | CAN_BR_PHASE1(PHASE1)\r
+ | CAN_BR_PROPAG(PROPAG)\r
+ | CAN_BR_SJW(SJW)\r
+ | CAN_BR_BRP(BRP)\r
+ | CAN_BR_SMP_ONCE;\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN baudrate register\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwBr Setting value for CAN_BR.\r
+ */\r
+void CAN_ConfigureBaudrate(Can *pCan, uint32_t dwBr)\r
+{\r
+ pCan->CAN_BR = dwBr;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN Sampling Mode\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bAvg3 Sample 3 times/sample once at sample point.\r
+ */\r
+void CAN_SetSamplingMode(Can *pCan, uint8_t bAvg3)\r
+{\r
+ if (bAvg3) pCan->CAN_BR |= CAN_BR_SMP;\r
+ else pCan->CAN_BR &= ~CAN_BR_SMP;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Timer Register\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetTimer(Can *pCan)\r
+{\r
+ return pCan->CAN_TIM;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN TimeStamp Register\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetTimestamp(Can *pCan)\r
+{\r
+ return pCan->CAN_TIMESTP;\r
+}\r
+\r
+/**\r
+ * \brief Return Error Count (TEC << 16) + REC\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetErrorCount(Can *pCan)\r
+{\r
+ return pCan->CAN_ECR;\r
+}\r
+\r
+/**\r
+ * \brief Return Receive Error Count\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetRxErrorCount(Can *pCan)\r
+{\r
+ return (pCan->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos;\r
+}\r
+\r
+/**\r
+ * \brief Return Transmit Error Count\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+uint32_t CAN_GetTxErrorCount(Can *pCan)\r
+{\r
+ return (pCan->CAN_ECR & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos;\r
+}\r
+\r
+/**\r
+ * \brief Set Transfer Command Register to initialize transfer requests.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwRequests Transfer Command Requests.\r
+ */\r
+void CAN_Command(Can *pCan, uint32_t dwRequests)\r
+{\r
+ pCan->CAN_TCR = dwRequests;\r
+}\r
+\r
+/**\r
+ * \brief Resets CAN internal timer counter.\r
+ * \param pCan Pointer to Can instance.\r
+ */\r
+void CAN_ResetTimer(Can *pCan)\r
+{\r
+ pCan->CAN_TCR = CAN_TCR_TIMRST;\r
+}\r
+\r
+/**\r
+ * \brief Request transfer on mailbox.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_Tx(Can *pCan, uint8_t bMb)\r
+{\r
+ pCan->CAN_TCR = CAN_TCR_MB0 << bMb;\r
+}\r
+\r
+/**\r
+ * \brief Abort transfer on several mailboxes.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param dwAborts Abort requests.\r
+ */\r
+void CAN_Abort(Can *pCan, uint32_t dwAborts)\r
+{\r
+ pCan->CAN_ACR = dwAborts;\r
+}\r
+\r
+/**\r
+ * \brief Abort transfer on single mailbox.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_AbortMailbox(Can *pCan, uint8_t bMb)\r
+{\r
+ pCan->CAN_ACR = CAN_ACR_MB0 << bMb;\r
+}\r
+\r
+/**\r
+ * \brief Configure CAN Message Mode (_MMRx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMr Mode settings.\r
+ */\r
+void CAN_ConfigureMessageMode(Can *pCan, uint8_t bMb, uint32_t dwMr)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MMR = dwMr;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Mode (_MMRx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageMode(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MMR;\r
+}\r
+\r
+/**\r
+ * \brief Set Mailbox Timemark for Time Triggered Mode.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bTimemarks Mailbox timemarks.\r
+ */\r
+void CAN_SetTimemark(Can *pCan, uint8_t bMb, uint8_t bTimemarks)\r
+{\r
+ uint32_t dwMmr = (pCan->CAN_MB[bMb].CAN_MMR) & (~0xFFu);\r
+ pCan->CAN_MB[bMb].CAN_MMR = dwMmr | ((bTimemarks << 0) & 0xFF);\r
+}\r
+\r
+/**\r
+ * \brief Set Mailbox Priority.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bPriority Mailbox Priority.\r
+ */\r
+void CAN_SetPriority(Can *pCan, uint8_t bMb, uint8_t bPriority)\r
+{\r
+ uint32_t dwMmr = (pCan->CAN_MB[bMb].CAN_MMR & ~CAN_MMR_PRIOR_Msk);\r
+ pCan->CAN_MB[bMb].CAN_MMR = dwMmr | CAN_MMR_PRIOR(bPriority);\r
+}\r
+\r
+/**\r
+ * \brief Set Mailbox Object Type.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bType Mailbox Object Type.\r
+ */\r
+void CAN_SetObjectType(Can *pCan, uint8_t bMb, uint8_t bType)\r
+{\r
+ uint32_t dwMr = (pCan->CAN_MB[bMb].CAN_MMR & CAN_MMR_MOT_Msk) >> CAN_MMR_MOT_Pos;\r
+ pCan->CAN_MB[bMb].CAN_MMR |= dwMr | ((bType << CAN_MMR_MOT_Pos) & CAN_MMR_MOT_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Configure CAN Message Acceptance Mask (_MAMx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMam The setting value for _MAMx.\r
+ */\r
+void CAN_ConfigureMessageAcceptanceMask(Can *pCan, uint8_t bMb, uint32_t dwMAM)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MAM = dwMAM;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Acceptance Mask (_MAMx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageAcceptanceMask(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MAM;\r
+}\r
+\r
+/**\r
+ * \brief Configure Identifier Version in CAN Message Acceptance Mask (_MAMx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bIdCfg IDvA and IDvB/IDvA only Identify.\r
+ */\r
+void CAN_ConfigureIdentifierMask(Can *pCan, uint8_t bMb, uint8_t bIdCfg)\r
+{\r
+ if (bIdCfg) pCan->CAN_MB[bMb].CAN_MAM |= CAN_MAM_MIDE;\r
+ else pCan->CAN_MB[bMb].CAN_MAM &= ~CAN_MAM_MIDE;\r
+}\r
+\r
+/**\r
+ * \brief Set Identifier for standard frame mode (MIDvA) mask\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMIDvA Identifier for standard frame mode.\r
+ */\r
+void CAN_SetMIDvAMask(Can *pCan, uint8_t bMb, uint32_t dwIDvA)\r
+{\r
+ uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MAM & CAN_MAM_MIDvA_Msk;\r
+ pCan->CAN_MB[bMb].CAN_MAM = dwMam | CAN_MAM_MIDvA(dwIDvA);\r
+}\r
+\r
+/**\r
+ * \brief Set Complementary bits for identifier in extended frame mode (MIDvB) mask\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMIDvB Identifier for extended frame mode.\r
+ */\r
+void CAN_SetMIDvBMask(Can *pCan, uint8_t bMb, uint32_t dwIDvA)\r
+{\r
+ uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MAM & CAN_MAM_MIDvB_Msk;\r
+ pCan->CAN_MB[bMb].CAN_MAM = dwMam | CAN_MAM_MIDvB(dwIDvA);\r
+}\r
+\r
+/**\r
+ * \brief Configure CAN Message ID (_MIDx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMID The setting value for _MIDx.\r
+ */\r
+void CAN_ConfigureMessageID(Can *pCan, uint8_t bMb, uint32_t dwMID)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MID = dwMID;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message ID (_MIDx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageID(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MID;\r
+}\r
+\r
+/**\r
+ * \brief Configure Identifier Version in CAN Message ID register (_MIDx)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bIdVer 2.0 Part B/2.0 Part A.\r
+ */\r
+void CAN_ConfigureIdVer(Can *pCan, uint8_t bMb, uint8_t bIdVer)\r
+{\r
+ uint32_t dwMid = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDE;\r
+ pCan->CAN_MB[bMb].CAN_MID = dwMid | (bIdVer ? CAN_MID_MIDE : 0);\r
+}\r
+\r
+/**\r
+ * \brief Set Identifier for standard frame mode (MIDvA) value\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMIDvA Identifier for standard frame mode.\r
+ */\r
+void CAN_SetMIDvA(Can *pCan, uint8_t bMb, uint32_t dwIDvA)\r
+{\r
+ uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDvA_Msk;\r
+ pCan->CAN_MB[bMb].CAN_MID = dwMam | CAN_MID_MIDvA(dwIDvA);\r
+}\r
+\r
+/**\r
+ * \brief Set Complementary bits for identifier in extended frame mode (MIDvB) value\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwMIDvB Identifier for extended frame mode.\r
+ */\r
+void CAN_SetMIDvB(Can *pCan, uint8_t bMb, uint32_t dwIDvA)\r
+{\r
+ uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDvB_Msk;\r
+ pCan->CAN_MB[bMb].CAN_MID = dwMam | CAN_MID_MIDvB(dwIDvA);\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Family ID (Masked ID)\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetFamilyID(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MFID;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Status\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageStatus(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MSR;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Data Low\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageDataL(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MDL;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN Message Data Low\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwL Data Low Value.\r
+ */\r
+void CAN_SetMessageDataL(Can *pCan, uint8_t bMb, uint32_t dwL)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MDL = dwL;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN Message Data High\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwH Data High Value.\r
+ */\r
+void CAN_SetMessageDataH(Can *pCan, uint8_t bMb, uint32_t dwH)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MDH = dwH;\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Data High\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint32_t CAN_GetMessageDataH(Can *pCan, uint8_t bMb)\r
+{\r
+ return pCan->CAN_MB[bMb].CAN_MDH;\r
+}\r
+\r
+/**\r
+ * \brief Copy DW array to CAN Message Data.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param pDwData Pointer to a buffer for data.\r
+ */\r
+void CAN_SetMessage(Can *pCan, uint8_t bMb, uint32_t *pDwData)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MDL = pDwData[0];\r
+ pCan->CAN_MB[bMb].CAN_MDH = pDwData[1];\r
+}\r
+\r
+/**\r
+ * \brief Copy CAN Message Data to DW array.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param pDwData Pointer to a buffer for data.\r
+ */\r
+void CAN_GetMessage(Can *pCan, uint8_t bMb, uint32_t *pDwData)\r
+{\r
+ pDwData[0] = pCan->CAN_MB[bMb].CAN_MDL;\r
+ pDwData[1] = pCan->CAN_MB[bMb].CAN_MDH;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN Message Data in u64\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_SetMessageData64(Can *pCan, uint8_t bMb, uint64_t u64)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MDL = (uint32_t)u64;\r
+ pCan->CAN_MB[bMb].CAN_MDH = (u64 >> 32);\r
+}\r
+\r
+/**\r
+ * \brief Return CAN Message Data in u64\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+uint64_t CAN_GetMessageData64(Can *pCan, uint8_t bMb)\r
+{\r
+ uint64_t ddwMd = (uint64_t)pCan->CAN_MB[bMb].CAN_MDH << 32;\r
+ ddwMd += pCan->CAN_MB[bMb].CAN_MDL;\r
+ return ddwMd;\r
+}\r
+\r
+/**\r
+ * \brief Set CAN Message Control Register (_MCRx).\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param dwCtrl Control value.\r
+ */\r
+void CAN_MessageControl(Can *pCan, uint8_t bMb, uint32_t dwCtrl)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MCR = dwCtrl;\r
+}\r
+\r
+/**\r
+ * \brief Start remote frame.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_MessageRemote(Can *pCan, uint8_t bMb)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MRTR;\r
+}\r
+\r
+/**\r
+ * \brief Abort transmission.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_MessageAbort(Can *pCan, uint8_t bMb)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MACR;\r
+}\r
+\r
+/**\r
+ * \brief Start transmission.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ * \param bLen Message length.\r
+ */\r
+void CAN_MessageTx(Can *pCan, uint8_t bMb, uint8_t bLen)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MTCR | CAN_MCR_MDLC(bLen);\r
+}\r
+\r
+/**\r
+ * \brief Start reception.\r
+ * \param pCan Pointer to Can instance.\r
+ * \param bMb Mailbox number.\r
+ */\r
+void CAN_MessageRx(Can *pCan, uint8_t bMb)\r
+{\r
+ pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MTCR;\r
+}\r
+\r
+#endif\r
+/**@}*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup dacc_module Working with DACC\r
+ * \ingroup peripherals_module\r
+ * The DACC driver provides the interface to configure and use the DACC peripheral.\n\r
+ *\r
+ * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output.\r
+ * The data to be converted are sent in a common register for all channels. It offers up to 2\r
+ * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.\r
+ *\r
+ * To Enable a DACC conversion,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Select an appropriate reference voltage on ADVREF </li>\r
+ * <li> Configure the DACC according to its requirements and special needs,which could be\r
+ broken down into several parts:\r
+ * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR;\r
+ * -# Configure Refresh Period through setting REFRESH fields\r
+ * in DACC_MR; The refresh mechanism is used to protect the output analog value from\r
+ * decreasing.\r
+ * -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion\r
+ * is started right after at least one channel is enabled and data is written .\r
+ </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the DACC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref DACC.c\n\r
+ * \ref DACC.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Digital-to-Analog Converter Controller (DACC).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/* DMA driver instance */\r
+static uint32_t dacDmaTxChannel;\r
+static LinkedListDescriporView1 dmaWriteLinkList[256];\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configure the DMA Channels: 0 RX.\r
+ * Channels are disabled after configure.\r
+ * \returns 0 if the dma channel configuration successfully; otherwise returns\r
+ * DAC_ERROR_XXX.\r
+ */\r
+static uint8_t _DacConfigureDmaChannels( DacDma* pDacd )\r
+{\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pDacd->pXdmad, 0 );\r
+\r
+ XDMAD_FreeChannel( pDacd->pXdmad, dacDmaTxChannel);\r
+\r
+ /* Allocate a DMA channel for DAC0/1 TX. */\r
+ dacDmaTxChannel = XDMAD_AllocateChannel( pDacd->pXdmad, XDMAD_TRANSFER_MEMORY, ID_DACC);\r
+ {\r
+ if ( dacDmaTxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return DAC_ERROR;\r
+ }\r
+ }\r
+ if ( XDMAD_PrepareChannel( pDacd->pXdmad, dacDmaTxChannel )) \r
+ return DAC_ERROR;\r
+ return DAC_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the DMA source and destination with Linker List mode.\r
+ *\r
+ * \param pBuffer Pointer to dac buffer\r
+ * \param size length of buffer\r
+ */\r
+\r
+static uint8_t _Dac_configureLinkList(Dacc *pDacHw, void *pXdmad, DacCmd *pCommand)\r
+{\r
+ uint32_t xdmaCndc;\r
+ sXdmadCfg xdmadCfg;\r
+ uint32_t * pBuffer;\r
+ /* Setup TX Link List */\r
+ uint8_t i;\r
+ pBuffer = (uint32_t *)pCommand->pTxBuff;\r
+ for(i = 0; i < pCommand->TxSize; i++){\r
+ dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ | XDMA_UBC_NDE_FETCH_EN\r
+ | XDMA_UBC_NSEN_UPDATED\r
+ | XDMAC_CUBC_UBLEN(4);\r
+ dmaWriteLinkList[i].mbr_sa = (uint32_t)pBuffer;\r
+ dmaWriteLinkList[i].mbr_da = (uint32_t)&(pDacHw->DACC_CDR[pCommand->dacChannel]);\r
+ if ( i == (pCommand->TxSize - 1 )) {\r
+ if (pCommand->loopback) {\r
+ dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[0];\r
+ }\r
+ else {\r
+ dmaWriteLinkList[i].mbr_nda = 0;\r
+ }\r
+ } else {\r
+ dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[i+1];\r
+ }\r
+ pBuffer++;\r
+ }\r
+ xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_MEM2PER \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_WORD\r
+ | XDMAC_CC_SIF_AHB_IF0 \r
+ | XDMAC_CC_DIF_AHB_IF1 \r
+ | XDMAC_CC_SAM_INCREMENTED_AM \r
+ | XDMAC_CC_DAM_FIXED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_DACC, XDMAD_TRANSFER_TX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;\r
+ XDMAD_ConfigureTransfer( pXdmad, dacDmaTxChannel, &xdmadCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0]);\r
+ return DAC_OK;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Initializes the DacDma structure and the corresponding DAC & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX .\r
+ * The DMA channels are freed automatically when no DMA command processing.\r
+ *\r
+ * \param pDacd Pointer to a DacDma instance.\r
+ * \param pDacHw Associated Dac peripheral.\r
+ * \param DacId Dac peripheral identifier.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t Dac_ConfigureDma( DacDma *pDacd ,\r
+ Dacc *pDacHw ,\r
+ uint8_t DacId,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the Dac structure */\r
+ pDacd->pDacHw = pDacHw;\r
+ pDacd->dacId = DacId;\r
+ pDacd->semaphore = 1;\r
+ pDacd->pCurrentCommand = 0;\r
+ pDacd->pXdmad = pXdmad;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a DAC transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pDacd Pointer to a DacDma instance.\r
+ * \param pCommand Pointer to the Dac command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * DAC_ERROR_LOCK is the driver is in use, or DAC_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand)\r
+{\r
+ Dacc *pDacHw = pDacd->pDacHw;\r
+\r
+ /* Try to get the dataflash semaphore */\r
+ if (pDacd->semaphore == 0) {\r
+\r
+ return DAC_ERROR_LOCK;\r
+ }\r
+ pDacd->semaphore--;\r
+\r
+ // Initialize the callback\r
+ pDacd->pCurrentCommand = pCommand;\r
+\r
+ /* Initialize DMA controller using channel 0 for RX. */\r
+ if (_DacConfigureDmaChannels(pDacd) )\r
+ return DAC_ERROR_LOCK;\r
+\r
+ if (_Dac_configureLinkList(pDacHw, pDacd->pXdmad, pCommand))\r
+ return DAC_ERROR_LOCK;\r
+\r
+\r
+ /* Start DMA TX */\r
+ if (XDMAD_StartTransfer( pDacd->pXdmad, dacDmaTxChannel )) \r
+ return DAC_ERROR_LOCK;\r
+ return DAC_OK;;\r
+}\r
+\r
+\r
+\r
+#if 0\r
+\r
+/* DMA driver instance */\r
+static uint32_t dacDmaTxChannel;\r
+\r
+/** Global DMA driver for all transfer */\r
+static sXdmad dacDma;\r
+\r
+#define MAX_LINKER_LIST 256\r
+/** DMA Linker list descriptors */\r
+static LinkedListDescriporView1 dmaWriteLinkList[MAX_LINKER_LIST];\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * Set the Conversion Data\r
+ * \param pDACC Pointer to an Dacc instance.\r
+ * \param dwData date to be converted.\r
+ * \param channel Channel number\r
+ */\r
+extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData, uint32_t channel)\r
+{\r
+ pDACC->DACC_CDR[channel] = dwData ;\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA TX Channel .\r
+ * Channels are disabled after configure.\r
+ * \returns 0 if the dma channel configuration successfully; otherwise returns\r
+ * UARTD_ERROR_XXX.\r
+ */\r
+uint8_t dacConfigureDmaChannel(void)\r
+{\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( &dacDma, 0 );\r
+\r
+ /* Allocate a DMA channel for DAC TX. */\r
+ dacDmaTxChannel = XDMAD_AllocateChannel( &dacDma, XDMAD_TRANSFER_MEMORY, ID_DACC);\r
+ {\r
+ if ( dacDmaTxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return UARTD_ERROR;\r
+ }\r
+ }\r
+ if ( XDMAD_PrepareChannel( &dacDma, dacDmaTxChannel ))\r
+ return UARTD_ERROR;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA source and destination with Linker List mode.\r
+ *\r
+ * \param pBuffer Pointer to DAC buffer\r
+ * \param len length of buffer\r
+ * \param loopback 1: loopback, 0: fixed length of LLI\r
+ * \param channel Channel number\r
+ */\r
+uint8_t dacConfigureLinkList(Dacc *pDACC, uint32_t *pBuffer, uint32_t len, uint32_t loopback, uint32_t channel)\r
+{\r
+ uint8_t i;\r
+ uint32_t xdmaCndc;\r
+ sXdmadCfg xdmadCfg;\r
+ assert (len < MAX_LINKER_LIST);\r
+ for(i = 0; i < len; i++){\r
+ dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ | XDMA_UBC_NDE_FETCH_EN\r
+ | XDMA_UBC_NSEN_UPDATED\r
+ | XDMAC_CUBC_UBLEN(4);\r
+ dmaWriteLinkList[i].mbr_sa = (uint32_t)(pBuffer);\r
+ dmaWriteLinkList[i].mbr_da = (uint32_t)&(pDACC->DACC_CDR[channel]);\r
+ if ( i == (len - 1 )) {\r
+ if (loopback) {\r
+ dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[0];\r
+ }\r
+ else {\r
+ dmaWriteLinkList[i].mbr_nda = 0;\r
+ }\r
+ } else {\r
+ dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[i+1];\r
+ }\r
+ pBuffer++;\r
+ }\r
+ xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_MEM2PER \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_WORD\r
+ | XDMAC_CC_SIF_AHB_IF0 \r
+ | XDMAC_CC_DIF_AHB_IF1 \r
+ | XDMAC_CC_SAM_INCREMENTED_AM \r
+ | XDMAC_CC_DAM_FIXED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_DACC, XDMAD_TRANSFER_TX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;\r
+ XDMAD_ConfigureTransfer( &dacDma, dacDmaTxChannel, &xdmadCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0]);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Start DMA transfer.\r
+ *\r
+ * \param channel Channel number\r
+ */\r
+void dacStartConvert(Dacc *pDACC, uint32_t channel)\r
+{\r
+ XDMAD_StartTransfer( &dacDma, dacDmaTxChannel);\r
+\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup dacc_module Working with DACC\r
+ * \ingroup peripherals_module\r
+ * The DACC driver provides the interface to configure and use the DACC peripheral.\n\r
+ *\r
+ * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output.\r
+ * The data to be converted are sent in a common register for all channels. It offers up to 2\r
+ * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.\r
+ *\r
+ * To Enable a DACC conversion,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Select an appropriate reference voltage on ADVREF </li>\r
+ * <li> Configure the DACC according to its requirements and special needs,which could be\r
+ broken down into several parts:\r
+ * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR;\r
+ * -# Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields\r
+ * in DACC_MR; The refresh mechanism is used to protect the output analog value from\r
+ * decreasing.\r
+ * -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion\r
+ * is started right after at least one channel is enabled and data is written .\r
+ </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the DACC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref DACC.c\n\r
+ * \ref DACC.h\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Digital-to-Analog Converter Controller (DACC).\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize the DACC controller\r
+ * \param pDACC Pointer to an DACC instance.\r
+ * \param idDACC identifier of DAC peripheral\r
+ * \param trgEn trigger mode, free running mode or external Hardware trigger\r
+ * \param word transfer size,word or half word\r
+ * \param trgSel hardware trigger selection\r
+ * \param sleepMode sleep mode selection\r
+ * \param mck value of MCK in Hz\r
+ * \param refresh refresh period\r
+ * \param user_sel user channel selection ,0 or 1\r
+ * \param tag_mode tag for channel number\r
+ * \param startup value of the start up time (in DACCClock) (see datasheet)\r
+*/\r
+extern void DACC_Initialize( Dacc* pDACC,\r
+ uint8_t idDACC,\r
+ uint8_t trgEn,\r
+ uint8_t trgSel,\r
+ uint8_t word,\r
+ uint8_t sleepMode,\r
+ uint32_t mck,\r
+ uint8_t refresh, /* refresh period */\r
+ uint8_t user_sel, /* user channel selection */\r
+ uint32_t tag_mode, /* using tag for channel number */\r
+ uint32_t startup\r
+ )\r
+{\r
+ /* Stop warning */\r
+ mck = mck;\r
+\r
+ /* Enable peripheral clock*/\r
+ PMC->PMC_PCER0 = 1 << idDACC;\r
+\r
+ /* Reset the controller */\r
+ DACC_SoftReset(pDACC);\r
+\r
+ /* Write to the MR register */\r
+ DACC_CfgModeReg( pDACC,\r
+ ( trgEn & DACC_MR_TRGEN)\r
+ | DACC_MR_TRGSEL(trgSel)\r
+ | ( word & DACC_MR_WORD)\r
+ | ( sleepMode & DACC_MR_SLEEP)\r
+ | DACC_MR_REFRESH(refresh)\r
+ | ( user_sel & DACC_MR_USER_SEL_Msk)\r
+ | ( tag_mode & DACC_MR_TAG)\r
+ | ( startup & DACC_MR_STARTUP_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * Set the Conversion Data\r
+ * \param pDACC Pointer to an Dacc instance.\r
+ * \param data date to be converted.\r
+ */\r
+extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData )\r
+{\r
+ uint32_t dwMR = pDACC->DACC_MR ;\r
+\r
+ if ( dwMR & DACC_MR_WORD )\r
+ {\r
+ pDACC->DACC_CDR = dwData ;\r
+ }\r
+ else\r
+ {\r
+ pDACC->DACC_CDR = (dwData&0xFFFF) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Write converted data through PDC channel\r
+ * \param pDACC the pointer of DACC peripheral\r
+ * \param pBuffer the destination buffer\r
+ * \param size the size of the buffer\r
+*/\r
+extern uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t *pwBuffer, uint32_t dwSize )\r
+{\r
+\r
+ /* Check if the first PDC bank is free*/\r
+ if ( (pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0) )\r
+ {\r
+ pDACC->DACC_TPR = (uint32_t)pwBuffer ;\r
+ pDACC->DACC_TCR = dwSize ;\r
+ pDACC->DACC_PTCR = DACC_PTCR_TXTEN ;\r
+\r
+ return 1 ;\r
+ }\r
+ /* Check if the second PDC bank is free*/\r
+ else\r
+ {\r
+ if (pDACC->DACC_TNCR == 0)\r
+ {\r
+ pDACC->DACC_TNPR = (uint32_t)pwBuffer ;\r
+ pDACC->DACC_TNCR = dwSize ;\r
+\r
+ return 1 ;\r
+ }\r
+ else\r
+ {\r
+ return 0 ;\r
+ }\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup efc_module Working with EEFC\r
+ * \ingroup peripherals_module\r
+ * The EEFC driver provides the interface to configure and use the EEFC\r
+ * peripheral.\r
+ *\r
+ * The user needs to set the number of wait states depending on the frequency used.\n\r
+ * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR.\r
+ *\r
+ * It offers a function to send flash command to EEFC and waits for the\r
+ * flash to be ready.\r
+ *\r
+ * To send flash command, the user could do in either of following way:\r
+ * <ul>\r
+ * <li>Write a correct key, command and argument in EEFC_FCR. </li>\r
+ * <li>Or, Use IAP (In Application Programming) function which is executed from\r
+ * ROM directly, this allows flash programming to be done by code running in flash.</li>\r
+ * <li>Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt.\r
+ * </ul>\r
+ *\r
+ * The command argument could be a page number,GPNVM number or nothing, it depends on\r
+ * the command itself. Some useful functions in this driver could help user tranlate physical\r
+ * flash address into a page number and vice verse.\r
+ *\r
+ * For more accurate information, please look at the EEFC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref efc.c\n\r
+ * \ref efc.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Enhanced Embedded Flash Controller (EEFC).\r
+ *\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void EFC_WriteFMR( Efc* efc, uint32_t dwFmr );\r
+\r
+#ifdef __ICCARM__\r
+extern __ramfunc void EFC_WriteFMR( Efc* efc, uint32_t dwFmr )\r
+#else\r
+__attribute__ ((section (".ramfunc")))\r
+extern void EFC_WriteFMR( Efc* efc, uint32_t dwFmr )\r
+#endif\r
+{\r
+ efc->EEFC_FMR = dwFmr;\r
+}\r
+\r
+/**\r
+ * \brief Enables the flash ready interrupt source on the EEFC peripheral.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ */\r
+extern void EFC_EnableFrdyIt( Efc* efc )\r
+{\r
+ uint32_t dwFmr;\r
+\r
+ dwFmr = efc->EEFC_FMR |= EEFC_FMR_FRDY;\r
+ EFC_WriteFMR(efc, dwFmr);\r
+}\r
+\r
+/**\r
+ * \brief Disables the flash ready interrupt source on the EEFC peripheral.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ */\r
+extern void EFC_DisableFrdyIt( Efc* efc )\r
+{\r
+ uint32_t dwFmr;\r
+\r
+ dwFmr = efc->EEFC_FMR & (~EEFC_FMR_FRDY);\r
+ EFC_WriteFMR(efc, dwFmr);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Set read/write wait state on the EEFC perpherial.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ * \param cycles the number of wait states in cycle.\r
+ */\r
+extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles )\r
+{\r
+ uint32_t dwFmr ;\r
+\r
+ dwFmr = efc->EEFC_FMR ;\r
+ dwFmr &= ~((uint32_t)EEFC_FMR_FWS_Msk) ;\r
+ dwFmr |= EEFC_FMR_FWS(ucCycles);\r
+ EFC_WriteFMR(efc, dwFmr);\r
+}\r
+\r
+/**\r
+ * \brief Returns the current status of the EEFC.\r
+ *\r
+ * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE).\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ */\r
+extern uint32_t EFC_GetStatus( Efc* efc )\r
+{\r
+ return efc->EEFC_FSR ;\r
+}\r
+\r
+/**\r
+ * \brief Returns the result of the last executed command.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ */\r
+extern uint32_t EFC_GetResult( Efc* efc )\r
+{\r
+ return efc->EEFC_FRR ;\r
+}\r
+\r
+/**\r
+ * \brief Translates the given address page and offset values.\r
+ * \note The resulting values are stored in the provided variables if they are not null.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ * \param address Address to translate.\r
+ * \param pPage First page accessed.\r
+ * \param pOffset Byte offset in first page.\r
+ */\r
+extern void EFC_TranslateAddress( Efc** ppEfc, uint32_t dwAddress, uint16_t* pwPage, uint16_t* pwOffset )\r
+{\r
+ assert( dwAddress >= IFLASH_ADDR ) ;\r
+ assert( dwAddress <= (IFLASH_ADDR + IFLASH_SIZE) ) ;\r
+\r
+ /* Store values */\r
+ if ( ppEfc )\r
+ {\r
+ *ppEfc = EFC ;\r
+ }\r
+\r
+ if ( pwPage )\r
+ {\r
+ *pwPage = (dwAddress - IFLASH_ADDR) / IFLASH_PAGE_SIZE ;\r
+ }\r
+\r
+ if ( pwOffset )\r
+ {\r
+ *pwOffset = (dwAddress - IFLASH_ADDR) % IFLASH_PAGE_SIZE; ;\r
+ }\r
+}\r
+ \r
+\r
+/**\r
+ * \brief Computes the address of a flash access given the page and offset.\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ * \param page Page number.\r
+ * \param offset Byte offset inside page.\r
+ * \param pAddress Computed address (optional).\r
+ */\r
+extern void EFC_ComputeAddress( Efc *efc, uint16_t wPage, uint16_t wOffset, uint32_t *pdwAddress )\r
+{\r
+ uint32_t dwAddress ;\r
+\r
+ /* Stop warning */\r
+ efc = efc;\r
+\r
+ assert( efc ) ;\r
+ assert( wPage <= IFLASH_NB_OF_PAGES ) ;\r
+ assert( wOffset < IFLASH_PAGE_SIZE ) ;\r
+ dwAddress = IFLASH_ADDR + wPage * IFLASH_PAGE_SIZE + wOffset ;\r
+\r
+ /* Store result */\r
+ if ( pdwAddress != NULL )\r
+ {\r
+ *pdwAddress = dwAddress ;\r
+ }\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Performs the given command and wait until its completion (or an error).\r
+ *\r
+ * \param efc Pointer to a Efc instance\r
+ * \param command Command to perform.\r
+ * \param argument Optional command argument.\r
+ *\r
+ * \return 0 if successful, otherwise returns an error code.\r
+ */\r
+\r
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument, uint32_t dwUseIAP )\r
+{\r
+ if ( dwUseIAP != 0 )\r
+ {\r
+ /* Pointer on IAP function in ROM */\r
+ static uint32_t (*IAP_PerformCommand)( uint32_t, uint32_t ) ;\r
+\r
+ IAP_PerformCommand = (uint32_t (*)( uint32_t, uint32_t )) *((uint32_t*)CHIP_FLASH_IAP_ADDRESS ) ;\r
+ if (efc == EFC) {\r
+ IAP_PerformCommand( 0, EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ) ;\r
+ }\r
+ return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)) ;\r
+ }\r
+ else\r
+ {\r
+ uint32_t dwStatus ;\r
+\r
+ efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ;\r
+ do\r
+ {\r
+ dwStatus = efc->EEFC_FSR ;\r
+ }\r
+ while ( (dwStatus & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ;\r
+\r
+ return ( dwStatus & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) ) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set flash access mode.\r
+ *\r
+ * \param dwMode - 0:128-bit, (1<<24):64-bit\r
+ */\r
+extern void EFC_SetFlashAccessMode(Efc* efc, uint32_t dwMode)\r
+{\r
+ uint32_t dwFmr;\r
+\r
+ dwFmr = (efc->EEFC_FMR & (~EEFC_FMR_FAM)) | dwMode;\r
+ EFC_WriteFMR(efc, dwFmr);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * This file contains the default exception handlers.\r
+ *\r
+ * \note\r
+ * The exception handler has weak aliases.\r
+ * As they are weak aliases, any function with the same name will override\r
+ * this definition.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Flag to indicate whether the svc is done */\r
+volatile uint32_t dwRaisePriDone=0;\r
+\r
+/**\r
+ * \brief Default NMI interrupt handler.\r
+ */\r
+void NMI_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+__INLINE static uint32_t StackUnwind(void)\r
+{\r
+ uint32_t Fault_Add;\r
+ asm volatile (" mrs r0, msp " );\r
+ asm volatile (" ldr %0, [r0,#28]" :"=r" (Fault_Add)); \r
+ return Fault_Add;\r
+}\r
+\r
+static void HardFault_reason(void)\r
+{\r
+ uint32_t CFSRValue, BFAR;\r
+ printf("In Hard Fault Handler\n\r");\r
+ printf("SCB->HFSR = 0x%08x\n\r", SCB->HFSR);\r
+\r
+ if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk)) {\r
+ printf("Debug Event Hard Fault\n\r");\r
+ printf("SCB->DFSR = 0x%08x\n", SCB->DFSR );\r
+ }\r
+\r
+ if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk)) {\r
+ printf("Fault was due to vector table read on exception processing\n\r"); \r
+ }\r
+\r
+ if ((SCB->HFSR & SCB_HFSR_FORCED_Msk)) {\r
+ printf("Forced Hard Fault\n\r");\r
+ printf("SCB->CFSR = 0x%08x\n\r", SCB->CFSR );\r
+ // Usage Fault\r
+ if((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk)) \r
+ {\r
+ CFSRValue = SCB->CFSR;\r
+ printf("Usage fault: ");\r
+ CFSRValue >>= SCB_CFSR_USGFAULTSR_Pos; \r
+ if((CFSRValue & (1 << 9))) {\r
+ printf("Divide by zero\n\r");\r
+ }\r
+ if((CFSRValue & (1 << 8))) {\r
+ printf("Unaligned access error\n\r");\r
+ }\r
+ if((CFSRValue & (1 << 3))) {\r
+ printf("Coprocessor access error\n\r");\r
+ }\r
+ if((CFSRValue & (1 << 2))) {\r
+ printf("Integrity check error on EXC_RETURN\n\r");\r
+ }\r
+ }\r
+\r
+ // Bus Fault\r
+ if((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk)) \r
+ {\r
+ CFSRValue = SCB->CFSR;\r
+ printf("Bus fault: ");\r
+ CFSRValue >>= SCB_CFSR_BUSFAULTSR_Pos; \r
+\r
+ if((CFSRValue & (1 << 7)) && (CFSRValue & (1 << 1))) {\r
+ BFAR = SCB->BFAR;\r
+ printf("Precise data access error. Bus Fault Address Register is: %x \n\r", BFAR );\r
+ }\r
+ if((CFSRValue & (1 << 4))) {\r
+ printf("Bus fault has occurred on exception entry\n\r");\r
+ }\r
+ if((CFSRValue & (1 << 3))) {\r
+ printf("bus fault has occurred on exception return\n\r");\r
+ }\r
+ if((CFSRValue & (1 << 2))) {\r
+ printf("Imprecise data access error\n\r");\r
+ }\r
+\r
+ if((CFSRValue & (1 << 0))) {\r
+ printf("This bit indicates a bus fault on an instruction prefetch. \n\r");\r
+ }\r
+\r
+ }\r
+ }\r
+\r
+ // MemoryFault \r
+ if((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk)) \r
+ {\r
+ CFSRValue = SCB->CFSR;\r
+ printf("Memory fault: ");\r
+ CFSRValue >>= SCB_CFSR_MEMFAULTSR_Pos; \r
+ if((CFSRValue & (1 << 9)) != 0) {\r
+ printf("Divide by zero\n\r");\r
+ }\r
+ }\r
+ __ISB();\r
+ __DMB();\r
+ __ASM volatile("BKPT #01"); \r
+}\r
+/**\r
+ * \brief Default HardFault interrupt handler.\r
+ */\r
+\r
+void HardFault_Handler( void )\r
+{\r
+\r
+ printf("HardFault at addr 0X%x\n\r", StackUnwind());\r
+\r
+ __ISB();\r
+ __DMB();\r
+ HardFault_reason();\r
+\r
+}\r
+\r
+/**\r
+ * \brief Default MemManage interrupt handler.\r
+ */\r
+void MemManage_Handler( void )\r
+{\r
+ printf("MemoryMemFault (MPU fault) at addr 0X%x\n\r", StackUnwind());\r
+\r
+ __ISB();\r
+ __DMB();\r
+ __ASM volatile("BKPT #01"); \r
+}\r
+\r
+/**\r
+ * \brief Default BusFault interrupt handler.\r
+ */\r
+void BusFault_Handler( void )\r
+{\r
+ asm("nop");\r
+ asm("nop");\r
+ printf("Bus Fault at addr 0X%x\n\r", StackUnwind());\r
+\r
+ __ISB();\r
+ __DMB();\r
+ __ASM volatile("BKPT #01"); \r
+}\r
+\r
+/**\r
+ * \brief Default UsageFault interrupt handler.\r
+ */\r
+void UsageFault_Handler( void )\r
+{\r
+ printf("Usage fault at addr 0X%x", StackUnwind());\r
+\r
+ __ISB();\r
+ __DMB();\r
+ __ASM volatile("BKPT #01"); \r
+}\r
+\r
+/**\r
+ * \brief Default SVC interrupt handler.\r
+ */\r
+WEAK void SVC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default DebugMon interrupt handler.\r
+ */\r
+WEAK void DebugMon_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default PendSV interrupt handler.\r
+ */\r
+void PendSV_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SysTick interrupt handler.\r
+ */\r
+WEAK void SysTick_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for Supply Controller.\r
+ */\r
+WEAK void SUPC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for Reset Controller.\r
+ */\r
+WEAK void RSTC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for Real Time Clock.\r
+ */\r
+WEAK void RTC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for Real Time Timer.\r
+ */\r
+WEAK void RTT_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for Watchdog Timer.\r
+ */\r
+WEAK void WDT0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for PMC.\r
+ */\r
+WEAK void PMC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for EEFC.\r
+ */\r
+WEAK void EFC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for UART0.\r
+ */\r
+WEAK void UART0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for UART1.\r
+ */\r
+WEAK void UART1_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for SMC.\r
+ */\r
+WEAK void TC10_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for PIOA Controller.\r
+ */\r
+WEAK void PIOA_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for PIOB Controller.\r
+ */\r
+WEAK void PIOB_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for PIOC Controller.\r
+ */\r
+WEAK void PIOC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for USART0.\r
+ */\r
+WEAK void USART0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for USART1.\r
+ */\r
+WEAK void USART1_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for USART2.\r
+ */\r
+WEAK void USART2_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for MCI.\r
+ */\r
+WEAK void HSMCI_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for TWI0.\r
+ */\r
+WEAK void TWI0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for TWI1.\r
+ */\r
+WEAK void TWI1_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for SPI.\r
+ */\r
+WEAK void SPI0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for SSC.\r
+ */\r
+WEAK void SSC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for TC0.\r
+ */\r
+WEAK void TC0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for TC1.\r
+ */\r
+WEAK void TC1_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default interrupt handler for TC2.\r
+ */\r
+WEAK void TC2_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for TC3.\r
+ */\r
+WEAK void TC3_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for TC4.\r
+ */\r
+WEAK void TC4_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for TC5.\r
+ */\r
+WEAK void TC5_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for ADC.\r
+ */\r
+WEAK void AFEC1_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for DAC.\r
+ */\r
+WEAK void DACC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for PWM.\r
+ */\r
+WEAK void PWM0_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for CRCCU.\r
+ */\r
+WEAK void TC9_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for ACC.\r
+ */\r
+WEAK void ACC_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Default SUPC interrupt handler for USBD.\r
+ */\r
+WEAK void TC11_Handler( void )\r
+{\r
+ while ( 1 ) ;\r
+}\r
+\r
+WEAK void USBHS_Handler(void)\r
+{\r
+ // udd_interrupt();\r
+ while(1);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup flashd_module Flash Memory Interface\r
+ * The flash driver manages the programming, erasing, locking and unlocking sequences\r
+ * with dedicated commands.\r
+ *\r
+ * To implement flash programing operation, the user has to follow these few steps :\r
+ * <ul>\r
+ * <li>Configue flash wait states to initializes the flash. </li>\r
+ * <li>Checks whether a region to be programmed is locked. </li>\r
+ * <li>Unlocks the user region to be programmed if the region have locked before.</li>\r
+ * <li>Erases the user page before program (optional).</li>\r
+ * <li>Writes the user page from the page buffer.</li>\r
+ * <li>Locks the region of programmed area if any.</li>\r
+ * </ul>\r
+ *\r
+ * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.\r
+ * A check of this validity and padding for 32-bit alignment should be done in write algorithm.\r
+\r
+ * Lock/unlock range associated with the user address range is automatically translated.\r
+ *\r
+ * This security bit can be enabled through the command "Set General Purpose NVM Bit 0".\r
+ *\r
+ * A 128-bit factory programmed unique ID could be read to serve several purposes.\r
+ *\r
+ * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module.\r
+ * For more accurate information, please look at the EEFC section of the Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref flashd.c\n\r
+ * \ref flashd.h.\n\r
+ * \ref efc.c\n\r
+ * \ref efc.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * The flash driver provides the unified interface for flash program operations.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define GPNVM_NUM_MAX 8\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint32_t _pdwPageBuffer[IFLASH_PAGE_SIZE/sizeof(uint32_t)] ;\r
+static uint32_t _dwUseIAP = 1; /* Use IAP interface by default. */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define min( a, b ) (((a) < (b)) ? (a) : (b))\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Computes the lock range associated with the given address range.\r
+ *\r
+ * \param dwStart Start address of lock range.\r
+ * \param dwEnd End address of lock range.\r
+ * \param pdwActualStart Actual start address of lock range.\r
+ * \param pdwActualEnd Actual end address of lock range.\r
+ */\r
+static void ComputeLockRange( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd )\r
+{\r
+ Efc* pStartEfc ;\r
+ Efc* pEndEfc ;\r
+ uint16_t wStartPage ;\r
+ uint16_t wEndPage ;\r
+ uint16_t wNumPagesInRegion ;\r
+ uint16_t wActualStartPage ;\r
+ uint16_t wActualEndPage ;\r
+\r
+ /* Convert start and end address in page numbers */\r
+ EFC_TranslateAddress( &pStartEfc, dwStart, &wStartPage, 0 ) ;\r
+ EFC_TranslateAddress( &pEndEfc, dwEnd, &wEndPage, 0 ) ;\r
+\r
+ /* Find out the first page of the first region to lock */\r
+ wNumPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;\r
+ wActualStartPage = wStartPage - (wStartPage % wNumPagesInRegion) ;\r
+ wActualEndPage = wEndPage ;\r
+\r
+ if ( (wEndPage % wNumPagesInRegion) != 0 )\r
+ {\r
+ wActualEndPage += wNumPagesInRegion - (wEndPage % wNumPagesInRegion) ;\r
+ }\r
+ /* Store actual page numbers */\r
+ EFC_ComputeAddress( pStartEfc, wActualStartPage, 0, pdwActualStart ) ;\r
+ EFC_ComputeAddress( pEndEfc, wActualEndPage, 0, pdwActualEnd ) ;\r
+ TRACE_DEBUG( "Actual lock range is 0x%06X - 0x%06X\n\r",\r
+ (unsigned int)*pdwActualStart, (unsigned int)*pdwActualEnd ) ;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initializes the flash driver.\r
+ *\r
+ * \param dwMCk Master clock frequency in Hz.\r
+ * \param dwUseIAP 0: use EEFC controller interface, 1: use IAP interface.\r
+ * dwUseIAP should be set to 1 when running out of flash.\r
+ */\r
+\r
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP )\r
+{\r
+ dwMCk = dwMCk; /* avoid warnings */\r
+\r
+ EFC_DisableFrdyIt( EFC ) ;\r
+ _dwUseIAP = dwUseIAP ;\r
+}\r
+\r
+/**\r
+ * \brief Erases the entire flash.\r
+ *\r
+ * \param dwAddress Flash start address.\r
+ * \return 0 if successful; otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_Erase( uint32_t dwAddress )\r
+{\r
+ Efc* pEfc ;\r
+ uint16_t wPage ;\r
+ uint16_t wOffset ;\r
+ uint32_t dwError ;\r
+\r
+ assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ;\r
+\r
+ /* Translate write address */\r
+ EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ;\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EA, 0, _dwUseIAP ) ;\r
+\r
+ return dwError ;\r
+}\r
+\r
+/**\r
+ * \brief Erases flash by sector.\r
+ *\r
+ * \param dwAddress Start address of be erased sector.\r
+ *\r
+ * \return 0 if successful; otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_EraseSector( uint32_t dwAddress )\r
+{\r
+ Efc* pEfc ;\r
+ uint16_t wPage ;\r
+ uint16_t wOffset ;\r
+ uint32_t dwError ;\r
+\r
+ assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ;\r
+\r
+ /* Translate write address */\r
+ EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ;\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_ES, wPage, _dwUseIAP ) ;\r
+\r
+ return dwError ;\r
+}\r
+\r
+/**\r
+ * \brief Erases flash by pages.\r
+ *\r
+ * \param dwAddress Start address of be erased pages.\r
+ * \param dwPageNum Number of pages to be erased with EPA command (4, 8, 16, 32)\r
+ *\r
+ * \return 0 if successful; otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_ErasePages( uint32_t dwAddress, uint32_t dwPageNum )\r
+{\r
+ Efc* pEfc ;\r
+ uint16_t wPage ;\r
+ uint16_t wOffset ;\r
+ uint32_t dwError ;\r
+ static uint32_t dwFarg ;\r
+\r
+ assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ;\r
+\r
+ /* Translate write address */\r
+ EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ;\r
+\r
+ /* Get FARG field for EPA command:\r
+ * The first page to be erased is specified in the FARG[15:2] field of\r
+ * the MC_FCR register. The first page number must be modulo 4, 8,16 or 32\r
+ * according to the number of pages to erase at the same time.\r
+ *\r
+ * The 2 lowest bits of the FARG field define the number of pages to\r
+ * be erased (FARG[1:0]).\r
+ */\r
+ if (dwPageNum == 32)\r
+ {\r
+ wPage &= ~(32u - 1u);\r
+ dwFarg = (wPage << 2) | 3; /* 32 pages */\r
+ }\r
+ else if (dwPageNum == 16)\r
+ {\r
+ wPage &= ~(16u - 1u);\r
+ dwFarg = (wPage << 2) | 2; /* 16 pages */\r
+ }\r
+ else if (dwPageNum == 8)\r
+ {\r
+ wPage &= ~(8u - 1u);\r
+ dwFarg = (wPage << 2) | 1; /* 8 pages */\r
+ }\r
+ else\r
+ {\r
+ wPage &= ~(4u - 1u);\r
+ dwFarg = (wPage << 2) | 0; /* 4 pages */\r
+ }\r
+\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EPA, dwFarg, _dwUseIAP ) ;\r
+\r
+ return dwError ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Writes a data buffer in the internal flash\r
+ *\r
+ * \note This function works in polling mode, and thus only returns when the\r
+ * data has been effectively written.\r
+ * \param address Write address.\r
+ * \param pBuffer Data buffer.\r
+ * \param size Size of data buffer in bytes.\r
+ * \return 0 if successful, otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, uint32_t dwSize )\r
+{\r
+ Efc* pEfc ;\r
+ uint16_t page ;\r
+ uint16_t offset ;\r
+ uint32_t writeSize ;\r
+ uint32_t pageAddress ;\r
+ uint16_t padding ;\r
+ uint32_t dwError ;\r
+ uint32_t dwIdx ;\r
+ uint32_t *pAlignedDestination ;\r
+ uint8_t *pucPageBuffer = (uint8_t *)_pdwPageBuffer;\r
+\r
+ assert( pvBuffer ) ;\r
+ assert( dwAddress >=IFLASH_ADDR ) ;\r
+ assert( (dwAddress + dwSize) <= (IFLASH_ADDR + IFLASH_SIZE) ) ;\r
+\r
+ /* Translate write address */\r
+ EFC_TranslateAddress( &pEfc, dwAddress, &page, &offset ) ;\r
+\r
+ /* Write all pages */\r
+ while ( dwSize > 0 )\r
+ {\r
+ /* Copy data in temporary buffer to avoid alignment problems */\r
+ writeSize = min((uint32_t)IFLASH_PAGE_SIZE - offset, dwSize ) ;\r
+ EFC_ComputeAddress(pEfc, page, 0, &pageAddress ) ;\r
+ padding = IFLASH_PAGE_SIZE - offset - writeSize ;\r
+\r
+ /* Pre-buffer data */\r
+ memcpy( pucPageBuffer, (void *) pageAddress, offset);\r
+\r
+ /* Buffer data */\r
+ memcpy( pucPageBuffer + offset, pvBuffer, writeSize);\r
+\r
+ /* Post-buffer data */\r
+ memcpy( pucPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding);\r
+\r
+ /* Write page\r
+ * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption\r
+ */\r
+ pAlignedDestination = (uint32_t*)pageAddress ;\r
+ for (dwIdx = 0; dwIdx < (IFLASH_PAGE_SIZE / sizeof(uint32_t)); ++ dwIdx) {\r
+ *pAlignedDestination++ = _pdwPageBuffer[dwIdx];\r
+ }\r
+\r
+ /* Note for sam3s16 and sam4s:\r
+ * It is not possible to use Erase and write Command (EWP) on all Flash (this\r
+ * command is available on the First 2 Small Sector, 16K Bytes). For the next\r
+ * block, Erase them first then use Write page command.\r
+ */\r
+ /* Send writing command */\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_WP, page, _dwUseIAP ) ;\r
+ if ( dwError )\r
+ {\r
+ return dwError ;\r
+ }\r
+\r
+ /* Progression */\r
+ pvBuffer = (void *)((uint32_t) pvBuffer + writeSize) ;\r
+ dwSize -= writeSize ;\r
+ page++;\r
+ offset = 0;\r
+ }\r
+\r
+ return 0 ;\r
+}\r
+/**\r
+ * \brief Locks all the regions in the given address range. The actual lock range is\r
+ * reported through two output parameters.\r
+ *\r
+ * \param start Start address of lock range.\r
+ * \param end End address of lock range.\r
+ * \param pActualStart Start address of the actual lock range (optional).\r
+ * \param pActualEnd End address of the actual lock range (optional).\r
+ * \return 0 if successful, otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_Lock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )\r
+{\r
+ Efc *pEfc ;\r
+ uint32_t actualStart, actualEnd ;\r
+ uint16_t startPage, endPage ;\r
+ uint32_t dwError ;\r
+ uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;\r
+\r
+ /* Compute actual lock range and store it */\r
+ ComputeLockRange( start, end, &actualStart, &actualEnd ) ;\r
+ if ( pActualStart != NULL )\r
+ {\r
+ *pActualStart = actualStart ;\r
+ }\r
+ if ( pActualEnd != NULL )\r
+ {\r
+ *pActualEnd = actualEnd;\r
+ }\r
+\r
+ /* Compute page numbers */\r
+ EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;\r
+ EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;\r
+\r
+ /* Lock all pages */\r
+ while ( startPage < endPage )\r
+ {\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_SLB, startPage, _dwUseIAP ) ;\r
+ if ( dwError )\r
+ {\r
+ return dwError ;\r
+ }\r
+ startPage += numPagesInRegion;\r
+ }\r
+\r
+ return 0 ;\r
+}\r
+\r
+/**\r
+ * \brief Unlocks all the regions in the given address range. The actual unlock range is\r
+ * reported through two output parameters.\r
+ * \param start Start address of unlock range.\r
+ * \param end End address of unlock range.\r
+ * \param pActualStart Start address of the actual unlock range (optional).\r
+ * \param pActualEnd End address of the actual unlock range (optional).\r
+ * \return 0 if successful, otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_Unlock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )\r
+{\r
+ Efc* pEfc ;\r
+ uint32_t actualStart, actualEnd ;\r
+ uint16_t startPage, endPage ;\r
+ uint32_t dwError ;\r
+ uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;\r
+\r
+ /* Compute actual unlock range and store it */\r
+ ComputeLockRange(start, end, &actualStart, &actualEnd);\r
+ if ( pActualStart != NULL )\r
+ {\r
+ *pActualStart = actualStart ;\r
+ }\r
+ if ( pActualEnd != NULL )\r
+ {\r
+ *pActualEnd = actualEnd ;\r
+ }\r
+\r
+ /* Compute page numbers */\r
+ EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;\r
+ EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;\r
+\r
+ /* Unlock all pages */\r
+ while ( startPage < endPage )\r
+ {\r
+ dwError = EFC_PerformCommand( pEfc, EFC_FCMD_CLB, startPage, _dwUseIAP ) ;\r
+ if ( dwError )\r
+ {\r
+ return dwError ;\r
+ }\r
+ startPage += numPagesInRegion ;\r
+ }\r
+ return 0 ;\r
+}\r
+\r
+/**\r
+ * \brief Returns the number of locked regions inside the given address range.\r
+ *\r
+ * \param start Start address of range\r
+ * \param end End address of range.\r
+ */\r
+extern uint32_t FLASHD_IsLocked( uint32_t start, uint32_t end )\r
+{\r
+ uint32_t i, j;\r
+ Efc *pEfc ;\r
+ uint16_t startPage, endPage ;\r
+ uint8_t startRegion, endRegion ;\r
+ uint32_t numPagesInRegion ;\r
+ uint32_t status[IFLASH_NB_OF_LOCK_BITS / 32u] ;\r
+ uint32_t numLockedRegions = 0 ;\r
+\r
+ assert( end >= start ) ;\r
+ assert( (start >=IFLASH_ADDR) && (end <= IFLASH_ADDR + IFLASH_SIZE) ) ;\r
+\r
+ /* Compute page numbers */\r
+ EFC_TranslateAddress( &pEfc, start, &startPage, 0 ) ;\r
+ EFC_TranslateAddress( 0, end, &endPage, 0 ) ;\r
+\r
+ /* Compute region numbers */\r
+ numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;\r
+ startRegion = startPage / numPagesInRegion ;\r
+ endRegion = endPage / numPagesInRegion ;\r
+ if ((endPage % numPagesInRegion) != 0)\r
+ {\r
+ endRegion++ ;\r
+ }\r
+\r
+ /* Retrieve lock status */\r
+ EFC_PerformCommand( pEfc, EFC_FCMD_GLB, 0, _dwUseIAP ) ;\r
+ for (i = 0; i < (IFLASH_NB_OF_LOCK_BITS / 32u); i++)\r
+ {\r
+ status[i] = EFC_GetResult( pEfc ) ;\r
+ }\r
+\r
+ /* Check status of each involved region */\r
+ while ( startRegion < endRegion )\r
+ {\r
+ i = startRegion / 32u;\r
+ j = startRegion % 32u;\r
+ if ( (status[i] & (1 << j)) != 0 )\r
+ {\r
+ numLockedRegions++ ;\r
+ }\r
+ startRegion++ ;\r
+ }\r
+\r
+ return numLockedRegions ;\r
+}\r
+\r
+/**\r
+ * \brief Check if the given GPNVM bit is set or not.\r
+ *\r
+ * \param gpnvm GPNVM bit index.\r
+ * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0.\r
+ */\r
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t ucGPNVM )\r
+{\r
+ uint32_t dwStatus ;\r
+\r
+ assert( ucGPNVM < GPNVM_NUM_MAX ) ;\r
+\r
+ /* Get GPNVMs status */\r
+ EFC_PerformCommand( EFC, EFC_FCMD_GFB, 0, _dwUseIAP ) ;\r
+ dwStatus = EFC_GetResult( EFC ) ;\r
+\r
+ /* Check if GPNVM is set */\r
+ if ( (dwStatus & (1 << ucGPNVM)) != 0 )\r
+ {\r
+ return 1 ;\r
+ }\r
+ else\r
+ {\r
+ return 0 ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets the selected GPNVM bit.\r
+ *\r
+ * \param gpnvm GPNVM bit index.\r
+ * \returns 0 if successful; otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_SetGPNVM( uint8_t ucGPNVM )\r
+{\r
+ assert( ucGPNVM < GPNVM_NUM_MAX ) ;\r
+\r
+ if ( !FLASHD_IsGPNVMSet( ucGPNVM ) )\r
+ {\r
+ return EFC_PerformCommand( EFC, EFC_FCMD_SFB, ucGPNVM, _dwUseIAP ) ;\r
+ }\r
+ else\r
+ {\r
+ return 0 ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Clears the selected GPNVM bit.\r
+ *\r
+ * \param gpnvm GPNVM bit index.\r
+ * \returns 0 if successful; otherwise returns an error code.\r
+ */\r
+extern uint32_t FLASHD_ClearGPNVM( uint8_t ucGPNVM )\r
+{\r
+ assert( ucGPNVM < GPNVM_NUM_MAX ) ;\r
+\r
+ if ( FLASHD_IsGPNVMSet( ucGPNVM ) )\r
+ {\r
+ return EFC_PerformCommand( EFC, EFC_FCMD_CFB, ucGPNVM, _dwUseIAP ) ;\r
+ }\r
+ else\r
+ {\r
+ return 0 ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Read the unique ID.\r
+ *\r
+ * \param pdwUniqueID pointer on a 4bytes char containing the unique ID value.\r
+ * \returns 0 if successful; otherwise returns an error code.\r
+ */\r
+#ifdef __ICCARM__\r
+extern __ramfunc uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID )\r
+#else\r
+ __attribute__ ((section (".ramfunc")))\r
+uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID )\r
+#endif\r
+{\r
+ uint32_t status ;\r
+ if (pdwUniqueID == NULL) {\r
+ return 1;\r
+ }\r
+\r
+ pdwUniqueID[0] = 0 ;\r
+ pdwUniqueID[1] = 0 ;\r
+ pdwUniqueID[2] = 0 ;\r
+ pdwUniqueID[3] = 0 ;\r
+\r
+ /* Send the Start Read unique Identifier command (STUI) by writing the Flash\r
+ Command Register with the STUI command.*/\r
+ EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EFC_FCMD_STUI;\r
+\r
+ /* When the Unique Identifier is ready to be read, the FRDY bit in the Flash\r
+ Programming Status Register (EEFC_FSR) falls. */\r
+ do\r
+ {\r
+ status = EFC->EEFC_FSR ;\r
+ } while ( (status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY ) ;\r
+\r
+ /* The Unique Identifier is located in the first 128 bits of the Flash\r
+ memory mapping. So, at the address 0x400000-0x40000F. */\r
+ pdwUniqueID[0] = *(uint32_t *)IFLASH_ADDR;\r
+ pdwUniqueID[1] = *(uint32_t *)(IFLASH_ADDR + 4);\r
+ pdwUniqueID[2] = *(uint32_t *)(IFLASH_ADDR + 8);\r
+ pdwUniqueID[3] = *(uint32_t *)(IFLASH_ADDR + 12);\r
+\r
+ /* To stop the Unique Identifier mode, the user needs to send the Stop Read\r
+ unique Identifier command (SPUI) by writing the Flash Command Register\r
+ with the SPUI command. */\r
+ EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EFC_FCMD_SPUI ;\r
+\r
+ /* When the Stop read Unique Unique Identifier command (SPUI) has been\r
+ performed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR)\r
+ rises. */\r
+ do\r
+ {\r
+ status = EFC->EEFC_FSR ;\r
+ } while ( (status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ;\r
+\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Internal functions\r
+ *----------------------------------------------------------------------------*/\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Return 1 if PHY is idle\r
+ */\r
+uint8_t GMAC_IsIdle(Gmac *pGmac)\r
+{\r
+ return ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) > 0);\r
+}\r
+\r
+\r
+/**\r
+ * Execute PHY maintanance command\r
+ */\r
+void GMAC_PHYMaintain(Gmac *pGmac,\r
+ uint8_t bPhyAddr,\r
+ uint8_t bRegAddr,\r
+ uint8_t bRW,\r
+ uint16_t wData)\r
+{\r
+ /* Wait until bus idle */\r
+ while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);\r
+ /* Write maintain register */\r
+ pGmac->GMAC_MAN = (~GMAC_MAN_WZO & GMAC_MAN_CLTTO)\r
+ | (GMAC_MAN_OP(bRW ? 0x2 : 0x1))\r
+ | GMAC_MAN_WTN(0x02)\r
+ | GMAC_MAN_PHYA(bPhyAddr)\r
+ | GMAC_MAN_REGA(bRegAddr)\r
+ | GMAC_MAN_DATA(wData) ;\r
+}\r
+\r
+/**\r
+ * Return PHY maintainance data returned\r
+ */\r
+uint16_t GMAC_PHYData(Gmac *pGmac)\r
+{\r
+ /* Wait until bus idle */\r
+ while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);\r
+ /* Return data */\r
+ return (uint16_t)(pGmac->GMAC_MAN & GMAC_MAN_DATA_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Set MDC clock according to current board clock. Per 802.3, MDC should be \r
+ * less then 2.5MHz.\r
+ * \param pGmac Pointer to an Gmac instance. \r
+ * \param mck Mdc clock\r
+ * \return 1 if successfully, 0 if MDC clock not found.\r
+ */\r
+uint8_t GMAC_SetMdcClock( Gmac *pGmac, uint32_t mck )\r
+{\r
+ uint32_t clock_dividor;\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ if (mck <= 20000000) {\r
+ clock_dividor = GMAC_NCFGR_CLK_MCK_8; // MDC clock = MCK/8\r
+ }\r
+ else if (mck <= 40000000) {\r
+ clock_dividor = GMAC_NCFGR_CLK_MCK_16; // MDC clock = MCK/16\r
+ }\r
+ else if (mck <= 80000000) {\r
+ clock_dividor = GMAC_NCFGR_CLK_MCK_32; // MDC clock = MCK/32\r
+ }\r
+ else if (mck <= 160000000) {\r
+ clock_dividor = GMAC_NCFGR_CLK_MCK_64; // MDC clock = MCK/64\r
+ }\r
+ else if (mck <= 240000000) {\r
+ clock_dividor = GMAC_NCFGR_CLK_MCK_96; // MDC clock = MCK/96\r
+ }\r
+ else {\r
+ TRACE_ERROR("E: No valid MDC clock.\n\r");\r
+ return 0;\r
+ }\r
+ pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Enable MDI with PHY\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ */\r
+void GMAC_EnableMdio( Gmac *pGmac )\r
+{\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ pGmac->GMAC_NCR |= GMAC_NCR_MPE;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+/**\r
+ * \brief Enable MDI with PHY\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ */\r
+void GMAC_DisableMdio( Gmac *pGmac )\r
+{\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ pGmac->GMAC_NCR &= ~GMAC_NCR_MPE;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+/**\r
+ * \brief Enable MII mode for GMAC, called once after autonegotiate\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ */\r
+void GMAC_EnableMII( Gmac *pGmac )\r
+{\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ pGmac->GMAC_UR &= ~GMAC_UR_RMIIMII;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+/**\r
+ * \brief Enable GMII mode for GMAC, called once after autonegotiate\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ */\r
+void GMAC_EnableGMII( Gmac *pGmac )\r
+{\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ /* RGMII disable */\r
+ pGmac->GMAC_UR &= ~GMAC_UR_RMIIMII;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+#define GMAC_NCFGR_GBE (0x1u << 10)\r
+/**\r
+ * \brief Enable RGMII mode for GMAC, called once after autonegotiate\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ * \param duplex: 1 full duplex 0 half duplex\r
+ * \param speed: 0 10M 1 100M \r
+ */\r
+void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed)\r
+{\r
+ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ if (duplex == GMAC_DUPLEX_HALF)\r
+ {\r
+ pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;\r
+ }\r
+ else \r
+ {\r
+ pGmac->GMAC_NCFGR |= GMAC_NCFGR_FD;\r
+ }\r
+\r
+\r
+ if (speed == GMAC_SPEED_10M)\r
+ {\r
+ pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;\r
+ }\r
+ else if(speed == GMAC_SPEED_100M) \r
+ {\r
+ pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;\r
+ }\r
+ else\r
+ {\r
+ pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;\r
+ }\r
+\r
+ /* RGMII enable */\r
+ pGmac->GMAC_UR = 0;\r
+ pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+ return;\r
+}\r
+\r
+/**\r
+ * \brief Setup the GMAC for the link : speed 100M/10M and Full/Half duplex\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ * \param speed Link speed, 0 for 10M, 1 for 100M\r
+ * \param fullduplex 1 for Full Duplex mode\r
+ */\r
+void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex)\r
+{\r
+ uint32_t ncfgr;\r
+ ncfgr = pGmac->GMAC_NCFGR;\r
+ ncfgr &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD);\r
+ if (speed) {\r
+\r
+ ncfgr |= GMAC_NCFGR_SPD;\r
+ }\r
+ if (fullduplex) {\r
+\r
+ ncfgr |= GMAC_NCFGR_FD;\r
+ }\r
+ pGmac->GMAC_NCFGR = ncfgr;\r
+ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+/**\r
+ * \brief set local loop back\r
+ * \param pGmac Pointer to an Gmac instance.\r
+ */\r
+uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac)\r
+{\r
+ pGmac->GMAC_NCR |= GMAC_NCR_LBL;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Return interrupt mask.\r
+ */\r
+uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx)\r
+{\r
+\r
+ if(!queueIdx)\r
+ {\r
+ return pGmac->GMAC_IMR;\r
+ }\r
+ else\r
+ {\r
+ return pGmac->GMAC_IMRPQ[queueIdx -1];\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * Return transmit status\r
+ */\r
+uint32_t GMAC_GetTxStatus(Gmac *pGmac)\r
+{\r
+ return pGmac->GMAC_TSR; \r
+}\r
+\r
+/**\r
+ * Clear transmit status\r
+ */\r
+void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus)\r
+{\r
+ pGmac->GMAC_TSR = dwStatus;\r
+}\r
+\r
+/**\r
+ * Return receive status\r
+ */\r
+uint32_t GMAC_GetRxStatus(Gmac *pGmac)\r
+{\r
+ return pGmac->GMAC_RSR;\r
+}\r
+\r
+/**\r
+ * Clear receive status\r
+ */\r
+void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus)\r
+{\r
+ pGmac->GMAC_RSR = dwStatus;\r
+}\r
+\r
+\r
+/**\r
+ * Enable/Disable GMAC receive.\r
+ */\r
+void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis)\r
+{\r
+ if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_RXEN;\r
+ else pGmac->GMAC_NCR &= ~GMAC_NCR_RXEN;\r
+}\r
+\r
+/**\r
+ * Enable/Disable GMAC transmit.\r
+ */\r
+void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis)\r
+{\r
+ if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_TXEN;\r
+ else pGmac->GMAC_NCR &= ~GMAC_NCR_TXEN;\r
+}\r
+\r
+\r
+/**\r
+ * Set Rx Queue\r
+ */\r
+void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)\r
+{\r
+ if(!queueIdx)\r
+ {\r
+ pGmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & dwAddr;\r
+ }\r
+ else\r
+ {\r
+ pGmac->GMAC_RBQBAPQ[queueIdx - 1] = GMAC_RBQB_ADDR_Msk & dwAddr;\r
+ }\r
+}\r
+\r
+/**\r
+ * Get Rx Queue Address\r
+ */\r
+uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx)\r
+{\r
+ if(!queueIdx)\r
+ {\r
+ return pGmac->GMAC_RBQB;\r
+ }\r
+ else\r
+ {\r
+ return pGmac->GMAC_RBQBAPQ[queueIdx - 1];\r
+ } \r
+}\r
+\r
+/**\r
+ * Set Tx Queue\r
+ */\r
+void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)\r
+{\r
+ if(!queueIdx)\r
+ {\r
+ pGmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & dwAddr;\r
+ }\r
+ else\r
+ {\r
+ pGmac->GMAC_TBQBAPQ[queueIdx - 1] = GMAC_TBQB_ADDR_Msk & dwAddr;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * Get Tx Queue\r
+ */\r
+uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx)\r
+{\r
+\r
+ if(!queueIdx)\r
+ {\r
+ return pGmac->GMAC_TBQB;\r
+\r
+ }\r
+ else\r
+ {\r
+ return pGmac->GMAC_TBQBAPQ[queueIdx - 1];\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * Write control value\r
+ */\r
+void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR)\r
+{\r
+ pGmac->GMAC_NCR = bmNCR;\r
+}\r
+\r
+\r
+/**\r
+ * Get control value\r
+ */\r
+uint32_t GMAC_GetNetworkControl(Gmac *pGmac)\r
+{\r
+ return pGmac->GMAC_NCR;\r
+}\r
+\r
+\r
+/**\r
+ * Enable interrupt(s).\r
+ */\r
+void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)\r
+{\r
+ if(!queueIdx)\r
+ {\r
+ pGmac->GMAC_IER = dwSources;\r
+ }\r
+ else\r
+ {\r
+ pGmac->GMAC_IERPQ[queueIdx-1] = dwSources;\r
+ }\r
+}\r
+\r
+/**\r
+ * Disable interrupt(s).\r
+ */\r
+void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources)\r
+{\r
+ pGmac->GMAC_IDR = dwSources;\r
+ pGmac->GMAC_IDRPQ[0] = dwSources;\r
+ pGmac->GMAC_IDRPQ[1] = dwSources;\r
+}\r
+\r
+/**\r
+ * Disable interrupt(s).\r
+ */\r
+void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources)\r
+{\r
+ pGmac->GMAC_IER = dwSources;\r
+ pGmac->GMAC_IERPQ[0] = dwSources;\r
+ pGmac->GMAC_IERPQ[1] = dwSources;\r
+}\r
+\r
+/**\r
+ * Disable interrupt(s).\r
+ */\r
+void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)\r
+{\r
+\r
+ if(!queueIdx)\r
+ {\r
+ pGmac->GMAC_IDR = dwSources;\r
+ }\r
+ else\r
+ {\r
+ pGmac->GMAC_IDRPQ[queueIdx-1] = dwSources;\r
+ }\r
+}\r
+\r
+/**\r
+ * Return interrupt status.\r
+ */\r
+uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx)\r
+{ \r
+ if(!queueIdx)\r
+ {\r
+ return pGmac->GMAC_ISR;\r
+ }\r
+ else\r
+ {\r
+ return pGmac->GMAC_ISRPQ[queueIdx-1];\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * Set MAC Address\r
+ */\r
+void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr)\r
+{\r
+\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAB = (pMacAddr[3] << 24)\r
+ | (pMacAddr[2] << 16)\r
+ | (pMacAddr[1] << 8)\r
+ | (pMacAddr[0] )\r
+ ;\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAT = (pMacAddr[5] << 8)\r
+ | (pMacAddr[4] )\r
+ ;\r
+}\r
+\r
+/**\r
+ * Set MAC Address via 2 DW\r
+ */\r
+void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB)\r
+{\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAB = dwMacB;\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAT = dwMacT;\r
+}\r
+\r
+/**\r
+ * Set MAC Address via int64\r
+ */\r
+void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac)\r
+{\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAB = (uint32_t)ddwMac;\r
+ pGmac->GMAC_SA[bIndex].GMAC_SAT = (uint32_t)(ddwMac >> 32);\r
+}\r
+\r
+\r
+/**\r
+ * Clear all statistics registers\r
+ */\r
+void GMAC_ClearStatistics(Gmac *pGmac)\r
+{\r
+ pGmac->GMAC_NCR |= GMAC_NCR_CLRSTAT;\r
+}\r
+\r
+/**\r
+ * Increase all statistics registers\r
+ */\r
+void GMAC_IncreaseStatistics(Gmac *pGmac)\r
+{\r
+ pGmac->GMAC_NCR |= GMAC_NCR_INCSTAT;\r
+}\r
+\r
+/**\r
+ * Enable/Disable statistics registers writing.\r
+ */\r
+void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis)\r
+{\r
+ if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_WESTAT;\r
+ else pGmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;\r
+}\r
+\r
+\r
+/**\r
+ * Setup network configuration register\r
+ */\r
+void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg)\r
+{\r
+ pGmac->GMAC_NCFGR = dwCfg;\r
+}\r
+\r
+/**\r
+ * Setup network configuration register\r
+ */\r
+void GMAC_DmaConfigure(Gmac *pGmac, uint32_t dwCfg)\r
+{\r
+ pGmac->GMAC_DCFGR = dwCfg;\r
+}\r
+\r
+/**\r
+ * Return network configuration.\r
+ */\r
+uint32_t GMAC_GetConfigure(Gmac *pGmac)\r
+{\r
+ return pGmac->GMAC_NCFGR;\r
+}\r
+\r
+\r
+/**\r
+ * Start transmission\r
+ */\r
+void GMAC_TransmissionStart(Gmac *pGmac)\r
+{\r
+ pGmac->GMAC_NCR |= GMAC_NCR_TSTART;\r
+}\r
+\r
+/**\r
+ * Halt transmission\r
+ */\r
+void GMAC_TransmissionHalt(Gmac *pGmac)\r
+{\r
+ pGmac->GMAC_NCR |= GMAC_NCR_THALT;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+ /** \file */\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <string.h>\r
+\r
+/** \addtogroup gmacd_defines\r
+ @{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macro\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/** ISO/IEC 14882:2003(E) - 5.6 Multiplicative operators:\r
+ * The binary / operator yields the quotient, and the binary % operator yields the remainder \r
+ * from the division of the first expression by the second. \r
+ * If the second operand of / or % is zero the behavior is undefined; otherwise (a/b)*b + a%b is equal to a.\r
+ * If both operands are nonnegative then the remainder is nonnegative;\r
+ * if not, the sign of the remainder is implementation-defined 74).\r
+ */\r
+static inline int fixed_mod(int a, int b)\r
+{\r
+ int rem = a % b;\r
+ while (rem < 0)\r
+ rem += b;\r
+\r
+ return rem;\r
+}\r
+\r
+/** Return count in buffer */\r
+#define GCIRC_CNT(head,tail,size) fixed_mod((head) - (tail), (size))\r
+\r
+/** Return space available, 0..size-1. always leave one free char as a completely full buffer \r
+ has head == tail, which is the same as empty */\r
+#define GCIRC_SPACE(head,tail,size) GCIRC_CNT((tail),((head)+1),(size))\r
+\r
+/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once,\r
+ so they can change underneath us without returning inconsistent results */\r
+#define GCIRC_CNT_TO_END(head,tail,size) \\r
+ ({int end = (size) - (tail); \\r
+ int n = fixed_mod((head) + end, (size)); \\r
+ n < end ? n : end;})\r
+\r
+/** Return space available up to the end of the buffer */\r
+#define GCIRC_SPACE_TO_END(head,tail,size) \\r
+ ({int end = (size) - 1 - (head); \\r
+ int n = fixed_mod(end + (tail), (size)); \\r
+ n <= end ? n : end+1;})\r
+\r
+/** Increment head or tail */\r
+#define GCIRC_INC(headortail,size) \\r
+ headortail++; \\r
+ if(headortail >= size) { \\r
+ headortail = 0; \\r
+ }\r
+\r
+/** Circular buffer is empty ? */\r
+#define GCIRC_EMPTY(head, tail) (head == tail)\r
+\r
+/** Clear circular buffer */\r
+#define GCIRC_CLEAR(head, tail) (head = tail = 0)\r
+\r
+\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Local functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Disable TX & reset registers and descriptor list\r
+ * \param pDrv Pointer to GMAC Driver instance.\r
+ */\r
+static void GMACD_ResetTx(sGmacd *pDrv, gmacQueList_t queIdx)\r
+{\r
+ Gmac *pHw = pDrv->pHw;\r
+ uint8_t *pTxBuffer = pDrv->queueList[queIdx].pTxBuffer;\r
+ sGmacTxDescriptor *pTd = pDrv->queueList[queIdx].pTxD;\r
+ uint32_t Index;\r
+ uint32_t Address;\r
+\r
+ /* Disable TX */\r
+ GMAC_TransmitEnable(pHw, 0);\r
+ \r
+ /* Setup the TX descriptors. */\r
+ GCIRC_CLEAR(pDrv->queueList[queIdx].wTxHead, pDrv->queueList[queIdx].wTxTail);\r
+ for(Index = 0; Index < pDrv->queueList[queIdx].wTxListSize; Index++) {\r
+ Address = (uint32_t)(&(pTxBuffer[Index * GMAC_TX_UNITSIZE]));\r
+ pTd[Index].addr = Address;\r
+ pTd[Index].status.val = (uint32_t)GMAC_TX_USED_BIT;\r
+ }\r
+ \r
+ pTd[pDrv->queueList[queIdx].wTxListSize - 1].status.val = GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT; \r
+ \r
+ /* Transmit Buffer Queue Pointer Register */\r
+ \r
+ GMAC_SetTxQueue(pHw, (uint32_t)pTd, queIdx);\r
+}\r
+ \r
+/**\r
+ * \brief Disable RX & reset registers and descriptor list\r
+ * \param pDrv Pointer to GMAC Driver instance. \r
+ */\r
+static void GMACD_ResetRx(sGmacd *pDrv, gmacQueList_t queIdx )\r
+{\r
+ Gmac *pHw = pDrv->pHw;\r
+ uint8_t *pRxBuffer = pDrv->queueList[queIdx].pRxBuffer;\r
+ sGmacRxDescriptor *pRd = pDrv->queueList[queIdx].pRxD;\r
+\r
+ uint32_t Index;\r
+ uint32_t Address;\r
+\r
+ /* Disable RX */\r
+ GMAC_ReceiveEnable(pHw, 0);\r
+\r
+ /* Setup the RX descriptors. */\r
+ pDrv->queueList[queIdx].wRxI = 0;\r
+ for(Index = 0; Index < pDrv->queueList[queIdx].wRxListSize; Index++)\r
+ {\r
+ Address = (uint32_t)(&(pRxBuffer[Index * GMAC_RX_UNITSIZE]));\r
+ /* Remove GMAC_RXD_bmOWNERSHIP and GMAC_RXD_bmWRAP */\r
+ pRd[Index].addr.val = Address & GMAC_ADDRESS_MASK;\r
+ pRd[Index].status.val = 0;\r
+ }\r
+ \r
+ pRd[pDrv->queueList[queIdx].wRxListSize - 1].addr.val |= GMAC_RX_WRAP_BIT;\r
+ \r
+ /* Receive Buffer Queue Pointer Register */ \r
+ GMAC_SetRxQueue(pHw, (uint32_t) pRd, queIdx);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Process successfully sent packets\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void GMACD_TxCompleteHandler(sGmacd *pGmacd, gmacQueList_t qId)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+ sGmacTxDescriptor *pTxTd;\r
+ fGmacdTransferCallback fTxCb;\r
+ uint32_t tsr;\r
+\r
+ /* Clear status */\r
+ tsr = GMAC_GetTxStatus(pHw);\r
+ GMAC_ClearTxStatus(pHw, tsr);\r
+\r
+ while (!GCIRC_EMPTY(pGmacd->queueList[qId].wTxHead, pGmacd->queueList[qId].wTxTail)) {\r
+ pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];\r
+\r
+ /* Make hw descriptor updates visible to CPU */\r
+ memory_barrier();\r
+\r
+ /* Exit if frame has not been sent yet:\r
+ * On TX completion, the GMAC set the USED bit only into the\r
+ * very first buffer descriptor of the sent frame.\r
+ * Otherwise it updates this descriptor with status error bits.\r
+ * This is the descriptor writeback.\r
+ */\r
+ if ((pTxTd->status.val & GMAC_TX_USED_BIT) == 0)\r
+ break;\r
+\r
+ /* Process all buffers of the current transmitted frame */\r
+ while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) {\r
+ GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);\r
+ pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];\r
+ }\r
+\r
+ /* Notify upper layer that a frame has been sent */\r
+ fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail];\r
+ if (fTxCb)\r
+ fTxCb(tsr);\r
+\r
+ /* Go to next frame */\r
+ GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);\r
+ }\r
+\r
+ /* If a wakeup has been scheduled, notify upper layer that it can\r
+ send other packets, send will be successfull. */\r
+ if (pGmacd->queueList[qId].fWakupCb &&\r
+ GCIRC_SPACE(pGmacd->queueList[qId].wTxHead,\r
+ pGmacd->queueList[qId].wTxTail,\r
+ pGmacd->queueList[qId].wTxListSize) >= pGmacd->queueList[qId].bWakeupThreshold)\r
+ pGmacd->queueList[qId].fWakupCb();\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reset TX queue when errors are detected\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void GMACD_TxErrorHandler(sGmacd *pGmacd, gmacQueList_t qId)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+ sGmacTxDescriptor *pTxTd;\r
+ fGmacdTransferCallback fTxCb;\r
+ uint32_t tsr;\r
+\r
+ /* Clear TXEN bit into the Network Configuration Register:\r
+ * this is a workaround to recover from TX lockups that \r
+ * occur on sama5d3 gmac (r1p24f2) when using scatter-gather.\r
+ * This issue has never been seen on sama5d4 gmac (r1p31).\r
+ */\r
+ GMAC_TransmitEnable(pHw, 0);\r
+\r
+ /* The following step should be optional since this function is called \r
+ * directly by the IRQ handler. Indeed, according to Cadence \r
+ * documentation, the transmission is halted on errors such as\r
+ * too many retries or transmit under run.\r
+ * However it would become mandatory if the call of this function\r
+ * were scheduled as a task by the IRQ handler (this is how Linux \r
+ * driver works). Then this function might compete with GMACD_Send().\r
+ *\r
+ * Setting bit 10, tx_halt, of the Network Control Register is not enough:\r
+ * We should wait for bit 3, tx_go, of the Transmit Status Register to \r
+ * be cleared at transmit completion if a frame is being transmitted.\r
+ */\r
+ GMAC_TransmissionHalt(pHw);\r
+ while (GMAC_GetTxStatus(pHw) & GMAC_TSR_TXGO);\r
+\r
+ /* Treat frames in TX queue including the ones that caused the error. */\r
+ while (!GCIRC_EMPTY(pGmacd->queueList[qId].wTxHead, pGmacd->queueList[qId].wTxTail)) {\r
+ int tx_completed = 0;\r
+ pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];\r
+\r
+ /* Make hw descriptor updates visible to CPU */\r
+ memory_barrier();\r
+\r
+ /* Check USED bit on the very first buffer descriptor to validate\r
+ * TX completion.\r
+ */\r
+ if (pTxTd->status.val & GMAC_TX_USED_BIT)\r
+ tx_completed = 1;\r
+\r
+ /* Go to the last buffer descriptor of the frame */\r
+ while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) {\r
+ GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);\r
+ pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];\r
+ }\r
+\r
+ /* Notify upper layer that a frame status */\r
+ fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail];\r
+ if (fTxCb)\r
+ fTxCb(tx_completed ? GMAC_TSR_TXCOMP : 0); // TODO: which error to notify?\r
+\r
+ /* Go to next frame */\r
+ GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);\r
+ } \r
+\r
+ /* Reset TX queue */\r
+ GMACD_ResetTx(pGmacd, qId);\r
+ \r
+ /* Clear status */\r
+ tsr = GMAC_GetTxStatus(pHw);\r
+ GMAC_ClearTxStatus(pHw, tsr);\r
+\r
+ /* Now we are ready to start transmission again */\r
+ GMAC_TransmitEnable(pHw, 1);\r
+ if (pGmacd->queueList[qId].fWakupCb)\r
+ pGmacd->queueList[qId].fWakupCb();\r
+}\r
+\r
+ \r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+ \r
+ \r
+/**\r
+ * \brief GMAC Interrupt handler\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ */\r
+void GMACD_Handler(sGmacd *pGmacd, gmacQueList_t queIdx)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+ uint32_t isr;\r
+ uint32_t rsr;\r
+ \r
+ \r
+ \r
+ /* Interrupt Status Register is cleared on read */\r
+ while ( (isr = GMAC_GetItStatus(pHw, queIdx)) !=0) {\r
+ /* RX packet */\r
+ if (isr & GMAC_INT_RX_BITS) {\r
+ /* Clear status */\r
+ rsr = GMAC_GetRxStatus(pHw);\r
+ GMAC_ClearRxStatus(pHw, rsr);\r
+\r
+ /* Invoke callback */\r
+ if (pGmacd->queueList[queIdx].fRxCb)\r
+ pGmacd->queueList[queIdx].fRxCb(rsr);\r
+ }\r
+\r
+ /* TX error */\r
+ if (isr & GMAC_INT_TX_ERR_BITS) {\r
+ GMACD_TxErrorHandler(pGmacd, queIdx);\r
+ break;\r
+ }\r
+\r
+ /* TX packet */\r
+ if (isr & GMAC_IER_TCOMP)\r
+ GMACD_TxCompleteHandler(pGmacd, queIdx);\r
+\r
+ if (isr & GMAC_IER_HRESP) {\r
+ TRACE_ERROR("HRESP\n\r");\r
+ }\r
+ \r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Initialize the GMAC with the Gmac controller address\r
+ * \param pGmacd Pointer to GMAC Driver instance. \r
+ * \param pHw Pointer to HW address for registers.\r
+ * \param bID HW ID for power management\r
+ * \param enableCAF Enable/Disable CopyAllFrame.\r
+ * \param enableNBC Enable/Disable NoBroadCast.\r
+ */\r
+ void GMACD_Init(sGmacd *pGmacd,\r
+ Gmac *pHw,\r
+ uint8_t bID, \r
+ uint8_t enableCAF, \r
+ uint8_t enableNBC )\r
+{\r
+ uint32_t dwNcfgr, dwDcfgr;\r
+ \r
+ /* Check parameters */\r
+// assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);\r
+\r
+ TRACE_DEBUG("GMAC_Init\n\r");\r
+\r
+ /* Initialize struct */\r
+ pGmacd->pHw = pHw;\r
+ pGmacd->bId = bID;\r
+\r
+ /* Power ON */\r
+ PMC_EnablePeripheral(bID);\r
+\r
+ /* Disable TX & RX and more */\r
+ GMAC_NetworkControl(pHw, 0);\r
+ GMAC_DisableAllQueueIt(pHw, ~0u);\r
+ \r
+ GMAC_ClearStatistics(pHw);\r
+ /* Clear all status bits in the receive status register. */\r
+ GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);\r
+\r
+ /* Clear all status bits in the transmit status register */\r
+ GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE\r
+ | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP\r
+ | GMAC_TSR_UND | GMAC_TSR_HRESP );\r
+\r
+ /* Clear All interrupts */\r
+ GMAC_GetItStatus(pHw, GMAC_QUE_0);\r
+ GMAC_GetItStatus(pHw, GMAC_QUE_1);\r
+ GMAC_GetItStatus(pHw, GMAC_QUE_2);\r
+\r
+ /* Enable the copy of data into the buffers\r
+ ignore broadcasts, and don't copy FCS. */\r
+ dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64;\r
+ /* enable 1536 buffer */\r
+// dwNcfgr |= GMAC_NCFGR_MAXFS;\r
+ if( enableCAF ) {\r
+ dwNcfgr |= GMAC_NCFGR_CAF;\r
+ }\r
+ if( enableNBC ) {\r
+ dwNcfgr |= GMAC_NCFGR_NBC;\r
+ }\r
+ \r
+ dwDcfgr = (GMAC_DCFGR_DRBS(8) | (0<<8) | (0<<10) );\r
+ GMAC_Configure(pHw, dwNcfgr);\r
+ GMAC_DmaConfigure(pHw, dwDcfgr);\r
+}\r
+\r
+\r
+/**\r
+ * Initialize necessary allocated buffer lists for GMAC Driver to transfer data.\r
+ * Must be invoked after GMACD_Init() but before RX/TX start.\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ * \param pRxBuffer Pointer to allocated buffer for RX. The address should\r
+ * be 8-byte aligned and the size should be\r
+ * GMAC_RX_UNITSIZE * wRxSize.\r
+ * \param pRxD Pointer to allocated RX descriptor list.\r
+ * \param wRxSize RX size, in number of registered units (RX descriptors).\r
+ * \param pTxBuffer Pointer to allocated buffer for TX. The address should\r
+ * be 8-byte aligned and the size should be\r
+ * GMAC_TX_UNITSIZE * wTxSize.\r
+ * \param pTxD Pointer to allocated TX descriptor list.\r
+ * \param pTxCb Pointer to allocated TX callback list.\r
+ * \param wTxSize TX size, in number of registered units (TX descriptors).\r
+ * \return GMACD_OK or GMACD_PARAM.\r
+ * \note If input address is not 8-byte aligned the address is automatically\r
+ * adjusted and the list size is reduced by one.\r
+ */\r
+uint8_t GMACD_InitTransfer( sGmacd *pGmacd,\r
+ uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,\r
+ uint16_t wRxSize,\r
+ uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,\r
+ uint16_t wTxSize,\r
+ gmacQueList_t queIdx)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+\r
+ if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;\r
+\r
+ /* Assign RX buffers */\r
+ if ( ((uint32_t)pRxBuffer & 0x7)\r
+ || ((uint32_t)pRxD & 0x7) )\r
+ {\r
+ wRxSize --;\r
+ TRACE_DEBUG("RX list address adjusted\n\r");\r
+ }\r
+ pGmacd->queueList[queIdx].pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);\r
+ pGmacd->queueList[queIdx].pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);\r
+ pGmacd->queueList[queIdx].wRxListSize = wRxSize;\r
+ /* Assign TX buffers */\r
+ if ( ((uint32_t)pTxBuffer & 0x7)\r
+ || ((uint32_t)pTxD & 0x7) )\r
+ {\r
+ wTxSize --;\r
+ TRACE_DEBUG("TX list address adjusted\n\r");\r
+ }\r
+ pGmacd->queueList[queIdx].pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);\r
+ pGmacd->queueList[queIdx].pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);\r
+ pGmacd->queueList[queIdx].wTxListSize = wTxSize;\r
+ pGmacd->queueList[queIdx].fTxCbList = pTxCb;\r
+ \r
+ /* Reset TX & RX */\r
+ GMACD_ResetRx(pGmacd, queIdx);\r
+ GMACD_ResetTx(pGmacd, queIdx);\r
+ \r
+ \r
+ /* Setup the interrupts for RX/TX completion (and errors) */\r
+ switch(queIdx) \r
+ {\r
+ case GMAC_QUE_0:\r
+ /* YBP: Que 0 should be configured last so as to enable transmit and Receive in the NCR register */\r
+ \r
+ /* Enable Rx and Tx, plus the stats register. */\r
+ GMAC_TransmitEnable(pHw, 1);\r
+ GMAC_ReceiveEnable(pHw, 1);\r
+ GMAC_StatisticsWriteEnable(pHw, 1);\r
+\r
+ GMAC_EnableIt(pHw,\r
+ GMAC_INT_RX_BITS |\r
+ GMAC_INT_TX_BITS |\r
+ GMAC_INT_TX_ERR_BITS, GMAC_QUE_0);\r
+ break;\r
+ \r
+ case GMAC_QUE_1:\r
+ \r
+ \r
+ GMAC_EnableIt(pHw,\r
+ GMAC_INT_RX_BITS |\r
+ GMAC_INT_TX_BITS |\r
+ GMAC_INT_TX_ERR_BITS, GMAC_QUE_1);\r
+ break;\r
+ case GMAC_QUE_2:\r
+ \r
+ GMAC_EnableIt(pHw,\r
+ GMAC_INT_RX_BITS |\r
+ GMAC_INT_TX_BITS |\r
+ GMAC_INT_TX_ERR_BITS, GMAC_QUE_2);\r
+ break;\r
+ };\r
+ \r
+ return GMACD_OK;\r
+}\r
+\r
+\r
+/**\r
+ * Reset TX & RX queue & statistics\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ */\r
+void GMACD_Reset(sGmacd *pGmacd)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+\r
+ GMACD_ResetRx(pGmacd, GMAC_QUE_0);\r
+ GMACD_ResetRx(pGmacd, GMAC_QUE_1);\r
+ GMACD_ResetRx(pGmacd, GMAC_QUE_2);\r
+ \r
+ GMACD_ResetTx(pGmacd, GMAC_QUE_0);\r
+ GMACD_ResetTx(pGmacd, GMAC_QUE_1);\r
+ GMACD_ResetTx(pGmacd, GMAC_QUE_2);\r
+ \r
+ //memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats));\r
+ GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN\r
+ | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);\r
+}\r
+\r
+/**\r
+ * \brief Send a frame splitted into buffers. If the frame size is larger than transfer buffer size\r
+ * error returned. If frame transfer status is monitored, specify callback for each frame.\r
+ * \param pGmacd Pointer to GMAC Driver instance. \r
+ * \param sgl Pointer to a scatter-gather list describing the buffers of the ethernet frame.\r
+ */\r
+uint8_t GMACD_SendSG(sGmacd *pGmacd,\r
+ const sGmacSGList *sgl,\r
+ fGmacdTransferCallback fTxCb,\r
+ gmacQueList_t queIdx)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+ sGmacTxDescriptor *pTd = pGmacd->queueList[queIdx].pTxD;\r
+ sGmacTxDescriptor *pTxTd;\r
+ uint16_t wTxPos, wTxHead;\r
+ int i;\r
+\r
+ TRACE_DEBUG("%s\n\r", __FUNCTION__);\r
+\r
+ /* Check parameter */\r
+ if (!sgl->len) {\r
+ TRACE_ERROR("%s:: ethernet frame is empty.\r\n", __FUNCTION__);\r
+ return GMACD_PARAM;\r
+ }\r
+ if (sgl->len >= pGmacd->queueList[queIdx].wTxListSize) {\r
+ TRACE_ERROR("%s: ethernet frame has too many buffers.\r\n", __FUNCTION__);\r
+ return GMACD_PARAM;\r
+ }\r
+\r
+ /* Check available space */\r
+ if (GCIRC_SPACE(pGmacd->queueList[queIdx].wTxHead, pGmacd->queueList[queIdx].wTxTail, pGmacd->queueList[queIdx].wTxListSize) < (int)sgl->len)\r
+ return GMACD_TX_BUSY;\r
+\r
+ /* Tag end of TX queue */\r
+ wTxHead = fixed_mod(pGmacd->queueList[queIdx].wTxHead + sgl->len, pGmacd->queueList[queIdx].wTxListSize);\r
+ wTxPos = wTxHead;\r
+ pGmacd->queueList[queIdx].fTxCbList[wTxPos] = NULL;\r
+ pTxTd = &pTd[wTxPos];\r
+ pTxTd->status.val = GMAC_TX_USED_BIT; \r
+\r
+ /* Update buffer descriptors in reverse order to avoid a race \r
+ * condition with hardware.\r
+ */\r
+ for (i = (int)(sgl->len-1); i >= 0; --i) {\r
+ const sGmacSG *sg = &sgl->sg[i];\r
+ uint32_t status;\r
+\r
+ if (sg->size > GMAC_TX_UNITSIZE) {\r
+ TRACE_ERROR("%s: buffer size is too big.\r\n", __FUNCTION__);\r
+ return GMACD_PARAM;\r
+ }\r
+\r
+ if (wTxPos == 0)\r
+ wTxPos = pGmacd->queueList[queIdx].wTxListSize-1;\r
+ else\r
+ wTxPos--;\r
+\r
+ /* Reset TX callback */\r
+ pGmacd->queueList[queIdx].fTxCbList[wTxPos] = NULL;\r
+\r
+ pTxTd = &pTd[wTxPos];\r
+#ifdef GMAC_ZERO_COPY\r
+ /** Update buffer descriptor address word:\r
+ * MUST be done before status word to avoid a race condition.\r
+ */\r
+ pTxTd->addr = (uint32_t)sg->pBuffer; \r
+#else\r
+ /* Copy data into transmittion buffer */\r
+ if (sg->pBuffer && sg->size)\r
+ memcpy((void *)pTxTd->addr, sg->pBuffer, sg->size); \r
+#endif\r
+\r
+ /* Compute buffer descriptor status word */\r
+ status = sg->size & GMAC_LENGTH_FRAME;\r
+ if (i == (int)(sgl->len-1)) {\r
+ status |= GMAC_TX_LAST_BUFFER_BIT;\r
+ pGmacd->queueList[queIdx].fTxCbList[wTxPos] = fTxCb;\r
+ }\r
+ if (wTxPos == pGmacd->queueList[queIdx].wTxListSize-1)\r
+ status |= GMAC_TX_WRAP_BIT;\r
+\r
+ /* Update buffer descriptor status word: clear USED bit */\r
+ pTxTd->status.val = status;\r
+\r
+ /* Make newly initialized descriptor visible to hardware */\r
+ memory_barrier();\r
+ }\r
+\r
+ /* Update TX ring buffer pointers */\r
+ pGmacd->queueList[queIdx].wTxHead = wTxHead;\r
+\r
+ memory_barrier();\r
+ /* Now start to transmit if it is not already done */\r
+ GMAC_TransmissionStart(pHw);\r
+\r
+ return GMACD_OK;\r
+}\r
+\r
+/**\r
+ * \brief Send a packet with GMAC. If the packet size is larger than transfer buffer size \r
+ * error returned. If packet transfer status is monitored, specify callback for each packet.\r
+ * \param pGmacd Pointer to GMAC Driver instance. \r
+ * \param buffer The buffer to be send\r
+ * \param size The size of buffer to be send\r
+ * \param fGMAC_TxCallback Threshold Wakeup callback\r
+ * \param fWakeUpCb TX Wakeup\r
+ * \return OK, Busy or invalid packet\r
+ */\r
+uint8_t GMACD_Send(sGmacd *pGmacd,\r
+ void *pBuffer,\r
+ uint32_t size,\r
+ fGmacdTransferCallback fTxCb,\r
+ gmacQueList_t queIdx)\r
+{\r
+ sGmacSGList sgl;\r
+ sGmacSG sg;\r
+\r
+ /* Init single entry scatter-gather list */\r
+ sg.size = size;\r
+ sg.pBuffer = pBuffer;\r
+ sgl.len = 1;\r
+ sgl.sg = &sg;\r
+\r
+ return GMACD_SendSG(pGmacd, &sgl, fTxCb, queIdx);\r
+}\r
+\r
+\r
+/**\r
+ * Return current load of TX.\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ */\r
+uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx)\r
+{\r
+ uint16_t head = pGmacd->queueList[queIdx].wTxHead;\r
+ uint16_t tail = pGmacd->queueList[queIdx].wTxTail;\r
+ return GCIRC_CNT(head, tail, pGmacd->queueList[queIdx].wTxListSize);\r
+}\r
+\r
+/**\r
+ * \brief Receive a packet with GMAC.\r
+ * If not enough buffer for the packet, the remaining data is lost but right\r
+ * frame length is returned.\r
+ * \param pGmacd Pointer to GMAC Driver instance. \r
+ * \param pFrame Buffer to store the frame\r
+ * \param frameSize Size of the frame\r
+ * \param pRcvSize Received size\r
+ * \return OK, no data, or frame too small\r
+ */\r
+uint8_t GMACD_Poll(sGmacd * pGmacd, \r
+ uint8_t *pFrame, \r
+ uint32_t frameSize, \r
+ uint32_t *pRcvSize,\r
+ gmacQueList_t queIdx)\r
+{\r
+\r
+ uint16_t bufferLength;\r
+ uint32_t tmpFrameSize = 0;\r
+ uint8_t *pTmpFrame = 0;\r
+ uint32_t tmpIdx = pGmacd->queueList[queIdx].wRxI;\r
+ volatile sGmacRxDescriptor *pRxTd = &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; \r
+\r
+ uint8_t isFrame = 0;\r
+ \r
+ if (pFrame == NULL) return GMACD_PARAM;\r
+\r
+ /* Set the default return value */\r
+ *pRcvSize = 0;\r
+ \r
+ /* Process received RxTd */\r
+ while ((pRxTd->addr.val & GMAC_RX_OWNERSHIP_BIT) == GMAC_RX_OWNERSHIP_BIT)\r
+ {\r
+ /* A start of frame has been received, discard previous fragments */\r
+ if ((pRxTd->status.val & GMAC_RX_SOF_BIT) == GMAC_RX_SOF_BIT)\r
+ {\r
+ /* Skip previous fragment */\r
+ while (tmpIdx != pGmacd->queueList[queIdx].wRxI)\r
+ {\r
+ pRxTd = &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; \r
+ pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);\r
+ GCIRC_INC(pGmacd->queueList[queIdx].wRxI, pGmacd->queueList[queIdx].wRxListSize);\r
+ }\r
+ pTmpFrame = pFrame;\r
+ tmpFrameSize = 0;\r
+ /* Start to gather buffers in a frame */\r
+ isFrame = 1;\r
+ }\r
+ /* Increment the pointer */\r
+ GCIRC_INC(tmpIdx, pGmacd->queueList[queIdx].wRxListSize); \r
+ /* Copy data in the frame buffer */\r
+ if (isFrame) {\r
+ if (tmpIdx == pGmacd->queueList[queIdx].wRxI)\r
+ {\r
+ TRACE_INFO("no EOF (Invalid of buffers too small)\n\r");\r
+\r
+ do {\r
+ pRxTd = &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; \r
+ pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);\r
+ GCIRC_INC(pGmacd->queueList[queIdx].wRxI, pGmacd->queueList[queIdx].wRxListSize);\r
+ } while(tmpIdx != pGmacd->queueList[queIdx].wRxI);\r
+ return GMACD_RX_NULL;\r
+ }\r
+\r
+ /* Copy the buffer into the application frame */\r
+ bufferLength = GMAC_RX_UNITSIZE;\r
+ if ((tmpFrameSize + bufferLength) > frameSize)\r
+ {\r
+ bufferLength = frameSize - tmpFrameSize;\r
+ }\r
+ \r
+ memcpy(pTmpFrame, (void*)(pRxTd->addr.val & GMAC_ADDRESS_MASK), bufferLength); \r
+ pTmpFrame += bufferLength;\r
+ tmpFrameSize += bufferLength;\r
+\r
+ /* An end of frame has been received, return the data */\r
+ if ((pRxTd->status.val & GMAC_RX_EOF_BIT) == GMAC_RX_EOF_BIT)\r
+ {\r
+ /* Frame size from the GMAC */\r
+ *pRcvSize = (pRxTd->status.val & GMAC_LENGTH_FRAME);\r
+\r
+ /* Application frame buffer is too small all data have not been copied */\r
+ if (tmpFrameSize < *pRcvSize) {\r
+ return GMACD_SIZE_TOO_SMALL;\r
+ }\r
+ TRACE_DEBUG("packet %d-%d (%d)\n\r", pGmacd->queueList[queIdx].wRxI, tmpIdx, *pRcvSize);\r
+ /* All data have been copied in the application frame buffer => release TD */\r
+ while (pGmacd->queueList[queIdx].wRxI != tmpIdx)\r
+ {\r
+ pRxTd = &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; \r
+ pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);\r
+ GCIRC_INC(pGmacd->queueList[queIdx].wRxI, pGmacd->queueList[queIdx].wRxListSize);\r
+ }\r
+ return GMACD_OK;\r
+ }\r
+ }\r
+ \r
+ /* SOF has not been detected, skip the fragment */\r
+ else {\r
+ pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);\r
+ pGmacd->queueList[queIdx].wRxI = tmpIdx;\r
+ }\r
+ \r
+ /* Process the next buffer */\r
+ pRxTd = &pGmacd->queueList[queIdx].pRxD[tmpIdx];\r
+ memory_barrier();\r
+ }\r
+ return GMACD_RX_NULL;\r
+}\r
+\r
+/**\r
+ * \brief Registers pRxCb callback. Callback will be invoked after the next received\r
+ * frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task call GMAC_Set_RxCb()\r
+ * to register pRxCb() callback and enters suspend state. The callback is in charge \r
+ * to resume the task once a new frame has been received. The next time GMAC_Poll()\r
+ * is called, it will be successfull.\r
+ * \param pGmacd Pointer to GMAC Driver instance. \r
+ * \param pRxCb Pointer to callback function\r
+ * \return OK, no data, or frame too small\r
+ */\r
+\r
+void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb, gmacQueList_t queIdx)\r
+{\r
+ Gmac *pHw = pGmacd->pHw;\r
+\r
+ if (fRxCb == NULL)\r
+ {\r
+ GMAC_DisableIt(pHw, GMAC_IDR_RCOMP, queIdx);\r
+ pGmacd->queueList[queIdx].fRxCb = NULL;\r
+ }\r
+ else\r
+ {\r
+ pGmacd->queueList[queIdx].fRxCb = fRxCb;\r
+ GMAC_EnableIt(pHw, GMAC_IER_RCOMP, queIdx);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * Register/Clear TX wakeup callback.\r
+ *\r
+ * When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application \r
+ * task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and \r
+ * enters suspend state. The callback is in charge to resume the task once \r
+ * several TD have been released. The next time GMACD_Send() will be called,\r
+ * it shall be successfull.\r
+ *\r
+ * This function is usually invoked with NULL callback from the TX wakeup\r
+ * callback itself, to unregister. Once the callback has resumed the\r
+ * application task, there is no need to invoke the callback again.\r
+ *\r
+ * \param pGmacd Pointer to GMAC Driver instance.\r
+ * \param fWakeup Wakeup callback.\r
+ * \param bThreshould Number of free TD before wakeup callback invoked.\r
+ * \return GMACD_OK, GMACD_PARAM on parameter error.\r
+ */\r
+uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,\r
+ fGmacdWakeupCallback fWakeup,\r
+ uint8_t bThreshold,\r
+ gmacQueList_t queIdx)\r
+{\r
+ if (fWakeup == NULL)\r
+ {\r
+ pGmacd->queueList[queIdx].fWakupCb = NULL;\r
+ }\r
+ else\r
+ {\r
+ if (bThreshold <= pGmacd->queueList[queIdx].wTxListSize)\r
+ {\r
+ pGmacd->queueList[queIdx].fWakupCb = fWakeup;\r
+ pGmacd->queueList[queIdx].bWakeupThreshold = bThreshold;\r
+ }\r
+ else\r
+ {\r
+ return GMACD_PARAM;\r
+ }\r
+ }\r
+\r
+ return GMACD_OK;\r
+}\r
+\r
+//uint32_t GMACD_GetQ0BuffBaseAddr (uint8_t ** baseAddrPtr)\r
+//{\r
+// *baseAddrPtr = &gs_uc_rx_buffer[0u];\r
+// return sizeof(gs_uc_rx_buffer);\r
+//}\r
+//\r
+//uint32_t GMACD_GetQ1BuffBaseAddr (uint8_t ** baseAddrPtr)\r
+//{\r
+// *baseAddrPtr = &gs_uc_q1_rx_buffer[0u];\r
+// return sizeof(gs_uc_q1_rx_buffer);\r
+//}\r
+//\r
+//uint32_t GMACD_GetQ2BuffBaseAddr (uint8_t ** baseAddrPtr)\r
+//{\r
+// *baseAddrPtr = &gs_uc_q2_rx_buffer[0u];\r
+// return sizeof(gs_uc_q2_rx_buffer);\r
+//}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ *\r
+ * Implementation of High Speed MultiMedia Card Interface (HSMCI) controller.\r
+ */\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <assert.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup hsmci_functions\r
+ *@{\r
+ */\r
+\r
+/**\r
+ * \brief Enable Multi-Media Interface\r
+ *\r
+ * \param pRMci Pointer to a Hsmci instance\r
+ */\r
+extern void HSMCI_Enable(Hsmci* pRMci)\r
+{\r
+ pRMci->HSMCI_CR = HSMCI_CR_MCIEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable Multi-Media Interface\r
+ *\r
+ * \param pRMci Pointer to a Hsmci instance\r
+ */\r
+extern void HSMCI_Disable(Hsmci* pRMci)\r
+{\r
+ pRMci->HSMCI_CR = HSMCI_CR_MCIDIS;\r
+}\r
+\r
+/**\r
+ * \brief Reset (& Disable) Multi-Media Interface\r
+ *\r
+ * \param mci Pointer to a Hsmci instance\r
+ * \param bBackup Backup registers values to keep previous settings, including\r
+ * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG.\r
+ */\r
+extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup)\r
+{\r
+ if (bBackup)\r
+ {\r
+ uint32_t mr = pRMci->HSMCI_MR;\r
+ uint32_t dtor = pRMci->HSMCI_DTOR;\r
+ uint32_t sdcr = pRMci->HSMCI_SDCR;\r
+ uint32_t cstor = pRMci->HSMCI_CSTOR;\r
+ uint32_t dma = pRMci->HSMCI_DMA;\r
+ uint32_t cfg = pRMci->HSMCI_CFG;\r
+\r
+ pRMci->HSMCI_CR = HSMCI_CR_SWRST;\r
+\r
+ pRMci->HSMCI_MR = mr;\r
+ pRMci->HSMCI_DTOR = dtor;\r
+ pRMci->HSMCI_SDCR = sdcr;\r
+ pRMci->HSMCI_CSTOR = cstor;\r
+ pRMci->HSMCI_DMA = dma;\r
+ pRMci->HSMCI_CFG = cfg;\r
+ }\r
+ else\r
+ {\r
+ pRMci->HSMCI_CR = HSMCI_CR_SWRST;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Select slot\r
+ * \param pRMci Pointer to a Hsmci instance\r
+ * \param bSlot Slot ID (0~3 for A~D).\r
+ */\r
+extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth)\r
+{\r
+ uint32_t dwSdcr;\r
+ dwSdcr = (HSMCI_SDCR_SDCSEL_Msk & bSlot);\r
+ switch(bBusWidth)\r
+ {\r
+ case 1:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1;\r
+ break;\r
+ case 4:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4;\r
+ break;\r
+ case 8:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set slot\r
+ * \param pRMci Pointer to a Hsmci instance\r
+ * \param bSlot Slot ID (0~3 for A~D).\r
+ */\r
+extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot)\r
+{\r
+ uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCSEL_Msk;\r
+ pRMci->HSMCI_SDCR = dwSdcr | (HSMCI_SDCR_SDCSEL_Msk & bSlot);\r
+}\r
+\r
+/**\r
+ * \brief Set bus width of MCI\r
+ * \param pRMci Pointer to a Hsmci instance\r
+ * \param bBusWidth 1,4 or 8 (bits).\r
+ */\r
+extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth)\r
+{\r
+ uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk;\r
+ switch(bBusWidth)\r
+ {\r
+ case 1:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1;\r
+ break;\r
+ case 4:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4;\r
+ break;\r
+ case 8:\r
+ pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return bus width setting.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \return 1, 4 or 8.\r
+ */\r
+extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci)\r
+{\r
+ switch(pRMci->HSMCI_SDCR & HSMCI_SDCR_SDCBUS_Msk)\r
+ {\r
+ case HSMCI_SDCR_SDCBUS_1: return 1;\r
+ case HSMCI_SDCR_SDCBUS_4: return 4;\r
+ case HSMCI_SDCR_SDCBUS_8: return 8;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configures a MCI peripheral as specified.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \param dwMode Value of the MCI Mode register.\r
+ */\r
+extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode)\r
+{\r
+ pRMci->HSMCI_MR = dwMode;\r
+}\r
+\r
+/**\r
+ * \brief Return mode register\r
+ * \param pRMci Pointer to an MCI instance.\r
+ */\r
+extern uint32_t HSMCI_GetMode(Hsmci * pRMci)\r
+{\r
+ return pRMci->HSMCI_MR;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable R/W proof\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \param bRdProof Read proof enable/disable.\r
+ * \param bWrProof Write proof enable/disable.\r
+ */\r
+extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof)\r
+{\r
+ uint32_t mr = pRMci->HSMCI_MR;\r
+ pRMci->HSMCI_MR = (mr & (~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF)))\r
+ | (bRdProof ? HSMCI_MR_RDPROOF : 0)\r
+ | (bWrProof ? HSMCI_MR_WRPROOF : 0)\r
+ ;\r
+}\r
+\r
+/**\r
+ * \brief Padding value setting.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \param bPadvEn Padding value 0xFF/0x00.\r
+ */\r
+extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv)\r
+{\r
+ if (bPadv)\r
+ {\r
+ pRMci->HSMCI_MR |= HSMCI_MR_PADV;\r
+ }\r
+ else\r
+ {\r
+ pRMci->HSMCI_MR &= ~HSMCI_MR_PADV;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Force byte transfer enable/disable.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \param bFByteEn FBYTE enable/disable.\r
+ */\r
+extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn)\r
+{\r
+ if (bFByteEn)\r
+ {\r
+ pRMci->HSMCI_MR |= HSMCI_MR_FBYTE;\r
+ }\r
+ else\r
+ {\r
+ pRMci->HSMCI_MR &= ~HSMCI_MR_FBYTE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if Force Byte mode enabled.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \return 1 if _FBYTE is enabled.\r
+ */\r
+extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci)\r
+{\r
+ return ((pRMci->HSMCI_MR & HSMCI_MR_FBYTE) > 0);\r
+}\r
+\r
+/**\r
+ * \brief Set Clock Divider & Power save divider for MCI.\r
+ *\r
+ * \param pRMci Pointer to an MCI instance.\r
+ * \param bClkDiv Clock Divider value (0 ~ 255).\r
+ * \param bPwsDiv Power Saving Divider (1 ~ 7).\r
+ */\r
+extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv)\r
+{\r
+ uint32_t mr = pRMci->HSMCI_MR;\r
+ uint32_t clkdiv ,clkodd;\r
+ clkdiv = bClkDiv - 2 ;\r
+ clkodd = (bClkDiv & 1)? HSMCI_MR_CLKODD: 0;\r
+ clkdiv = clkdiv >> 1;\r
+\r
+ pRMci->HSMCI_MR = (mr & ~(HSMCI_MR_CLKDIV_Msk | HSMCI_MR_PWSDIV_Msk))\r
+ | HSMCI_MR_CLKDIV(clkdiv)\r
+ | HSMCI_MR_PWSDIV(bPwsDiv)\r
+ | clkodd\r
+ ;\r
+}\r
+\r
+/**\r
+ * \brief Enables one or more interrupt sources of MCI peripheral.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources)\r
+{\r
+ pRMci->HSMCI_IER = dwSources;\r
+}\r
+\r
+/**\r
+ * \brief Disable one or more interrupt sources of MCI peripheral.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources)\r
+{\r
+ pRMci->HSMCI_IDR = dwSources;\r
+}\r
+\r
+/**\r
+ * \brief Return the interrupt mask register.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return MCI interrupt mask register.\r
+ */\r
+extern uint32_t HSMCI_GetItMask(Hsmci *pRMci)\r
+{\r
+ return (pRMci->HSMCI_IMR) ;\r
+}\r
+\r
+/**\r
+ * \brief Set block len & count for transfer\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param wBlkLen Block size.\r
+ * \param wCnt Block(byte) count.\r
+ */\r
+extern void HSMCI_ConfigureTransfer(Hsmci *pRMci,\r
+ uint16_t wBlkLen,\r
+ uint16_t wCnt)\r
+{\r
+ pRMci->HSMCI_BLKR = (wBlkLen << 16) | wCnt;\r
+}\r
+\r
+/**\r
+ * \brief Set block length\r
+ *\r
+ * Count is reset to 0.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param wBlkSize Block size.\r
+ */\r
+extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize)\r
+{\r
+ pRMci->HSMCI_BLKR = wBlkSize << 16;\r
+}\r
+\r
+/**\r
+ * \brief Set block (byte) count\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param wBlkCnt Block(byte) count.\r
+ */\r
+extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt)\r
+{\r
+ pRMci->HSMCI_BLKR |= wBlkCnt;\r
+}\r
+\r
+/**\r
+ * \brief Configure the Completion Signal Timeout\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwConfigure Completion Signal Timeout configure.\r
+ */\r
+extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure)\r
+{\r
+ pRMci->HSMCI_CSTOR = dwConfigure;\r
+}\r
+\r
+/**\r
+ * \brief Configure the Data Timeout\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwConfigure Data Timeout configure.\r
+ */\r
+extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure)\r
+{\r
+ pRMci->HSMCI_DTOR = dwConfigure;\r
+}\r
+\r
+/**\r
+ * \brief Send command\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwCmd Command register value.\r
+ * \param dwArg Argument register value.\r
+ */\r
+extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg)\r
+{\r
+ pRMci->HSMCI_ARGR = dwArg;\r
+ pRMci->HSMCI_CMDR = dwCmd;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return the response register.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return MCI response register.\r
+ */\r
+extern uint32_t HSMCI_GetResponse(Hsmci *pRMci)\r
+{\r
+ return pRMci->HSMCI_RSPR[0];\r
+}\r
+\r
+/**\r
+ * \brief Return the receive data register.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return MCI receive data register.\r
+ */\r
+extern uint32_t HSMCI_Read(Hsmci *pRMci)\r
+{\r
+ return pRMci->HSMCI_RDR;\r
+}\r
+\r
+/**\r
+ * \brief Read from FIFO\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param pdwData Pointer to data buffer.\r
+ * \param dwSize Size of data buffer (in DWord).\r
+ */\r
+extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize)\r
+{\r
+ volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO);\r
+ register uint32_t c4, c1;\r
+\r
+ if (dwSize == 0)\r
+ return;\r
+\r
+ c4 = dwSize >> 2;\r
+ c1 = dwSize & 0x3;\r
+\r
+ for(;c4;c4 --)\r
+ {\r
+ *pdwData ++ = *pFIFO ++;\r
+ *pdwData ++ = *pFIFO ++;\r
+ *pdwData ++ = *pFIFO ++;\r
+ *pdwData ++ = *pFIFO ++;\r
+ }\r
+ for(;c1;c1 --)\r
+ {\r
+ *pdwData ++ = *pFIFO ++;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sends data through MCI peripheral.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param\r
+ */\r
+extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData)\r
+{\r
+ pRMci->HSMCI_TDR = dwData;\r
+}\r
+\r
+/**\r
+ * \brief Write to FIFO\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param pdwData Pointer to data buffer.\r
+ * \param dwSize Size of data buffer (In DWord).\r
+ */\r
+extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize)\r
+{\r
+ volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO);\r
+ register uint32_t c4, c1;\r
+\r
+ if (dwSize == 0)\r
+ return;\r
+\r
+ c4 = dwSize >> 2;\r
+ c1 = dwSize & 0x3;\r
+\r
+ for(;c4;c4 --)\r
+ {\r
+ *pFIFO ++ = *pdwData ++;\r
+ *pFIFO ++ = *pdwData ++;\r
+ *pFIFO ++ = *pdwData ++;\r
+ *pFIFO ++ = *pdwData ++;\r
+ }\r
+ for(;c1;c1 --)\r
+ {\r
+ *pFIFO ++ = *pdwData ++;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return the status register.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return MCI status register.\r
+ */\r
+extern uint32_t HSMCI_GetStatus(Hsmci *pRMci)\r
+{\r
+ return pRMci->HSMCI_SR;\r
+}\r
+\r
+/**\r
+ * \brief Configure the HSMCI DMA\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwConfigure Configure value. \r
+ */\r
+extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure)\r
+{\r
+ pRMci->HSMCI_DMA = dwConfigure;\r
+}\r
+\r
+/**\r
+ * \brief Enable the HSMCI DMA\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param bEnable 1 to enable, 0 to disable.\r
+ */\r
+extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable)\r
+{\r
+ if (bEnable)\r
+ {\r
+ pRMci->HSMCI_DMA |= HSMCI_DMA_DMAEN ;//| HSMCI_DMA_CHKSIZE_32;\r
+ }\r
+ else\r
+ {\r
+ pRMci->HSMCI_DMA &= ~HSMCI_DMA_DMAEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure the HSMCI\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwConfigure Configure value. \r
+ */\r
+extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure)\r
+{\r
+ pRMci->HSMCI_CFG = dwConfigure;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable High-Speed mode for MCI\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param bHsEnable Enable/Disable high-speed.\r
+ */\r
+extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable)\r
+{\r
+ if (bHsEnable)\r
+ {\r
+ pRMci->HSMCI_CFG |= HSMCI_CFG_HSMODE;\r
+ }\r
+ else\r
+ {\r
+ pRMci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if High-speed mode is enabled on MCI\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return 1 \r
+ */\r
+extern uint8_t HSMCI_IsHsEnabled(Hsmci * pRMci)\r
+{\r
+ return ((pRMci->HSMCI_CFG & HSMCI_CFG_HSMODE) > 0);\r
+}\r
+\r
+/**\r
+ * \brief Configure the Write Protection Mode\r
+ * \r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \param dwConfigure WP mode configure value. \r
+ */\r
+extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure)\r
+{\r
+ pRMci->HSMCI_WPMR = dwConfigure;\r
+}\r
+\r
+/**\r
+ * \brief Return the write protect status register.\r
+ *\r
+ * \param pRMci Pointer to an Hsmci instance.\r
+ * \return MCI write protect status register.\r
+ */\r
+extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci)\r
+{\r
+ return pRMci->HSMCI_WPSR;\r
+}\r
+\r
+/**@}*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT ICMLL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup icm_module Working with ICM\r
+ * The TWI driver provides the interface to True Random Number Generator (ICM) passes the American NIST Special Publication 800-22 and Diehard\r
+ Random Tests Suites.\r
+ The ICM may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by\r
+ FIPS PUB 140-2 and 140-3. use the TWI\r
+ * peripheral.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Configures a TWI peripheral to operate in master mode, at the given\r
+ * frequency (in Hz) using TWI_Configure(). </li>\r
+ * <li> Sends a STOP condition on the TWI using TWI_Stop().</li>\r
+ * <li> Starts a read operation on the TWI bus with the specified slave using\r
+ * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever\r
+ * a byte is available (poll using TWI_ByteReceived()).</li>\r
+ * <li> Starts a write operation on the TWI to access the selected slave using\r
+ * TWI_StartWrite(). A byte of data must be provided to start the write;\r
+ * other bytes are written next.</li>\r
+ * <li> Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().\r
+ * This function must be called once before TWI_StartWrite() with the first byte of data\r
+ * to send, then it ICMll be called repeatedly after that to send the remaining bytes.</li>\r
+ * <li> Check if a byte has been received and can be read on the given TWI\r
+ * peripheral using TWI_ByteReceived().<\r
+ * Check if a byte has been sent using TWI_ByteSent().</li>\r
+ * <li> Check if the current transmission is complete (the STOP has been sent)\r
+ * using TWI_TransferComplete().</li>\r
+ * <li> Enables & disable the selected interrupts sources on a TWI peripheral\r
+ * using TWI_EnableIt() and TWI_DisableIt().</li>\r
+ * <li> Get current status register of the given TWI peripheral using\r
+ * TWI_GetStatus(). Get current status register of the given TWI peripheral, but\r
+ * masking interrupt sources which are not currently enabled using\r
+ * TWI_GetMaskedStatus().</li>\r
+ * </ul>\r
+ * For more accurate information, please look at the TWI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref twi.c\n\r
+ * \ref twi.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of True Random Number Generator (ICM)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enable ICM, the ICM controller is activated\r
+ */\r
+void ICM_Enable(void)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_ENABLE;\r
+}\r
+\r
+/**\r
+ * \brief Disable ICM, if a region is active, this region is terminated\r
+ */\r
+void ICM_Disable(void)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_DISABLE;\r
+}\r
+\r
+/**\r
+ * \brief Resets the ICM controller.\r
+ */\r
+void ICM_SoftReset(void)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_SWRST;\r
+}\r
+\r
+/**\r
+ * \brief Recompute Internal hash.\r
+ * \param region, When REHASH[region] is set to one, the region digest is re-computed. \r
+ * \note This bit is only available when Region monitoring is disabled.\r
+ */\r
+void ICM_ReComputeHash(uint8_t region)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_REHASH(region);\r
+}\r
+\r
+/**\r
+ * \brief Enable region monitoring for given region\r
+ * \param region, When bit RMEN[region] is set to one, the monitoring of Region is activated.\r
+ */\r
+void ICM_EnableMonitor(uint8_t region)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_RMEN(region);\r
+}\r
+\r
+/**\r
+ * \brief Disable region monitoring for given region\r
+ * \param region, When bit RMDIS[region] is set to one, the monitoring of Region is disabled.\r
+ */\r
+void ICM_DisableMonitor(uint8_t region)\r
+{\r
+ ICM->ICM_CTRL = ICM_CTRL_RMDIS(region);\r
+}\r
+\r
+/**\r
+ * \brief Configures an ICM peripheral with the specified parameters.\r
+ * \param mode Desired value for the ICM mode register (see the datasheet).\r
+ */\r
+void ICM_Configure(uint32_t mode)\r
+{\r
+ ICM->ICM_CFG = mode; \r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a ICM peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void ICM_EnableIt(uint32_t sources)\r
+{\r
+ ICM->ICM_IER = sources;\r
+}\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a ICM peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void ICM_DisableIt(uint32_t sources)\r
+{\r
+ ICM->ICM_IDR = sources;\r
+}\r
+\r
+/**\r
+ * \brief Get the current interrupt status register of the given ICM peripheral.\r
+ * \return ICM status register.\r
+ */\r
+uint32_t ICM_GetIntStatus(void)\r
+{\r
+ return ICM->ICM_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given ICM peripheral.\r
+ * \return ICM status register.\r
+ */\r
+uint32_t ICM_GetStatus(void)\r
+{\r
+ return ICM->ICM_SR;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get the undefined access status register of the given ICM peripheral.\r
+ * \return ICM status register.\r
+ */\r
+uint32_t ICM_GetUStatus(void)\r
+{\r
+ return ICM->ICM_UASR;\r
+}\r
+\r
+/**\r
+ * \brief Set descriptor area start address register.\r
+ * \param addr start address\r
+ * \note The start address is a multiple of the total size of the data structure (64 bytes).\r
+ */\r
+void ICM_SetDescStartAddress(uint32_t addr)\r
+{\r
+ ICM->ICM_DSCR = addr;\r
+}\r
+\r
+/**\r
+ * \brief Set hash area start address register.\r
+ * \param addr start address\r
+ * \note This field points at the Hash memory location. The address must be a multiple of 128 bytes.\r
+ */\r
+void ICM_SetHashStartAddress(uint32_t addr)\r
+{\r
+ ICM->ICM_HASH = addr;\r
+}\r
+\r
+/**\r
+ * \brief Set ICM user initial Hash value register.\r
+ * \param val Initial Hash Value\r
+ */\r
+void ICM_SetInitHashValue(uint32_t val)\r
+{\r
+ ICM->ICM_UIHVAL[0] = ICM_UIHVAL_VAL(val);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enable ISI\r
+ */\r
+void ISI_Enable(void)\r
+{\r
+ REG_ISI_CR |= ISI_CR_ISI_EN;\r
+ while( (REG_ISI_SR & ISI_CR_ISI_EN)!=ISI_CR_ISI_EN);\r
+ REG_ISI_DMA_CHER |= ISI_DMA_CHER_P_CH_EN | ISI_DMA_CHER_C_CH_EN;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable ISI\r
+ */\r
+void ISI_Disable(void)\r
+{\r
+ REG_ISI_CR |= ISI_CR_ISI_DIS;\r
+ REG_ISI_DMA_CHDR |= ISI_DMA_CHDR_P_CH_DIS;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable ISI interrupt\r
+ * \param flag of interrupt to enable\r
+ */\r
+void ISI_EnableInterrupt(uint32_t flag)\r
+{\r
+ REG_ISI_IER = flag;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable ISI interrupt\r
+ * \param flag of interrupt to disable\r
+ */\r
+void ISI_DisableInterrupt(uint32_t flag)\r
+{\r
+ REG_ISI_IDR = flag;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Return ISI status register\r
+ * \return Status of ISI register\r
+ */\r
+uint32_t ISI_StatusRegister(void)\r
+{\r
+ return(REG_ISI_SR);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable Codec path for capture next frame\r
+ */\r
+void ISI_CodecPathFull(void)\r
+{\r
+ // The codec path is enabled and the next frame is captured.\r
+ // Both codec and preview datapaths are working simultaneously\r
+ REG_ISI_CR |= ISI_CR_ISI_CDC;\r
+ REG_ISI_CFG1 |= ISI_CFG1_FULL;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Set frame rate\r
+ * \param frate frame rate capture\r
+ */\r
+void ISI_SetFrame(uint32_t frate)\r
+{\r
+ if( frate > 7 ) {\r
+ TRACE_ERROR("FRate too big\n\r");\r
+ frate = 7;\r
+ }\r
+ REG_ISI_CFG1 |= ISI_CFG1_FRATE(frate);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get the number of byte per pixels\r
+ * \param bmpRgb BMP type can be YUV or RGB\r
+ */\r
+uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb)\r
+{\r
+ uint8_t nbByte_Pixel;\r
+\r
+ if (bmpRgb == RGB) {\r
+ if ((REG_ISI_CFG2 & ISI_CFG2_RGB_MODE) == ISI_CFG2_RGB_MODE){\r
+ // RGB: 5:6:5 16bits/pixels\r
+ nbByte_Pixel = 2;\r
+ } \r
+ else {\r
+ // RGB: 8:8:8 24bits/pixels\r
+ nbByte_Pixel = 3;\r
+ }\r
+ } \r
+ else {\r
+ // YUV: 2 pixels for 4 bytes\r
+ nbByte_Pixel = 2;\r
+ }\r
+ return nbByte_Pixel;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reset ISI\r
+ */\r
+void ISI_Reset(void)\r
+{\r
+ uint32_t timeout=0;\r
+\r
+ // Resets the image sensor interface.\r
+ // Finish capturing the current frame and then shut down the module.\r
+ REG_ISI_CR = ISI_CR_ISI_SRST | ISI_CR_ISI_DIS;\r
+ // wait Software reset has completed successfully.\r
+ while( (!(REG_ISI_SR & ISI_SR_SRST))\r
+ && (timeout < 0x5000) ){\r
+ timeout++;\r
+ }\r
+ if( timeout == 0x5000 ) {\r
+ TRACE_ERROR("ISI-Reset timeout\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief ISI initialize\r
+ * \param pVideo structure of video driver\r
+ */\r
+void ISI_Init(pIsi_Video pVideo)\r
+{\r
+ uint32_t hRatio, vRatio;\r
+ ISI_Reset();\r
+\r
+ // SLD pixel clock periods to wait before the beginning of a line.\r
+ // SFD lines are skipped at the beginning of the frame.\r
+ REG_ISI_CFG1 |= ISI_CFG1_SLD(pVideo->Hblank) + ISI_CFG1_SFD(pVideo->Vblank);\r
+ REG_ISI_CFG1 |=ISI_CFG1_DISCR;\r
+ TRACE_DEBUG("ISI_CFG1=0x%X\n\r", REG_ISI_CFG1);\r
+\r
+ // IM_VSIZE: Vertical size of the Image sensor [0..2047]\r
+ // Vertical size = IM_VSIZE + 1\r
+ // IM_HSIZE: Horizontal size of the Image sensor [0..2047]\r
+ // Horizontal size = IM_HSIZE + 1\r
+ // YCC_SWAP : YCC image data \r
+ REG_ISI_CFG2 = ISI_CFG2_IM_VSIZE(pVideo->codec_vsize - 1)\r
+ + ISI_CFG2_IM_HSIZE(pVideo->codec_hsize - 1);\r
+ \r
+ if (pVideo->rgb_or_yuv == RGB) {\r
+ REG_ISI_CFG2 |= ISI_CFG2_COL_SPACE | ISI_CFG2_RGB_MODE ;\r
+ }\r
+ else {\r
+ REG_ISI_CFG2|= ISI_CFG2_YCC_SWAP_MODE2 ;\r
+ }\r
+ TRACE_DEBUG("ISI_CFG2=0x%X\n\r", REG_ISI_CFG2);\r
+\r
+ // Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).\r
+ // Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).\r
+\r
+ if( (pVideo->lcd_vsize > 480) || (pVideo->lcd_hsize > 640)) {\r
+ TRACE_ERROR("Size LCD bad define %d, %d\n\r",pVideo->lcd_vsize ,pVideo->lcd_hsize);\r
+ REG_ISI_PSIZE = ((480 - 1) ) + (((640-1) << 16) );\r
+ }\r
+ else {\r
+ REG_ISI_PSIZE = ((pVideo->lcd_vsize -1)) + (((pVideo->lcd_hsize -1) << 16) );\r
+ }\r
+ // DEC_FACTOR is 8-bit width, range is from 16 to 255. \r
+ // Values from 0 to 16 do not perform any decimation.\r
+ //REG_ISI_PDECF = (16 * pVideo->codec_hsize)/640;\r
+ hRatio = (16 * pVideo->codec_hsize)/(pVideo->lcd_hsize); \r
+ vRatio = (16 * pVideo->codec_vsize)/(pVideo->lcd_vsize); \r
+ REG_ISI_PDECF = (hRatio > vRatio )? vRatio: hRatio;\r
+\r
+ if (REG_ISI_PDECF < 16) REG_ISI_PDECF = 16;\r
+\r
+ REG_ISI_DMA_P_DSCR = pVideo->Isi_fbd_base;\r
+ REG_ISI_DMA_P_CTRL = ISI_DMA_P_CTRL_P_FETCH;\r
+ REG_ISI_DMA_P_ADDR = pVideo->lcd_fb_addr;\r
+\r
+ REG_ISI_DMA_C_DSCR = pVideo->codec_fbd_base;\r
+ REG_ISI_DMA_C_CTRL = ISI_DMA_C_CTRL_C_FETCH;\r
+ REG_ISI_DMA_C_ADDR = pVideo->codec_fb_addr;\r
+\r
+ // C0: Color Space Conversion Matrix Coefficient C0\r
+ // C1: Color Space Conversion Matrix Coefficient C1\r
+ // C2: Color Space Conversion Matrix Coefficient C2\r
+ // C3: Color Space Conversion Matrix Coefficient C3\r
+ REG_ISI_Y2R_SET0 = ISI_Y2R_SET0_C0(0x95)\r
+ + ISI_Y2R_SET0_C1(0xFF)\r
+ + ISI_Y2R_SET0_C2(0x68)\r
+ + ISI_Y2R_SET0_C3(0x32);\r
+\r
+ // C4: Color Space Conversion Matrix coefficient C4\r
+ // Yoff: Color Space Conversion Luminance 128 offset\r
+ // Croff: Color Space Conversion Red Chrominance 16 offset\r
+ // Cboff: Color Space Conversion Blue Chrominance 16 offset\r
+ REG_ISI_Y2R_SET1 = ISI_Y2R_SET1_C4(0xCC)\r
+ + ISI_Y2R_SET1_Yoff\r
+ + ISI_Y2R_SET1_Croff\r
+ + ISI_Y2R_SET1_Cboff;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ *\r
+ * Implement for SD/MMC low level commands.\r
+ *\r
+ * \sa \ref hsmci_module, \ref sdmmc_module\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "libsdmmc.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local constants\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtorgoup mcid_defines\r
+ * @{*/\r
+\r
+/** Enable MCI */\r
+#define MCI_ENABLE(pMciHw) HSMCI_Enable(pMciHw)\r
+/** Disable MCI */\r
+#define MCI_DISABLE(pMciHw) HSMCI_Disable(pMciHw)\r
+/** Reset MCI */\r
+#define MCI_RESET(pMciHw) HSMCI_Reset(pMciHw, 0)\r
+\r
+/** Return halfword(16-bit) count from byte count */\r
+#define toHWCOUNT(byteCnt) (((byteCnt)&0x1) ? (((byteCnt)/2)+1) : ((byteCnt)/2))\r
+/** Return word(32-bit) count from byte count */\r
+#define toWCOUNT(byteCnt) (((byteCnt)&0x3) ? (((byteCnt)/4)+1) : ((byteCnt)/4))\r
+\r
+\r
+/** Bit mask for status register errors. */\r
+#define STATUS_ERRORS ((uint32_t)(HSMCI_SR_UNRE \\r
+ | HSMCI_SR_OVRE \\r
+ | HSMCI_SR_ACKRCVE \\r
+ | HSMCI_SR_CSTOE \\r
+ | HSMCI_SR_DTOE \\r
+ | HSMCI_SR_DCRCE \\r
+ | HSMCI_SR_RTOE \\r
+ | HSMCI_SR_RENDE \\r
+ | HSMCI_SR_RCRCE \\r
+ | HSMCI_SR_RDIRE \\r
+ | HSMCI_SR_RINDE))\r
+\r
+/** Bit mask for response errors */\r
+#define STATUS_ERRORS_RESP ((uint32_t)(HSMCI_SR_CSTOE \\r
+ | HSMCI_SR_RTOE \\r
+ | HSMCI_SR_RENDE \\r
+ | HSMCI_SR_RCRCE \\r
+ | HSMCI_SR_RDIRE \\r
+ | HSMCI_SR_RINDE))\r
+\r
+/** Bit mask for data errors */\r
+#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \\r
+ | HSMCI_SR_OVRE \\r
+ | HSMCI_SR_DTOE \\r
+ | HSMCI_SR_DCRCE))\r
+\r
+/** Max DMA size in a single transfer */\r
+#define MAX_DMA_SIZE (XDMAC_MAX_BT_SIZE & 0xFFFFFF00)\r
+\r
+/** SD/MMC memory Single block */\r
+#define _CMDR_SDMEM_SINGLE \\r
+ (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_SINGLE)\r
+/** SD/MMC memory Multi block */\r
+#define _CMDR_SDMEM_MULTI \\r
+ (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_MULTIPLE)\r
+/** SDIO byte transfer */\r
+#define _CMDR_SDIO_BYTE \\r
+ (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BYTE)\r
+/** SDIO block transfer */\r
+#define _CMDR_SDIO_BLOCK \\r
+ (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BLOCK)\r
+\r
+/** @}*/\r
+/*---------------------------------------------------------------------------\r
+ * Local types\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variable\r
+ *----------------------------------------------------------------------------*/\r
+\r
+//#define MCID_DBG 0\r
+//static uint8_t bMcidDBG = 0;\r
+\r
+/** HAL for SD/MMC bus mode (MCI interface) */\r
+static sSdHalFunctions sdHal = {\r
+ (fSdmmcLock)MCID_Lock,\r
+ (fSdmmcRelease)MCID_Release,\r
+ (fSdmmcSendCommand)MCID_SendCmd,\r
+ (fSdmmcIOCtrl)MCID_IOCtrl\r
+};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Internal functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup mcid_functions\r
+ *@{\r
+ */\r
+\r
+/**\r
+ * Enable MCI peripheral access clock\r
+ */\r
+static uint8_t _PeripheralEnable(uint32_t id)\r
+{\r
+ if (PMC_IsPeriphEnabled(id)) return 0;\r
+ PMC_EnablePeripheral(id);\r
+ return 1;\r
+}\r
+\r
+static void MciDma_Cb(uint32_t channel, sMcid* pArg)\r
+{\r
+\r
+ pArg->bOpStatus = 0;\r
+ memory_barrier(); \r
+ XDMAD_FreeChannel(pArg->pXdmad, channel);\r
+}\r
+\r
+/**\r
+ * HSMCI DMA R/W prepare\r
+ */\r
+static uint32_t _MciDMAPrepare(sMcid *pMcid, uint8_t bRd)\r
+{\r
+ sXdmad *pXdmad = pMcid->pXdmad;\r
+ /* Allocate a channel */\r
+ if (bRd){\r
+ while(pMcid->bOpStatus);\r
+ pMcid->bOpStatus = 1;\r
+ pMcid->dwDmaCh = XDMAD_AllocateChannel(pXdmad, pMcid->bID, XDMAD_TRANSFER_MEMORY);\r
+ }\r
+ else { \r
+ while(pMcid->bOpStatus);\r
+ pMcid->bOpStatus = 2;\r
+ pMcid->dwDmaCh = XDMAD_AllocateChannel(pXdmad, XDMAD_TRANSFER_MEMORY, pMcid->bID);\r
+ }\r
+ if (pMcid->dwDmaCh == XDMAD_ALLOC_FAILED)\r
+ {\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ XDMAD_SetCallback(pXdmad, pMcid->dwDmaCh, (XdmadTransferCallback)MciDma_Cb, pMcid);\r
+ // XDMAD_SetCallback(pXdmad, pMcid->dwDmaCh, 0,0);\r
+ XDMAD_PrepareChannel( pXdmad, pMcid->dwDmaCh );\r
+ return SDMMC_SUCCESS;\r
+}\r
+\r
+/**\r
+ * HSMCI DMA R/W\r
+ * \return 1 if DMA started.\r
+ */\r
+\r
+/* Linked lists for multi transfer buffer chaining structure instance. */\r
+#if defined ( __ICCARM__ ) /* IAR Ewarm */\r
+#pragma location = "region_dma_nocache"\r
+#elif defined ( __GNUC__ ) /* GCC CS3 */\r
+__attribute__((__section__(".region_dma_nocache")))\r
+#endif\r
+static LinkedListDescriporView1 dmaLinkList[256];\r
+\r
+static uint32_t _MciDMA(sMcid *pMcid, uint32_t bFByte, uint8_t bRd)\r
+{\r
+ Hsmci *pHw = pMcid->pMciHw;\r
+ sXdmad *pXdmad = pMcid->pXdmad;\r
+ sSdmmcCommand *pCmd = pMcid->pCmd;\r
+ sXdmadCfg xdmadRxCfg,xdmadTxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t hsmciId;\r
+ uint8_t i;\r
+ uint32_t totalSize = pCmd->wNbBlocks * pCmd->wBlockSize;\r
+ uint32_t maxXSize;\r
+ uint32_t memAddress;\r
+ uint8_t bMByte;\r
+\r
+ if (pMcid->dwXfrNdx >= totalSize) return 0;\r
+ /* Prepare DMA transfer */\r
+ if(pCmd->wBlockSize != 1){\r
+ pMcid->dwXSize = totalSize - pMcid->dwXfrNdx;\r
+ hsmciId = ID_HSMCI;\r
+ if (bRd){\r
+ //printf("_MciDMA read %d,%d \n\r",pCmd->wBlockSize, pCmd->bCmd );\r
+ for ( i = 0; i < pCmd->wNbBlocks; i++){\r
+ dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ | (( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)\r
+ | XDMA_UBC_NDEN_UPDATED \r
+ | pCmd->wBlockSize /4 ;\r
+ dmaLinkList[i].mbr_sa = (uint32_t)&(pHw->HSMCI_FIFO[i]);\r
+ dmaLinkList[i].mbr_da = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize];\r
+ if ( i == pCmd->wNbBlocks - 1)\r
+ dmaLinkList[i].mbr_nda = 0;\r
+ else\r
+ dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ];\r
+\r
+ }\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_PER2MEM \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_WORD\r
+ | XDMAC_CC_SIF_AHB_IF1 \r
+ | XDMAC_CC_DIF_AHB_IF0 \r
+ | XDMAC_CC_SAM_FIXED_AM \r
+ | XDMAC_CC_DAM_INCREMENTED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(hsmciId, XDMAD_TRANSFER_RX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;\r
+ if (XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadRxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0])) {\r
+ return 0;\r
+ }\r
+ if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) {\r
+ return 0;\r
+ }\r
+ //Write\r
+ } else {\r
+ //printf("_MciDMA write %d,%d \n\r",pCmd->wBlockSize, pCmd->bCmd );\r
+ for ( i = 0; i < pCmd->wNbBlocks; i++){\r
+ dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ |(( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)\r
+ | XDMA_UBC_NDEN_UPDATED \r
+ | pCmd->wBlockSize /4 ;\r
+ dmaLinkList[i].mbr_sa = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize];\r
+ dmaLinkList[i].mbr_da = (uint32_t)&(pHw->HSMCI_FIFO[i]);\r
+ if ( i == pCmd->wNbBlocks - 1) dmaLinkList[i].mbr_nda = 0;\r
+ else dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ];\r
+\r
+ }\r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_MEM2PER \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_WORD\r
+ | XDMAC_CC_SIF_AHB_IF0 \r
+ | XDMAC_CC_DIF_AHB_IF1 \r
+ | XDMAC_CC_SAM_INCREMENTED_AM \r
+ | XDMAC_CC_DAM_FIXED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(hsmciId, XDMAD_TRANSFER_TX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;\r
+\r
+ if(XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadTxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0])){\r
+ return 0;\r
+ }\r
+ if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) {\r
+ return 0;\r
+ }\r
+ }\r
+ } else {\r
+ /* Memory address and alignment */\r
+ memAddress = (uint32_t)&pCmd->pData[pMcid->dwXfrNdx];\r
+ bMByte = bFByte ? 1 : (((memAddress & 0x3) || (totalSize & 0x3)));\r
+ /* P to M: Max size is P size */\r
+ if (bRd)\r
+ {\r
+ maxXSize = bFByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4);\r
+ }\r
+ /* M to P: Max size is M size */\r
+ else\r
+ {\r
+ maxXSize = bMByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4);\r
+ }\r
+ /* Update index */\r
+ pMcid->dwXSize = totalSize - pMcid->dwXfrNdx;\r
+ if (pMcid->dwXSize > maxXSize)\r
+ {\r
+ pMcid->dwXSize = maxXSize;\r
+ }\r
+ /* Prepare DMA transfer */\r
+ if (bRd)\r
+ {\r
+ xdmadRxCfg.mbr_ubc = bFByte ? pMcid->dwXSize : toWCOUNT(pMcid->dwXSize);\r
+ xdmadRxCfg.mbr_sa = (uint32_t)&(pHw->HSMCI_RDR);\r
+ xdmadRxCfg.mbr_da = (uint32_t)memAddress;\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MEMSET_NORMAL_MODE |\r
+ XDMAC_CC_DSYNC_PER2MEM|\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ (bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) |\r
+ XDMAC_CC_SIF_AHB_IF1 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_FIXED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM;\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadRxCfg, 0, 0);\r
+ memory_barrier();\r
+ }\r
+ else\r
+ {\r
+ xdmadTxCfg.mbr_ubc = toWCOUNT(pMcid->dwXSize);\r
+ xdmadTxCfg.mbr_sa = (uint32_t)memAddress; \r
+ xdmadTxCfg.mbr_da = (uint32_t)&(pHw->HSMCI_TDR);\r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MEMSET_NORMAL_MODE |\r
+ XDMAC_CC_DSYNC_MEM2PER |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ (bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) |\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF1 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_FIXED_AM;\r
+ xdmadTxCfg.mbr_bc = 0;\r
+ XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadTxCfg, 0, 0);\r
+ }\r
+ XDMAD_StartTransfer(pXdmad, pMcid->dwDmaCh);\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Reset MCI HW interface and disable it.\r
+ * \param keepSettings Keep old register settings, including\r
+ * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG.\r
+ */\r
+static void MCI_Reset(sMcid *pMci, uint8_t keepSettings)\r
+{\r
+ Hsmci *pMciHw = pMci->pMciHw;\r
+\r
+ assert(pMci);\r
+ assert(pMci->pMciHw);\r
+\r
+ HSMCI_Reset( pMciHw, keepSettings );\r
+}\r
+\r
+/**\r
+ * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is\r
+ * MCK/2 and corresponds to CLKDIV = 0\r
+ * \param pMci Pointer to the low level MCI driver.\r
+ * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed.\r
+ * \param mck MCK to generate MCI Clock, in Hz\r
+ * \return The actual speed used, 0 for fail.\r
+ */\r
+static uint32_t MCI_SetSpeed( sMcid* pMci, uint32_t mciSpeed, uint32_t mck )\r
+{\r
+ Hsmci *pMciHw = pMci->pMciHw;\r
+ uint32_t clkdiv;\r
+ assert(pMci);\r
+ assert(pMciHw);\r
+\r
+ if((mck % mciSpeed) == 0)\r
+ {\r
+ clkdiv = mck /mciSpeed;\r
+ } \r
+ else \r
+ {\r
+ clkdiv = ((mck + mciSpeed)/mciSpeed);\r
+ }\r
+ mciSpeed = mck / clkdiv;\r
+\r
+ /* Modify MR */\r
+ HSMCI_DivCtrl( pMciHw, clkdiv, 0x7);\r
+ return (mciSpeed);\r
+}\r
+\r
+/**\r
+*/\r
+static void _FinishCmd( sMcid* pMcid, uint8_t bStatus )\r
+{\r
+ sSdmmcCommand *pCmd = pMcid->pCmd;\r
+ sXdmad *pXdmad = pMcid->pXdmad;\r
+ //uint32_t memAddress;\r
+ /* Release DMA channel (if used) */\r
+ if (pMcid->dwDmaCh != XDMAD_ALLOC_FAILED)\r
+ {\r
+ if (XDMAD_FreeChannel(pXdmad, pMcid->dwDmaCh)) \r
+ TRACE_DEBUG("-E- Can't free channel \n\r");\r
+ pMcid->dwDmaCh = XDMAD_ALLOC_FAILED;\r
+ }\r
+ /* Release command */\r
+ pMcid->pCmd = NULL;\r
+ pMcid->bState = MCID_LOCKED;\r
+ pCmd->bStatus = bStatus;\r
+ /* Invoke callback */\r
+ if (pCmd->fCallback)\r
+ {\r
+ (pCmd->fCallback)(pCmd->bStatus, pCmd->pArg);\r
+ }\r
+}\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Select MCI slot.\r
+ */\r
+void MCID_SetSlot(Hsmci *pMci, uint8_t slot)\r
+\r
+{\r
+ HSMCI_SetSlot(pMci, slot);\r
+}\r
+\r
+/**\r
+ * Initialize MCI driver.\r
+ */\r
+void MCID_Init(sMcid *pMcid,\r
+ Hsmci *pMci, uint8_t bID, uint32_t dwMck,\r
+ sXdmad *pXdmad,\r
+ uint8_t bPolling)\r
+{\r
+ uint16_t clkDiv;\r
+\r
+ assert(pMcid);\r
+ assert(pMci);\r
+\r
+ /* Initialize driver struct */\r
+ pMcid->pMciHw = pMci;\r
+ pMcid->pCmd = NULL;\r
+\r
+ pMcid->pXdmad = pXdmad;\r
+ pMcid->dwDmaCh = XDMAD_ALLOC_FAILED;\r
+ pMcid->dwXfrNdx = 0;\r
+\r
+ pMcid->dwMck = dwMck;\r
+\r
+ pMcid->bID = bID;\r
+ pMcid->bPolling = bPolling;\r
+ pMcid->bState = MCID_IDLE;\r
+\r
+ pMcid->bOpStatus = 0;\r
+\r
+ _PeripheralEnable( bID );\r
+\r
+ MCI_RESET( pMci );\r
+ MCI_DISABLE ( pMci );\r
+ HSMCI_DisableIt( pMci, 0xFFFFFFFF );\r
+ HSMCI_ConfigureDataTO( pMci, HSMCI_DTOR_DTOCYC(0xFF)\r
+ |HSMCI_DTOR_DTOMUL_1048576 );\r
+ HSMCI_ConfigureCompletionTO( pMci , HSMCI_CSTOR_CSTOCYC(0xFF)\r
+ |HSMCI_CSTOR_CSTOMUL_1048576 );\r
+ /* Set the Mode Register: 400KHz */\r
+ clkDiv = (dwMck / (MCI_INITIAL_SPEED << 1)) - 1;\r
+ HSMCI_ConfigureMode( pMci, (clkDiv | HSMCI_MR_PWSDIV(0x7)) );\r
+\r
+ HSMCI_Enable( pMci );\r
+ HSMCI_Configure( pMci, HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL );\r
+ /* Enable DMA */\r
+ HSMCI_EnableDma( pMci, 1 );\r
+ //_PeripheralDisable( bID );\r
+}\r
+\r
+/**\r
+ * Lock the MCI driver for slot N access\r
+ */\r
+uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot)\r
+{\r
+ Hsmci *pHw = pMcid->pMciHw;\r
+ uint32_t sdcr;\r
+\r
+ assert(pMcid);\r
+ assert(pMcid->pMciHw);\r
+\r
+ if (bSlot > 0)\r
+ {\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ if (pMcid->bState >= MCID_LOCKED)\r
+ {\r
+ return SDMMC_ERROR_LOCKED;\r
+ }\r
+ pMcid->bState = MCID_LOCKED;\r
+ sdcr = pHw->HSMCI_SDCR & ~(uint32_t)HSMCI_SDCR_SDCSEL_Msk;\r
+ pHw->HSMCI_SDCR = sdcr | (bSlot << HSMCI_SDCR_SDCSEL_Pos);\r
+ return SDMMC_OK;\r
+}\r
+\r
+/**\r
+ * Release the driver.\r
+ */\r
+uint32_t MCID_Release(sMcid *pMcid)\r
+{\r
+ assert(pMcid);\r
+\r
+ if (pMcid->bState >= MCID_CMD)\r
+ {\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ pMcid->bState = MCID_IDLE;\r
+ return SDMMC_OK;\r
+}\r
+\r
+/**\r
+ * SD/MMC command.\r
+ */\r
+uint32_t MCID_SendCmd(sMcid *pMcid, void *pCommand)\r
+{\r
+ Hsmci *pHw = pMcid->pMciHw;\r
+ sSdmmcCommand *pCmd = pCommand;\r
+ uint32_t mr, ier;\r
+ uint32_t cmdr;\r
+\r
+ assert(pMcid);\r
+ assert(pMcid->pMciHw);\r
+ assert(pCmd);\r
+ //printf("cmd = %d \n\r",pCmd->bCmd);\r
+ if (!MCID_IsCmdCompleted(pMcid))\r
+ {\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ pMcid->bState = MCID_CMD;\r
+ pMcid->pCmd = pCmd;\r
+\r
+ //_PeripheralEnable(pMcid->bID);\r
+ MCI_DISABLE(pHw);\r
+ mr = HSMCI_GetMode(pHw) & (~(uint32_t)(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF |HSMCI_MR_FBYTE));\r
+ /* Special: PowerON Init */\r
+ if (pCmd->cmdOp.wVal == SDMMC_CMD_POWERONINIT){\r
+ HSMCI_ConfigureMode(pHw, mr);\r
+ ier = HSMCI_IER_XFRDONE;\r
+ }\r
+ /* Normal command: idle the bus */\r
+ else if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR)\r
+ {\r
+ HSMCI_ConfigureMode(pHw, mr);\r
+ ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP;\r
+ }\r
+ /* No data transfer */\r
+ else if ((pCmd->cmdOp.wVal & SDMMC_CMD_CNODATA(0xF)) == SDMMC_CMD_CNODATA(0))\r
+ {\r
+ ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP;\r
+ /* R3 response, no CRC */\r
+ if (pCmd->cmdOp.bmBits.respType == 3)\r
+ {\r
+ ier &= ~(uint32_t)HSMCI_IER_RCRCE;\r
+ }\r
+ }\r
+ /* Data command but no following */\r
+ else if (pCmd->wNbBlocks == 0 || pCmd->pData == 0)\r
+ {\r
+ HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF\r
+ | HSMCI_MR_RDPROOF);\r
+ HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks);\r
+ ier = HSMCI_IER_CMDRDY | STATUS_ERRORS_RESP;\r
+ }\r
+ /* Command with data */\r
+ else\r
+ {\r
+ /* Setup block size */\r
+ if (pCmd->cmdOp.bmBits.sendCmd)\r
+ {\r
+ HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks);\r
+ }\r
+ /* Block size is 0, force byte */\r
+ if (pCmd->wBlockSize == 0)\r
+ pCmd->wBlockSize = 1;\r
+\r
+ /* Force byte transfer */\r
+ if (pCmd->wBlockSize & 0x3)\r
+ {\r
+ mr |= HSMCI_MR_FBYTE;\r
+ }\r
+ /* Set block size & MR */\r
+ HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF\r
+ | HSMCI_MR_RDPROOF\r
+ | (pCmd->wBlockSize << 16));\r
+ memory_barrier();\r
+ /* DMA write */\r
+ if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX)\r
+ {\r
+ if (_MciDMAPrepare(pMcid, 0))\r
+ {\r
+ _FinishCmd(pMcid, SDMMC_ERROR_BUSY);\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),0);\r
+ ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA;\r
+ if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY;\r
+ }\r
+ else\r
+ {\r
+ if (_MciDMAPrepare(pMcid, 1))\r
+ {\r
+ _FinishCmd(pMcid, SDMMC_ERROR_BUSY);\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),1);\r
+ ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA;\r
+ if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY;\r
+ }\r
+ }\r
+ MCI_ENABLE(pHw);\r
+ if (pCmd->cmdOp.wVal & (SDMMC_CMD_bmPOWERON | SDMMC_CMD_bmCOMMAND))\r
+ {\r
+ cmdr = pCmd->bCmd;\r
+\r
+ if (pCmd->cmdOp.bmBits.powerON)\r
+ {\r
+ cmdr |= (HSMCI_CMDR_OPDCMD | HSMCI_CMDR_SPCMD_INIT);\r
+ }\r
+ if (pCmd->cmdOp.bmBits.odON)\r
+ {\r
+ cmdr |= HSMCI_CMDR_OPDCMD;\r
+ }\r
+ if (pCmd->cmdOp.bmBits.sendCmd)\r
+ {\r
+ cmdr |= HSMCI_CMDR_MAXLAT;\r
+ }\r
+ switch(pCmd->cmdOp.bmBits.xfrData)\r
+ {\r
+ case SDMMC_CMD_TX:\r
+ if (pCmd->cmdOp.bmBits.ioCmd)\r
+ {\r
+ cmdr |= (pCmd->wBlockSize == 1) ?\r
+ _CMDR_SDIO_BYTE :\r
+ _CMDR_SDIO_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ cmdr |= (pCmd->wNbBlocks == 1) ?\r
+ _CMDR_SDMEM_SINGLE :\r
+ _CMDR_SDMEM_MULTI;\r
+ }\r
+ break;\r
+\r
+ case SDMMC_CMD_RX:\r
+ if (pCmd->cmdOp.bmBits.ioCmd)\r
+ {\r
+ cmdr |= HSMCI_CMDR_TRDIR_READ\r
+ |((pCmd->wBlockSize == 1) ?\r
+ _CMDR_SDIO_BYTE :\r
+ _CMDR_SDIO_BLOCK)\r
+ ;\r
+ }\r
+ else\r
+ {\r
+ cmdr |= HSMCI_CMDR_TRDIR_READ\r
+ |((pCmd->wNbBlocks == 1) ?\r
+ _CMDR_SDMEM_SINGLE :\r
+ _CMDR_SDMEM_MULTI)\r
+ ;\r
+ }\r
+ break;\r
+\r
+ case SDMMC_CMD_STOPXFR:\r
+ cmdr |= HSMCI_CMDR_TRCMD_STOP_DATA;\r
+ break;\r
+\r
+ }\r
+ switch(pCmd->cmdOp.bmBits.respType)\r
+ {\r
+ case 3: case 4:\r
+ /* ignore CRC error */\r
+ ier &= ~(uint32_t)HSMCI_IER_RCRCE;\r
+ case 1: case 5: case 6: case 7:\r
+ cmdr |= HSMCI_CMDR_RSPTYP_48_BIT;\r
+ break;\r
+ case 2:\r
+ cmdr |= HSMCI_CMDR_RSPTYP_136_BIT;\r
+ break;\r
+ /* No response, ignore RTOE */\r
+ default:\r
+ ier &= ~(uint32_t)HSMCI_IER_RTOE;\r
+ }\r
+\r
+ pHw->HSMCI_ARGR = pCmd->dwArg;\r
+ pHw->HSMCI_CMDR = cmdr;\r
+ }\r
+\r
+ /* Ignore CRC error for R3 & R4 */\r
+ if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR)\r
+ {\r
+ ier &= ~STATUS_ERRORS_DATA;\r
+ }\r
+\r
+ /* Enable status flags */\r
+ HSMCI_EnableIt(pHw, ier);\r
+\r
+ return SDMMC_OK;\r
+}\r
+static uint32_t dwMsk;\r
+/**\r
+ * Process pending events on the given MCI driver.\r
+ */\r
+void MCID_Handler(sMcid *pMcid)\r
+{\r
+ Hsmci *pHw = pMcid->pMciHw;\r
+ sSdmmcCommand *pCmd = pMcid->pCmd;\r
+ //uint32_t dwSr, dwMsk, dwMaskedSr;\r
+ uint32_t dwSr, dwMaskedSr;\r
+ assert(pMcid);\r
+ assert(pMcid->pMciHw);\r
+\r
+ /* Do nothing if no pending command */\r
+ if (pCmd == NULL)\r
+ {\r
+ if (pMcid->bState >= MCID_CMD)\r
+ {\r
+ pMcid->bState = MCID_LOCKED;\r
+ }\r
+ return;\r
+ }\r
+\r
+ /* Read status */\r
+ dwSr = HSMCI_GetStatus(pHw);\r
+ dwMsk = HSMCI_GetItMask(pHw);\r
+ dwMaskedSr = dwSr & dwMsk;\r
+ /* Check errors */\r
+ if (dwMaskedSr & STATUS_ERRORS)\r
+ {\r
+ if (dwMaskedSr & HSMCI_SR_RTOE)\r
+ {\r
+ pCmd->bStatus = SDMMC_ERROR_NORESPONSE;\r
+ }\r
+\r
+ if (pCmd->bCmd != 12) pMcid->bState = MCID_ERROR;\r
+ //pMcid->bState = MCID_ERROR;\r
+ }\r
+ dwMsk &= ~STATUS_ERRORS;\r
+\r
+ /* Check command complete */\r
+ if (dwMaskedSr & HSMCI_SR_CMDRDY)\r
+ { \r
+ //printf("HSMCI_SR_CMDRDY \n\r");\r
+ HSMCI_DisableIt(pHw, HSMCI_IDR_CMDRDY);\r
+ dwMsk &= ~(uint32_t)HSMCI_IMR_CMDRDY;\r
+ }\r
+\r
+ /* Check if not busy */\r
+ if (dwMaskedSr & HSMCI_SR_NOTBUSY)\r
+ {\r
+ //printf("NOTBUSY ");\r
+ HSMCI_DisableIt(pHw, HSMCI_IDR_NOTBUSY);\r
+ dwMsk &= ~(uint32_t)HSMCI_IMR_NOTBUSY;\r
+ }\r
+ /* Check if TX ready */\r
+ if (dwMaskedSr & HSMCI_SR_TXRDY)\r
+ { \r
+ // printf("TXRDY ");\r
+ dwMsk &= ~(uint32_t)HSMCI_IMR_TXRDY;\r
+ }\r
+ /* Check if FIFO empty (all data sent) */\r
+ if (dwMaskedSr & HSMCI_SR_FIFOEMPTY)\r
+ {\r
+\r
+ /* Disable FIFO empty */\r
+ HSMCI_DisableIt(pHw, HSMCI_IDR_FIFOEMPTY);\r
+ dwMsk &= ~(uint32_t)HSMCI_IMR_FIFOEMPTY;\r
+ //printf("FIFOEMPTY %x \n\r",dwMsk);\r
+ }\r
+\r
+ /* Check if DMA finished */\r
+ if (dwMaskedSr & HSMCI_SR_XFRDONE)\r
+ {\r
+\r
+ HSMCI_DisableIt(pHw, HSMCI_IDR_XFRDONE);\r
+ dwMsk &= ~(uint32_t)HSMCI_IMR_XFRDONE;\r
+ //printf("HSMCI_SR_XFRDONE %x \n\r",dwMsk);\r
+ }\r
+\r
+ /* All none error mask done, complete the command */\r
+ if (0 == dwMsk || pMcid->bState == MCID_ERROR)\r
+ {\r
+ /* Error reset */\r
+ if (pMcid->bState == MCID_ERROR)\r
+ {\r
+ MCI_Reset(pMcid, 1);\r
+ }\r
+ else \r
+ {\r
+ pCmd->bStatus = SDMMC_SUCCESS;\r
+\r
+ if (pCmd->pResp)\r
+ {\r
+ uint8_t bRspSize, i;\r
+ switch(pCmd->cmdOp.bmBits.respType)\r
+ {\r
+ case 1: case 3: case 4: case 5: case 6: case 7:\r
+ bRspSize = 1;\r
+ break;\r
+\r
+ case 2:\r
+ bRspSize = 4;\r
+ break;\r
+\r
+ default:\r
+ bRspSize = 0;\r
+ }\r
+ for (i = 0; i < bRspSize; i ++)\r
+ {\r
+ pCmd->pResp[i] = HSMCI_GetResponse(pHw);\r
+ }\r
+ }\r
+ }\r
+ /* Disable interrupts */\r
+ HSMCI_DisableIt(pHw, HSMCI_GetItMask(pHw));\r
+ /* Disable peripheral */\r
+ //_PeripheralDisable(pMcid->bID);\r
+ /* Command is finished */\r
+ memory_barrier();\r
+ _FinishCmd(pMcid, pCmd->bStatus);\r
+ }\r
+}\r
+\r
+/**\r
+ * Cancel pending SD/MMC command.\r
+ */\r
+uint32_t MCID_CancelCmd(sMcid *pMcid)\r
+{\r
+ if (pMcid->bState == MCID_IDLE)\r
+ {\r
+ return SDMMC_ERROR_STATE;\r
+ }\r
+ if (pMcid->bState == MCID_CMD)\r
+ {\r
+ /* Cancel ... */\r
+ MCI_Reset(pMcid, 1);\r
+ /* Command is finished */\r
+ _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL);\r
+ }\r
+ return SDMMC_OK;\r
+}\r
+\r
+/**\r
+ * Reset MCID and disable HW\r
+ */\r
+void MCID_Reset(sMcid * pMcid)\r
+{\r
+ Hsmci *pHw = pMcid->pMciHw;\r
+\r
+ MCID_CancelCmd(pMcid);\r
+\r
+ //_PeripheralEnable(pMcid->bID);\r
+\r
+ /* Disable */\r
+ MCI_DISABLE(pHw);\r
+ /* MR reset */\r
+ HSMCI_ConfigureMode(pHw, HSMCI_GetMode(pHw) & (HSMCI_MR_CLKDIV_Msk\r
+ | HSMCI_MR_PWSDIV_Msk));\r
+ /* BLKR reset */\r
+ HSMCI_ConfigureTransfer(pHw, 0, 0);\r
+\r
+ /* Cancel ... */\r
+ MCI_Reset(pMcid, 1);\r
+ //_PeripheralDisable(pMcid->bID);\r
+\r
+ if (pMcid->bState == MCID_CMD)\r
+ {\r
+ /* Command is finished */\r
+ _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL);\r
+ }\r
+}\r
+\r
+/**\r
+ * Check if the command is finished\r
+ */\r
+uint32_t MCID_IsCmdCompleted(sMcid *pMcid)\r
+{\r
+ sSdmmcCommand *pCmd = pMcid->pCmd;\r
+\r
+ if (pMcid->bPolling)\r
+ {\r
+ MCID_Handler(pMcid);\r
+ }\r
+ if (pMcid->bState == MCID_CMD)\r
+ {\r
+ return 0;\r
+ }\r
+ if (pCmd)\r
+ {\r
+ return 0;\r
+ }\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * IO control functions\r
+ */\r
+uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param)\r
+{\r
+ Hsmci *pMciHw = pMcid->pMciHw;\r
+ assert(pMcid);\r
+ assert(pMcid->pMciHw);\r
+\r
+ //mciDis = _PeripheralEnable(pMcid->bID);\r
+\r
+ switch (bCtl)\r
+ {\r
+ case SDMMC_IOCTL_BUSY_CHECK:\r
+ *(uint32_t*)param = !MCID_IsCmdCompleted(pMcid);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_POWER:\r
+ return SDMMC_ERROR_NOT_SUPPORT;\r
+\r
+ case SDMMC_IOCTL_RESET:\r
+ MCID_Reset(pMcid);\r
+ return SDMMC_SUCCESS;\r
+\r
+ case SDMMC_IOCTL_CANCEL_CMD:\r
+ return MCID_CancelCmd(pMcid);\r
+\r
+ case SDMMC_IOCTL_SET_CLOCK:\r
+ *(uint32_t*)param = MCI_SetSpeed(pMcid,\r
+ *(uint32_t*)param,\r
+ pMcid->dwMck);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_HSMODE:\r
+ HSMCI_HsEnable( pMciHw, *(uint32_t*)param );\r
+ *(uint32_t*)param = HSMCI_IsHsEnabled( pMciHw );\r
+\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_BUSMODE:\r
+ HSMCI_SetBusWidth( pMciHw, *(uint32_t*)param );\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_BUSMODE:\r
+ //*(uint32_t*)param = 8; /* Max 4-bit bus */\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_HSMODE:\r
+ *(uint32_t*)param = 1; /* Supported */\r
+ break;\r
+\r
+ default:\r
+ return SDMMC_ERROR_NOT_SUPPORT;\r
+\r
+ }\r
+ return SDMMC_OK;\r
+}\r
+\r
+/**\r
+ * Initialize the SD/MMC card driver struct for SD/MMC bus mode\r
+ * \note defined in SD/MMC bus mode low level (Here uses MCI interface)\r
+ */\r
+void SDD_InitializeSdmmcMode(sSdCard * pSd,void * pDrv,uint8_t bSlot)\r
+{\r
+ SDD_Initialize(pSd, pDrv, bSlot, &sdHal);\r
+}\r
+\r
+/**@}*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup mediaLB\r
+ * \ingroup peripherals_module\r
+ * The mediaLB driver provides the interface to configure and use the peripheral.\r
+ *\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of mediaLB controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \r
+ * \addtogroup mmu MMU Initialization\r
+ *\r
+ * \section Usage\r
+ *\r
+ * Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or\r
+ * translation table entries. TLBs avoid the requirement for every memory access to perform a translation table\r
+ * lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a\r
+ * similar way to the requirements for caches, the architecture only defines certain principles for TLBs:\r
+ * \r
+ * The MMU supports memory accesses based on memory sections or pages:\r
+ * Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.\r
+ * -# Sections Consist of 1MB blocks of memory.\r
+ * -# Large pages Consist of 64KB blocks of memory.\r
+ * -# Small pages Consist of 4KB blocks of memory.\r
+ *\r
+ * Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.\r
+ * Memory region attributes\r
+ * Each TLB entry has an associated set of memory region attributes. These control accesses to the caches,\r
+ * how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.\r
+ *\r
+ * Related files:\n\r
+ * \ref mmu.c\n\r
+ * \ref mmu.h \n\r
+ */\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Headers */\r
+/*------------------------------------------------------------------------------ */\r
+#include <chip.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Enables the MPU module.\r
+ *\r
+ * \param dwMPUEnable Enable/Disable the memory region.\r
+ */\r
+void MPU_Enable( uint32_t dwMPUEnable )\r
+{\r
+ MPU->CTRL = dwMPUEnable ;\r
+}\r
+\r
+/**\r
+ * \brief Set active memory region.\r
+ *\r
+ * \param dwRegionNum The memory region to be active.\r
+ */\r
+void MPU_SetRegionNum( uint32_t dwRegionNum )\r
+{\r
+ MPU->RNR = dwRegionNum;\r
+}\r
+\r
+/**\r
+ * \brief Disable the current active region.\r
+ */\r
+extern void MPU_DisableRegion( void )\r
+{\r
+ MPU->RASR &= 0xfffffffe;\r
+}\r
+\r
+/**\r
+ * \brief Setup a memory region.\r
+ *\r
+ * \param dwRegionBaseAddr Memory region base address.\r
+ * \param dwRegionAttr Memory region attributes. \r
+ */\r
+void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr )\r
+{\r
+ MPU->RBAR = dwRegionBaseAddr;\r
+ MPU->RASR = dwRegionAttr;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Calculate region size for the RASR.\r
+ */\r
+uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes )\r
+{\r
+ uint32_t dwRegionSize = 32;\r
+ uint32_t dwReturnValue = 4;\r
+\r
+ while( dwReturnValue < 31 )\r
+ {\r
+ if( dwActualSizeInBytes <= dwRegionSize )\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ dwReturnValue++;\r
+ }\r
+\r
+ dwRegionSize <<= 1;\r
+ }\r
+\r
+ return ( dwReturnValue << 1 );\r
+}\r
+\r
+\r
+/**\r
+ * \brief Update MPU regions.\r
+ *\r
+ * \return Unused (ANSI-C compatibility).\r
+ */\r
+void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,\r
+ uint32_t dwRegionAttr)\r
+{\r
+ /* Raise privilege, the MPU register could be set only in privilege mode */\r
+ asm volatile(" swi 0x00 ");\r
+ while (!dwRaisePriDone);\r
+ dwRaisePriDone = 0;\r
+\r
+ /* Disable interrupt */\r
+ __disable_irq();\r
+\r
+ /* Clean up data and instruction buffer */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Set active region */\r
+ MPU_SetRegionNum(dwRegionNum);\r
+\r
+ /* Disable region */\r
+ MPU_DisableRegion();\r
+\r
+ /* Update region attribute */\r
+ MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);\r
+\r
+ /* Clean up data and instruction buffer to make the new region taking \r
+ effect at once */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Enable the interrupt */\r
+ __enable_irq();\r
+\r
+ /* Reset to thread mode */\r
+ __set_CONTROL(USER_MODE);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by\r
+ * peripheral A. Optionally, the corresponding internal pull-up(s) can be enabled.\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask of one or more pin(s) to configure.\r
+ * \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+static void PIO_SetPeripheralA(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ unsigned int abcdsr;\r
+ /* Disable interrupts on the pin(s) */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (enablePullUp) {\r
+ pio->PIO_PUER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_PUDR = mask;\r
+ }\r
+\r
+ abcdsr = pio->PIO_ABCDSR[0];\r
+ pio->PIO_ABCDSR[0] &= (~mask & abcdsr);\r
+ abcdsr = pio->PIO_ABCDSR[1];\r
+ pio->PIO_ABCDSR[1] &= (~mask & abcdsr);\r
+ pio->PIO_PDR = mask;\r
+}\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by\r
+ * peripheral B. Optionally, the corresponding internal pull-up(s) can be enabled.\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask of one or more pin(s) to configure.\r
+ * \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+static void PIO_SetPeripheralB(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ unsigned int abcdsr;\r
+ /* Disable interrupts on the pin(s) */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (enablePullUp) {\r
+\r
+ pio->PIO_PUER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_PUDR = mask;\r
+ }\r
+\r
+ abcdsr = pio->PIO_ABCDSR[0];\r
+ pio->PIO_ABCDSR[0] = (mask | abcdsr);\r
+ abcdsr = pio->PIO_ABCDSR[1];\r
+ pio->PIO_ABCDSR[1] &= (~mask & abcdsr);\r
+\r
+ pio->PIO_PDR = mask;\r
+}\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by\r
+ * peripheral C. Optionally, the corresponding internal pull-up(s) can be enabled.\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask of one or more pin(s) to configure.\r
+ * \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+static void PIO_SetPeripheralC(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ unsigned int abcdsr;\r
+ /* Disable interrupts on the pin(s) */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (enablePullUp) {\r
+\r
+ pio->PIO_PUER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_PUDR = mask;\r
+ }\r
+\r
+ abcdsr = pio->PIO_ABCDSR[0];\r
+ pio->PIO_ABCDSR[0] &= (~mask & abcdsr);\r
+ abcdsr = pio->PIO_ABCDSR[1];\r
+ pio->PIO_ABCDSR[1] = (mask | abcdsr);\r
+\r
+ pio->PIO_PDR = mask;\r
+}\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by\r
+ * peripheral D. Optionally, the corresponding internal pull-up(s) can be enabled.\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask of one or more pin(s) to configure.\r
+ * \param enablePullUp Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+static void PIO_SetPeripheralD(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char enablePullUp)\r
+{\r
+ unsigned int abcdsr;\r
+ /* Disable interrupts on the pin(s) */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (enablePullUp) {\r
+\r
+ pio->PIO_PUER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_PUDR = mask;\r
+ }\r
+\r
+ abcdsr = pio->PIO_ABCDSR[0];\r
+ pio->PIO_ABCDSR[0] = (mask | abcdsr);\r
+ abcdsr = pio->PIO_ABCDSR[1];\r
+ pio->PIO_ABCDSR[1] = (mask | abcdsr);\r
+\r
+ pio->PIO_PDR = mask;\r
+}\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,\r
+ * the corresponding internal pull-up(s) and glitch filter(s) can be enabled.\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask indicating which pin(s) to configure as input(s).\r
+ * \param enablePullUp Indicates if the internal pull-up(s) must be enabled.\r
+ * \param enableFilter Indicates if the glitch filter(s) must be enabled.\r
+ */\r
+static void PIO_SetInput(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char attribute)\r
+{\r
+ /* Disable interrupts */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable pull-up(s) if necessary */\r
+ if (attribute & PIO_PULLUP)\r
+ pio->PIO_PUER = mask;\r
+ else\r
+ pio->PIO_PUDR = mask;\r
+\r
+ /* Enable Input Filter if necessary */\r
+ if (attribute & (PIO_DEGLITCH | PIO_DEBOUNCE))\r
+ pio->PIO_IFER = mask;\r
+ else\r
+ pio->PIO_IFDR = mask;\r
+\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (attribute & PIO_DEGLITCH)\r
+ {\r
+ pio->PIO_IFSCDR = mask;\r
+ }\r
+ else\r
+ {\r
+ if (attribute & PIO_DEBOUNCE)\r
+ {\r
+ pio->PIO_IFSCER = mask;\r
+ }\r
+ }\r
+\r
+ /* Configure pin as input */\r
+ pio->PIO_ODR = mask;\r
+ pio->PIO_PER = mask;\r
+}\r
+\r
+/**\r
+ * \brief Configures one or more pin(s) of a PIO controller as outputs, with the\r
+ * given default value. Optionally, the multi-drive feature can be enabled\r
+ * on the pin(s).\r
+ *\r
+ * \param pio Pointer to a PIO controller.\r
+ * \param mask Bitmask indicating which pin(s) to configure.\r
+ * \param defaultValue Default level on the pin(s).\r
+ * \param enableMultiDrive Indicates if the pin(s) shall be configured as\r
+ * open-drain.\r
+ * \param enablePullUp Indicates if the pin shall have its pull-up activated.\r
+ */\r
+static void PIO_SetOutput(\r
+ Pio *pio,\r
+ unsigned int mask,\r
+ unsigned char defaultValue,\r
+ unsigned char enableMultiDrive,\r
+ unsigned char enablePullUp)\r
+{\r
+ /* Disable interrupts */\r
+ pio->PIO_IDR = mask;\r
+\r
+ /* Enable pull-up(s) if necessary */\r
+ if (enablePullUp) {\r
+\r
+ pio->PIO_PUER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_PUDR = mask;\r
+ }\r
+\r
+ /* Enable multi-drive if necessary */\r
+ if (enableMultiDrive) {\r
+\r
+ pio->PIO_MDER = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_MDDR = mask;\r
+ }\r
+\r
+ /* Set default value */\r
+ if (defaultValue) {\r
+\r
+ pio->PIO_SODR = mask;\r
+ }\r
+ else {\r
+\r
+ pio->PIO_CODR = mask;\r
+ }\r
+\r
+ /* Configure pin(s) as output(s) */\r
+ pio->PIO_OER = mask;\r
+ pio->PIO_PER = mask;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a list of Pin instances, each of which can either hold a single\r
+ * pin or a group of pins, depending on the mask value; all pins are configured\r
+ * by this function. The size of the array must also be provided and is easily\r
+ * computed using PIO_LISTSIZE whenever its length is not known in advance.\r
+ *\r
+ * \param list Pointer to a list of Pin instances.\r
+ * \param size Size of the Pin list (calculated using PIO_LISTSIZE).\r
+ *\r
+ * \return 1 if the pins have been configured properly; otherwise 0.\r
+ */\r
+uint8_t PIO_Configure( const Pin *list, uint32_t size )\r
+{\r
+ /* Configure pins */\r
+ while ( size > 0 )\r
+ {\r
+ switch ( list->type )\r
+ {\r
+\r
+ case PIO_PERIPH_A:\r
+ PIO_SetPeripheralA(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ PIO_SetPeripheralB(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ case PIO_PERIPH_C:\r
+ PIO_SetPeripheralC(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ case PIO_PERIPH_D:\r
+ PIO_SetPeripheralD(list->pio,\r
+ list->mask,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+ case PIO_INPUT:\r
+#ifndef __FPGA\r
+ PMC_EnablePeripheral(list->id);\r
+#endif\r
+ PIO_SetInput(list->pio,\r
+ list->mask,\r
+ list->attribute);\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ PIO_SetOutput(list->pio,\r
+ list->mask,\r
+ (list->type == PIO_OUTPUT_1),\r
+ (list->attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (list->attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default: return 0;\r
+ }\r
+\r
+ list++;\r
+ size--;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Sets a high output level on all the PIOs defined in the given Pin instance.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will memorize the value they are changed to outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void PIO_Set(const Pin *pin)\r
+{\r
+ pin->pio->PIO_SODR = pin->mask;\r
+}\r
+\r
+/**\r
+ * \brief Sets a low output level on all the PIOs defined in the given Pin instance.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will memorize the value they are changed to outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void PIO_Clear(const Pin *pin)\r
+{\r
+ pin->pio->PIO_CODR = pin->mask;\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * PIO_GetOutputDataStatus() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that currently has\r
+ * a high level; otherwise 0.\r
+ */\r
+unsigned char PIO_Get( const Pin *pin )\r
+{\r
+ unsigned int reg ;\r
+\r
+ if ( (pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1) )\r
+ {\r
+ reg = pin->pio->PIO_ODSR ;\r
+ }\r
+ else\r
+ {\r
+ reg = pin->pio->PIO_PDSR ;\r
+ }\r
+\r
+ if ( (reg & pin->mask) == 0 )\r
+ {\r
+ return 0 ;\r
+ }\r
+ else\r
+ {\r
+ return 1 ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a\r
+ * high level (even if they are not output).\r
+ * To get the actual value of the pin, use PIO_Get() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that is configured\r
+ * to output a high level; otherwise 0.\r
+ */\r
+unsigned char PIO_GetOutputDataStatus(const Pin *pin)\r
+{\r
+ if ((pin->pio->PIO_ODSR & pin->mask) == 0) {\r
+\r
+ return 0;\r
+ }\r
+ else {\r
+\r
+ return 1;\r
+ }\r
+}\r
+\r
+/*\r
+ * \brief Configures Glitch or Debouncing filter for input.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ * \param cuttoff Cutt off frequency for debounce filter.\r
+ */\r
+void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff )\r
+{\r
+ Pio *pio = pin->pio;\r
+\r
+ pio->PIO_IFSCER = pin->mask; /* set Debouncing, 0 bit field no effect */\r
+ pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF; /* the lowest 14 bits work */\r
+}\r
+\r
+/*\r
+ * \brief Enable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void PIO_EnableWriteProtect( const Pin *pin )\r
+{\r
+ Pio *pio = pin->pio;\r
+\r
+ pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_EN );\r
+}\r
+\r
+/*\r
+ * \brief Disable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+\r
+void PIO_DisableWriteProtect( const Pin *pin )\r
+{\r
+ Pio *pio = pin->pio;\r
+\r
+ pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_DIS );\r
+}\r
+\r
+/*\r
+ * \brief Get write protect violation information.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+\r
+uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin )\r
+{\r
+ Pio *pio = pin->pio;\r
+ return (pio->PIO_WPSR);\r
+}\r
+/* \brief Set pin type\r
+ * the pin is controlled by the corresponding peripheral (A, B, C, D,E)\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ * \param pinType PIO_PERIPH_A, PIO_PERIPH_B, ...\r
+ */\r
+\r
+void PIO_SetPinType( Pin * pin, uint8_t pinType)\r
+{\r
+ pin->type = pinType;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode\r
+ * \ingroup peripherals_module\r
+ * The PIO Parallel Capture Mode driver provides the interface to configure and use the\r
+ * PIO Parallel Capture Mode peripheral.\n\r
+ *\r
+ * The PIO Controller integrates an interface able to read data from a CMOS digital\r
+ * image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous\r
+ * mode, etc.... For better understanding and to ease reading, the following\r
+ * description uses an example with a CMOS digital image sensor\r
+ *\r
+ * To use the PIO Parallel Capture, the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Enable PIOA peripheral clock </li>\r
+ * <li> Configure the PDC </li>\r
+ * <li> Configure the PIO Capture interrupt </li>\r
+ * <li> Enable the PDC </li>\r
+ * <li> Enable the PIO Capture </li>\r
+ * <li> Wait for interrupt </li>\r
+ * <li> Disable the interrupt </li>\r
+ * <li> Read the DATA </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the PIO Parallel Capture Mode section of the\r
+ * Datasheet.\r
+ *\r
+ * <b>API Usage:</b>\r
+ *\r
+ * -# Configurate the interrupt for PIOA, can be done by PIO_InitializeInterrupts()\r
+ * -# Initialize the PIO Parallel Capture API by filing the SpioCaptureInit structur.\r
+ * 2 options:\r
+ * - alwaysSampling: for sample data with or without take in account ENABLE pins.\r
+ * - halfSampling: for sample all data or only one time out of two\r
+ * -# Call PIO_CaptureInit() for init and enable the PDC, init the PIO capture.\r
+ * -# Call PIO_CaptureEnable() for enable the PIO Parallel Capture.\r
+ * -# When an interrupt is received, the PIO_CaptureHandler() is call and the respective\r
+ * callback is launch.\r
+ * -# When the transfer is complete, the user need to disable interrupt with\r
+ * PIO_CaptureDisableIt(). Otherway, the PDC will send an interrupt.\r
+ * -# The data receive by the PIO Parallel Capture is inside the buffer passed in the\r
+ * PIO_CaptureInit().\r
+ *\r
+ * Related files :\n\r
+ * \ref pio_capture.c\n\r
+ * \ref pio_capture.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of PIO Parallel Capture.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Functions\r
+ *----------------------------------------------------------------------------*/\r
+/** Copy the API structure for interrupt handler */\r
+static SpioCaptureInit* _PioCaptureCopy;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt\r
+ * Service Routine with the corresponding PIO Capture instance.\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+extern void PIO_CaptureHandler( void )\r
+{\r
+ volatile uint32_t pio_captureSr;\r
+ uint32_t k;\r
+\r
+ /* Read the status register*/\r
+ pio_captureSr = PIOA->PIO_PCISR ;\r
+ k = pio_captureSr;\r
+ pio_captureSr = k & PIOA->PIO_PCIMR ;\r
+\r
+ if (pio_captureSr & PIO_PCISR_DRDY)\r
+ {\r
+ /* Parallel Capture Mode Data Ready */\r
+ if ( _PioCaptureCopy->CbkDataReady != NULL )\r
+ {\r
+ _PioCaptureCopy->CbkDataReady( _PioCaptureCopy );\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r");\r
+ }\r
+ }\r
+\r
+ if (pio_captureSr & PIO_PCISR_OVRE)\r
+ {\r
+ /* Parallel Capture Mode Overrun Error */\r
+ if ( _PioCaptureCopy->CbkOverrun != NULL )\r
+ {\r
+ _PioCaptureCopy->CbkOverrun( _PioCaptureCopy );\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r");\r
+ }\r
+ }\r
+\r
+ if (pio_captureSr & PIO_PCISR_RXBUFF)\r
+ {\r
+ /* Reception Buffer Full */\r
+ if ( _PioCaptureCopy->CbkBuffFull != NULL )\r
+ {\r
+ _PioCaptureCopy->CbkBuffFull( _PioCaptureCopy );\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG("IT PIO Capture Reception Buffer Full received (no callback)\n\r");\r
+ }\r
+ }\r
+\r
+ if (pio_captureSr & PIO_PCISR_ENDRX)\r
+ {\r
+ /* End of Reception Transfer */\r
+ if ( _PioCaptureCopy->CbkEndReception != NULL )\r
+ {\r
+ _PioCaptureCopy->CbkEndReception( _PioCaptureCopy );\r
+ }\r
+ else\r
+ {\r
+ TRACE_DEBUG("IT PIO Capture End of Reception Transfer received (no callback)\n\r");\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Disable Interupt of the PIO Capture\r
+ * \param itToDisable : Interrupt to disable\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+void PIO_CaptureDisableIt( uint32_t itToDisable )\r
+{\r
+ /* Parallel capture mode is enabled */\r
+ PIOA->PIO_PCIDR = itToDisable;\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Enable Interupt of the PIO Capture\r
+ * \param itToEnable : Interrupt to enable\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+void PIO_CaptureEnableIt( uint32_t itToEnable )\r
+{\r
+ /* Parallel capture mode is enabled */\r
+ PIOA->PIO_PCIER = itToEnable;\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Enable the PIO Capture\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+void PIO_CaptureEnable( void )\r
+{\r
+ /* PDC: Receive Pointer Register */\r
+// PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ;\r
+// /* PDC: Receive Counter Register */\r
+// /* Starts peripheral data transfer if corresponding channel is active */\r
+// PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ;\r
+\r
+ /* Parallel capture mode is enabled */\r
+ PIOA->PIO_PCMR |= PIO_PCMR_PCEN ;\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Disable the PIO Capture\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+void PIO_CaptureDisable( void )\r
+{\r
+ /* Parallel capture mode is disabled */\r
+ PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ;\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initialize the PIO Capture\r
+ * Be careful to configure the PDC before enable interrupt on pio capture.\r
+ * Otherway, the pdc will go in interrupt handler continuously.\r
+ * \param dsize :\r
+ * 0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).\r
+ * 1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).\r
+ * 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).\r
+ * \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling\r
+ * 0 = The parallel capture mode samples the data when both data enables are active.\r
+ * 1 = The parallel capture mode samples the data whatever the data enables are.\r
+ * \param halfSampling: HALFS: Parallel Capture Mode Half Sampling\r
+ * 0 = The parallel capture mode samples all the data.\r
+ * 1 = The parallel capture mode samples the data only one time out of two.\r
+ * \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample\r
+ * This bit is useful only if the HALFS bit is set to 1. If data are numbered\r
+ * in the order that they are received with an index from 0 to n:\r
+ * 0 = Only data with an even index are sampled.\r
+ * 1 = Only data with an odd index are sampled.\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+void PIO_CaptureInit( SpioCaptureInit *pInit )\r
+{\r
+ PMC_EnablePeripheral( ID_PIOA );\r
+\r
+ assert( (pInit->dsize < 0x4) ) ;\r
+ assert( (pInit->alwaysSampling < 2) );\r
+ assert( (pInit->halfSampling < 2) );\r
+ assert( (pInit->modeFirstSample < 2) );\r
+\r
+ /* PDC: Transfer Control Register */\r
+ /* Disables the PDC transmitter channel requests */\r
+// PIOA->PIO_PTCR = PIO_PTCR_RXTDIS;\r
+ /* PDC: Receive Pointer Register */\r
+// PIOA->PIO_RPR = (uint32_t)pInit->pData;\r
+ /* PDC: Receive Counter Register */\r
+ /* Starts peripheral data transfer if corresponding channel is active */\r
+// PIOA->PIO_RCR = PIO_RCR_RXCTR(pInit->dPDCsize);\r
+\r
+ /* PDC: Transfer Control Register */\r
+ /* Enables PDC receiver channel requests if RXTDIS is not set */\r
+// PIOA->PIO_PTCR = PIO_PTCR_RXTEN ;\r
+\r
+\r
+ /* Copy the API structure for interrupt handler */\r
+ _PioCaptureCopy = pInit;\r
+ /* PIO Parallel Capture Mode */\r
+// PIOA->PIO_PCMR = PIO_PCMR_DSIZE(pInit->dsize)\r
+// | ((pInit->alwaysSampling<<9) & PIO_PCMR_ALWYS)\r
+// | ((pInit->halfSampling<<10) & PIO_PCMR_HALFS)\r
+// | ((pInit->modeFirstSample<<11) & PIO_PCMR_FRSTS);\r
+\r
+ if ( pInit->CbkDataReady != NULL )\r
+ {\r
+ PIOA->PIO_PCIER = PIO_PCISR_DRDY;\r
+ }\r
+\r
+ if ( pInit->CbkOverrun != NULL )\r
+ {\r
+ PIOA->PIO_PCIER = PIO_PCISR_OVRE;\r
+ }\r
+\r
+ if ( pInit->CbkEndReception != NULL )\r
+ {\r
+ PIOA->PIO_PCIER = PIO_PCISR_ENDRX;\r
+ }\r
+\r
+ if ( pInit->CbkBuffFull != NULL )\r
+ {\r
+ PIOA->PIO_PCIER = PIO_PCISR_RXBUFF;\r
+ }\r
+// else\r
+// {\r
+// TRACE_INFO("No interruption, no callback\n\r");\r
+// }\r
+\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ * \file\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Maximum number of interrupt sources that can be defined. This\r
+ * constant can be increased, but the current value is the smallest possible\r
+ * that will be compatible with all existing projects. */\r
+#define MAX_INTERRUPT_SOURCES 7\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Describes a PIO interrupt source, including the PIO instance triggering the\r
+ * interrupt and the associated interrupt handler.\r
+ */\r
+typedef struct _InterruptSource\r
+{\r
+ /* Pointer to the source pin instance. */\r
+ const Pin *pPin;\r
+\r
+ /* Interrupt handler. */\r
+ void (*handler)( const Pin* ) ;\r
+} InterruptSource ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* List of interrupt sources. */\r
+static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;\r
+\r
+/* Number of currently defined interrupt sources. */\r
+static uint32_t _dwNumSources = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Handles all interrupts on the given PIO controller.\r
+ * \param id PIO controller ID.\r
+ * \param pPio PIO controller base address.\r
+ */\r
+extern void PioInterruptHandler( uint32_t id, Pio *pPio )\r
+{\r
+ uint32_t status;\r
+ uint32_t i;\r
+\r
+ /* Read PIO controller status */\r
+ status = pPio->PIO_ISR;\r
+ status &= pPio->PIO_IMR;\r
+\r
+ /* Check pending events */\r
+ if ( status != 0 )\r
+ {\r
+ TRACE_DEBUG( "PIO interrupt on PIO controller #%d\n\r", id ) ;\r
+\r
+ /* Find triggering source */\r
+ i = 0;\r
+ while ( status != 0 )\r
+ {\r
+ /* There cannot be an unconfigured source enabled. */\r
+ assert(i < _dwNumSources);\r
+\r
+ /* Source is configured on the same controller */\r
+ if (_aIntSources[i].pPin->id == id)\r
+ {\r
+ /* Source has PIOs whose statuses have changed */\r
+ if ( (status & _aIntSources[i].pPin->mask) != 0 )\r
+ {\r
+ TRACE_DEBUG( "Interrupt source #%d triggered\n\r", i ) ;\r
+\r
+ _aIntSources[i].handler(_aIntSources[i].pPin);\r
+ status &= ~(_aIntSources[i].pPin->mask);\r
+ }\r
+ }\r
+ i++;\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Parallel IO Controller A interrupt handler\r
+ * \Redefined PIOA interrupt handler for NVIC interrupt table.\r
+ */\r
+extern void PIOA_Handler( void )\r
+{\r
+ PioInterruptHandler( ID_PIOA, PIOA ) ;\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller B interrupt handler\r
+ * \Redefined PIOB interrupt handler for NVIC interrupt table.\r
+ */\r
+extern void PIOB_Handler( void )\r
+{\r
+ PioInterruptHandler( ID_PIOB, PIOB ) ;\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller C interrupt handler\r
+ * \Redefined PIOC interrupt handler for NVIC interrupt table.\r
+ */\r
+extern void PIOC_Handler( void )\r
+{\r
+ PioInterruptHandler( ID_PIOC, PIOC ) ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Parallel IO Controller D interrupt handler\r
+ * \Redefined PIOD interrupt handler for NVIC interrupt table.\r
+ */\r
+extern void PIOD_Handler( void )\r
+{\r
+ PioInterruptHandler( ID_PIOD, PIOD ) ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Parallel IO Controller E interrupt handler\r
+ * \Redefined PIOE interrupt handler for NVIC interrupt table.\r
+ */\r
+extern void PIOE_Handler( void )\r
+{\r
+ PioInterruptHandler( ID_PIOE, PIOE ) ;\r
+}\r
+\r
+/**\r
+ * \brief Initializes the PIO interrupt management logic\r
+ *\r
+ * The desired priority of PIO interrupts must be provided.\r
+ * Calling this function multiple times result in the reset of currently\r
+ * configured interrupts.\r
+ *\r
+ * \param priority PIO controller interrupts priority.\r
+ */\r
+extern void PIO_InitializeInterrupts( uint32_t dwPriority )\r
+{\r
+ TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;\r
+\r
+ /* Reset sources */\r
+ _dwNumSources = 0 ;\r
+\r
+ /* Configure PIO interrupt sources */\r
+ TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;\r
+ PMC_EnablePeripheral( ID_PIOA ) ;\r
+ PIOA->PIO_ISR ;\r
+ PIOA->PIO_IDR = 0xFFFFFFFF ;\r
+ NVIC_DisableIRQ( PIOA_IRQn ) ;\r
+ NVIC_ClearPendingIRQ( PIOA_IRQn ) ;\r
+ NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;\r
+ NVIC_EnableIRQ( PIOA_IRQn ) ;\r
+\r
+ TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;\r
+ PMC_EnablePeripheral( ID_PIOB ) ;\r
+ PIOB->PIO_ISR ;\r
+ PIOB->PIO_IDR = 0xFFFFFFFF ;\r
+ NVIC_DisableIRQ( PIOB_IRQn ) ;\r
+ NVIC_ClearPendingIRQ( PIOB_IRQn ) ;\r
+ NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;\r
+ NVIC_EnableIRQ( PIOB_IRQn ) ;\r
+\r
+ TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;\r
+ PMC_EnablePeripheral( ID_PIOC ) ;\r
+ PIOC->PIO_ISR ;\r
+ PIOC->PIO_IDR = 0xFFFFFFFF ;\r
+ NVIC_DisableIRQ( PIOC_IRQn ) ;\r
+ NVIC_ClearPendingIRQ( PIOC_IRQn ) ;\r
+ NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;\r
+ NVIC_EnableIRQ( PIOC_IRQn ) ;\r
+\r
+ TRACE_DEBUG( "PIO_Initialize: Configuring PIOD\n\r" ) ;\r
+ PMC_EnablePeripheral( ID_PIOD ) ;\r
+ PIOD->PIO_ISR ;\r
+ PIOD->PIO_IDR = 0xFFFFFFFF ;\r
+ NVIC_DisableIRQ( PIOD_IRQn ) ;\r
+ NVIC_ClearPendingIRQ( PIOD_IRQn ) ;\r
+ NVIC_SetPriority( PIOD_IRQn, dwPriority ) ;\r
+ NVIC_EnableIRQ( PIOD_IRQn ) ;\r
+\r
+ TRACE_DEBUG( "PIO_Initialize: Configuring PIOE\n\r" ) ;\r
+ PMC_EnablePeripheral( ID_PIOE ) ;\r
+ PIOE->PIO_ISR ;\r
+ PIOE->PIO_IDR = 0xFFFFFFFF ;\r
+ NVIC_DisableIRQ( PIOE_IRQn ) ;\r
+ NVIC_ClearPendingIRQ( PIOE_IRQn ) ;\r
+ NVIC_SetPriority( PIOE_IRQn, dwPriority ) ;\r
+ NVIC_EnableIRQ( PIOE_IRQn ) ;\r
+}\r
+\r
+/**\r
+ * Configures a PIO or a group of PIO to generate an interrupt on status\r
+ * change. The provided interrupt handler will be called with the triggering\r
+ * pin as its parameter (enabling different pin instances to share the same\r
+ * handler).\r
+ * \param pPin Pointer to a Pin instance.\r
+ * \param handler Interrupt handler function pointer.\r
+ */\r
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )\r
+{\r
+ Pio* pio ;\r
+ InterruptSource* pSource ;\r
+\r
+ TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;\r
+\r
+ assert( pPin ) ;\r
+ pio = pPin->pio ;\r
+ assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;\r
+\r
+ /* Define new source */\r
+ TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%d.\n\r", _dwNumSources ) ;\r
+\r
+ pSource = &(_aIntSources[_dwNumSources]) ;\r
+ pSource->pPin = pPin ;\r
+ pSource->handler = handler ;\r
+ _dwNumSources++ ;\r
+\r
+ /* PIO3 with additional interrupt support\r
+ * Configure additional interrupt mode registers */\r
+ if ( pPin->attribute & PIO_IT_AIME )\r
+ {\r
+ // enable additional interrupt mode\r
+ pio->PIO_AIMER = pPin->mask ;\r
+\r
+ // if bit field of selected pin is 1, set as Rising Edge/High level detection event\r
+ if ( pPin->attribute & PIO_IT_RE_OR_HL )\r
+ {\r
+ pio->PIO_REHLSR = pPin->mask ;\r
+ }\r
+ else\r
+ {\r
+ pio->PIO_FELLSR = pPin->mask;\r
+ }\r
+\r
+ /* if bit field of selected pin is 1, set as edge detection source */\r
+ if (pPin->attribute & PIO_IT_EDGE)\r
+ pio->PIO_ESR = pPin->mask;\r
+ else\r
+ pio->PIO_LSR = pPin->mask;\r
+ }\r
+ else\r
+ {\r
+ /* disable additional interrupt mode */\r
+ pio->PIO_AIMDR = pPin->mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * Enables the given interrupt source if it has been configured. The status\r
+ * register of the corresponding PIO controller is cleared prior to enabling\r
+ * the interrupt.\r
+ * \param pPin Interrupt source to enable.\r
+ */\r
+extern void PIO_EnableIt( const Pin *pPin )\r
+{\r
+ TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ;\r
+\r
+ assert( pPin != NULL ) ;\r
+\r
+#ifndef NOASSERT\r
+ uint32_t i = 0;\r
+ uint32_t dwFound = 0;\r
+\r
+ while ( (i < _dwNumSources) && !dwFound )\r
+ {\r
+ if ( _aIntSources[i].pPin == pPin )\r
+ {\r
+ dwFound = 1 ;\r
+ }\r
+ i++ ;\r
+ }\r
+ assert( dwFound != 0 ) ;\r
+#endif\r
+\r
+ pPin->pio->PIO_ISR;\r
+ pPin->pio->PIO_IER = pPin->mask ;\r
+}\r
+\r
+/**\r
+ * Disables a given interrupt source, with no added side effects.\r
+ *\r
+ * \param pPin Interrupt source to disable.\r
+ */\r
+extern void PIO_DisableIt( const Pin *pPin )\r
+{\r
+ assert( pPin != NULL ) ;\r
+\r
+ TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ;\r
+\r
+ pPin->pio->PIO_IDR = pPin->mask;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define MASK_STATUS0 0xFFFFFFFC\r
+#define MASK_STATUS1 0xFFFFFFFF\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Switch MCK to PLLA clock.\r
+ */\r
+static void _PMC_SwitchMck2PllaClock(void)\r
+\r
+{\r
+ /* Select PLLA as input clock for MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK ;\r
+\r
+ /* Wait until the master clock is established */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Switch MCK to main clock.\r
+ */\r
+static void _PMC_SwitchMck2MainClock(void)\r
+{\r
+ /* Select Main Oscillator as input clock for MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK ;\r
+\r
+ /* Wait until the master clock is established */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+ PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Switch MCK to slow clock.\r
+ */\r
+static void _PMC_SwitchMck2SlowClock(void)\r
+{\r
+ /* Select Slow Clock as input clock for MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_SLOW_CLK ;\r
+\r
+ /* Wait until the master clock is established */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Set prescaler for MCK.\r
+ *\r
+ * \param prescaler Master Clock prescaler\r
+ */\r
+static void _PMC_SetMckPrescaler(uint32_t prescaler)\r
+{\r
+ /* Change MCK Prescaler divider in PMC_MCKR register */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | prescaler;\r
+\r
+ /* Wait until the master clock is established */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables the clock of a peripheral. The peripheral ID is used\r
+ * to identify which peripheral is targeted.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern void PMC_EnablePeripheral( uint32_t dwId )\r
+{\r
+ assert( dwId < 63 ) ;\r
+\r
+ if ( dwId < 32 )\r
+ {\r
+ if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )\r
+ {\r
+ TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", (unsigned int)dwId ) ;\r
+ }\r
+ else\r
+ {\r
+ PMC->PMC_PCER0 = 1 << dwId ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ dwId -= 32;\r
+ if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))\r
+ {\r
+ TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", (unsigned int)(dwId + 32) ) ;\r
+ }\r
+ else\r
+ {\r
+ PMC->PMC_PCER1 = 1 << dwId ;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disables the clock of a peripheral. The peripheral ID is used\r
+ * to identify which peripheral is targeted.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern void PMC_DisablePeripheral( uint32_t dwId )\r
+{\r
+ assert( dwId < 63 ) ;\r
+\r
+ if ( dwId < 32 )\r
+ {\r
+ if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )\r
+ {\r
+ TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", (unsigned int)dwId ) ;\r
+ }\r
+ else\r
+ {\r
+ PMC->PMC_PCDR0 = 1 << dwId ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ dwId -= 32 ;\r
+ if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )\r
+ {\r
+ TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", (unsigned int)(dwId + 32) ) ;\r
+ }\r
+ else\r
+ {\r
+ PMC->PMC_PCDR1 = 1 << dwId ;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable all the periph clock via PMC.\r
+ */\r
+extern void PMC_EnableAllPeripherals( void )\r
+{\r
+ PMC->PMC_PCER0 = MASK_STATUS0 ;\r
+ while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ;\r
+\r
+ PMC->PMC_PCER1 = MASK_STATUS1 ;\r
+ while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ;\r
+\r
+ TRACE_DEBUG( "Enable all periph clocks\n\r" ) ;\r
+}\r
+\r
+/**\r
+ * \brief Disable all the periph clock via PMC.\r
+ */\r
+extern void PMC_DisableAllPeripherals( void )\r
+{\r
+ PMC->PMC_PCDR0 = MASK_STATUS0 ;\r
+ while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ;\r
+\r
+ PMC->PMC_PCDR1 = MASK_STATUS1 ;\r
+ while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ;\r
+\r
+ TRACE_DEBUG( "Disable all periph clocks\n\r" ) ;\r
+}\r
+\r
+/**\r
+ * \brief Get Periph Status for the given peripheral ID.\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId )\r
+{\r
+ assert( dwId < ID_PERIPH_COUNT ) ;\r
+\r
+ if ( dwId < 32 )\r
+ {\r
+ return ( PMC->PMC_PCSR0 & (1 << dwId) ) ;\r
+ }\r
+ else {\r
+ return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable external oscilator as main clock input.\r
+ */\r
+extern void PMC_EnableExtOsc(void)\r
+{\r
+ uint32_t read_MOR;\r
+\r
+ /* Before switching MAIN OSC on external crystal : enable it and don't disable\r
+ * at the same time RC OSC in case of if MAIN OSC is still using RC OSC\r
+ */\r
+\r
+ read_MOR = PMC->CKGR_MOR;\r
+\r
+ read_MOR &= ~CKGR_MOR_MOSCRCF_Msk; /* reset MOSCRCF field in MOR register before select RC 12MHz */\r
+ read_MOR |= (CKGR_MOR_KEY_PASSWD \r
+ | CKGR_MOR_MOSCRCF_12_MHz\r
+ | CKGR_MOR_MOSCXTEN \r
+ | CKGR_MOR_MOSCRCEN \r
+ | CKGR_MOR_MOSCXTST(DEFAUTL_MAIN_OSC_COUNT)); /* enable external crystal - enable RC OSC */\r
+\r
+ PMC->CKGR_MOR = read_MOR;\r
+\r
+ while( !(PMC->PMC_SR & PMC_SR_MOSCRCS ) ); /* wait end of RC oscillator stabilization */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+\r
+ read_MOR |= CKGR_MOR_MOSCSEL; /* select external crystal */\r
+\r
+ PMC->CKGR_MOR = read_MOR;\r
+\r
+ while( !(PMC->PMC_SR & PMC_SR_MOSCSELS ) ); /* Wait end of Main Oscillator Selection */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Disable external 12MHz oscilator.\r
+ */\r
+extern void PMC_DisableExtOsc(void)\r
+{\r
+ uint32_t read_MOR;\r
+\r
+ read_MOR = PMC->CKGR_MOR;\r
+\r
+ read_MOR &= ~CKGR_MOR_MOSCXTEN; /* disable main xtal osc */\r
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | read_MOR;\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Select external OSC.\r
+ */\r
+extern void PMC_SelectExtOsc(void)\r
+{ \r
+ /* switch from internal RC 12 MHz to external OSC 12 MHz */\r
+ /* wait Main XTAL Oscillator stabilisation*/\r
+ if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) == CKGR_MOR_MOSCSEL){\r
+ PMC_DisableIntRC4_8_12MHz();\r
+ return;\r
+ }\r
+ /* enable external OSC 12 MHz */\r
+ PMC->CKGR_MOR |= CKGR_MOR_MOSCXTEN | CKGR_MOR_KEY_PASSWD; \r
+ /* wait Main CLK Ready */\r
+ while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY)); \r
+ /* switch MAIN clock to external OSC 12 MHz*/\r
+ PMC->CKGR_MOR |= CKGR_MOR_MOSCSEL | CKGR_MOR_KEY_PASSWD;\r
+ /* wait MAIN clock status change for external OSC 12 MHz selection*/\r
+ while(!(PMC->PMC_SR & PMC_SR_MOSCSELS));\r
+ /* in case where MCK is running on MAIN CLK */\r
+ while(!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ PMC_DisableIntRC4_8_12MHz();\r
+}\r
+\r
+\r
+/**\r
+ * \brief Select external OSC.\r
+ */\r
+extern void PMC_SelectExtBypassOsc(void)\r
+{ \r
+ volatile uint32_t timeout;\r
+ if((PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY) != CKGR_MOR_MOSCXTBY){\r
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD |\r
+ CKGR_MOR_MOSCRCEN | \r
+ CKGR_MOR_MOSCXTST(0xFF) |\r
+ CKGR_MOR_MOSCXTBY;\r
+ PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;\r
+ /* wait MAIN clock status change for external OSC 12 MHz selection*/\r
+ while(!(PMC->PMC_SR & PMC_SR_MOSCSELS));\r
+ // Check if an external clock is provided\r
+ for(timeout = 0; timeout<0xffff;timeout++);\r
+ while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY));\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable internal 4/8/12MHz fast RC as main clock input.\r
+ *\r
+ * \param freqSelect fast RC frequency (FAST_RC_4MHZ, FAST_RC_8MHZ, FAST_RC_12MHZ).\r
+ */\r
+extern void PMC_EnableIntRC4_8_12MHz(uint32_t freqSelect)\r
+{\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */\r
+ PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Change Fast RC oscillator frequency */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ CKGR_MOR_KEY_PASSWD | freqSelect;\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Switch to Fast RC */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |\r
+ CKGR_MOR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * \brief Disable internal 4/8/12MHz fast RC.\r
+ */\r
+extern void PMC_DisableIntRC4_8_12MHz(void)\r
+{\r
+ uint32_t read_MOR;\r
+\r
+ read_MOR = PMC->CKGR_MOR;\r
+\r
+ read_MOR &= ~CKGR_MOR_MOSCRCF_Msk; /* reset MOSCRCF field in MOR register */\r
+ read_MOR &= ~CKGR_MOR_MOSCRCEN; /* disable fast RC */\r
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | read_MOR;\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+}\r
+\r
+/**\r
+ * \brief Configure PLLA clock by giving MUL and DIV.\r
+ * Disable PLLA when 'mul' set to 0.\r
+ *\r
+ * \param mul PLL multiplier factor.\r
+ * \param div PLL divider factor.\r
+ */\r
+extern void PMC_SetPllaClock(uint32_t mul, uint32_t div)\r
+{\r
+ if (mul != 0)\r
+ {\r
+ /* Init PLL speed */\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE \r
+ | CKGR_PLLAR_PLLACOUNT(DEFAUTL_PLLA_COUNT)\r
+ | CKGR_PLLAR_MULA(mul - 1)\r
+ | CKGR_PLLAR_DIVA(div);\r
+\r
+ /* Wait for PLL stabilization */\r
+ while( !(PMC->PMC_SR & PMC_SR_LOCKA) );\r
+ }\r
+ else\r
+ {\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE; /* disable PLL A */\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Selection of Master Clock.\r
+ *\r
+ * \param clockSource Master Clock source.\r
+ * \param prescaler Master Clock prescaler.\r
+ *\r
+ * \note\r
+ * The PMC_MCKR register must not be programmed in a single write\r
+ * operation (see. Product Data Sheet).\r
+ */\r
+extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler)\r
+{\r
+ switch ( clockSource )\r
+ {\r
+ case PMC_MCKR_CSS_SLOW_CLK :\r
+ _PMC_SwitchMck2SlowClock();\r
+ _PMC_SetMckPrescaler(prescaler);\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_MAIN_CLK :\r
+ _PMC_SwitchMck2MainClock();\r
+ _PMC_SetMckPrescaler(prescaler);\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_PLLA_CLK :\r
+ _PMC_SetMckPrescaler(prescaler);\r
+ _PMC_SwitchMck2PllaClock();\r
+ break ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable all clocks.\r
+ */\r
+extern void PMC_DisableAllClocks(void)\r
+{\r
+ uint32_t read_reg;\r
+\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2 | PMC_SCDR_PCK3 | PMC_SCDR_PCK4 | PMC_SCDR_PCK5 | PMC_SCDR_PCK6; /* disable PCK */\r
+\r
+ _PMC_SwitchMck2MainClock();\r
+\r
+ PMC->CKGR_PLLAR = PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk; /* disable PLL A */\r
+\r
+ _PMC_SwitchMck2SlowClock();\r
+\r
+ read_reg = PMC->CKGR_MOR;\r
+\r
+ read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY_PASSWD; /* disable RC OSC */\r
+\r
+ PMC->CKGR_MOR = read_reg;\r
+\r
+ PMC_DisableAllPeripherals(); /* disable all peripheral clocks */\r
+}\r
+\r
+/**\r
+ * \brief Configure PLLA as clock input for MCK.\r
+ *\r
+ * \param mul PLL multiplier factor (not shifted, don't minus 1).\r
+ * \param div PLL divider factor (not shifted).\r
+ * \param prescaler Master Clock prescaler (shifted as in register).\r
+ */\r
+extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, uint32_t prescaler)\r
+{\r
+ /* First, select Main OSC as input clock for MCK */\r
+ _PMC_SwitchMck2MainClock();\r
+\r
+ /* Then, Set PLLA clock */\r
+ PMC_SetPllaClock(mul, div);\r
+\r
+ /* Wait until the master clock is established for the case we already turn on the PLL */\r
+ while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );\r
+\r
+ /* Finally, select PllA as input clock for MCK */\r
+ PMC_SetMckSelection(PMC_MCKR_CSS_PLLA_CLK, prescaler);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure PLLA as clock input for MCK.\r
+ *\r
+ * \param mul PLL multiplier factor (not shifted, don't minus 1).\r
+ * \param div PLL divider factor (not shifted).\r
+ * \param prescaler Master Clock prescaler (shifted as in register).\r
+ */\r
+extern void PMC_EnableXT32KFME(void)\r
+{\r
+\r
+ uint32_t read_MOR;\r
+\r
+ /* Before switching MAIN OSC on external crystal : enable it and don't disable\r
+ * at the same time RC OSC in case of if MAIN OSC is still using RC OSC\r
+ */\r
+\r
+ read_MOR = PMC->CKGR_MOR;\r
+\r
+ read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME); /* enable external crystal - enable RC OSC */\r
+\r
+ PMC->CKGR_MOR = read_MOR;\r
+\r
+}\r
+\r
+/**\r
+ * \brief Configure PLLA as clock input for MCK.\r
+ *\r
+ * \param mul PLL multiplier factor (not shifted, don't minus 1).\r
+ * \param div PLL divider factor (not shifted).\r
+ * \param prescaler Master Clock prescaler (shifted as in register).\r
+ */\r
+extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK2; /* disable PCK */\r
+\r
+ while((PMC->PMC_SCSR)& PMC_SCSR_PCK2);\r
+ PMC->PMC_PCK[2] = MasterClk | prescaler; \r
+ PMC->PMC_SCER = PMC_SCER_PCK2;\r
+ while(!((PMC->PMC_SR) & PMC_SR_PCKRDY2));\r
+\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pwm_module Working with PWM\r
+ * \ingroup peripherals_module\r
+ * The PWM driver provides the interface to configure and use the PWM\r
+ * peripheral.\r
+ *\r
+ * The PWM macrocell controls square output waveforms of 4 channels.\r
+ * Characteristics of output waveforms such as period, duty-cycle,\r
+ * dead-time can be configured.\n\r
+ * Some of PWM channels can be linked together as synchronous channel and\r
+ * duty-cycle of synchronous channels can be updated by PDC automaticly.\r
+ *\r
+ * Before enabling the channels, they must have been configured first.\r
+ * The main settings include:\r
+ * <ul>\r
+ * <li>Configuration of the clock generator.</li>\r
+ * <li>Selection of the clock for each channel.</li>\r
+ * <li>Configuration of output waveform characteristics, such as period, duty-cycle etc.</li>\r
+ * <li>Configuration for synchronous channels if needed.</li>\r
+ * - Selection of the synchronous channels.\r
+ * - Selection of the moment when the WRDY flag and the corresponding PDC\r
+ * transfer request are set (PTRM and PTRCS in the PWM_SCM register).\r
+ * - Configuration of the update mode (UPDM in the PWM_SCM register).\r
+ * - Configuration of the update period (UPR in the PWM_SCUP register).\r
+ * </ul>\r
+ *\r
+ * After the channels is enabled, the user must use respective update registers\r
+ * to change the wave characteristics to prevent unexpected output waveform.\r
+ * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle\r
+ * when the channel is enabled.\r
+ *\r
+ * For more accurate information, please look at the PWM section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref pwmc.c\n\r
+ * \ref pwmc.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Finds a prescaler/divisor couple to generate the desired frequency\r
+ * from MCK.\r
+ *\r
+ * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be\r
+ * met.\r
+ *\r
+ * \param frequency Desired frequency in Hz.\r
+ * \param mck Master clock frequency in Hz.\r
+ */\r
+static uint16_t FindClockConfiguration(\r
+ uint32_t frequency,\r
+ uint32_t mck)\r
+{\r
+ uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};\r
+ uint8_t divisor = 0;\r
+ uint32_t prescaler;\r
+\r
+ assert(frequency < mck);\r
+\r
+ /* Find prescaler and divisor values */\r
+ prescaler = (mck / divisors[divisor]) / frequency;\r
+ while ((prescaler > 255) && (divisor < 11)) {\r
+\r
+ divisor++;\r
+ prescaler = (mck / divisors[divisor]) / frequency;\r
+ }\r
+\r
+ /* Return result */\r
+ if ( divisor < 11 )\r
+ {\r
+ TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", divisors[divisor], prescaler, frequency ) ;\r
+\r
+ return prescaler | (divisor << 8) ;\r
+ }\r
+ else\r
+ {\r
+ return 0 ;\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures PWM a channel with the given parameters, basic configure function.\r
+ *\r
+ * The PWM controller must have been clocked in the PMC prior to calling this\r
+ * function.\r
+ * Beware: this function disables the channel. It waits until disable is effective.\r
+ *\r
+ * \param channel Channel number.\r
+ * \param prescaler Channel prescaler.\r
+ * \param alignment Channel alignment.\r
+ * \param polarity Channel polarity.\r
+ */\r
+void PWMC_ConfigureChannel(\r
+ Pwm* pPwm,\r
+ uint8_t channel,\r
+ uint32_t prescaler,\r
+ uint32_t alignment,\r
+ uint32_t polarity)\r
+{\r
+ pPwm->PWM_CH_NUM[0].PWM_CMR = 1;\r
+\r
+ // assert(prescaler < PWM_CMR0_CPRE_MCKB);\r
+ assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);\r
+ assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);\r
+\r
+ /* Disable channel (effective at the end of the current period) */\r
+ if ((pPwm->PWM_SR & (1 << channel)) != 0) {\r
+ pPwm->PWM_DIS = 1 << channel;\r
+ while ((pPwm->PWM_SR & (1 << channel)) != 0);\r
+ }\r
+\r
+ /* Configure channel */\r
+ pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity;\r
+}\r
+\r
+/**\r
+ * \brief Configures PWM a channel with the given parameters, extend configure function.\r
+ *\r
+ * The PWM controller must have been clocked in the PMC prior to calling this\r
+ * function.\r
+ * Beware: this function disables the channel. It waits until disable is effective.\r
+ *\r
+ * \param channel Channel number.\r
+ * \param prescaler Channel prescaler.\r
+ * \param alignment Channel alignment.\r
+ * \param polarity Channel polarity.\r
+ * \param countEventSelect Channel counter event selection.\r
+ * \param DTEnable Channel dead time generator enable.\r
+ * \param DTHInverte Channel Dead-Time PWMHx output Inverted.\r
+ * \param DTLInverte Channel Dead-Time PWMHx output Inverted.\r
+ */\r
+void PWMC_ConfigureChannelExt(\r
+ Pwm* pPwm,\r
+ uint8_t channel,\r
+ uint32_t prescaler,\r
+ uint32_t alignment,\r
+ uint32_t polarity,\r
+ uint32_t countEventSelect,\r
+ uint32_t DTEnable,\r
+ uint32_t DTHInverte,\r
+ uint32_t DTLInverte)\r
+{\r
+ // assert(prescaler < PWM_CMR0_CPRE_MCKB);\r
+ assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);\r
+ assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);\r
+ assert((countEventSelect & (uint32_t)~PWM_CMR_CES) == 0);\r
+ assert((DTEnable & (uint32_t)~PWM_CMR_DTE) == 0);\r
+ assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0);\r
+ assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0);\r
+\r
+ /* Disable channel (effective at the end of the current period) */\r
+ if ((pPwm->PWM_SR & (1 << channel)) != 0) {\r
+ pPwm->PWM_DIS = 1 << channel;\r
+ while ((pPwm->PWM_SR & (1 << channel)) != 0);\r
+ }\r
+\r
+ /* Configure channel */\r
+ pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity |\r
+ countEventSelect | DTEnable | DTHInverte | DTLInverte;\r
+}\r
+\r
+/**\r
+ * \brief Configures PWM clocks A & B to run at the given frequencies.\r
+ *\r
+ * This function finds the best MCK divisor and prescaler values automatically.\r
+ *\r
+ * \param clka Desired clock A frequency (0 if not used).\r
+ * \param clkb Desired clock B frequency (0 if not used).\r
+ * \param mck Master clock frequency.\r
+ */\r
+void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t clka, uint32_t clkb, uint32_t mck)\r
+{\r
+ uint32_t mode = 0;\r
+ uint32_t result;\r
+\r
+ /* Clock A */\r
+ if (clka != 0) {\r
+\r
+ result = FindClockConfiguration(clka, mck);\r
+ assert( result != 0 ) ;\r
+ mode |= result;\r
+ }\r
+\r
+ /* Clock B */\r
+ if (clkb != 0) {\r
+\r
+ result = FindClockConfiguration(clkb, mck);\r
+ assert( result != 0 ) ;\r
+ mode |= (result << 16);\r
+ }\r
+\r
+ /* Configure clocks */\r
+ TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ;\r
+ pPwm->PWM_CLK = mode;\r
+}\r
+\r
+/**\r
+ * \brief Sets the period value used by a PWM channel.\r
+ *\r
+ * This function writes directly to the CPRD register if the channel is disabled;\r
+ * otherwise, it uses the update register CPRDUPD.\r
+ *\r
+ * \param channel Channel number.\r
+ * \param period Period value.\r
+ */\r
+void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period)\r
+{\r
+ /* If channel is disabled, write to CPRD */\r
+ if ((pPwm->PWM_SR & (1 << channel)) == 0) {\r
+\r
+ pPwm->PWM_CH_NUM[channel].PWM_CPRD = period;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+\r
+ pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets the duty cycle used by a PWM channel.\r
+ * This function writes directly to the CDTY register if the channel is disabled;\r
+ * otherwise it uses the update register CDTYUPD.\r
+ * Note that the duty cycle must always be inferior or equal to the channel\r
+ * period.\r
+ *\r
+ * \param channel Channel number.\r
+ * \param duty Duty cycle value.\r
+ */\r
+void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty)\r
+{\r
+ assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);\r
+\r
+ /* If channel is disabled, write to CDTY */\r
+ if ((pPwm->PWM_SR & (1 << channel)) == 0) {\r
+\r
+ pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+\r
+ pPwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets the dead time used by a PWM channel.\r
+ * This function writes directly to the DT register if the channel is disabled;\r
+ * otherwise it uses the update register DTUPD.\r
+ * Note that the dead time must always be inferior or equal to the channel\r
+ * period.\r
+ *\r
+ * \param channel Channel number.\r
+ * \param timeH Dead time value for PWMHx output.\r
+ * \param timeL Dead time value for PWMLx output.\r
+ */\r
+void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL)\r
+{\r
+ assert(timeH <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);\r
+ assert(timeL <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);\r
+\r
+ /* If channel is disabled, write to DT */\r
+ if ((pPwm->PWM_SR & (1 << channel)) == 0) {\r
+\r
+ pPwm->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16);\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+ pPwm->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures Syncronous channel with the given parameters.\r
+ * Beware: At this time, the channels should be disabled.\r
+ *\r
+ * \param channels Bitwise OR of Syncronous channels.\r
+ * \param updateMode Syncronous channel update mode.\r
+ * \param requestMode PDC transfer request mode.\r
+ * \param requestComparisonSelect PDC transfer request comparison selection.\r
+ */\r
+void PWMC_ConfigureSyncChannel( Pwm* pPwm,\r
+ uint32_t channels,\r
+ uint32_t updateMode,\r
+ uint32_t requestMode,\r
+ uint32_t requestComparisonSelect)\r
+{\r
+ pPwm->PWM_SCM = channels | updateMode | requestMode | requestComparisonSelect;\r
+}\r
+\r
+/**\r
+ * \brief Sets the update period of the synchronous channels.\r
+ * This function writes directly to the SCUP register if the channel #0 is disabled;\r
+ * otherwise it uses the update register SCUPUPD.\r
+ *\r
+ * \param period update period.\r
+ */\r
+void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period)\r
+{\r
+ /* If channel is disabled, write to SCUP */\r
+ if ((pPwm->PWM_SR & (1 << 0)) == 0) {\r
+\r
+ pPwm->PWM_SCUP = period;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+\r
+ pPwm->PWM_SCUPUPD = period;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets synchronous channels update unlock.\r
+ *\r
+ * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1\r
+ * triggers the update of the period value, the duty-cycle and\r
+ * the dead-time values of synchronous channels at the beginning\r
+ * of the next PWM period. If the field UPDM is set to 1 or 2,\r
+ * writing the UPDULOCK bit to 1 triggers only the update of\r
+ * the period value and of the dead-time values of synchronous channels.\r
+ * This bit is automatically reset when the update is done.\r
+ */\r
+void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm )\r
+{\r
+ pPwm->PWM_SCUC = PWM_SCUC_UPDULOCK;\r
+}\r
+\r
+/**\r
+ * \brief Enables the given PWM channel.\r
+ *\r
+ * This does NOT enable the corresponding pin;this must be done in the user code.\r
+ *\r
+ * \param channel Channel number.\r
+ */\r
+void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel)\r
+{\r
+ pPwm->PWM_ENA = 1 << channel;\r
+}\r
+\r
+/**\r
+ * \brief Disables the given PWM channel.\r
+ *\r
+ * Beware, channel will be effectively disabled at the end of the current period.\r
+ * Application can check channel is disabled using the following wait loop:\r
+ * while ((PWM->PWM_SR & (1 << channel)) != 0);\r
+ *\r
+ * \param channel Channel number.\r
+ */\r
+void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel)\r
+{\r
+ pPwm->PWM_DIS = 1 << channel;\r
+}\r
+\r
+/**\r
+ * \brief Enables the period interrupt for the given PWM channel.\r
+ *\r
+ * \param channel Channel number.\r
+ */\r
+void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel)\r
+{\r
+ pPwm->PWM_IER1 = 1 << channel;\r
+}\r
+\r
+/**\r
+ * \brief Return PWM Interrupt Status2 Register\r
+ *\r
+ */\r
+uint32_t PWMC_GetStatus2( Pwm* pPwm)\r
+{\r
+ return pPwm->PWM_ISR2;\r
+}\r
+\r
+/**\r
+ * \brief Disables the period interrupt for the given PWM channel.\r
+ *\r
+ * \param channel Channel number.\r
+ */\r
+void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel)\r
+{\r
+ pPwm->PWM_IDR1 = 1 << channel;\r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a PWMC peripheral.\r
+ *\r
+ * \param sources1 Bitwise OR of selected interrupt sources of PWM_IER1.\r
+ * \param sources2 Bitwise OR of selected interrupt sources of PWM_IER2.\r
+ */\r
+void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)\r
+{\r
+ pPwm->PWM_IER1 = sources1;\r
+ pPwm->PWM_IER2 = sources2;\r
+}\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a PWMC peripheral.\r
+ *\r
+ * \param sources1 Bitwise OR of selected interrupt sources of PWM_IDR1.\r
+ * \param sources2 Bitwise OR of selected interrupt sources of PWM_IDR2.\r
+ */\r
+void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)\r
+{\r
+ pPwm->PWM_IDR1 = sources1;\r
+ pPwm->PWM_IDR2 = sources2;\r
+}\r
+\r
+/**\r
+ * \brief Set PWM output override value.\r
+ *\r
+ * \param value Bitwise OR of output override value.\r
+ */\r
+void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value)\r
+{\r
+ pPwm->PWM_OOV = value;\r
+}\r
+\r
+/**\r
+ * \brief Enalbe override output.\r
+ *\r
+ * \param value Bitwise OR of output selection.\r
+ * \param sync 0: enable the output asyncronously, 1: enable it syncronously\r
+ */\r
+void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)\r
+{\r
+ if (sync) {\r
+\r
+ pPwm->PWM_OSSUPD = value;\r
+ } else {\r
+\r
+ pPwm->PWM_OSS = value;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Output Selection for override PWM output.\r
+ *\r
+ * \param value Bitwise OR of output override value.\r
+ */\r
+void PWMC_OutputOverrideSelection( Pwm* pPwm, uint32_t value )\r
+{\r
+ pPwm->PWM_OS = value;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disalbe override output.\r
+ *\r
+ * \param value Bitwise OR of output selection.\r
+ * \param sync 0: enable the output asyncronously, 1: enable it syncronously\r
+ */\r
+void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)\r
+{\r
+ if (sync) {\r
+\r
+ pPwm->PWM_OSCUPD = value;\r
+ } else {\r
+\r
+ pPwm->PWM_OSC = value;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set PWM fault mode.\r
+ *\r
+ * \param mode Bitwise OR of fault mode.\r
+ */\r
+void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode)\r
+{\r
+ pPwm->PWM_FMR = mode;\r
+}\r
+\r
+/**\r
+ * \brief PWM fault clear.\r
+ *\r
+ * \param fault Bitwise OR of fault to clear.\r
+ */\r
+void PWMC_FaultClear( Pwm* pPwm, uint32_t fault)\r
+{\r
+ pPwm->PWM_FCR = fault;\r
+}\r
+\r
+/**\r
+ * \brief Set PWM fault protection value.\r
+ *\r
+ * \param value Bitwise OR of fault protection value.\r
+ */\r
+void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value)\r
+{\r
+ pPwm->PWM_FPV1 = value;\r
+}\r
+\r
+/**\r
+ * \brief Enable PWM fault protection.\r
+ *\r
+ * \param value Bitwise OR of FPEx[y].\r
+ */\r
+void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value)\r
+{\r
+ pPwm->PWM_FPE = value;\r
+}\r
+\r
+/**\r
+ * \brief Configure comparison unit.\r
+ *\r
+ * \param x comparison x index\r
+ * \param value comparison x value.\r
+ * \param mode comparison x mode\r
+ */\r
+void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode)\r
+{\r
+ assert(x < 8);\r
+\r
+ /* If channel is disabled, write to CMPxM & CMPxV */\r
+ if ((pPwm->PWM_SR & (1 << 0)) == 0) {\r
+ pPwm->PWM_CMP[x].PWM_CMPM = mode;\r
+ pPwm->PWM_CMP[x].PWM_CMPV = value;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+ pPwm->PWM_CMP[x].PWM_CMPMUPD = mode;\r
+ pPwm->PWM_CMP[x].PWM_CMPVUPD = value;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure event line mode.\r
+ *\r
+ * \param x Line x\r
+ * \param mode Bitwise OR of line mode selection\r
+ */\r
+void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode)\r
+{\r
+ assert(x < 2);\r
+\r
+ if (x == 0) {\r
+ pPwm->PWM_ELMR[0] = mode;\r
+ } else if (x == 1) {\r
+ pPwm->PWM_ELMR[1] = mode;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup spi_module Working with QSPI\r
+ * \ingroup peripherals_module\r
+ * The QSPI driver provides the interface to configure and use the QSPI\r
+ * peripheral.\r
+ *\r
+ * The Serial Peripheral Interface (QSPI) circuit is a synchronous serial\r
+ * data link that provides communication with external devices in Master\r
+ * or Slave Mode.\r
+ *\r
+ * To use the QSPI, the user has to follow these few steps:\r
+ * -# Enable the QSPI pins required by the application (see pio.h).\r
+ * -# Configure the QSPI using the \ref QSPI_Configure(). This enables the\r
+ * peripheral clock. The mode register is loaded with the given value.\r
+ * -# Configure all the necessary chip selects with \ref QSPI_ConfigureNPCS().\r
+ * -# Enable the QSPI by calling \ref QSPI_Enable().\r
+ * -# Send/receive data using \ref QSPI_Write() and \ref QSPI_Read(). Note that \ref QSPI_Read()\r
+ * must be called after \ref QSPI_Write() to retrieve the last value read.\r
+ * -# Send/receive data using the PDC with the \ref QSPI_WriteBuffer() and\r
+ * \ref QSPI_ReadBuffer() functions.\r
+ * -# Disable the QSPI by calling \ref QSPI_Disable().\r
+ *\r
+ * For more accurate information, please look at the QSPI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref qspi.c\n\r
+ * \ref qspi.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Serial Peripheral Interface (QSPI) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "stdlib.h"\r
+#include "string.h" \r
+\r
+#include <stdint.h>\r
+\r
+\r
+\r
+volatile uint8_t INSTRE_Flag =0;\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables a QSPI peripheral.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ */\r
+extern void QSPI_Enable( Qspi* qspi )\r
+{\r
+ qspi->QSPI_CR = QSPI_CR_QSPIEN ;\r
+ while(!(qspi->QSPI_SR & QSPI_SR_QSPIENS));\r
+}\r
+\r
+/**\r
+ * \brief Disables a SPI peripheral.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ */\r
+extern void QSPI_Disable( Qspi* qspi )\r
+{\r
+ qspi->QSPI_CR = QSPI_CR_QSPIDIS ;\r
+}\r
+\r
+/**\r
+ * \brief Reset a QSPI peripheral.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ */\r
+extern void QSPI_SwReset( Qspi* qspi )\r
+{\r
+ qspi->QSPI_CR = QSPI_CR_SWRST ;\r
+ qspi->QSPI_CR = QSPI_CR_SWRST ;\r
+}\r
+\r
+/**\r
+ * \brief Enables one or more interrupt sources of a QSPI peripheral.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void QSPI_EnableIt( Qspi* qspi, uint32_t dwSources )\r
+{\r
+ qspi->QSPI_IER = dwSources ;\r
+}\r
+\r
+/**\r
+ * \brief Disables one or more interrupt sources of a QSPI peripheral.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void QSPI_DisableIt( Qspi* qspi, uint32_t dwSources )\r
+{\r
+ qspi->QSPI_IDR = dwSources ;\r
+}\r
+\r
+/**\r
+ * \brief Return the interrupt mask register.\r
+ *\r
+ * \return Qspi interrupt mask register.\r
+ */\r
+extern uint32_t QSPI_GetItMask( Qspi* qspi )\r
+{\r
+ return (qspi->QSPI_IMR) ;\r
+}\r
+\r
+/**\r
+ * \brief Configures a QSPI peripheral as specified. The configuration can be computed\r
+ * using several macros (see \ref spi_configuration_macros).\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ * \param id Peripheral ID of the QSPI.\r
+ * \param configuration Value of the QSPI configuration register.\r
+ */\r
+extern void QSPI_Configure( Qspi* qspi, uint32_t dwConfiguration )\r
+{\r
+ qspi->QSPI_CR = QSPI_CR_QSPIDIS ;\r
+\r
+ /* Execute a software reset of the QSPI twice */\r
+ QSPI_SwReset(qspi);\r
+ qspi->QSPI_MR = dwConfiguration ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configures a chip select of a QSPI peripheral. The chip select configuration\r
+ * is computed using several macros (see \ref spi_configuration_macros).\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ * \param npcs Chip select to configure (0, 1, 2 or 3).\r
+ * \param configuration Desired chip select configuration.\r
+ */\r
+void QSPI_ConfigureClock( Qspi* qspi,uint32_t dwConfiguration )\r
+{\r
+ qspi->QSPI_SCR = dwConfiguration ;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given QSPI peripheral.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param qspi Pointer to a Qspi instance.\r
+ * \return QSPI status register.\r
+ */\r
+extern uint32_t QSPI_GetStatus( Qspi* qspi )\r
+{\r
+ return qspi->QSPI_SR ;\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the last word of data received by a SPI peripheral. This\r
+ * method must be called after a successful SPI_Write call.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ *\r
+ * \return readed data.\r
+ */\r
+extern uint32_t QSPI_Read( Qspi* qspi )\r
+{\r
+ while ( (qspi->QSPI_SR & SPI_SR_RDRF) == 0 ) ;\r
+\r
+ return qspi->QSPI_RDR & 0xFFFF ;\r
+}\r
+\r
+/**\r
+ * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed\r
+ * peripheral select, the npcs value is meaningless. Otherwise, it identifies\r
+ * the component which shall be addressed.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param npcs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param data Word of data to send.\r
+ */\r
+extern void QSPI_Write( Qspi* qspi, uint16_t wData )\r
+{\r
+ /* Send data */\r
+ while ( (qspi->QSPI_SR & QSPI_SR_TXEMPTY) == 0 ) ;\r
+ qspi->QSPI_TDR = wData ;\r
+ while ( (qspi->QSPI_SR & QSPI_SR_TDRE) == 0 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Sends last data through a SPI peripheral.\r
+ * If the SPI is configured to use a fixed peripheral select, the npcs value is\r
+ * meaningless. Otherwise, it identifies the component which shall be addressed.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param npcs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param data Word of data to send.\r
+ */\r
+extern void QSPI_WriteLast( Qspi* qspi, uint16_t wData )\r
+{\r
+ /* Send data */\r
+ while ( (qspi->QSPI_SR & QSPI_SR_TXEMPTY) == 0 ) ;\r
+ qspi->QSPI_TDR = wData ;\r
+ qspi->QSPI_CR |= QSPI_CR_LASTXFER;\r
+ while ( (qspi->QSPI_SR & QSPI_SR_TDRE) == 0 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Enable QSPI Chip Select.\r
+ * \param qspi Pointer to a Qspi instance.\r
+ * \param cs QSPI chip select index.\r
+ */\r
+extern void QSPI_ConfigureCs( Qspi* qspi, uint8_t spiCs )\r
+{\r
+ uint32_t dwSpiMr;\r
+\r
+ /* Write to the MR register*/\r
+ dwSpiMr = qspi->QSPI_MR ;\r
+ dwSpiMr &= ~QSPI_MR_CSMODE_Msk ;\r
+ dwSpiMr |= spiCs;\r
+ qspi->QSPI_MR=dwSpiMr ;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Returns if data has been received. This\r
+ * method must be called after a successful QSPI_Write call.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return 1 if no data has been received else return return 0.\r
+ */\r
+extern int QSPI_RxEmpty(Qspi *qspi)\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_RDRF) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if application can write data. This\r
+ * method must be called before QSPI_Write call.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return 1 if application can write to the QSPI_TDR register else return return 0.\r
+ */\r
+extern int QSPI_TxRdy(Qspi *qspi)\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_TDRE) != 0);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Check if QSPI transfer finish.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if there is no pending write operation on the QSPI; otherwise\r
+ * returns 0.\r
+ */\r
+extern uint32_t QSPI_IsFinished( Qspi* qspi )\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_TXEMPTY) != 0) ;\r
+}\r
+\r
+/**\r
+ * \brief Check if QSPI Cs is asserted.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if tThe chip select is not asserted; otherwise\r
+ * returns 0.\r
+ */\r
+extern uint32_t QSPI_IsCsAsserted( Qspi* qspi )\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_CSS) != 0) ;\r
+}\r
+\r
+/**\r
+ * \brief Check if QSPI Cs is asserted.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if At least one chip select rise has been detected since the last read of QSPI_SR; otherwise\r
+ * returns 0.\r
+ */\r
+extern uint32_t QSPI_IsCsRise( Qspi* qspi )\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_CSR) != 0) ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Check if QSPI Cs is asserted.\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if At least one instruction end has been detected since the last read of QSPI_SR.; otherwise\r
+ * returns 0.\r
+ */\r
+extern uint32_t QSPI_IsEOFInst( Qspi* qspi )\r
+{\r
+ return ((qspi->QSPI_SR & QSPI_SR_INSTRE) != 0) ;\r
+}\r
+\r
+/**\r
+ * \brief Send instrucion over SPI or QSPI\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if At least one instruction end has been detected since the last read of QSPI_SR.; otherwise\r
+ * returns 0.\r
+ */\r
+extern void QSPI_SendFrame( Qspi* qspi, qspiFrame *pFrame, AccesType ReadWrite)\r
+{ \r
+ uint32_t regIFR, regICR, DummyRead;\r
+ uint32_t *pQspiBuffer = (uint32_t *)QSPIMEM_ADDR;\r
+\r
+ assert((qspi->QSPI_MR) & QSPI_MR_SMM);\r
+\r
+ regIFR = (pFrame->spiMode | QSPI_IFR_INSTEN | (pFrame->OptionLen << QSPI_IFR_OPTL_Pos) | (pFrame->DummyCycles << QSPI_IFR_NBDUM_Pos) | (pFrame->ContinuousRead << 14)) ;\r
+ // Write the instruction to reg\r
+ regICR = ( QSPI_ICR_OPT(pFrame->Option) | QSPI_ICR_INST(pFrame->Instruction));\r
+\r
+ if(pFrame->OptionEn)\r
+ {\r
+ regIFR|=QSPI_IFR_OPTEN;\r
+ }\r
+\r
+ /* Instruction frame without Data, only Instruction**/ \r
+ if(!(pFrame->DataSize)) \r
+ {\r
+ if(pFrame->InstAddrFlag) // If contain Address, put in IAr reg \r
+ {\r
+ qspi->QSPI_IAR = pFrame->InstAddr;\r
+ regIFR |= QSPI_IFR_ADDREN;\r
+ } \r
+ qspi->QSPI_ICR = regICR; // update Instruction code reg\r
+ qspi->QSPI_IFR = regIFR; // Instruction Frame reg \r
+ }\r
+ else /* Instruction frame with Data and Instruction**/\r
+ { \r
+ regIFR |= QSPI_IFR_DATAEN; \r
+ if(ReadWrite)\r
+ {\r
+ regIFR |= QSPI_IFR_TFRTYP_TRSFR_WRITE; \r
+ qspi->QSPI_ICR = regICR;\r
+ qspi->QSPI_IFR = regIFR ;\r
+ DummyRead = qspi->QSPI_IFR; // to synchronize system bus accesses \r
+ if(pFrame->InstAddrFlag)\r
+ {\r
+ pQspiBuffer += pFrame->InstAddr;\r
+ }\r
+ memcpy(pQspiBuffer ,pFrame->pData, pFrame->DataSize); \r
+ } \r
+ else\r
+ { \r
+ qspi->QSPI_ICR = regICR;\r
+ qspi->QSPI_IFR = regIFR ;\r
+ DummyRead = qspi->QSPI_IFR; // to synchronize system bus accesses \r
+ memcpy(pFrame->pData, pQspiBuffer, pFrame->DataSize); \r
+ }\r
+\r
+ }\r
+ memory_barrier();\r
+ qspi->QSPI_CR = QSPI_CR_LASTXFER; // End transmission after all data has been sent\r
+ while(!(qspi->QSPI_SR & QSPI_SR_INSTRE)); // poll CR reg to know status if Intrustion has end\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * \brief Send instrucion over SPI or QSPI\r
+ *\r
+ * \param qspi Pointer to an Qspi instance.\r
+ *\r
+ * \return Returns 1 if At least one instruction end has been detected since the last read of QSPI_SR.; otherwise\r
+ * returns 0.\r
+ */\r
+extern void QSPI_SendFrameToMem( Qspi* qspi, qspiFrame *pFrame, AccesType ReadWrite)\r
+{\r
+ uint32_t regIFR, regICR, DummyRead ;\r
+ uint8_t *pQspiMem = (uint8_t *)QSPIMEM_ADDR;\r
+\r
+ assert((qspi->QSPI_MR) & QSPI_MR_SMM); \r
+\r
+ regIFR = (pFrame->spiMode | QSPI_IFR_INSTEN | QSPI_IFR_DATAEN | QSPI_IFR_ADDREN | (pFrame->OptionLen << QSPI_IFR_OPTL_Pos) | (pFrame->DummyCycles << QSPI_IFR_NBDUM_Pos) | (pFrame->ContinuousRead << 14)) ;\r
+ // Write the instruction to reg\r
+ regICR = ( QSPI_ICR_OPT(pFrame->Option) | QSPI_ICR_INST(pFrame->Instruction));\r
+ if(pFrame->OptionEn)\r
+ {\r
+ regIFR|=QSPI_IFR_OPTEN;\r
+ }\r
+ pQspiMem += pFrame->InstAddr;\r
+ if(ReadWrite)\r
+ { \r
+ regIFR |= QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY;\r
+ memory_barrier();\r
+ qspi->QSPI_ICR = regICR;\r
+ qspi->QSPI_IFR = regIFR ;\r
+ DummyRead = qspi->QSPI_IFR; // to synchronize system bus accesses \r
+\r
+ memcpy(pQspiMem ,pFrame->pData, pFrame->DataSize); \r
+\r
+ }\r
+ else\r
+ {\r
+ regIFR |= QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY;\r
+ memory_barrier();\r
+ qspi->QSPI_ICR = regICR;\r
+ qspi->QSPI_IFR = regIFR ;\r
+ DummyRead = qspi->QSPI_IFR; // to synchronize system bus accesses \r
+ memcpy(pFrame->pData, pQspiMem , pFrame->DataSize); // Read QSPI AHB memory space \r
+\r
+ } \r
+ memory_barrier();\r
+ qspi->QSPI_CR = QSPI_CR_LASTXFER; // End transmission after all data has been sent\r
+ while(!(qspi->QSPI_SR & QSPI_SR_INSTRE)); // poll CR reg to know status if Intrustion has end\r
+\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \addtogroup spi_dma_module SPI xDMA driver\r
+ * \ingroup lib_spiflash\r
+ * \section Usage\r
+ *\r
+ * <ul>\r
+ * <li> QSPID_Configure() initializes and configures the SPI peripheral and xDMA for data transfer.</li>\r
+ * <li> Configures the parameters for the device corresponding to the cs value by QSPID_ConfigureCS(). </li>\r
+ * <li> Starts a SPI master transfer. This is a non blocking function QSPID_SendCommand(). It will\r
+ * return as soon as the transfer is started..</li>\r
+ * </ul>\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the SPI Flash with xDMA driver.\r
+ *\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** xDMA support */\r
+#define USE_QSPI_DMA\r
+\r
+#define TX_MICROBLOCK_LEN 256\r
+#define RX_MICROBLOCK_LEN 256\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/* DMA driver instance */\r
+static uint32_t qspiDmaTxChannel;\r
+static uint32_t qspiDmaRxChannel;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief SPI xDMA Rx callback\r
+ * Invoked on SPi DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to Qspid instance. \r
+ */ \r
+static void QSPID_Rx_Cb(uint32_t channel, Qspid* pArg)\r
+{\r
+ QspidCmd *pQspidCmd = pArg->pCurrentCommand;\r
+ Qspi *pQspiHw = pArg->pQspiHw;\r
+ if (channel != qspiDmaRxChannel)\r
+ return;\r
+\r
+ /* Disable the SPI TX & RX */\r
+ QSPI_Disable ( pQspiHw );\r
+\r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_DisableIRQ(XDMAC_IRQn);\r
+\r
+ /* Disable the SPI Peripheral */\r
+ PMC_DisablePeripheral ( pArg->spiId );\r
+\r
+ /* Release CS */\r
+ QSPI_ReleaseCS(pQspiHw);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, qspiDmaRxChannel);\r
+ XDMAD_FreeChannel(pArg->pXdmad, qspiDmaTxChannel);\r
+\r
+ /* Release the dataflash semaphore */\r
+ pArg->semaphore++;\r
+\r
+ printf("\n\r%s\n\r",pArg->pCurrentCommand->pRxBuff);\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pQspidCmd && pQspidCmd->callback) {\r
+ //printf("p %d", pArg->semaphore);\r
+ pQspidCmd->callback(0, pQspidCmd->pArgument);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA Channels: 0 RX, 1 TX.\r
+ * Channels are disabled after configure.\r
+ * \returns 0 if the dma channel configuration successfully; otherwise returns\r
+ * QSPID_ERROR_XXX.\r
+ */\r
+static uint8_t _qspid_configureDmaChannels( Qspid* pQspid )\r
+{\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pQspid->pXdmad, 0 );\r
+\r
+ XDMAD_FreeChannel( pQspid->pXdmad, qspiDmaTxChannel);\r
+ XDMAD_FreeChannel( pQspid->pXdmad, qspiDmaRxChannel);\r
+\r
+ /* Allocate a DMA channel for SPI0/1 TX. */\r
+ qspiDmaTxChannel = XDMAD_AllocateChannel( pQspid->pXdmad, XDMAD_TRANSFER_MEMORY, pQspid->spiId);\r
+ {\r
+ if ( qspiDmaTxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return QSPID_ERROR;\r
+ }\r
+ }\r
+ /* Allocate a DMA channel for SPI0/1 RX. */\r
+ qspiDmaRxChannel = XDMAD_AllocateChannel( pQspid->pXdmad, pQspid->spiId, XDMAD_TRANSFER_MEMORY);\r
+ {\r
+ if ( qspiDmaRxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return QSPID_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Setup callbacks for SPI0/1 RX */\r
+ XDMAD_SetCallback(pQspid->pXdmad, qspiDmaRxChannel, (XdmadTransferCallback)QSPID_Rx_Cb, pQspid);\r
+ if (XDMAD_PrepareChannel( pQspid->pXdmad, qspiDmaRxChannel ))\r
+ return QSPID_ERROR;\r
+\r
+ /* Setup callbacks for SPI0/1 TX (ignored) */\r
+ XDMAD_SetCallback(pQspid->pXdmad, qspiDmaTxChannel, NULL, NULL);\r
+ if ( XDMAD_PrepareChannel( pQspid->pXdmad, qspiDmaTxChannel ))\r
+ return QSPID_ERROR;\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA source and destination with Linker List mode.\r
+ *\r
+ * \param pCommand Pointer to command\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * QSPID_ERROR_XXX.\r
+ */\r
+static uint8_t _spid_configureLinkList(Qspi *pQspiHw, void *pXdmad, QspidCmd *pCommand)\r
+{\r
+ sXdmadCfg xdmadRxCfg,xdmadTxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t qspiId;\r
+ if ((unsigned int)pQspiHw == (unsigned int)QSPI ) qspiId = ID_QSPI;\r
+\r
+\r
+\r
+ /* Setup TX */ \r
+\r
+ xdmadTxCfg.mbr_ubc = TX_MICROBLOCK_LEN;\r
+ xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff;\r
+ xdmadTxCfg.mbr_da = (uint32_t)QSPIMEM_ADDR;\r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_MEMSET_NORMAL_MODE |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( qspiId, XDMAD_TRANSFER_TX ));\r
+\r
+ xdmadTxCfg.mbr_bc = 0;\r
+ xdmadTxCfg.mbr_ds = 0;\r
+ xdmadTxCfg.mbr_sus = 0;\r
+ xdmadTxCfg.mbr_dus = 0; \r
+\r
+\r
+ /* Setup RX Link List */\r
+\r
+ xdmadRxCfg.mbr_ubc = RX_MICROBLOCK_LEN;\r
+ xdmadRxCfg.mbr_sa = (uint32_t)QSPIMEM_ADDR;\r
+ xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_MEMSET_NORMAL_MODE |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( qspiId, XDMAD_TRANSFER_RX ));\r
+\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ xdmadRxCfg.mbr_ds = 0;\r
+ xdmadRxCfg.mbr_sus = 0;\r
+ xdmadRxCfg.mbr_dus = 0; \r
+\r
+\r
+ if (XDMAD_ConfigureTransfer( pXdmad, qspiDmaRxChannel, &xdmadRxCfg, 0, 0))\r
+ return QSPID_ERROR;\r
+\r
+ if (XDMAD_ConfigureTransfer( pXdmad, qspiDmaTxChannel, &xdmadTxCfg, 0, 0))\r
+ return QSPID_ERROR;\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initializes the Qspid structure and the corresponding SPI & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no SPI command processing.\r
+ *\r
+ * \param pQspid Pointer to a Qspid instance.\r
+ * \param pQspiHw Associated SPI peripheral.\r
+ * \param spiId SPI peripheral identifier.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t QSPID_Configure( Qspid *pQspid ,\r
+ Qspi *pQspiHw , \r
+ uint8_t spiId,\r
+ uint8_t QspiMode,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the SPI structure */\r
+ pQspid->pQspiHw = pQspiHw;\r
+ pQspid->spiId = spiId;\r
+ pQspid->semaphore = 1;\r
+ pQspid->pCurrentCommand = 0;\r
+ pQspid->pXdmad = pXdmad;\r
+\r
+ /* Enable the SPI Peripheral ,Execute a software reset of the SPI, Configure SPI in Master Mode*/\r
+ QSPI_Configure ( pQspiHw, pQspid->spiId, QspiMode );\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Starts a SPI master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pQspid Pointer to a Qspid instance.\r
+ * \param pCommand Pointer to the SPI command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * QQSPID_ERROR_LOCK is the driver is in use, or QQSPID_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t QSPID_SendCommand( Qspid *pQspid, QspidCmd *pCommand)\r
+{\r
+ Qspi *pQspiHw = pQspid->pQspiHw;\r
+\r
+ /* Try to get the dataflash semaphore */\r
+ if (pQspid->semaphore == 0) {\r
+\r
+ return QQSPID_ERROR_LOCK;\r
+ }\r
+ pQspid->semaphore--;\r
+\r
+ /* Enable the SPI Peripheral */\r
+ PMC_EnablePeripheral (pQspid->spiId );\r
+\r
+ /* SPI chip select */\r
+ SPI_ChipSelect (pQspiHw, 1 << pCommand->spiCs);\r
+\r
+ // Initialize the callback\r
+ pQspid->pCurrentCommand = pCommand;\r
+\r
+ /* Initialize DMA controller using channel 0 for RX, 1 for TX. */\r
+ if (_spid_configureDmaChannels(pQspid) )\r
+ return QQSPID_ERROR_LOCK;\r
+\r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_SetPriority( XDMAC_IRQn ,1);\r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+\r
+ if (_spid_configureLinkList(pQspiHw, pQspid->pXdmad, pCommand))\r
+ return QSPID_ERROR_LOCK;\r
+\r
+ /* Enables the SPI to transfer and receive data. */\r
+ SPI_Enable (pQspiHw );\r
+\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ if (XDMAD_StartTransfer( pQspid->pXdmad, qspiDmaRxChannel )) \r
+ return QSPID_ERROR_LOCK;\r
+ if (XDMAD_StartTransfer( pQspid->pXdmad, qspiDmaTxChannel )) \r
+ return QSPID_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if the SPI driver is busy.\r
+ *\r
+ * \param pQspid Pointer to a Qspid instance.\r
+ * \returns 1 if the SPI driver is currently busy executing a command; otherwise\r
+ */\r
+uint32_t QSPID_IsBusy(const Qspid *pQspid)\r
+{\r
+ if (pQspid->semaphore == 0) {\r
+ return 1;\r
+ }\r
+ else {\r
+ return 0;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include <chip.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Defines\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/** Keywords to write to the reset registers */\r
+#define RSTC_KEY_PASSWORD RSTC_MR_KEY(0xA5U)\r
+\r
+#define RSTC_MR_URSTEN (1ul )\r
+#define RSTC_MR_URSTIEN (1ul << 4)\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Configure the mode of the RSTC peripheral.\r
+ * The configuration is computed by the lib (RSTC_RMR_*).\r
+ * \param mr Desired mode configuration.\r
+ */\r
+void RSTC_ConfigureMode(uint32_t mr)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ mr &= ~RSTC_MR_KEY_Msk;\r
+ pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Enable/Disable the detection of a low level on the pin NRST as User Reset\r
+ * \param enable 1 to enable & 0 to disable.\r
+ */\r
+void RSTC_SetUserResetEnable(uint8_t enable)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk);\r
+ if (enable)\r
+ {\r
+ mr |= RSTC_MR_URSTEN;\r
+ }\r
+ else\r
+ {\r
+ mr &= ~RSTC_MR_URSTEN;\r
+ }\r
+ pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).\r
+ * \param enable 1 to enable & 0 to disable.\r
+ */\r
+void RSTC_SetUserResetInterruptEnable(uint8_t enable)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk);\r
+ if (enable)\r
+ {\r
+ mr |= RSTC_MR_URSTIEN;\r
+ }\r
+ else {\r
+\r
+ mr &= ~RSTC_MR_URSTIEN;\r
+ }\r
+ pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Setup the external reset length. The length is asserted during a time of\r
+ * pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.\r
+ * \param powl Power length defined.\r
+ */\r
+void RSTC_SetExtResetLength(uint8_t powl)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ uint32_t mr = pHw->RSTC_MR;\r
+ mr &= ~(RSTC_MR_KEY_Msk | RSTC_MR_ERSTL_Msk);\r
+ mr |= RSTC_MR_ERSTL(powl);\r
+ pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+\r
+/**\r
+ * Resets the processor.\r
+ */\r
+void RSTC_ProcessorReset(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ pHw->RSTC_CR = RSTC_CR_PROCRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Resets the peripherals.\r
+ */\r
+void RSTC_PeripheralReset(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ pHw->RSTC_CR = RSTC_CR_PERRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Asserts the NRST pin for external resets.\r
+ */\r
+void RSTC_ExtReset(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ pHw->RSTC_CR = RSTC_CR_EXTRST | RSTC_KEY_PASSWORD;\r
+}\r
+\r
+/**\r
+ * Return NRST pin level ( 1 or 0 ).\r
+ */\r
+uint8_t RSTC_GetNrstLevel(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ return ((pHw->RSTC_SR & RSTC_SR_NRSTL) > 0);\r
+}\r
+\r
+/**\r
+ * Returns 1 if at least one high-to-low transition of NRST (User Reset) has\r
+ * been detected since the last read of RSTC_RSR.\r
+ */\r
+uint8_t RSTC_IsUserResetDetected(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ if (pHw->RSTC_SR & RSTC_SR_URSTS)\r
+ {\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Return 1 if a software reset command is being performed by the reset\r
+ * controller. The reset controller is busy.\r
+ */\r
+uint8_t RSTC_IsBusy(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ if (pHw->RSTC_SR & RSTC_SR_SRCMP)\r
+ {\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Get the status\r
+ */\r
+uint32_t RSTC_GetStatus(void)\r
+{\r
+ Rstc *pHw = RSTC;\r
+ return (pHw->RSTC_SR);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup rtc_module Working with RTC\r
+ * \ingroup peripherals_module\r
+ * The RTC driver provides the interface to configure and use the RTC\r
+ * peripheral.\r
+ *\r
+ * It manages date, time, and alarms.\n\r
+ * This timer is clocked by the 32kHz system clock, and is not impacted by\r
+ * power management settings (PMC). To be accurate, it is better to use an\r
+ * external 32kHz crystal instead of the internal 32kHz RC.\n\r
+ *\r
+ * It uses BCD format, and time can be set in AM/PM or 24h mode through a\r
+ * configuration bit in the mode register.\n\r
+ *\r
+ * To update date or time, the user has to follow these few steps :\r
+ * <ul>\r
+ * <li>Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,</li>\r
+ * <li>Polling or IRQ on the ACKUPD bit of RTC_CR,</li>\r
+ * <li>Clear ACKUPD bit in RTC_SCCR,</li>\r
+ * <li>Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),</li>\r
+ * <li>Clear UPDTIM and/or UPDCAL bit in RTC_CR.</li>\r
+ * </ul>\r
+ * An alarm can be set to happen on month, date, hours, minutes or seconds,\r
+ * by setting the proper "Enable" bit of each of these fields in the Time and\r
+ * Calendar registers.\r
+ * This allows a large number of configurations to be available for the user.\r
+ * Alarm occurence can be detected even by polling or interrupt.\r
+ *\r
+ * A check of the validity of the date and time format and values written by the user is automatically done.\r
+ * Errors are reported through the Valid Entry Register.\r
+ *\r
+ * For more accurate information, please look at the RTC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref rtc.c\n\r
+ * \ref rtc.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Real Time Clock (RTC) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Sets the RTC in either 12 or 24 hour mode.\r
+ *\r
+ * \param mode Hour mode.\r
+ */\r
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode )\r
+{\r
+ assert((dwMode & 0xFFFFFFFE) == 0);\r
+\r
+ pRtc->RTC_MR = dwMode ;\r
+}\r
+\r
+/**\r
+ * \brief Gets the RTC mode.\r
+ *\r
+ * \return Hour mode.\r
+ */\r
+extern uint32_t RTC_GetHourMode( Rtc* pRtc )\r
+{\r
+ uint32_t dwMode ;\r
+\r
+ TRACE_DEBUG( "RTC_SetHourMode()\n\r" ) ;\r
+\r
+ dwMode = pRtc->RTC_MR;\r
+ dwMode &= 0xFFFFFFFE;\r
+\r
+ return dwMode ;\r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupt sources of the RTC.\r
+ *\r
+ * \param sources Interrupt sources to enable.\r
+ */\r
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources )\r
+{\r
+ assert((dwSources & (uint32_t)(~0x1F)) == 0);\r
+\r
+ TRACE_DEBUG( "RTC_EnableIt()\n\r" ) ;\r
+\r
+ pRtc->RTC_IER = dwSources ;\r
+}\r
+\r
+/**\r
+* \brief Disables the selected interrupt sources of the RTC.\r
+*\r
+* \param sources Interrupt sources to disable.\r
+*/\r
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources )\r
+{\r
+ assert((dwSources & (uint32_t)(~0x1F)) == 0);\r
+\r
+ TRACE_DEBUG( "RTC_DisableIt()\n\r" ) ;\r
+\r
+ pRtc->RTC_IDR = dwSources ;\r
+}\r
+\r
+/**\r
+ * \brief Sets the current time in the RTC.\r
+ *\r
+ * \note In successive update operations, the user must wait at least one second\r
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these\r
+ * bits again. Please look at the RTC section of the datasheet for detail.\r
+ *\r
+ * \param ucHour Current hour in 12 or 24 hour mode.\r
+ * \param ucMinute Current minute.\r
+ * \param ucSecond Current second.\r
+ *\r
+ * \return 0 sucess, 1 fail to set\r
+ */\r
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond )\r
+{\r
+ uint32_t dwTime=0 ;\r
+ uint8_t ucHour_bcd ;\r
+ uint8_t ucMin_bcd ;\r
+ uint8_t ucSec_bcd ;\r
+\r
+ TRACE_DEBUG( "RTC_SetTime(%02d:%02d:%02d)\n\r", ucHour, ucMinute, ucSecond ) ;\r
+\r
+ /* if 12-hour mode, set AMPM bit */\r
+ if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD )\r
+ {\r
+ if ( ucHour > 12 )\r
+ {\r
+ ucHour -= 12 ;\r
+ dwTime |= RTC_TIMR_AMPM ;\r
+ }\r
+ }\r
+ ucHour_bcd = (ucHour%10) | ((ucHour/10)<<4) ;\r
+ ucMin_bcd = (ucMinute%10) | ((ucMinute/10)<<4) ;\r
+ ucSec_bcd = (ucSecond%10) | ((ucSecond/10)<<4) ;\r
+\r
+ /* value overflow */\r
+ if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) |\r
+ (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) |\r
+ (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK)))\r
+ {\r
+ return 1 ;\r
+ }\r
+\r
+ dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ;\r
+\r
+ pRtc->RTC_CR |= RTC_CR_UPDTIM ;\r
+ while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;\r
+ pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ;\r
+ pRtc->RTC_TIMR = dwTime ;\r
+ pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;\r
+ pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ;\r
+\r
+ return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ;\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current time as stored in the RTC in several variables.\r
+ *\r
+ * \param pucHour If not null, current hour is stored in this variable.\r
+ * \param pucMinute If not null, current minute is stored in this variable.\r
+ * \param pucSecond If not null, current second is stored in this variable.\r
+ */\r
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )\r
+{\r
+ uint32_t dwTime ;\r
+\r
+ TRACE_DEBUG( "RTC_GetTime()\n\r" ) ;\r
+\r
+ /* Get current RTC time */\r
+ dwTime = pRtc->RTC_TIMR ;\r
+ while ( dwTime != pRtc->RTC_TIMR )\r
+ {\r
+ dwTime = pRtc->RTC_TIMR ;\r
+ }\r
+\r
+ /* Hour */\r
+ if ( pucHour )\r
+ {\r
+ *pucHour = ((dwTime & 0x00300000) >> 20) * 10\r
+ + ((dwTime & 0x000F0000) >> 16);\r
+\r
+ if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM )\r
+ {\r
+ *pucHour += 12 ;\r
+ }\r
+ }\r
+\r
+ /* Minute */\r
+ if ( pucMinute )\r
+ {\r
+ *pucMinute = ((dwTime & 0x00007000) >> 12) * 10\r
+ + ((dwTime & 0x00000F00) >> 8);\r
+ }\r
+\r
+ /* Second */\r
+ if ( pucSecond )\r
+ {\r
+ *pucSecond = ((dwTime & 0x00000070) >> 4) * 10\r
+ + (dwTime & 0x0000000F);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets a time alarm on the RTC.\r
+ * The match is performed only on the provided variables;\r
+ * Setting all pointers to 0 disables the time alarm.\r
+ *\r
+ * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for\r
+ * AM (as expected in the time registers).\r
+ *\r
+ * \param pucHour If not null, the time alarm will hour-match this value.\r
+ * \param pucMinute If not null, the time alarm will minute-match this value.\r
+ * \param pucSecond If not null, the time alarm will second-match this value.\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )\r
+{\r
+ uint32_t dwAlarm=0 ;\r
+\r
+ TRACE_DEBUG( "RTC_SetTimeAlarm()\n\r" ) ;\r
+\r
+ /* Hour */\r
+ if ( pucHour )\r
+ {\r
+ dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16);\r
+ }\r
+\r
+ /* Minute */\r
+ if ( pucMinute )\r
+ {\r
+ dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) | ((*pucMinute % 10) << 8);\r
+ }\r
+\r
+ /* Second */\r
+ if ( pucSecond )\r
+ {\r
+ dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10);\r
+ }\r
+\r
+ pRtc->RTC_TIMALR = dwAlarm ;\r
+\r
+ return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ;\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current year, month and day from the RTC.\r
+ * Month, day and week values are numbered starting at 1.\r
+ *\r
+ * \param pYwear Current year (optional).\r
+ * \param pucMonth Current month (optional).\r
+ * \param pucDay Current day (optional).\r
+ * \param pucWeek Current day in current week (optional).\r
+ */\r
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek )\r
+{\r
+ uint32_t dwDate ;\r
+\r
+ /* Get current date (multiple reads are necessary to insure a stable value) */\r
+ do\r
+ {\r
+ dwDate = pRtc->RTC_CALR ;\r
+ }\r
+ while ( dwDate != pRtc->RTC_CALR ) ;\r
+\r
+ /* Retrieve year */\r
+ if ( pwYear )\r
+ {\r
+ *pwYear = (((dwDate >> 4) & 0x7) * 1000)\r
+ + ((dwDate & 0xF) * 100)\r
+ + (((dwDate >> 12) & 0xF) * 10)\r
+ + ((dwDate >> 8) & 0xF);\r
+ }\r
+\r
+ /* Retrieve month */\r
+ if ( pucMonth )\r
+ {\r
+ *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF);\r
+ }\r
+\r
+ /* Retrieve day */\r
+ if ( pucDay )\r
+ {\r
+ *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF);\r
+ }\r
+\r
+ /* Retrieve week */\r
+ if ( pucWeek )\r
+ {\r
+ *pucWeek = ((dwDate >> 21) & 0x7);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets the current year, month and day in the RTC.\r
+ * Month, day and week values must be numbered starting from 1.\r
+ *\r
+ * \note In successive update operations, the user must wait at least one second\r
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these\r
+ * bits again. Please look at the RTC section of the datasheet for detail.\r
+ *\r
+ * \param wYear Current year.\r
+ * \param ucMonth Current month.\r
+ * \param ucDay Current day.\r
+ * \param ucWeek Day number in current week.\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek )\r
+{\r
+ uint32_t wDate ;\r
+ uint8_t ucCent_bcd ;\r
+ uint8_t ucYear_bcd ;\r
+ uint8_t ucMonth_bcd ;\r
+ uint8_t ucDay_bcd ;\r
+ uint8_t ucWeek_bcd ;\r
+\r
+ ucCent_bcd = ((wYear/100)%10) | ((wYear/1000)<<4);\r
+ ucYear_bcd = (wYear%10) | (((wYear/10)%10)<<4);\r
+ ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4);\r
+ ucDay_bcd = ((ucDay%10) | (ucDay/10)<<4);\r
+ ucWeek_bcd = ((ucWeek%10) | (ucWeek/10)<<4);\r
+\r
+ /* value over flow */\r
+ if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) |\r
+ (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) |\r
+ (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) |\r
+ (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) |\r
+ (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))\r
+ )\r
+ {\r
+ return 1 ;\r
+ }\r
+\r
+\r
+ /* Convert values to date register value */\r
+ wDate = ucCent_bcd |\r
+ (ucYear_bcd << 8) |\r
+ (ucMonth_bcd << 16) |\r
+ (ucWeek_bcd << 21) |\r
+ (ucDay_bcd << 24);\r
+\r
+ /* Update calendar register */\r
+ pRtc->RTC_CR |= RTC_CR_UPDCAL ;\r
+ while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;\r
+\r
+ pRtc->RTC_SCCR = RTC_SCCR_ACKCLR;\r
+ pRtc->RTC_CALR = wDate ;\r
+ pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;\r
+ pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */\r
+\r
+ return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ;\r
+}\r
+\r
+/**\r
+ * \brief Sets a date alarm in the RTC.\r
+ * The alarm will match only the provided values;\r
+ * Passing a null-pointer disables the corresponding field match.\r
+ *\r
+ * \param pucMonth If not null, the RTC alarm will month-match this value.\r
+ * \param pucDay If not null, the RTC alarm will day-match this value.\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay )\r
+{\r
+ uint32_t dwAlarm ;\r
+\r
+ dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000);\r
+\r
+ TRACE_DEBUG( "RTC_SetDateAlarm()\n\r" ) ;\r
+\r
+ /* Compute alarm field value */\r
+ if ( pucMonth )\r
+ {\r
+ dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) | ((*pucMonth % 10) << 16);\r
+ }\r
+\r
+ if ( pucDay )\r
+ {\r
+ dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) | ((*pucDay % 10) << 24);\r
+ }\r
+\r
+ /* Set alarm */\r
+ pRtc->RTC_CALALR = dwAlarm ;\r
+\r
+ return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ;\r
+}\r
+\r
+/**\r
+ * \brief Clear flag bits of status clear command register in the RTC.\r
+ *\r
+ * \param mask Bits mask of cleared events\r
+ */\r
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask )\r
+{\r
+ /* Clear all flag bits in status clear command register */\r
+ dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ;\r
+\r
+ pRtc->RTC_SCCR = dwMask ;\r
+}\r
+\r
+/**\r
+ * \brief Get flag bits of status register in the RTC.\r
+ *\r
+ * \param mask Bits mask of Status Register\r
+ *\r
+ * \return Status register & mask\r
+ */\r
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask )\r
+{\r
+ uint32_t dwEvent ;\r
+\r
+ dwEvent = pRtc->RTC_SR ;\r
+\r
+ return (dwEvent & dwMask) ;\r
+}\r
+\r
+#if defined(sam3s8) || defined(sam3sd8)\r
+/**\r
+ * \brief Select a output source in the RTC.\r
+ *\r
+ * \param dwWaveMode is the RTC output source selection value.\r
+ */\r
+extern void RTC_SetWaveForm( Rtc* pRtc, uint32_t dwWaveMode )\r
+{\r
+ uint32_t dwRtcMode;\r
+\r
+ dwRtcMode = pRtc->RTC_MR & (~RTC_MR_OUT1_Msk);\r
+ pRtc->RTC_MR = dwRtcMode | dwWaveMode;\r
+}\r
+#endif\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup rtt_module Working with RTT\r
+ * \ingroup peripherals_module\r
+ * The RTT driver provides the interface to configure and use the RTT\r
+ * peripheral.\r
+ *\r
+ * The Real-time Timer is used to count elapsed seconds.\n\r
+ * This timer is clocked by the 32kHz system clock divided by a programmable\r
+ * 16-bit balue. To be accurate, it is better to use an\r
+ * external 32kHz crystal instead of the internal 32kHz RC.\n\r
+ *\r
+ * To count elapsed seconds, the user could follow these few steps:\r
+ * <ul>\r
+ * <li>Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.</li>\r
+ * <li>Writing the bit RTTRST in RTT_MR to restart the timer with new settings.</li>\r
+ * </ul>\r
+ *\r
+ * An alarm can be set to happen on second by setting alarm value in RTT_AR.\r
+ * Alarm occurence can be detected by polling or interrupt.\r
+ *\r
+ * For more accurate information, please look at the RTT section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref rtt.c\n\r
+ * \ref rtt.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Real Time Timer (RTT) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Changes the prescaler value of the given RTT and restarts it.\r
+ *\r
+ * \note This function disables RTT interrupt sources.\r
+ *\r
+ * \param rtt Pointer to a Rtt instance.\r
+ * \param prescaler Prescaler value for the RTT.\r
+ */\r
+void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler)\r
+{\r
+ rtt->RTT_MR = (prescaler | RTT_MR_RTTRST);\r
+}\r
+\r
+/**\r
+ * \brief Returns the current value of the RTT timer value.\r
+ *\r
+ * \param rtt Pointer to a Rtt instance.\r
+ */\r
+uint32_t RTT_GetTime(Rtt *rtt)\r
+{\r
+ return rtt->RTT_VR;\r
+}\r
+\r
+/**\r
+ * \brief Enables the specified RTT interrupt sources.\r
+ *\r
+ * \param rtt Pointer to a Rtt instance.\r
+ * \param sources Bitmask of interrupts to enable.\r
+ */\r
+void RTT_EnableIT(Rtt *rtt, uint32_t sources)\r
+{\r
+ assert( (sources & 0x0004FFFF) == 0 ) ;\r
+ rtt->RTT_MR |= sources;\r
+}\r
+\r
+/**\r
+ * \brief Returns the status register value of the given RTT.\r
+ *\r
+ * \param rtt Pointer to an Rtt instance.\r
+ */\r
+uint32_t RTT_GetStatus(Rtt *rtt)\r
+{\r
+ return rtt->RTT_SR;\r
+}\r
+\r
+/**\r
+ * \brief Configures the RTT to generate an alarm at the given time.\r
+ *\r
+ * \param pRtt Pointer to an Rtt instance.\r
+ * \param time Alarm time.\r
+ */\r
+void RTT_SetAlarm(Rtt *pRtt, uint32_t time)\r
+{\r
+ assert(time > 0);\r
+\r
+ pRtt->RTT_AR = time - 1;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of memories configuration on board.\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+* Headers\r
+*----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+* Local functions\r
+*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Calculate the sdram controller config register value.\r
+ * \param pMemory Pointer to the sdram structure.\r
+ * \return Configure register value.\r
+ */\r
+static uint32_t SDRAMC_compute_CR_value( SSdramc_Memory* pMemory )\r
+{\r
+ uint32_t dw=0 ;\r
+\r
+ dw |= pMemory->cfg.dwColumnBits ;\r
+ dw |= pMemory->cfg.dwRowBits ;\r
+ dw |= pMemory->cfg.dwBanks ; //NB, number of banks\r
+ dw |= pMemory->cfg.dwCAS ; //CAS, CAS latency\r
+ dw |= pMemory->cfg.dwDataBusWidth ; //DBW, data bus width\r
+ dw |= SDRAMC_CR_TWR( pMemory->cfg.dwWriteRecoveryDelay ) ; //TWR, Write Recovery Delay\r
+ dw |= SDRAMC_CR_TRC_TRFC( pMemory->cfg.dwRowCycleDelay_RowRefreshCycle ) ; //TRC_TRFC,Row Cycle Delay and Row Refresh Cycle\r
+ dw |= SDRAMC_CR_TRP( pMemory->cfg.dwRowPrechargeDelay ) ; //TRP, Row Precharge Delay\r
+ dw |= SDRAMC_CR_TRCD( pMemory->cfg.dwRowColumnDelay ) ; //TRCD, Row to Column Delay\r
+ dw |= SDRAMC_CR_TRAS( pMemory->cfg.dwActivePrechargeDelay ) ; //TRAS, Active to Precharge Delay\r
+ dw |= SDRAMC_CR_TXSR( pMemory->cfg.dwExitSelfRefreshActiveDelay ) ; //TXSR, Exit Self Refresh to Active Delay\r
+\r
+ return dw ;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+* Exported functions\r
+*----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Configure and initialize the SDRAM controller.\r
+ * \param pMemory Pointer to the sdram structure.\r
+ * \param dwClockFrequency SDRAM clock frequency.\r
+ */\r
+extern void SDRAMC_Configure( SSdramc_Memory* pMemory, uint32_t dwClockFrequency )\r
+{\r
+ volatile uint32_t dw ;\r
+\r
+ /* SDRAM hardware init */\r
+ /* Enable peripheral clock */\r
+ PMC_EnablePeripheral( ID_SMC ) ;\r
+\r
+ /* SDRAM device configure */\r
+ /* Step 1. */\r
+ /* Program the features of SDRAM device into the Configuration Register.*/\r
+ SDRAMC->SDRAMC_CR = SDRAMC_compute_CR_value( pMemory ) ;\r
+\r
+ /* Step 2. */\r
+ /* For low-power SDRAM, temperature-compensated self refresh (TCSR),\r
+ drive strength (DS) and partial array self refresh (PASR) must be set\r
+ in the Low-power Register.*/\r
+ SDRAMC->SDRAMC_LPR = 0;\r
+\r
+ /* Step 3. */\r
+ /* Program the memory device type into the Memory Device Register */\r
+ SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;\r
+\r
+ /* Step 4 */\r
+ /* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.\r
+ (6 core cycles per iteration) */\r
+ for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ )\r
+ {\r
+ ;\r
+ }\r
+\r
+ /* Step 5. */\r
+ /* A NOP command is issued to the SDR-SDRAM. Program NOP command into\r
+ Mode Register, the application must set Mode to 1 in the Mode Register.\r
+ Perform a write access to any SDR-SDRAM address to acknowledge this command.\r
+ Now the clock which drives SDR-SDRAM device is enabled.*/\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR) = 0;\r
+\r
+ /* Step 6. */\r
+ /* An all banks precharge command is issued to the SDR-SDRAM. Program all\r
+ banks precharge command into Mode Register, the application must set Mode to\r
+ 2 in the Mode Register . Perform a write access to any SDRSDRAM address to\r
+ acknowledge this command. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0;\r
+\r
+ /* add some delays after precharge */\r
+ for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ )\r
+ {\r
+ ;\r
+ }\r
+\r
+ /* Step 7. */\r
+ /* Eight auto-refresh (CBR) cycles are provided. Program the auto refresh\r
+ command (CBR) into Mode Register, the application must set Mode to 4 in\r
+ the Mode Register. Once in the idle state, eight AUTO REFRESH cycles must\r
+ be performed. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x1;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x2;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x3;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x4;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x5;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x6;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x7;\r
+\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x8;\r
+\r
+ /* Step 8. */\r
+ /* A Mode Register set (MRS) cycle is issued to program the parameters of\r
+ the SDRAM devices, in particular CAS latency and burst length. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR + 0x22) = 0xcafe;\r
+\r
+ /* Step 9. */\r
+ /* For low-power SDR-SDRAM initialization, an Extended Mode Register set\r
+ (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS).\r
+ The write address must be chosen so that BA[1] is set to 1 and BA[0] is set\r
+ to 0 */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;\r
+ *((uint16_t *)(EBI_SDRAMC_ADDR + (1 << pMemory->cfg.dwBK1))) = 0;\r
+\r
+ /* Step 10. */\r
+ /* The application must go into Normal Mode, setting Mode to 0 in the Mode\r
+ Register and perform a write access at any location in the SDRAM to\r
+ acknowledge this command. */\r
+ SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;\r
+ *(uint16_t *)(EBI_SDRAMC_ADDR ) = 0x0;\r
+\r
+ /* Step 11. */\r
+ /* Write the refresh rate into the count field in the SDRAMC Refresh\r
+ Timer register. Set Refresh timer 15.625 us*/\r
+ dw=dwClockFrequency/1000u ;\r
+ dw*=15625u ;\r
+ dw/=1000000u ;\r
+ SDRAMC->SDRAMC_TR = SDRAMC_TR_COUNT( dw ) ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2010, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of NFC functions.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+static SmcStatus smcStatus;\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Counts and return the number of bits set to '1' in the given hsiao code.\r
+ * \param code Hsizo code.\r
+ */\r
+static unsigned char CountBitsInByte(unsigned char byte)\r
+{\r
+ unsigned char count = 0;\r
+ while (byte > 0) {\r
+\r
+ if (byte & 1) {\r
+\r
+ count++;\r
+ }\r
+ byte >>= 1;\r
+ }\r
+\r
+ return count;\r
+}\r
+\r
+/**\r
+ * \brief Counts and return the number of bits set to '1' in the given hsiao code.\r
+ * \param code Hsizo code.\r
+ */\r
+static unsigned char CountBitsInCode(unsigned char *code)\r
+{\r
+ return CountBitsInByte(code[0])\r
+ + CountBitsInByte(code[1])\r
+ + CountBitsInByte(code[2]);\r
+}\r
+\r
+/**\r
+ * \brief Clear the corresponding interrupt flag.\r
+ */\r
+static void SMC_Clear_Status (void)\r
+{\r
+ smcStatus.BStatus = 0;\r
+}\r
+\r
+/**\r
+ * \brief Check the STATUS and set the corresponding interrupt flag.\r
+ */\r
+static void SMC_Handler(void)\r
+{\r
+ uint32_t status;\r
+ status = SMC->SMC_SR;\r
+#if 0\r
+ if ((status & SMC_SR_SMCSTS) == SMC_SR_SMCSTS) \r
+ /* NAND Flash Controller is enabled */\r
+ smcStatus.bStatus.smcSts = 1; \r
+#endif\r
+ if ((status & SMC_SR_XFRDONE) == SMC_SR_XFRDONE)\r
+ /* When set to one, this flag indicates that the NFC has terminated the Data Transfer. This flag is reset after a status read\r
+ operation. */\r
+ smcStatus.bStatus.xfrDone = 1; \r
+ if ((status & SMC_SR_CMDDONE) == SMC_SR_CMDDONE)\r
+ /* When set to one, this flag indicates that the NFC has terminated the Command. This flag is reset after a status read\r
+ operation.*/\r
+ smcStatus.bStatus.cmdDone = 1; \r
+ if ((status & (1<<24)) == (1<<24)) \r
+ /* If set to one, this flag indicates that an edge has been detected on the Ready/Busy Line x. Depending on the EDGE CTRL\r
+ field located in the SMC_CFG register, only rising or falling edge is detected. This flag is reset after a status read operation. */\r
+ smcStatus.bStatus.rbEdge = 1; \r
+ if ((status & SMC_SR_ECCRDY) == SMC_SR_ECCRDY)\r
+ /* When set to one, this flag indicates that the Hamming ECC computation is completed. This flag is reset after a status read\r
+ operation.*/\r
+ smcStatus.bStatus.hammingReady = 1; \r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Sets NFC configuration.\r
+ * \param cfg NFC configuration.\r
+ */\r
+void SMC_NFC_Configure(uint32_t cfg)\r
+{\r
+ SMC->SMC_CFG = cfg;\r
+}\r
+\r
+/**\r
+ * \brief Reset NFC controller.\r
+ */\r
+void SMC_NFC_Reset(void)\r
+{\r
+ /* Disable all the SMC NFC interrupts */\r
+ SMC->SMC_IDR = 0xFFFFFFFF;\r
+ SMC->SMC_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable NFC controller.\r
+ */\r
+void SMC_NFC_EnableNfc(void)\r
+{\r
+ SMC->SMC_CTRL |= SMC_CTRL_NFCEN;\r
+}\r
+\r
+/**\r
+ * \brief Enable NFC controller reads both main and spare area in read mode.\r
+ */\r
+void SMC_NFC_EnableSpareRead(void)\r
+{\r
+ SMC->SMC_CFG |= SMC_CFG_RSPARE;\r
+}\r
+\r
+/**\r
+ * \brief The NFC controller skips spare area in read mode.\r
+ */\r
+void SMC_NFC_DisableSpareRead(void)\r
+{\r
+ SMC->SMC_CFG &= (~SMC_CFG_RSPARE);\r
+}\r
+\r
+/**\r
+ * \brief Enables the NFC controller writes both main and spare area in write\r
+ */\r
+void SMC_NFC_EnableSpareWrite(void)\r
+{\r
+ SMC->SMC_CFG |= SMC_CFG_WSPARE;\r
+}\r
+\r
+/**\r
+ * \brief The NFC controller skips spare area in write mode.\r
+ */\r
+void SMC_NFC_DisableSpareWrite(void)\r
+{\r
+ SMC->SMC_CFG &= (~SMC_CFG_WSPARE);\r
+}\r
+\r
+/**\r
+ * \brief Check if spare area be read in read mode.\r
+ *\r
+ * \return Returns 1 if NFC controller reads both main and spare area in\r
+ * read mode, otherwise returns 0.\r
+ */\r
+uint8_t SMC_NFC_isSpareRead(void)\r
+{\r
+ return (((SMC->SMC_CFG) >> 9) & 0x1);\r
+}\r
+\r
+/**\r
+ * \brief Check if spare area be written in write mode.\r
+ *\r
+ * \return Returns 1 if NFC controller writes both main and spare area in\r
+ * write mode, otherwise returns 0.\r
+ */\r
+uint8_t SMC_NFC_isSpareWrite(void)\r
+{\r
+ return (((SMC->SMC_CFG) >> 8) & 0x1);\r
+}\r
+\r
+/**\r
+ * \brief Check if NFC transfer complete.\r
+ * \return Returns 1 if NFC controller has terminated the data transmission,\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t SMC_NFC_isTransferComplete(void)\r
+{\r
+ return ((SMC->SMC_SR & SMC_SR_XFRDONE) == SMC_SR_XFRDONE);\r
+}\r
+\r
+/**\r
+ * \brief Check Ready/Busy line.\r
+ *\r
+ * \return Returns 1 if edge has been detected on the Ready/Busy line,\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t SMC_NFC_isReadyBusy(void)\r
+{\r
+ return ((SMC->SMC_SR & SMC_SR_RB_EDGE0) == SMC_SR_RB_EDGE0);\r
+}\r
+\r
+/**\r
+ * \brief Check if NFC Controller is busy.\r
+ *\r
+ * \return Returns 1 if NFC Controller is activated and accesses the memory device,\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t SMC_NFC_isNfcBusy(void)\r
+{\r
+ return ((SMC->SMC_SR & SMC_SR_NFCBUSY) == SMC_SR_NFCBUSY);\r
+}\r
+\r
+/**\r
+ * \brief Get NFC Status.\r
+ *\r
+ * \return Returns the current status register of SMC NFC Status Register.\r
+ * This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ */\r
+uint32_t SMC_NFC_GetStatus(void)\r
+{\r
+ return SMC->SMC_SR;\r
+}\r
+\r
+/*\r
+ * HOST command functions\r
+ */\r
+\r
+/**\r
+ * \brief Check if the host controller is busy.\r
+ * \return Returns 1 if the host controller is busy, otherwise returns 0.\r
+ */\r
+static uint8_t SMC_NFC_isHostBusy(void)\r
+{\r
+ return (((*((volatile uint32_t *) (NFC_CMD_BASE_ADDR + NFCADDR_CMD_NFCCMD))) & 0x8000000) == 0x8000000);\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC command has done.\r
+*/\r
+void SMC_NFC_Wait_CommandDone(void)\r
+{\r
+ while (smcStatus.bStatus.cmdDone == 0)\r
+ {\r
+ SMC_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC Data Transfer Terminated.\r
+*/\r
+void SMC_NFC_Wait_XfrDone(void)\r
+{\r
+ while (smcStatus.bStatus.xfrDone == 0)\r
+ {\r
+ SMC_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC Data Transfer Terminated.\r
+*/\r
+void SMC_NFC_Wait_HammingReady(void)\r
+{\r
+ while (smcStatus.bStatus.hammingReady ==0)\r
+ {\r
+ SMC_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC Ready/Busy Line 3 Edge Detected.\r
+*/\r
+void SMC_NFC_Wait_RBbusy(void)\r
+{\r
+ while (smcStatus.bStatus.rbEdge == 0)\r
+ {\r
+ SMC_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Uses the HOST nandflash conntroller to send a command to the NFC.\r
+ * \param cmd command to send.\r
+ * \param addressCycle address cycle when command access id decoded.\r
+ * \param cycle0 address at first cycle.\r
+ */\r
+void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, uint32_t cycle0)\r
+{\r
+ volatile uint32_t *pCommandAddress;\r
+ SMC_Clear_Status();\r
+ /* Wait until host controller is not busy. */\r
+ while(SMC_NFC_isHostBusy());\r
+ /* Send the command plus the ADDR_CYCLE */\r
+ pCommandAddress = (volatile uint32_t *) (cmd + NFC_CMD_BASE_ADDR);\r
+ SMC->SMC_ADDR = cycle0;\r
+ *pCommandAddress = addressCycle;\r
+ SMC_NFC_Wait_CommandDone();\r
+}\r
+\r
+/* ECC function */\r
+\r
+/**\r
+ * \brief Get 24-bit ECC code for 8-bit data path NAND flash.\r
+ * 24-bit ECC is generated in order to perform one bit correction\r
+ * for 512 byte in page 512/1024/2048/4096 for 8-bit words\r
+ *\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ */\r
+static void _smc_ecc_GetW9BitPer512Ecc(uint32_t pageDataSize, uint8_t *code)\r
+{\r
+ uint8_t i;\r
+ uint8_t numEcc;\r
+ uint32_t eccParity;\r
+ uint32_t ecc[16];\r
+\r
+ SMC_ECC_GetValue(ecc);\r
+ numEcc = pageDataSize / 512;\r
+ /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */\r
+ /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */\r
+ /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */\r
+ for (i = 0; i < numEcc; i++) {\r
+ /* Get Parity and NParity value. */\r
+ eccParity = ecc[i];\r
+ eccParity = ~eccParity;\r
+ code[i * 3] = eccParity & 0xff;\r
+ code[i * 3 + 1] = (eccParity >> 8) & 0xff;\r
+ code[i * 3 + 2] = (eccParity >> 16) & 0xff;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get 24-bit ECC code for 8-bit data path NAND flash.\r
+ * 24-bit ECC is generated in order to perform one bit correction\r
+ * for 256 byte in page 512/1024/2048/4096 for 8-bit words\r
+ *\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ */\r
+static void _smc_ecc_GetW8BitPer256Ecc(uint32_t pageDataSize, uint8_t *code)\r
+{\r
+ uint8_t i;\r
+ uint8_t numEcc;\r
+ uint32_t eccParity;\r
+ uint32_t ecc[16];\r
+\r
+ SMC_ECC_GetValue(ecc);\r
+ numEcc = pageDataSize / 256;\r
+\r
+ /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */\r
+ /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */\r
+ /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */\r
+ for (i = 0; i < numEcc; i++) {\r
+ /* Get Parity and NParity value. */\r
+ eccParity = ecc[i];\r
+ eccParity = ~eccParity; \r
+ TRACE_DEBUG("ecc Parity%d is 0x%08x \n\r", (int)i, (uint32_t)eccParity);\r
+ code[i * 3] = eccParity & 0xff;\r
+ code[i * 3 + 1] = (eccParity >> 8) & 0xff;\r
+ code[i * 3 + 2] = (eccParity >> 16) & 0xff;\r
+ }\r
+}\r
+\r
+/**\r
+ * \breif Get 32-bit ECC code for 16-bit data path NAND flash.\r
+ * 32-bit ECC is generated in order to perform one bit correction\r
+ * for a page in page 512/1024/2048/4096 for 16-bit words\r
+ *\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ */\r
+static void _smc_ecc_GetW12BitPerPageEcc(uint32_t pageDataSize, uint8_t *code)\r
+{\r
+ uint32_t eccParity;\r
+ uint32_t eccNparity;\r
+ uint32_t ecc[16];\r
+\r
+ pageDataSize = pageDataSize; /* stop warning */\r
+ /* Get Parity value. */\r
+ SMC_ECC_GetValue(ecc);\r
+\r
+ /* ---- P16384'P8192'P4096'P2048' P1024'P512'P256' --- 4th. Ecc Byte to store */\r
+ /* P128' P64' P32' P16' P8' P4' P2' P1' --- 3rd. Ecc Byte to store */\r
+ /* ---- P16384 P8192 P4096 P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */\r
+ /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */\r
+\r
+ /* Invert codes (linux compatibility) */\r
+ eccParity = ecc[0];\r
+ eccNparity = ecc[1];\r
+ code[0] = eccParity & 0xff;\r
+ code[1] = (eccParity >> 8 )& 0xff;\r
+ code[2] = eccNparity & 0xff;\r
+ code[3] = (eccNparity >> 8 )& 0xff;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configures ECC mode.\r
+ * \param type Type of correction.\r
+ * \param pageSize Page size of NAND flash device.\r
+ */\r
+void SMC_ECC_Configure(uint32_t type, uint32_t pageSize)\r
+{\r
+ /* Software Reset ECC. */\r
+ SMC->SMC_ECC_CTRL = (0x1 << 1) ;\r
+ SMC->SMC_ECC_MD = type | pageSize;\r
+}\r
+\r
+/**\r
+ * \brief Get ECC correction type.\r
+ *\r
+ * \return Returns type of ECC correction setting.\r
+ */\r
+uint32_t SMC_ECC_GetCorrectoinType(void)\r
+{\r
+ return ((SMC->SMC_ECC_MD)& SMC_ECC_MD_TYPCORREC_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Get ECC status.\r
+ * \param eccNumber ecc parity number from 0 to 15.\r
+ *\r
+ * \return Returns ECC status by giving ecc number.\r
+ */\r
+uint8_t SMC_ECC_GetStatus(uint8_t eccNumber)\r
+{\r
+ uint32_t status;\r
+\r
+ if (eccNumber < 8){\r
+ status = SMC->SMC_ECC_SR1;\r
+ }\r
+ else {\r
+ status = SMC->SMC_ECC_SR2;\r
+ eccNumber -=8;\r
+ }\r
+ return ((status >> (eccNumber * 4)) & 0x07);\r
+}\r
+\r
+/**\r
+ * \brief Get all ECC parity and Nparity value.\r
+ */\r
+void SMC_ECC_GetValue(uint32_t *ecc)\r
+{\r
+ ecc[0] = SMC->SMC_ECC_PR0;\r
+ ecc[1] = SMC->SMC_ECC_PR1;\r
+ ecc[2] = SMC->SMC_ECC_PR2;\r
+ ecc[3] = SMC->SMC_ECC_PR3;\r
+ ecc[4] = SMC->SMC_ECC_PR4;\r
+ ecc[5] = SMC->SMC_ECC_PR5;\r
+ ecc[6] = SMC->SMC_ECC_PR6;\r
+ ecc[7] = SMC->SMC_ECC_PR7;\r
+ ecc[8] = SMC->SMC_ECC_PR8;\r
+ ecc[9] = SMC->SMC_ECC_PR9;\r
+ ecc[10] = SMC->SMC_ECC_PR10;\r
+ ecc[11] = SMC->SMC_ECC_PR11;\r
+ ecc[12] = SMC->SMC_ECC_PR12;\r
+ ecc[13] = SMC->SMC_ECC_PR13;\r
+ ecc[14] = SMC->SMC_ECC_PR14;\r
+ ecc[15] = SMC->SMC_ECC_PR15;\r
+}\r
+\r
+/**\r
+ * \brief verifies 4-bytes hsiao codes for a data block whose size is a page Size\r
+ * word. Page words block is verified between the given HSIAO code \r
+ * generated by hardware and original HSIAO codes store has been previously stored.\r
+ * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC\r
+ * or Hsiao_ERROR_MULTIPLEBITS.\r
+ * \param data Data buffer to verify.\r
+ * \param originalCode Original codes.\r
+ * \param verifyCode codes to be verified.\r
+ */\r
+static uint8_t _smc_ecc_VerifyW12BitPerPageEcc(\r
+ uint8_t *data,\r
+ const uint8_t *originalCode,\r
+ const uint8_t *verifyCode)\r
+{\r
+ uint8_t correctionCode[4];\r
+ uint8_t bitCount;\r
+ // Xor both codes together\r
+ correctionCode[0] = verifyCode[0] ^ originalCode[0];\r
+ correctionCode[1] = verifyCode[1] ^ originalCode[1];\r
+ correctionCode[2] = verifyCode[2] ^ originalCode[2];\r
+ correctionCode[3] = verifyCode[3] ^ originalCode[3];\r
+ TRACE_DEBUG("Correction code = %02X %02X %02X %02X\n\r",\r
+ correctionCode[0], correctionCode[1], correctionCode[2], correctionCode[3]);\r
+ /* If all bytes are 0, there is no error */\r
+ if ((correctionCode[0] == 0)\r
+ && (correctionCode[1] == 0)\r
+ && (correctionCode[2] == 0)\r
+ && (correctionCode[3] == 0)) {\r
+\r
+ return 0;\r
+ }\r
+ /* If there is a single bit error, there are 15 bits set to 1 */\r
+ bitCount = CountBitsInByte(correctionCode[0]) + \r
+ CountBitsInByte(correctionCode[1]) + \r
+ CountBitsInByte(correctionCode[2]) + \r
+ CountBitsInByte(correctionCode[3]);\r
+ if (bitCount == 15) {\r
+ /* Get byte and bit indexes */\r
+ uint16_t byte = (correctionCode[0] & 0xf0) >> 4;\r
+ byte |= (correctionCode[1] & 0xff) << 4;\r
+ uint8_t bit = correctionCode[0] & 0x0f;\r
+ /* Correct bit */\r
+ printf("Correcting byte #%d at bit %d\n\r", byte, bit);\r
+ data[byte] ^= (1 << bit);\r
+\r
+ return Hsiao_ERROR_SINGLEBIT;\r
+ }\r
+ \r
+ /* Check if ECC has been corrupted */\r
+ if (bitCount == 1) {\r
+ return Hsiao_ERROR_ECC;\r
+ }\r
+ /* Otherwise, this is a multi-bit error */\r
+ else {\r
+ return Hsiao_ERROR_MULTIPLEBITS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief erifies 3-bytes hsiao codes for a data block whose size is a page Size\r
+ * word. Page words block is verified between the given HSIAO code \r
+ * generated by hardware and original HSIAO codes store has been previously stored.\r
+ * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC\r
+ * or Hsiao_ERROR_MULTIPLEBITS.\r
+ * \param data Data buffer to verify.\r
+ * \param originalCode Original codes.\r
+ * \param verifyCode codes to be verified.\r
+ */\r
+static uint8_t _smc_ecc_VerifyW8BitPer256Ecc(\r
+ uint8_t *data,\r
+ uint32_t size,\r
+ const uint8_t *originalCode,\r
+ const uint8_t *verifyCode)\r
+{\r
+ uint8_t correctionCode[3];\r
+ uint32_t position = 0;\r
+ uint8_t byte;\r
+ uint8_t bit;\r
+ uint8_t error = 0;\r
+ \r
+ TRACE_DEBUG("_smc_ecc_VerifyW8BitPer256Ecc()\n\r");\r
+ while (position < size) {\r
+ /* Xor both codes together */\r
+ correctionCode[0] = verifyCode[0] ^ originalCode[0];\r
+ correctionCode[1] = verifyCode[1] ^ originalCode[1];\r
+ correctionCode[2] = verifyCode[2] ^ originalCode[2];\r
+ TRACE_DEBUG("Correction code = %02X %02X %02X\n\r",\r
+ correctionCode[0], correctionCode[1], correctionCode[2]);\r
+ \r
+ /* If all bytes are 0, there is no error */\r
+ if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) {\r
+ /* If there is a single bit error, there are 11 bits set to 1 */\r
+ if (CountBitsInCode(correctionCode) == 11) {\r
+ /* Get byte and bit indexes */\r
+ byte = (correctionCode[0] & 0xf8) >> 3;\r
+ byte |= (correctionCode[1] & 0x07) << 5;\r
+ bit = correctionCode[0] & 0x07;\r
+ /* Correct bit */\r
+ printf("Correcting byte #%u at bit %u\n\r", (unsigned int)(position + byte), (unsigned int)bit);\r
+ data[byte] ^= (1 << bit);\r
+ error = Hsiao_ERROR_SINGLEBIT;\r
+ }\r
+ /* Check if ECC has been corrupted */\r
+ else if (CountBitsInCode(correctionCode) == 1) {\r
+ return Hsiao_ERROR_ECC;\r
+ }\r
+ else {\r
+ /* Otherwise, this is a multi-bit error */\r
+ return Hsiao_ERROR_MULTIPLEBITS;\r
+ }\r
+ }\r
+ data += 256;\r
+ originalCode += 3;\r
+ verifyCode += 3;\r
+ position += 256;\r
+ }\r
+ return error;\r
+}\r
+\r
+/**\r
+ * \brief 3-bytes hsiao codes for a data block whose size is multiple of\r
+ * 512 bytes. Each 512-bytes block is verified between the given HSIAO code \r
+ * generated by hardware and original HSIAO codes store has been previously stored.\r
+ * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC\r
+ * or Hsiao_ERROR_MULTIPLEBITS.\r
+ * \param data Data buffer to verify.\r
+ * \param originalCode Original codes.\r
+ * \param verifyCode codes to be verified.\r
+ */\r
+static uint8_t _smc_ecc_VerifyW9BitPer512Ecc(\r
+ uint8_t *data,\r
+ uint32_t size,\r
+ const uint8_t *originalCode,\r
+ const uint8_t *verifyCode)\r
+{\r
+ uint8_t correctionCode[3];\r
+ uint32_t position = 0;\r
+ uint16_t byte;\r
+ uint8_t bit;\r
+ uint8_t error = 0;\r
+ \r
+ TRACE_DEBUG("_smc_ecc_VerifyW9BitPer512Ecc()\n\r");\r
+ while (position < size) {\r
+ /* Xor both codes together */\r
+ correctionCode[0] = verifyCode[0] ^ originalCode[0];\r
+ correctionCode[1] = verifyCode[1] ^ originalCode[1];\r
+ correctionCode[2] = verifyCode[2] ^ originalCode[2];\r
+ TRACE_DEBUG("Correction code = %02X %02X %02X\n\r",\r
+ correctionCode[0], correctionCode[1], correctionCode[2]);\r
+ \r
+ /* If all bytes are 0, there is no error */\r
+ if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) {\r
+ // If there is a single bit error, there are 11 bits set to 1\r
+ if (CountBitsInCode(correctionCode) == 12) {\r
+ /* Get byte and bit indexes */\r
+ byte = (correctionCode[0] & 0xf8) >> 3;\r
+ byte |= (correctionCode[1] & 0x0f) << 5;\r
+ bit = correctionCode[0] & 0x07;\r
+ /* Correct bit */\r
+ printf("Correcting byte #%u at bit %u\n\r", (unsigned int)(position + byte), (unsigned int)bit);\r
+ data[byte] ^= (1 << bit);\r
+ error = Hsiao_ERROR_SINGLEBIT;\r
+ }\r
+ /* Check if ECC has been corrupted */\r
+ else if (CountBitsInCode(correctionCode) == 1) {\r
+ return Hsiao_ERROR_ECC;\r
+ }\r
+ else {\r
+ /* Otherwise, this is a multi-bit error */\r
+ return Hsiao_ERROR_MULTIPLEBITS;\r
+ }\r
+ }\r
+ data += 512;\r
+ originalCode += 3;\r
+ verifyCode += 3;\r
+ position += 512;\r
+ }\r
+ return error;\r
+}\r
+\r
+/**\r
+ * Get ECC code for 8bit/16-bit data path NAND flash by giving data path.\r
+ * 24-bit or 32-bit ECC is generated in order to perform one bit correction\r
+ * for a page in page 512/1024/2048/4096.\r
+ *\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ * \param busWidth 8bit/16bit data path.\r
+ */\r
+void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, uint8_t busWidth)\r
+{\r
+ uint8_t correctionType;\r
+\r
+ correctionType = SMC_ECC_GetCorrectoinType();\r
+ /* For 16-bit data path */\r
+ if (busWidth == 16 && correctionType == SMC_ECC_MD_TYPCORREC_CPAGE )\r
+ _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code);\r
+ /* For 8-bit data path */\r
+ else {\r
+ switch (correctionType){\r
+ case SMC_ECC_MD_TYPCORREC_CPAGE:\r
+ _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code);\r
+ break;\r
+ case SMC_ECC_MD_TYPCORREC_C256B:\r
+ _smc_ecc_GetW8BitPer256Ecc(pageDataSize, code);\r
+ break;\r
+ case SMC_ECC_MD_TYPCORREC_C512B:\r
+ _smc_ecc_GetW9BitPer512Ecc(pageDataSize, code);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * Verifies hsiao codes for a data block. The block is verified between the given \r
+ * HSIAO code generated by hardware and original HSIAO codes store has been \r
+ * previously stored.\r
+ * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC\r
+ * or Hsiao_ERROR_MULTIPLEBITS.\r
+ * \param data Data buffer to verify.\r
+ * \param size Size of the data in words.\r
+ * \param originalCode Original codes.\r
+ * \param verifyCode codes to be verified.\r
+ * \param dataPath 8bit/16bit data path.\r
+*/\r
+uint8_t SMC_ECC_VerifyHsiao(\r
+ uint8_t *data,\r
+ uint32_t size,\r
+ const uint8_t *originalCode,\r
+ const uint8_t *verifyCode,\r
+ uint8_t busWidth)\r
+{\r
+ uint8_t correctionType;\r
+ uint8_t error = 0;\r
+ correctionType = SMC_ECC_GetCorrectoinType();\r
+ /* For 16-bit data path */\r
+ if (busWidth == 16 && (correctionType == SMC_ECC_MD_TYPCORREC_CPAGE) ) {\r
+ error = _smc_ecc_VerifyW12BitPerPageEcc((uint8_t*)data, originalCode, verifyCode);\r
+ }\r
+ /* For 8-bit data path */\r
+ else {\r
+ switch (correctionType){\r
+ case SMC_ECC_MD_TYPCORREC_CPAGE:\r
+ error = _smc_ecc_VerifyW12BitPerPageEcc(data, originalCode, verifyCode);\r
+\r
+ break;\r
+ case SMC_ECC_MD_TYPCORREC_C256B:\r
+ error = _smc_ecc_VerifyW8BitPer256Ecc(data, size, originalCode, verifyCode);\r
+ break;\r
+ case SMC_ECC_MD_TYPCORREC_C512B:\r
+ error = _smc_ecc_VerifyW9BitPer512Ecc(data, size, originalCode, verifyCode);\r
+ break;\r
+ }\r
+ }\r
+ return error;\r
+}
\ No newline at end of file
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup spi_module Working with SPI\r
+ * The SPI driver provides the interface to configure and use the SPI\r
+ * peripheral.\r
+ *\r
+ * The Serial Peripheral Interface (SPI) circuit is a synchronous serial\r
+ * data link that provides communication with external devices in Master\r
+ * or Slave Mode.\r
+ *\r
+ * To use the SPI, the user has to follow these few steps:\r
+ * -# Enable the SPI pins required by the application (see pio.h).\r
+ * -# Configure the SPI using the \ref SPI_Configure(). This enables the\r
+ * peripheral clock. The mode register is loaded with the given value.\r
+ * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().\r
+ * -# Enable the SPI by calling \ref SPI_Enable().\r
+ * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()\r
+ * must be called after \ref SPI_Write() to retrieve the last value read. \r
+ * -# Disable the SPI by calling \ref SPI_Disable().\r
+ *\r
+ * For more accurate information, please look at the SPI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref spi.c\n\r
+ * \ref spi.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Serial Peripheral Interface (SPI) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void SPI_Enable( Spi* spi )\r
+{\r
+ spi->SPI_CR = SPI_CR_SPIEN ;\r
+}\r
+\r
+/**\r
+ * \brief Disables a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void SPI_Disable( Spi* spi )\r
+{\r
+ spi->SPI_CR = SPI_CR_SPIDIS ;\r
+}\r
+\r
+/**\r
+ * \brief Enables one or more interrupt sources of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources )\r
+{\r
+ spi->SPI_IER = dwSources ;\r
+}\r
+\r
+/**\r
+ * \brief Disables one or more interrupt sources of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources )\r
+{\r
+ spi->SPI_IDR = dwSources ;\r
+}\r
+\r
+/**\r
+ * \brief Configures a SPI peripheral as specified. The configuration can be computed\r
+ * using several macros (see \ref spi_configuration_macros).\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param id Peripheral ID of the SPI.\r
+ * \param configuration Value of the SPI configuration register.\r
+ */\r
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )\r
+{\r
+ PMC_EnablePeripheral( dwId ) ;\r
+ \r
+ spi->SPI_CR = SPI_CR_SPIDIS ;\r
+\r
+ /* Execute a software reset of the SPI twice */\r
+ spi->SPI_CR = SPI_CR_SWRST ;\r
+ spi->SPI_CR = SPI_CR_SWRST ;\r
+ spi->SPI_MR = dwConfiguration ;\r
+}\r
+\r
+/**\r
+ * \brief Configures SPI chip select.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param cS Chip select of NPSCx.\r
+ */\r
+extern void SPI_ChipSelect( Spi* spi, uint8_t cS)\r
+{\r
+ spi->SPI_MR |= SPI_MR_PCS_Msk ;\r
+ spi->SPI_MR &= ~(SPI_MR_PCS ( cS )) ;\r
+}\r
+\r
+/**\r
+ * \brief Configures SPI Mode Register.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param configuration Value of the SPI mode register.\r
+ */\r
+extern void SPI_SetMode( Spi* spi, \r
+ uint32_t dwConfiguration )\r
+{\r
+ spi->SPI_MR = dwConfiguration ;\r
+}\r
+\r
+/**\r
+ * \brief Configures SPI to release last used CS line.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void SPI_ReleaseCS( Spi* spi )\r
+{\r
+ spi->SPI_CR = SPI_CR_LASTXFER ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configures a chip select of a SPI peripheral. The chip select configuration\r
+ * is computed using several macros (see \ref spi_configuration_macros).\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param npcs Chip select to configure (0, 1, 2 or 3).\r
+ * \param configuration Desired chip select configuration.\r
+ */\r
+void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )\r
+{\r
+ spi->SPI_CSR[dwNpcs] = dwConfiguration ;\r
+}\r
+\r
+/**\r
+ * \brief Configures a chip select active mode of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwNpcs Chip select to configure (0, 1, 2 or 3).\r
+ * \param bReleaseOnLast CS controlled by last transfer.\r
+ * SPI_ReleaseCS() is used to deactive CS. \r
+ */\r
+void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast )\r
+{\r
+ if (bReleaseOnLast)\r
+ {\r
+ spi->SPI_CSR[dwNpcs] |= SPI_CSR_CSAAT;\r
+ }\r
+ else\r
+ {\r
+ spi->SPI_CSR[dwNpcs] &= ~SPI_CSR_CSAAT;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given SPI peripheral.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param spi Pointer to a Spi instance.\r
+ * \return SPI status register.\r
+ */\r
+extern uint32_t SPI_GetStatus( Spi* spi )\r
+{\r
+ return spi->SPI_SR ;\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns the last word of data received by a SPI peripheral. This\r
+ * method must be called after a successful SPI_Write call.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ *\r
+ * \return readed data.\r
+ */\r
+extern uint32_t SPI_Read( Spi* spi )\r
+{\r
+ while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ;\r
+\r
+ return spi->SPI_RDR & 0xFFFF ;\r
+}\r
+\r
+/**\r
+ * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed\r
+ * peripheral select, the npcs value is meaningless. Otherwise, it identifies\r
+ * the component which shall be addressed.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param npcs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param data Word of data to send.\r
+ */\r
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )\r
+{\r
+ /* Send data */\r
+ while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;\r
+ spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;\r
+ while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Sends last data through a SPI peripheral.\r
+ * If the SPI is configured to use a fixed peripheral select, the npcs value is\r
+ * meaningless. Otherwise, it identifies the component which shall be addressed.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param npcs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param data Word of data to send.\r
+ */\r
+extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData )\r
+{\r
+ /* Send data */\r
+ while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;\r
+ spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) | SPI_TDR_LASTXFER ;\r
+ while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;\r
+}\r
+\r
+/**\r
+ * \brief Check if SPI transfer finish.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ *\r
+ * \return Returns 1 if there is no pending write operation on the SPI; otherwise\r
+ * returns 0.\r
+ */\r
+extern uint32_t SPI_IsFinished( Spi* spi )\r
+{\r
+ return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ /**\r
+ * \addtogroup spi_dma_module SPI xDMA driver\r
+ * \ingroup lib_spiflash\r
+ * \section Usage\r
+ *\r
+ * <ul>\r
+ * <li> SPID_Configure() initializes and configures the SPI peripheral and xDMA for data transfer.</li>\r
+ * <li> Configures the parameters for the device corresponding to the cs value by SPID_ConfigureCS(). </li>\r
+ * <li> Starts a SPI master transfer. This is a non blocking function SPID_SendCommand(). It will\r
+ * return as soon as the transfer is started..</li>\r
+ * </ul>\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the SPI Flash with xDMA driver.\r
+ *\r
+ */\r
+\r
+ \r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** xDMA support */\r
+#define USE_SPI_DMA\r
+\r
+/** xDMA Link List size for spi transation*/\r
+#define DMA_SPI_LLI 2\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ /*----------------------------------------------------------------------------\r
+ * Local Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/* DMA driver instance */\r
+static uint32_t spiDmaTxChannel;\r
+static uint32_t spiDmaRxChannel;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief SPI xDMA Rx callback\r
+ * Invoked on SPi DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to Spid instance. \r
+ */ \r
+static void SPID_Rx_Cb(uint32_t channel, Spid* pArg)\r
+{\r
+ SpidCmd *pSpidCmd = pArg->pCurrentCommand;\r
+ Spi *pSpiHw = pArg->pSpiHw;\r
+ if (channel != spiDmaRxChannel)\r
+ return;\r
+ \r
+ /* Disable the SPI TX & RX */\r
+ SPI_Disable ( pSpiHw );\r
+ \r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_DisableIRQ(XDMAC_IRQn);\r
+ \r
+ /* Disable the SPI Peripheral */\r
+ PMC_DisablePeripheral ( pArg->spiId );\r
+ \r
+ /* Release CS */\r
+ SPI_ReleaseCS(pSpiHw);\r
+ \r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, spiDmaRxChannel);\r
+ XDMAD_FreeChannel(pArg->pXdmad, spiDmaTxChannel);\r
+\r
+ /* Release the dataflash semaphore */\r
+ pArg->semaphore++;\r
+ \r
+ printf("\n\r%s\n\r",pArg->pCurrentCommand->pRxBuff);\r
+ \r
+ /* Invoke the callback associated with the current command */\r
+ if (pSpidCmd && pSpidCmd->callback) {\r
+ //printf("p %d", pArg->semaphore);\r
+ pSpidCmd->callback(0, pSpidCmd->pArgument);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA Channels: 0 RX, 1 TX.\r
+ * Channels are disabled after configure.\r
+ * \returns 0 if the dma channel configuration successfully; otherwise returns\r
+ * SPID_ERROR_XXX.\r
+ */\r
+static uint8_t _spid_configureDmaChannels( Spid* pSpid )\r
+{\r
+ \r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pSpid->pXdmad, 0 );\r
+ \r
+ XDMAD_FreeChannel( pSpid->pXdmad, spiDmaTxChannel);\r
+ XDMAD_FreeChannel( pSpid->pXdmad, spiDmaRxChannel);\r
+ \r
+ /* Allocate a DMA channel for SPI0/1 TX. */\r
+ spiDmaTxChannel = XDMAD_AllocateChannel( pSpid->pXdmad, XDMAD_TRANSFER_MEMORY, pSpid->spiId);\r
+ {\r
+ if ( spiDmaTxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return SPID_ERROR;\r
+ }\r
+ }\r
+ /* Allocate a DMA channel for SPI0/1 RX. */\r
+ spiDmaRxChannel = XDMAD_AllocateChannel( pSpid->pXdmad, pSpid->spiId, XDMAD_TRANSFER_MEMORY);\r
+ {\r
+ if ( spiDmaRxChannel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return SPID_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Setup callbacks for SPI0/1 RX */\r
+ XDMAD_SetCallback(pSpid->pXdmad, spiDmaRxChannel, (XdmadTransferCallback)SPID_Rx_Cb, pSpid);\r
+ if (XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaRxChannel ))\r
+ return SPID_ERROR;\r
+\r
+ /* Setup callbacks for SPI0/1 TX (ignored) */\r
+ XDMAD_SetCallback(pSpid->pXdmad, spiDmaTxChannel, NULL, NULL);\r
+ if ( XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaTxChannel ))\r
+ return SPID_ERROR;\r
+ \r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure the DMA source and destination with Linker List mode.\r
+ *\r
+ * \param pCommand Pointer to command\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * SPID_ERROR_XXX.\r
+ */\r
+static uint8_t _spid_configureLinkList(Spi *pSpiHw, void *pXdmad, SpidCmd *pCommand)\r
+{\r
+ sXdmadCfg xdmadRxCfg,xdmadTxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t spiId;\r
+ if ((unsigned int)pSpiHw == (unsigned int)SPI0 ) spiId = ID_SPI0;\r
+ if ((unsigned int)pSpiHw == (unsigned int)SPI1 ) spiId = ID_SPI1;\r
+ \r
+ \r
+ \r
+ /* Setup TX */ \r
+ \r
+ xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff; \r
+ \r
+ xdmadTxCfg.mbr_da = (uint32_t)&pSpiHw->SPI_TDR;\r
+ \r
+ xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NSEN_UPDATED | pCommand->TxSize;\r
+ \r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_MEM2PER |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF1 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_FIXED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_TX ));\r
+ \r
+ \r
+ xdmadTxCfg.mbr_bc = 0;\r
+ xdmadTxCfg.mbr_sus = 0;\r
+ xdmadTxCfg.mbr_dus =0;\r
+ \r
+ /* Setup RX Link List */\r
+ \r
+ xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NDEN_UPDATED | pCommand->RxSize;\r
+ \r
+ xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;\r
+ \r
+ xdmadRxCfg.mbr_sa = (uint32_t)&pSpiHw->SPI_RDR;\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_PER2MEM |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF1 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_FIXED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_RX ));\r
+ \r
+\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ xdmadRxCfg.mbr_sus = 0;\r
+ xdmadRxCfg.mbr_dus =0;\r
+\r
+ xdmaCndc = 0;\r
+ \r
+\r
+ if (XDMAD_ConfigureTransfer( pXdmad, spiDmaRxChannel, &xdmadRxCfg, xdmaCndc, 0))\r
+ return SPID_ERROR;\r
+ \r
+ if (XDMAD_ConfigureTransfer( pXdmad, spiDmaTxChannel, &xdmadTxCfg, xdmaCndc, 0))\r
+ return SPID_ERROR;\r
+ return 0;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initializes the Spid structure and the corresponding SPI & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no SPI command processing.\r
+ *\r
+ * \param pSpid Pointer to a Spid instance.\r
+ * \param pSpiHw Associated SPI peripheral.\r
+ * \param spiId SPI peripheral identifier.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t SPID_Configure( Spid *pSpid ,\r
+ Spi *pSpiHw , \r
+ uint8_t spiId,\r
+ uint8_t SpiMode,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the SPI structure */\r
+ pSpid->pSpiHw = pSpiHw;\r
+ pSpid->spiId = spiId;\r
+ pSpid->semaphore = 1;\r
+ pSpid->pCurrentCommand = 0;\r
+ pSpid->pXdmad = pXdmad;\r
+\r
+ /* Enable the SPI Peripheral ,Execute a software reset of the SPI, Configure SPI in Master Mode*/\r
+ SPI_Configure ( pSpiHw, pSpid->spiId, SpiMode );\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configures the parameters for the device corresponding to the cs value.\r
+ *\r
+ * \param pSpid Pointer to a Spid instance.\r
+ * \param cs number corresponding to the SPI chip select.\r
+ * \param csr SPI_CSR value to setup.\r
+ */\r
+void SPID_ConfigureCS( Spid *pSpid, \r
+ uint32_t dwCS, \r
+ uint32_t dwCsr)\r
+{\r
+ Spi *pSpiHw = pSpid->pSpiHw;\r
+ \r
+ /* Enable the SPI Peripheral */\r
+ PMC_EnablePeripheral (pSpid->spiId );\r
+ /* Configure SPI Chip Select Register */\r
+ SPI_ConfigureNPCS( pSpiHw, dwCS, dwCsr );\r
+ \r
+ /* Disable the SPI Peripheral */\r
+ PMC_DisablePeripheral (pSpid->spiId );\r
+ \r
+}\r
+\r
+/**\r
+ * \brief Starts a SPI master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pSpid Pointer to a Spid instance.\r
+ * \param pCommand Pointer to the SPI command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t SPID_SendCommand( Spid *pSpid, SpidCmd *pCommand)\r
+{\r
+ Spi *pSpiHw = pSpid->pSpiHw;\r
+ \r
+ /* Try to get the dataflash semaphore */\r
+ if (pSpid->semaphore == 0) {\r
+ \r
+ return SPID_ERROR_LOCK;\r
+ }\r
+ pSpid->semaphore--;\r
+ \r
+ /* Enable the SPI Peripheral */\r
+ PMC_EnablePeripheral (pSpid->spiId );\r
+ \r
+ /* SPI chip select */\r
+ SPI_ChipSelect (pSpiHw, 1 << pCommand->spiCs);\r
+ \r
+ // Initialize the callback\r
+ pSpid->pCurrentCommand = pCommand;\r
+ \r
+ /* Initialize DMA controller using channel 0 for RX, 1 for TX. */\r
+ if (_spid_configureDmaChannels(pSpid) )\r
+ return SPID_ERROR_LOCK;\r
+ \r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_SetPriority( XDMAC_IRQn ,1);\r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+ \r
+ \r
+ if (_spid_configureLinkList(pSpiHw, pSpid->pXdmad, pCommand))\r
+ return SPID_ERROR_LOCK;\r
+ \r
+ /* Enables the SPI to transfer and receive data. */\r
+ SPI_Enable (pSpiHw );\r
+\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaRxChannel )) \r
+ return SPID_ERROR_LOCK;\r
+ if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaTxChannel )) \r
+ return SPID_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if the SPI driver is busy.\r
+ *\r
+ * \param pSpid Pointer to a Spid instance.\r
+ * \returns 1 if the SPI driver is currently busy executing a command; otherwise\r
+ */\r
+uint32_t SPID_IsBusy(const Spid *pSpid)\r
+{\r
+ if (pSpid->semaphore == 0) {\r
+ return 1;\r
+ }\r
+ else {\r
+ return 0;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup ssc_module Working with SSC\r
+ * The SSC driver provides the interface to configure and use the SSC\r
+ * peripheral.\r
+ *\r
+ * !Usage\r
+ *\r
+ * -# Enable the SSC interface pins.\r
+ * -# Configure the SSC to operate at a specific frequency by calling\r
+ * SSC_Configure(). This function enables the peripheral clock of the SSC,\r
+ * but not its PIOs.\r
+ * -# Configure the transmitter and/or the receiver using the\r
+ * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.\r
+ * -# Enable the PIOs or the transmitter and/or the received.\r
+ * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()\r
+ * and SSC_EnableReceiver()\r
+ * -# Send data through the transmitter using SSC_Write() \r
+ * -# Receive data from the receiver using SSC_Read() \r
+ * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()\r
+ * and SSC_DisableReceiver()\r
+ *\r
+ * For more accurate information, please look at the SSC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref ssc.c\n\r
+ * \ref ssc.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Synchronous Serial (SSC) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a SSC peripheral.If the divided clock is not used, the master\r
+ * clock frequency can be set to 0.\r
+ * \note The emitter and transmitter are disabled by this function.\r
+ * \param ssc Pointer to an SSC instance.\r
+ * \param bitRate bit rate.\r
+ * \param masterClock master clock.\r
+ */\r
+void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock)\r
+{\r
+ uint32_t id;\r
+ // uint32_t maxClock;\r
+ id = ID_SSC ;\r
+ // maxClock = PMC_SetPeriMaxClock(id, masterClock);\r
+\r
+ /* Reset, disable receiver & transmitter */\r
+ ssc->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST;\r
+\r
+ /* Configure clock frequency */\r
+ if (bitRate != 0) {\r
+\r
+ ssc->SSC_CMR = masterClock / (2 * bitRate);\r
+ }\r
+ else {\r
+\r
+ ssc->SSC_CMR = 0;\r
+ }\r
+ /* Enable SSC peripheral clock */\r
+ PMC_EnablePeripheral(id);\r
+}\r
+\r
+/**\r
+ * \brief Configures the transmitter of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ * \param tcmr Transmit Clock Mode Register value.\r
+ * \param tfmr Transmit Frame Mode Register value.\r
+ */\r
+void SSC_ConfigureTransmitter(Ssc *ssc,uint32_t tcmr, uint32_t tfmr)\r
+{\r
+ ssc->SSC_TCMR = tcmr;\r
+ ssc->SSC_TFMR = tfmr;\r
+}\r
+\r
+/**\r
+ * \brief Configures the receiver of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ * \param rcmr Receive Clock Mode Register value.\r
+ * \param rfmr Receive Frame Mode Register value.\r
+ */\r
+void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr)\r
+{\r
+ ssc->SSC_RCMR = rcmr;\r
+ ssc->SSC_RFMR = rfmr;\r
+}\r
+\r
+/**\r
+ * \brief Enables the transmitter of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+void SSC_EnableTransmitter(Ssc *ssc)\r
+{\r
+ ssc->SSC_CR = SSC_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disables the transmitter of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+void SSC_DisableTransmitter(Ssc *ssc)\r
+{\r
+ ssc->SSC_CR = SSC_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enables the receiver of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+void SSC_EnableReceiver(Ssc *ssc)\r
+{\r
+ ssc->SSC_CR = SSC_CR_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disables the receiver of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+void SSC_DisableReceiver(Ssc *ssc)\r
+{\r
+ ssc->SSC_CR = SSC_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enables one or more interrupt sources of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources)\r
+{\r
+ ssc->SSC_IER = sources;\r
+}\r
+\r
+/**\r
+ * \brief Disables one or more interrupt sources of a SSC peripheral.\r
+ * \param ssc Pointer to an SSC instance. \r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources)\r
+{\r
+ ssc->SSC_IDR = sources;\r
+}\r
+\r
+/**\r
+ * \brief Sends one data frame through a SSC peripheral. If another frame is currently\r
+ * being sent, this function waits for the previous transfer to complete.\r
+ * \param ssc Pointer to an SSC instance. \r
+ * \param frame Data frame to send.\r
+ */\r
+void SSC_Write(Ssc *ssc, uint32_t frame)\r
+{\r
+ while ((ssc->SSC_SR & SSC_SR_TXRDY) == 0);\r
+ ssc->SSC_THR = frame;\r
+}\r
+\r
+/**\r
+ * \brief Waits until one frame is received on a SSC peripheral, and returns it.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+uint32_t SSC_Read(Ssc *ssc)\r
+{\r
+ while ((ssc->SSC_SR & SSC_SR_RXRDY) == 0);\r
+ return ssc->SSC_RHR;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one frame is received, 0 otherwise.\r
+ * \param ssc Pointer to an SSC instance. \r
+ */\r
+uint8_t SSC_IsRxReady(Ssc *ssc)\r
+{\r
+ return ((ssc->SSC_SR & SSC_SR_RXRDY) > 0);\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+/**\r
+ * \brief Select external 32K Crystal.\r
+ *\r
+ * \note\r
+ * There's no option to return to internal slow RC after switching to ext 32kHz crystal.\r
+ */\r
+\r
+extern void SUPC_SelectExtCrystal32K(void)\r
+{\r
+ PMC_EnableXT32KFME();\r
+ /* Select XTAL 32k instead of internal slow RC 32k for slow clock */\r
+ if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST )\r
+ {\r
+ SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;\r
+\r
+ while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) );\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Timer Counter (TC).\r
+ *\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a Timer Counter Channel\r
+ *\r
+ * Configures a Timer Counter to operate in the given mode. Timer is stopped\r
+ * after configuration and must be restarted with TC_Start(). All the\r
+ * interrupts of the timer are also disabled.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param channel Channel number.\r
+ * \param mode Operating mode (TC_CMR value).\r
+ */\r
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode )\r
+{\r
+ TcChannel* pTcCh ;\r
+\r
+ assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;\r
+ pTcCh = pTc->TC_CHANNEL+dwChannel ;\r
+\r
+ /* Disable TC clock */\r
+ pTcCh->TC_CCR = TC_CCR_CLKDIS ;\r
+\r
+ /* Disable interrupts */\r
+ pTcCh->TC_IDR = 0xFFFFFFFF ;\r
+\r
+ /* Clear status register */\r
+ pTcCh->TC_SR ;\r
+\r
+ /* Set mode */\r
+ pTcCh->TC_CMR = dwMode ;\r
+}\r
+\r
+/**\r
+ * \brief Reset and Start the TC Channel\r
+ *\r
+ * Enables the timer clock and performs a software reset to start the counting.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param dwChannel Channel number.\r
+ */\r
+extern void TC_Start( Tc *pTc, uint32_t dwChannel )\r
+{\r
+ TcChannel* pTcCh ;\r
+\r
+ assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;\r
+\r
+ pTcCh = pTc->TC_CHANNEL+dwChannel ;\r
+ pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ;\r
+}\r
+\r
+/**\r
+ * \brief Stop TC Channel\r
+ *\r
+ * Disables the timer clock, stopping the counting.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param dwChannel Channel number.\r
+ */\r
+extern void TC_Stop(Tc *pTc, uint32_t dwChannel )\r
+{\r
+ TcChannel* pTcCh ;\r
+\r
+ assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;\r
+\r
+ pTcCh = pTc->TC_CHANNEL+dwChannel ;\r
+ pTcCh->TC_CCR = TC_CCR_CLKDIS ;\r
+}\r
+\r
+/**\r
+ * \brief Find best MCK divisor\r
+ *\r
+ * Finds the best MCK divisor given the timer frequency and MCK. The result\r
+ * is guaranteed to satisfy the following equation:\r
+ * \code\r
+ * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)\r
+ * \endcode\r
+ * with DIV being the highest possible value.\r
+ *\r
+ * \param dwFreq Desired timer frequency.\r
+ * \param dwMCk Master clock frequency.\r
+ * \param dwDiv Divisor value.\r
+ * \param dwTcClks TCCLKS field value for divisor.\r
+ * \param dwBoardMCK Board clock frequency.\r
+ *\r
+ * \return 1 if a proper divisor has been found, otherwise 0.\r
+ */\r
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK )\r
+{\r
+ const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ;\r
+\r
+ uint32_t dwIndex = 0 ;\r
+\r
+ /* Satisfy lower bound */\r
+ while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) )\r
+ {\r
+ dwIndex++ ;\r
+\r
+ /* If no divisor can be found, return 0 */\r
+ if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] )) )\r
+ {\r
+ return 0 ;\r
+ }\r
+ }\r
+\r
+ /* Try to maximize DIV while satisfying upper bound */\r
+ while ( dwIndex < 4 )\r
+ {\r
+\r
+ if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) )\r
+ {\r
+ break ;\r
+ }\r
+ dwIndex++ ;\r
+ }\r
+\r
+ /* Store results */\r
+ if ( dwDiv )\r
+ {\r
+ *dwDiv = adwDivisors[dwIndex] ;\r
+ }\r
+ if ( dwTcClks )\r
+ {\r
+ *dwTcClks = dwIndex ;\r
+ }\r
+\r
+ return 1 ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implement simple PIT usage as system tick.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Tick Counter united by ms */\r
+static volatile uint32_t _dwTickCount = 0 ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Handler for Sytem Tick interrupt.\r
+ *\r
+ * Process System Tick Event\r
+ * Increments the timestamp counter.\r
+ */\r
+void SysTick_Handler( void )\r
+{\r
+ _dwTickCount ++; \r
+}\r
+\r
+/**\r
+ * \brief Handler for Sytem Tick interrupt.\r
+ */\r
+extern void TimeTick_Increment( uint32_t dwInc )\r
+{\r
+ _dwTickCount += dwInc;\r
+}\r
+\r
+/**\r
+ * \brief Configures the PIT & reset tickCount.\r
+ * Systick interrupt handler will generates 1ms interrupt and increase a\r
+ * tickCount.\r
+ * \note IRQ handler must be configured before invoking this function.\r
+ * \note PIT is enabled automatically in this function.\r
+ * \param new_mck Current master clock.\r
+ */\r
+extern uint32_t TimeTick_Configure( uint32_t new_mck )\r
+{\r
+ _dwTickCount = 0 ;\r
+ /* Configure systick for 1 ms. */\r
+ printf( "Configure system tick to get 1ms tick period.\n\r" ) ;\r
+ if ( SysTick_Config( new_mck ) )\r
+ {\r
+ TRACE_ERROR("Systick configuration error\n\r" ) ;\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Get Delayed number of tick\r
+ * \param startTick Start tick point.\r
+ * \param endTick End tick point.\r
+ */\r
+extern uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick)\r
+{\r
+ if (endTick >= startTick) return (endTick - startTick);\r
+ return (endTick + (0xFFFFFFFF - startTick) + 1);\r
+}\r
+\r
+/**\r
+ * \brief Get current Tick Count, in ms.\r
+ */\r
+extern uint32_t GetTickCount( void )\r
+{\r
+ return _dwTickCount ;\r
+}\r
+\r
+/**\r
+ * \brief Sync Wait for several ms\r
+ */\r
+extern void Wait( volatile uint32_t dwMs )\r
+{\r
+ uint32_t dwStart ;\r
+ uint32_t dwCurrent ;\r
+\r
+ dwStart = _dwTickCount ;\r
+ do\r
+ {\r
+ dwCurrent = _dwTickCount ;\r
+ } while ( dwCurrent - dwStart < dwMs ) ;\r
+}\r
+\r
+/**\r
+ * \brief Sync Sleep for several ms\r
+ */\r
+extern void Sleep( volatile uint32_t dwMs )\r
+{\r
+ uint32_t dwStart ;\r
+ uint32_t dwCurrent ;\r
+ __ASM("CPSIE I");\r
+ dwStart = _dwTickCount ;\r
+\r
+ do\r
+ {\r
+ dwCurrent = _dwTickCount ;\r
+\r
+ if ( dwCurrent - dwStart > dwMs )\r
+ {\r
+ break ;\r
+ }\r
+ __ASM("WFI");\r
+ } while( 1 ) ;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup rtng_module Working with RTNG\r
+ * \ingroup peripherals_module\r
+ * The TRNG driver provides the interface to configure and use the TRNG peripheral.\r
+ * \n\r
+ *\r
+ * The True Random Number Generator (TRNG) passes the American NIST Special Publication\r
+ * 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_Enable()), \r
+ * the generator provides one 32-bit value every 84 clock cycles. \r
+ * Interrupt trng_int can be enabled through TRNG_EnableIt()(respectively disabled in TRNG_IDR).\r
+ * This interrupt is set when a new random value is available and is cleared when the status \r
+ * register is read (TRNG_SR register). The flag DATRDY of the status register (TRNG_ISR) is set\r
+ * when the random data is ready to be read out on the 32-bit output data through TRNG_GetRandData().\r
+ *\r
+ * For more accurate information, please look at the SHA section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref trng.c\n\r
+ * \ref trng.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of True Random Number Generator (TRNG)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables the TRNG to provide Random Values.\r
+ * \param key This key is to be written when the ENABLE bit is set.\r
+ */\r
+void TRNG_Enable(void)\r
+{\r
+ TRNG->TRNG_CR = TRNG_CR_ENABLE | TRNG_CR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * \brief Disables the TRNG to provide Random Values.\r
+ * \param key This key is to be written when the DISABLE bit is set.\r
+ */\r
+void TRNG_Disable(void)\r
+{\r
+ TRNG->TRNG_CR = TRNG_CR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * \brief Data Ready Interrupt enable.\r
+ */\r
+void TRNG_EnableIt(void)\r
+{\r
+ TRNG->TRNG_IER = TRNG_IER_DATRDY;\r
+}\r
+\r
+/**\r
+ * \brief Data Ready Interrupt Disable.\r
+ */\r
+void TRNG_DisableIt(void)\r
+{\r
+ TRNG->TRNG_IDR = TRNG_IDR_DATRDY;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given TRNG peripheral.\r
+ * \return TRNG status register.\r
+ */\r
+uint32_t TRNG_GetStatus(void)\r
+{\r
+ return TRNG->TRNG_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Get the 32-bit Output Data from TRNG peripheral.\r
+ * \return TRNG output data.\r
+ */\r
+uint32_t TRNG_GetRandData(void)\r
+{\r
+ return TRNG->TRNG_ODATA;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup twi_module Working with TWI\r
+ * \ingroup peripherals_module\r
+ * The TWI driver provides the interface to configure and use the TWI\r
+ * peripheral.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Configures a TWI peripheral to operate in master mode, at the given\r
+ * frequency (in Hz) using TWI_Configure(). </li>\r
+ * <li> Sends a STOP condition on the TWI using TWI_Stop().</li>\r
+ * <li> Starts a read operation on the TWI bus with the specified slave using\r
+ * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever\r
+ * a byte is available (poll using TWI_ByteReceived()).</li>\r
+ * <li> Starts a write operation on the TWI to access the selected slave using\r
+ * TWI_StartWrite(). A byte of data must be provided to start the write;\r
+ * other bytes are written next.</li>\r
+ * <li> Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().\r
+ * This function must be called once before TWI_StartWrite() with the first byte of data\r
+ * to send, then it shall be called repeatedly after that to send the remaining bytes.</li>\r
+ * <li> Check if a byte has been received and can be read on the given TWI\r
+ * peripheral using TWI_ByteReceived().<\r
+ * Check if a byte has been sent using TWI_ByteSent().</li>\r
+ * <li> Check if the current transmission is complete (the STOP has been sent)\r
+ * using TWI_TransferComplete().</li>\r
+ * <li> Enables & disable the selected interrupts sources on a TWI peripheral\r
+ * using TWI_EnableIt() and TWI_DisableIt().</li>\r
+ * <li> Get current status register of the given TWI peripheral using\r
+ * TWI_GetStatus(). Get current status register of the given TWI peripheral, but\r
+ * masking interrupt sources which are not currently enabled using\r
+ * TWI_GetMaskedStatus().</li>\r
+ * </ul>\r
+ * For more accurate information, please look at the TWI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref twi.c\n\r
+ * \ref twi.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Two Wire Interface (TWI).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a TWI peripheral to operate in master mode, at the given\r
+ * frequency (in Hz). The duty cycle of the TWI clock is set to 50%.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param twck Desired TWI clock frequency.\r
+ * \param mck Master clock frequency.\r
+ */\r
+void TWI_ConfigureMaster( Twihs *pTwi, uint32_t dwTwCk, uint32_t dwMCk )\r
+{\r
+ uint32_t dwCkDiv = 0 ;\r
+ uint32_t dwClDiv ;\r
+ uint32_t dwOk = 0 ;\r
+\r
+ TRACE_DEBUG( "TWI_ConfigureMaster()\n\r" ) ;\r
+ assert( pTwi ) ;\r
+\r
+ /* SVEN: TWI Slave Mode Enabled */\r
+ pTwi->TWIHS_CR = TWIHS_CR_SVEN ;\r
+ /* Reset the TWI */\r
+ pTwi->TWIHS_CR = TWIHS_CR_SWRST ;\r
+ pTwi->TWIHS_RHR ;\r
+\r
+ /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */\r
+ pTwi->TWIHS_CR = TWIHS_CR_SVDIS ;\r
+ pTwi->TWIHS_CR = TWIHS_CR_MSDIS ;\r
+\r
+ /* Set master mode */\r
+ pTwi->TWIHS_CR = TWIHS_CR_MSEN ;\r
+\r
+ /* Configure clock */\r
+ while ( !dwOk )\r
+ {\r
+ dwClDiv = ((dwMCk / (2 * dwTwCk)) - 4) / (1<<dwCkDiv) ;\r
+\r
+ if ( dwClDiv <= 255 )\r
+ {\r
+ dwOk = 1 ;\r
+ }\r
+ else\r
+ {\r
+ dwCkDiv++ ;\r
+ }\r
+ }\r
+\r
+ assert( dwCkDiv < 8 ) ;\r
+ TRACE_DEBUG( "Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", dwCkDiv, dwClDiv ) ;\r
+\r
+ pTwi->TWIHS_CWGR = 0 ;\r
+ pTwi->TWIHS_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ;\r
+}\r
+\r
+/**\r
+ * \brief Configures a TWI peripheral to operate in slave mode.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param slaveAddress Slave address.\r
+ */\r
+void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress)\r
+{\r
+ uint32_t i;\r
+\r
+ /* TWI software reset */\r
+ pTwi->TWIHS_CR = TWIHS_CR_SWRST;\r
+ pTwi->TWIHS_RHR;\r
+\r
+ /* Wait at least 10 ms */\r
+ for (i=0; i < 1000000; i++);\r
+\r
+ /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/\r
+ pTwi->TWIHS_CR = TWIHS_CR_SVDIS | TWIHS_CR_MSDIS;\r
+\r
+ /* Configure slave address. */\r
+ pTwi->TWIHS_SMR = 0;\r
+ pTwi->TWIHS_SMR = TWIHS_SMR_SADR(slaveAddress);\r
+\r
+ /* SVEN: TWI Slave Mode Enabled */\r
+ pTwi->TWIHS_CR = TWIHS_CR_SVEN;\r
+\r
+ /* Wait at least 10 ms */\r
+ for (i=0; i < 1000000; i++);\r
+ assert( (pTwi->TWIHS_CR & TWIHS_CR_SVDIS)!= TWIHS_CR_SVDIS ) ;\r
+}\r
+\r
+/**\r
+ * \brief Sends a STOP condition on the TWI.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ */\r
+void TWI_Stop( Twihs *pTwi )\r
+{\r
+ assert( pTwi != NULL ) ;\r
+\r
+ pTwi->TWIHS_CR = TWIHS_CR_STOP;\r
+}\r
+\r
+/**\r
+ * \brief Starts a read operation on the TWI bus with the specified slave, it returns\r
+ * immediately. Data must then be read using TWI_ReadByte() whenever a byte is\r
+ * available (poll using TWI_ByteReceived()).\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param address Slave address on the bus.\r
+ * \param iaddress Optional internal address bytes.\r
+ * \param isize Number of internal address bytes.\r
+ */\r
+void TWI_StartRead(\r
+ Twihs *pTwi,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWIHS_MMR = 0;\r
+ pTwi->TWIHS_MMR = (isize << 8) | TWIHS_MMR_MREAD | (address << 16);\r
+\r
+ /* Set internal address bytes */\r
+ pTwi->TWIHS_IADR = 0;\r
+ pTwi->TWIHS_IADR = iaddress;\r
+\r
+ /* Send START condition */\r
+ pTwi->TWIHS_CR = TWIHS_CR_START;\r
+}\r
+\r
+/**\r
+ * \brief Reads a byte from the TWI bus. The read operation must have been started\r
+ * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()).\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \return byte read.\r
+ */\r
+uint8_t TWI_ReadByte(Twihs *pTwi)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+\r
+ return pTwi->TWIHS_RHR;\r
+}\r
+\r
+/**\r
+ * \brief Sends a byte of data to one of the TWI slaves on the bus.\r
+ * \note This function must be called once before TWI_StartWrite() with\r
+ * the first byte of data to send, then it shall be called repeatedly\r
+ * after that to send the remaining bytes.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param byte Byte to send.\r
+ */\r
+void TWI_WriteByte(Twihs *pTwi, uint8_t byte)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+\r
+ pTwi->TWIHS_THR = byte;\r
+}\r
+\r
+/**\r
+ * \brief Starts a write operation on the TWI to access the selected slave, then\r
+ * returns immediately. A byte of data must be provided to start the write;\r
+ * other bytes are written next.\r
+ * after that to send the remaining bytes.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param address Address of slave to acccess on the bus.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param byte First byte to send.\r
+ */\r
+void TWI_StartWrite(\r
+ Twihs *pTwi,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t byte)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWIHS_MMR = 0;\r
+ pTwi->TWIHS_MMR = (isize << 8) | (address << 16);\r
+\r
+ /* Set internal address bytes. */\r
+ pTwi->TWIHS_IADR = 0;\r
+ pTwi->TWIHS_IADR = iaddress;\r
+\r
+ /* Write first byte to send.*/\r
+ TWI_WriteByte(pTwi, byte);\r
+}\r
+\r
+/**\r
+ * \brief Check if a byte have been receiced from TWI.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \return 1 if a byte has been received and can be read on the given TWI\r
+ * peripheral; otherwise, returns 0. This function resets the status register.\r
+ */\r
+uint8_t TWI_ByteReceived(Twihs *pTwi)\r
+{\r
+ return ((pTwi->TWIHS_SR & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Check if a byte have been sent to TWI.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \return 1 if a byte has been sent so another one can be stored for\r
+ * transmission; otherwise returns 0. This function clears the status register.\r
+ */\r
+uint8_t TWI_ByteSent(Twihs *pTwi)\r
+{\r
+ return ((pTwi->TWIHS_SR & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Check if current transmission is complet.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \return 1 if the current transmission is complete (the STOP has been sent);\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t TWI_TransferComplete(Twihs *pTwi)\r
+{\r
+ return ((pTwi->TWIHS_SR & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP);\r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a TWI peripheral.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void TWI_EnableIt(Twihs *pTwi, uint32_t sources)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+ assert( (sources & 0xFFFFF088) == 0 ) ;\r
+\r
+ pTwi->TWIHS_IER = sources;\r
+}\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a TWI peripheral.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void TWI_DisableIt(Twihs *pTwi, uint32_t sources)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+ assert( (sources & 0xFFFFF088) == 0 ) ;\r
+\r
+ pTwi->TWIHS_IDR = sources;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given TWI peripheral.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ * \return TWI status register.\r
+ */\r
+uint32_t TWI_GetStatus(Twihs *pTwi)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+\r
+ return pTwi->TWIHS_SR;\r
+}\r
+\r
+/**\r
+ * \brief Returns the current status register of the given TWI peripheral, but\r
+ * masking interrupt sources which are not currently enabled.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ */\r
+uint32_t TWI_GetMaskedStatus(Twihs *pTwi)\r
+{\r
+ uint32_t status;\r
+\r
+ assert( pTwi != NULL ) ;\r
+\r
+ status = pTwi->TWIHS_SR;\r
+ status &= pTwi->TWIHS_IMR;\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Sends a STOP condition. STOP Condition is sent just after completing\r
+ * the current byte transmission in master read mode.\r
+ * \param pTwi Pointer to an Twihs instance.\r
+ */\r
+void TWI_SendSTOPCondition(Twihs *pTwi)\r
+{\r
+ assert( pTwi != NULL ) ;\r
+\r
+ pTwi->TWIHS_CR |= TWIHS_CR_STOP;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+#define TWITIMEOUTMAX 50000\r
+static sXdmad twi_dma;\r
+static sXdmadCfg twi_dmaCfg;\r
+static uint32_t dmaWriteChannel,dmaReadChannel;\r
+static LinkedListDescriporView1 dmaWriteLinkList[1];\r
+static LinkedListDescriporView1 dmaReadLinkList[1];\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** TWI driver callback function.*/\r
+typedef void (*TwiCallback)(Async *);\r
+\r
+/** \brief TWI asynchronous transfer descriptor.*/\r
+typedef struct _AsyncTwi {\r
+\r
+ /** Asynchronous transfer status. */\r
+ volatile uint8_t status;\r
+ // Callback function to invoke when transfer completes or fails.*/\r
+ TwiCallback callback;\r
+ /** Pointer to the data buffer.*/\r
+ uint8_t *pData;\r
+ /** Total number of bytes to transfer.*/\r
+ uint32_t num;\r
+ /** Number of already transferred bytes.*/\r
+ uint32_t transferred;\r
+\r
+} AsyncTwi;\r
+\r
+/**\r
+ * \brief Initializes a TWI DMA Read channel.\r
+ */\r
+static void TWID_DmaInitializeRead(uint8_t TWI_ID)\r
+{\r
+ \r
+ /* Allocate a XDMA channel, Read accesses into TWI_THR */\r
+ dmaReadChannel = XDMAD_AllocateChannel( &twi_dma, TWI_ID, XDMAD_TRANSFER_MEMORY);\r
+ if ( dmaReadChannel == XDMAD_ALLOC_FAILED )\r
+ {\r
+ printf("-E- Can't allocate XDMA channel\n\r");\r
+ }\r
+ XDMAD_PrepareChannel(&twi_dma, dmaReadChannel );\r
+}\r
+\r
+/**\r
+ * \brief Initializes a TWI DMA write channel.\r
+ */\r
+static void TWID_DmaInitializeWrite(uint8_t TWI_ID)\r
+{\r
+ \r
+ /* Allocate a XDMA channel, Write accesses into TWI_THR */\r
+ dmaWriteChannel = XDMAD_AllocateChannel( &twi_dma, XDMAD_TRANSFER_MEMORY, TWI_ID);\r
+ if ( dmaWriteChannel == XDMAD_ALLOC_FAILED )\r
+ {\r
+ printf("-E- Can't allocate XDMA channel\n\r");\r
+ }\r
+ XDMAD_PrepareChannel(&twi_dma, dmaWriteChannel );\r
+\r
+ \r
+}\r
+\r
+/**\r
+ * \brief Configure xDMA write linker list for TWI transfer.\r
+ */\r
+static void TWID_XdmaConfigureWrite(uint8_t *buf, uint32_t len, uint8_t TWI_ID)\r
+{\r
+ uint32_t i;\r
+ uint32_t xdmaCndc, Thr;\r
+ \r
+ Thr = (uint32_t)&(TWI0->TWIHS_THR);\r
+ if(TWI_ID==ID_TWI1)\r
+ {\r
+ Thr = (uint32_t)&(TWI1->TWIHS_THR);\r
+ }\r
+ if(TWI_ID==ID_TWI2)\r
+ {\r
+ Thr = (uint32_t)&(TWI2->TWIHS_THR);\r
+ }\r
+ for ( i = 0; i < 1; i++){\r
+ dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ |(( i == len - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)\r
+ | len ;\r
+ dmaWriteLinkList[i].mbr_sa = (uint32_t)&buf[i];\r
+ dmaWriteLinkList[i].mbr_da = Thr;\r
+ if ( i == len - 1) dmaWriteLinkList[i].mbr_nda = 0;\r
+ else dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[ i + 1 ];\r
+ }\r
+ twi_dmaCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_MEM2PER \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_SIF_AHB_IF0 \r
+ | XDMAC_CC_DIF_AHB_IF1 \r
+ | XDMAC_CC_SAM_INCREMENTED_AM \r
+ | XDMAC_CC_DAM_FIXED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(TWI_ID, XDMAD_TRANSFER_TX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED ;\r
+ memory_barrier();\r
+ XDMAD_ConfigureTransfer( &twi_dma, dmaWriteChannel, &twi_dmaCfg, xdmaCndc, (uint32_t)&dmaWriteLinkList[0]);\r
+ memory_barrier();\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure xDMA read linker list for TWI transfer.\r
+ */\r
+static void TWID_XdmaConfigureRead(uint8_t *buf, uint32_t len, uint8_t TWI_ID)\r
+{\r
+ uint32_t i;\r
+ uint32_t xdmaCndc, Rhr;\r
+ \r
+ Rhr = (uint32_t)&(TWI0->TWIHS_RHR);\r
+ if(TWI_ID==ID_TWI1)\r
+ {\r
+ Rhr = (uint32_t)&(TWI1->TWIHS_RHR);\r
+ }\r
+ if(TWI_ID==ID_TWI2)\r
+ {\r
+ Rhr = (uint32_t)&(TWI2->TWIHS_RHR);\r
+ }\r
+ for ( i = 0; i < 1; i++){\r
+ dmaReadLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 \r
+ | (( i == len - 1) ? 0: XDMA_UBC_NDE_FETCH_EN)\r
+ | len ;\r
+ dmaReadLinkList[i].mbr_sa = Rhr;\r
+ dmaReadLinkList[i].mbr_da = (uint32_t)&buf[i];\r
+ if ( i == len - 1)\r
+ dmaReadLinkList[i].mbr_nda = 0;\r
+ else\r
+ dmaReadLinkList[i].mbr_nda = (uint32_t)&dmaReadLinkList[ i + 1 ];\r
+ }\r
+ twi_dmaCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN \r
+ | XDMAC_CC_MBSIZE_SINGLE \r
+ | XDMAC_CC_DSYNC_PER2MEM \r
+ | XDMAC_CC_CSIZE_CHK_1 \r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_SIF_AHB_IF1 \r
+ | XDMAC_CC_DIF_AHB_IF0 \r
+ | XDMAC_CC_SAM_FIXED_AM \r
+ | XDMAC_CC_DAM_INCREMENTED_AM \r
+ | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(TWI_ID, XDMAD_TRANSFER_RX ));\r
+ xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 \r
+ | XDMAC_CNDC_NDE_DSCR_FETCH_EN \r
+ | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED\r
+ | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ;\r
+ memory_barrier();\r
+ XDMAD_ConfigureTransfer( &twi_dma, dmaReadChannel, &twi_dmaCfg, xdmaCndc, (uint32_t)&dmaReadLinkList[0]);\r
+ memory_barrier();\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * \brief Returns 1 if the given transfer has ended; otherwise returns 0.\r
+ * \param pAsync Pointer to an Async instance.\r
+ */\r
+uint32_t ASYNC_IsFinished( Async* pAsync )\r
+{\r
+ return (pAsync->status != ASYNC_STATUS_PENDING) ;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Initializes a TWI driver instance, using the given TWI peripheral.\r
+ * \note The peripheral must have been initialized properly before calling this function.\r
+ * \param pTwid Pointer to the Twid instance to initialize.\r
+ * \param pTwi Pointer to the TWI peripheral to use.\r
+ */\r
+void TWID_Initialize(Twid *pTwid, Twihs *pTwi)\r
+{\r
+ TRACE_DEBUG( "TWID_Initialize()\n\r" ) ;\r
+ assert( pTwid != NULL ) ;\r
+ assert( pTwi != NULL ) ;\r
+\r
+ /* Initialize driver. */\r
+ pTwid->pTwi = pTwi;\r
+ pTwid->pTransfer = 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer\r
+ * occuring on the bus. This function MUST be called by the interrupt service\r
+ * routine of the TWI peripheral if asynchronous read/write are needed.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ */\r
+void TWID_Handler( Twid *pTwid )\r
+{\r
+ uint8_t status;\r
+ AsyncTwi *pTransfer ;\r
+ Twihs *pTwi ;\r
+\r
+ assert( pTwid != NULL ) ;\r
+\r
+ pTransfer = (AsyncTwi*)pTwid->pTransfer ;\r
+ assert( pTransfer != NULL ) ;\r
+ pTwi = pTwid->pTwi ;\r
+ assert( pTwi != NULL ) ;\r
+\r
+ /* Retrieve interrupt status */\r
+ status = TWI_GetMaskedStatus(pTwi);\r
+\r
+ /* Byte received */\r
+ if (TWI_STATUS_RXRDY(status)) {\r
+\r
+ pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi);\r
+ pTransfer->transferred++;\r
+\r
+ /* check for transfer finish */\r
+ if (pTransfer->transferred == pTransfer->num) {\r
+\r
+ TWI_DisableIt(pTwi, TWIHS_IDR_RXRDY);\r
+ TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP);\r
+ }\r
+ /* Last byte? */\r
+ else if (pTransfer->transferred == (pTransfer->num - 1)) {\r
+\r
+ TWI_Stop(pTwi);\r
+ }\r
+ }\r
+ /* Byte sent*/\r
+ else if (TWI_STATUS_TXRDY(status)) {\r
+\r
+ /* Transfer finished ? */\r
+ if (pTransfer->transferred == pTransfer->num) {\r
+\r
+ TWI_DisableIt(pTwi, TWIHS_IDR_TXRDY);\r
+ TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP);\r
+ TWI_SendSTOPCondition(pTwi);\r
+ }\r
+ /* Bytes remaining */\r
+ else {\r
+\r
+ TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]);\r
+ pTransfer->transferred++;\r
+ }\r
+ }\r
+ /* Transfer complete*/\r
+ else if (TWI_STATUS_TXCOMP(status)) {\r
+\r
+ TWI_DisableIt(pTwi, TWIHS_IDR_TXCOMP);\r
+ pTransfer->status = 0;\r
+ if (pTransfer->callback) {\r
+\r
+ pTransfer->callback((Async *) pTransfer);\r
+ }\r
+ pTwid->pTransfer = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously reads data from a slave on the TWI bus. An optional\r
+ * callback function is triggered when the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Internal address size in bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Number of bytes to read.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t TWID_Read(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync)\r
+{\r
+ Twihs *pTwi;\r
+ AsyncTwi *pTransfer;\r
+ uint32_t timeout;\r
+\r
+ assert( pTwid != NULL ) ;\r
+ pTwi = pTwid->pTwi;\r
+ pTransfer = (AsyncTwi *) pTwid->pTransfer;\r
+\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+ /* Check that no transfer is already pending*/\r
+ if (pTransfer) {\r
+\r
+ TRACE_ERROR("TWID_Read: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Set STOP signal if only one byte is sent*/\r
+ if (num == 1) {\r
+\r
+ TWI_Stop(pTwi);\r
+ }\r
+\r
+ /* Asynchronous transfer*/\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (AsyncTwi *) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 0;\r
+\r
+ /* Enable read interrupt and start the transfer */\r
+ TWI_EnableIt(pTwi, TWIHS_IER_RXRDY);\r
+ TWI_StartRead(pTwi, address, iaddress, isize);\r
+ }\r
+ /* Synchronous transfer*/\r
+ else {\r
+\r
+ /* Start read*/\r
+ TWI_StartRead(pTwi, address, iaddress, isize);\r
+\r
+ /* Read all bytes, setting STOP before the last byte*/\r
+ while (num > 0) {\r
+\r
+ /* Last byte ?*/\r
+ if (num == 1) {\r
+\r
+ TWI_Stop(pTwi);\r
+ }\r
+\r
+ /* Wait for byte then read and store it*/\r
+ timeout = 0;\r
+ while( !TWI_ByteReceived(pTwi) && (++timeout<TWITIMEOUTMAX) );\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout BR\n\r");\r
+ }\r
+ *pData++ = TWI_ReadByte(pTwi);\r
+ num--;\r
+ }\r
+\r
+ /* Wait for transfer to be complete */\r
+ timeout = 0;\r
+ while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout TC\n\r");\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously sends data to a slave on the TWI bus. An optional callback\r
+ * function is invoked whenever the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Data buffer to send.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t TWID_Write(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync)\r
+{\r
+ Twihs *pTwi = pTwid->pTwi;\r
+ AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;\r
+ uint32_t timeout;\r
+\r
+ assert( pTwi != NULL ) ;\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+\r
+ TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (AsyncTwi *) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 1;\r
+\r
+ /* Enable write interrupt and start the transfer */\r
+ TWI_StartWrite(pTwi, address, iaddress, isize, *pData);\r
+ TWI_EnableIt(pTwi, TWIHS_IER_TXRDY);\r
+ }\r
+ /* Synchronous transfer*/\r
+ else {\r
+\r
+ // Start write\r
+ TWI_StartWrite(pTwi, address, iaddress, isize, *pData++);\r
+ num--;\r
+\r
+ /* Send all bytes */\r
+ while (num > 0) {\r
+\r
+ /* Wait before sending the next byte */\r
+ timeout = 0;\r
+ while( !TWI_ByteSent(pTwi) && (++timeout<TWITIMEOUTMAX) );\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout BS\n\r");\r
+ }\r
+\r
+ TWI_WriteByte(pTwi, *pData++);\r
+ num--;\r
+ }\r
+\r
+ /* Wait for actual end of transfer */\r
+ timeout = 0;\r
+\r
+ /* Send a STOP condition */\r
+ TWI_SendSTOPCondition(pTwi);\r
+\r
+ while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout TC2\n\r");\r
+ }\r
+\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Initializes a TWI driver instance, using the given TWI peripheral.\r
+ * \note The peripheral must have been initialized properly before calling this function.\r
+ * \param pTwid Pointer to the Twid instance to initialize.\r
+ * \param pTwi Pointer to the TWI peripheral to use.\r
+ */\r
+void TWID_DmaInitialize(Twid *pTwid, Twihs *pTwi)\r
+{\r
+ TRACE_DEBUG( "TWID_Initialize()\n\r" ) ;\r
+ assert( pTwid != NULL ) ;\r
+ assert( pTwi != NULL ) ;\r
+\r
+ /* Initialize driver. */\r
+ pTwid->pTwi = pTwi;\r
+ pTwid->pTransfer = 0;\r
+ \r
+ /* Initialize XDMA driver instance with polling mode */\r
+ XDMAD_Initialize( &twi_dma, 1 );\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously reads data from a slave on the TWI bus. An optional\r
+ * callback function is triggered when the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Internal address size in bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Number of bytes to read.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \param TWI_ID TWI ID for TWI0, TWI1, TWI2.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t TWID_DmaRead(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync,\r
+ uint8_t TWI_ID)\r
+{\r
+ Twihs *pTwi;\r
+ AsyncTwi *pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t status;\r
+\r
+ assert( pTwid != NULL ) ;\r
+ pTwi = pTwid->pTwi;\r
+ pTransfer = (AsyncTwi *) pTwid->pTransfer;\r
+\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+ /* Check that no transfer is already pending*/\r
+ if (pTransfer) {\r
+\r
+ TRACE_ERROR("TWID_Read: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer*/\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (AsyncTwi *) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 0;\r
+\r
+ /* Enable read interrupt and start the transfer */\r
+ TWI_EnableIt(pTwi, TWI_IER_RXRDY);\r
+ TWI_StartRead(pTwi, address, iaddress, isize);\r
+ }\r
+ /* Synchronous transfer*/\r
+ else {\r
+\r
+ TWID_DmaInitializeRead(TWI_ID);\r
+ TWID_XdmaConfigureRead(pData, num, TWI_ID);\r
+ /* Start read*/\r
+ XDMAD_StartTransfer( &twi_dma, dmaReadChannel );\r
+ \r
+ TWI_StartRead(pTwi, address, iaddress, isize); \r
+ \r
+ while((XDMAD_IsTransferDone(&twi_dma, dmaReadChannel)) && (++timeout<TWITIMEOUTMAX));\r
+ \r
+ XDMAD_StopTransfer( &twi_dma, dmaReadChannel );\r
+ \r
+ status = TWI_GetStatus(pTwi);\r
+ timeout=0;\r
+ while( !(status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX));\r
+ \r
+ TWI_Stop(pTwi);\r
+ \r
+ TWI_ReadByte(pTwi);\r
+ \r
+ status = TWI_GetStatus(pTwi);\r
+ timeout=0;\r
+ while( !(status & TWI_SR_RXRDY) && (++timeout<TWITIMEOUTMAX));\r
+ \r
+ TWI_ReadByte(pTwi);\r
+ \r
+ status = TWI_GetStatus(pTwi);\r
+ timeout=0;\r
+ while( !(status & TWI_SR_TXCOMP) && (++timeout<TWITIMEOUTMAX));\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout Read\n\r");\r
+ }\r
+ XDMAD_FreeChannel(&twi_dma, dmaReadChannel);\r
+\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Asynchronously sends data to a slave on the TWI bus. An optional callback\r
+ * function is invoked whenever the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Data buffer to send.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \param TWI_ID TWI ID for TWI0, TWI1, TWI2.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t TWID_DmaWrite(\r
+ Twid *pTwid,\r
+ uint8_t address,\r
+ uint32_t iaddress,\r
+ uint8_t isize,\r
+ uint8_t *pData,\r
+ uint32_t num,\r
+ Async *pAsync,\r
+ uint8_t TWI_ID)\r
+{\r
+ Twihs *pTwi = pTwid->pTwi;\r
+ AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t status;\r
+ //uint8_t singleTransfer = 0;\r
+ assert( pTwi != NULL ) ;\r
+ assert( (address & 0x80) == 0 ) ;\r
+ assert( (iaddress & 0xFF000000) == 0 ) ;\r
+ assert( isize < 4 ) ;\r
+\r
+// if(num == 1) singleTransfer = 1;\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+\r
+ TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (AsyncTwi *) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 1;\r
+\r
+ /* Enable write interrupt and start the transfer */\r
+ TWI_StartWrite(pTwi, address, iaddress, isize, *pData);\r
+ TWI_EnableIt(pTwi, TWI_IER_TXRDY);\r
+ }\r
+ /* Synchronous transfer*/\r
+ else {\r
+\r
+ TWID_DmaInitializeWrite(TWI_ID);\r
+ TWID_XdmaConfigureWrite(pData, num, TWI_ID);\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWIHS_MMR = 0;\r
+ pTwi->TWIHS_MMR = (isize << 8) | (address << 16);\r
+\r
+ /* Set internal address bytes. */\r
+ pTwi->TWIHS_IADR = 0;\r
+ pTwi->TWIHS_IADR = iaddress;\r
+ XDMAD_StartTransfer( &twi_dma, dmaWriteChannel );\r
+ \r
+ while(XDMAD_IsTransferDone(&twi_dma, dmaWriteChannel));\r
+ \r
+ XDMAD_StopTransfer( &twi_dma, dmaWriteChannel );\r
+ \r
+ status = TWI_GetStatus(pTwi);\r
+ timeout = 0;\r
+ while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) )\r
+ {\r
+ status = TWI_GetStatus(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout TXRDY\n\r");\r
+ }\r
+ \r
+ /* Send a STOP condition */\r
+ TWI_Stop(pTwi);\r
+ \r
+ status = TWI_GetStatus(pTwi);\r
+ timeout = 0;\r
+ while( !(status & TWI_SR_TXCOMP) && (++timeout<TWITIMEOUTMAX))\r
+ {\r
+ status = TWI_GetStatus(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ TRACE_ERROR("TWID Timeout Write\n\r");\r
+ }\r
+ \r
+ XDMAD_FreeChannel(&twi_dma, dmaWriteChannel);\r
+ \r
+ }\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of UART (Universal Asynchronous Receiver Transmitter)\r
+ * controller.\r
+ *\r
+ */\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures an UART peripheral with the specified parameters.\r
+ *\r
+ *\r
+ * \param uart Pointer to the UART peripheral to configure.\r
+ * \param mode Desired value for the UART mode register (see the datasheet).\r
+ * \param baudrate Baudrate at which the UART should operate (in Hz).\r
+ * \param masterClock Frequency of the system master clock (in Hz).\r
+ */\r
+void UART_Configure(Uart *uart,\r
+ uint32_t mode,\r
+ uint32_t baudrate,\r
+ uint32_t masterClock)\r
+{\r
+ /* Reset and disable receiver & transmitter*/\r
+ uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX\r
+ | UART_CR_RXDIS | UART_CR_TXDIS | UART_CR_RSTSTA;\r
+\r
+ uart->UART_IDR = 0xFFFFFFFF;\r
+\r
+ /* Configure mode*/\r
+ uart->UART_MR = mode;\r
+\r
+ /* Configure baudrate*/\r
+ uart->UART_BRGR = (masterClock / baudrate) / 16;\r
+\r
+ uart->UART_CR = UART_CR_TXEN | UART_CR_RXEN;\r
+\r
+}\r
+/**\r
+ * \brief Enables or disables the transmitter of an UART peripheral.\r
+ *\r
+ *\r
+ * \param uart Pointer to an UART peripheral\r
+ * \param enabled If true, the transmitter is enabled; otherwise it is\r
+ * disabled.\r
+ */\r
+void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ uart->UART_CR = UART_CR_TXEN;\r
+ }\r
+ else {\r
+\r
+ uart->UART_CR = UART_CR_TXDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the receiver of an UART peripheral\r
+ *\r
+ *\r
+ * \param uart Pointer to an UART peripheral\r
+ * \param enabled If true, the receiver is enabled; otherwise it is disabled.\r
+ */\r
+void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ uart->UART_CR = UART_CR_RXEN;\r
+ }\r
+ else {\r
+\r
+ uart->UART_CR = UART_CR_RXDIS;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return 1 if a character can be read in UART\r
+ * \param uart Pointer to an UART peripheral.\r
+ */\r
+uint32_t UART_IsRxReady(Uart *uart)\r
+{\r
+ return (uart->UART_SR & UART_SR_RXRDY);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reads and returns a character from the UART.\r
+ *\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \param uart Pointer to an UART peripheral.\r
+ * \return Character received.\r
+ */\r
+uint8_t UART_GetChar(Uart *uart)\r
+{\r
+ while (!UART_IsRxReady(uart));\r
+ return uart->UART_RHR;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return 1 if a character can be send to UART\r
+ * \param uart Pointer to an UART peripheral.\r
+ */\r
+uint32_t UART_IsTxReady(Uart *uart)\r
+{\r
+ return (uart->UART_SR & UART_SR_TXRDY);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return 1 if a character can be send to UART\r
+ * \param uart Pointer to an UART peripheral.\r
+ */\r
+static uint32_t UART_IsTxSent(Uart *uart)\r
+{\r
+ return (uart->UART_SR & UART_SR_TXEMPTY);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Sends one packet of data through the specified UART peripheral. This\r
+ * function operates synchronously, so it only returns when the data has been\r
+ * actually sent.\r
+ *\r
+ * \param uart Pointer to an UART peripheral.\r
+ * \param c Character to send\r
+ */\r
+void UART_PutChar( Uart *uart, uint8_t c)\r
+{\r
+ /* Wait for the transmitter to be ready*/\r
+ while (!UART_IsRxReady(uart) && !UART_IsTxSent(uart));\r
+\r
+ /* Send character*/\r
+ uart->UART_THR = c;\r
+\r
+ /* Wait for the transfer to complete*/\r
+ while (!UART_IsTxSent(uart));\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \brief Get present status\r
+ * \param uart Pointer to an UART peripheral.\r
+ */\r
+uint32_t UART_GetStatus(Uart *uart)\r
+{\r
+ return uart->UART_SR;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt\r
+ * \param uart Pointer to an UART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void UART_EnableIt(Uart *uart,uint32_t mode)\r
+{\r
+ uart->UART_IER = mode;\r
+}\r
+\r
+/**\r
+ * \brief Disable interrupt\r
+ * \param uart Pointer to an UART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void UART_DisableIt(Uart *uart,uint32_t mode)\r
+{\r
+ uart->UART_IDR = mode;\r
+}\r
+\r
+/**\r
+ * \brief Return interrupt mask\r
+ * \param uart Pointer to an UART peripheral.\r
+ */\r
+uint32_t UART_GetItMask(Uart *uart)\r
+{\r
+ return uart->UART_IMR;\r
+}\r
+\r
+void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen)\r
+{\r
+ uint8_t *pData = pBuffer;\r
+ uint32_t Len =0;\r
+\r
+ for(Len =0; Len<BuffLen; Len++ )\r
+ {\r
+ UART_PutChar(uart, *pData);\r
+ pData++;\r
+ }\r
+}\r
+\r
+void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen)\r
+{\r
+ uint32_t Len =0;\r
+\r
+ for(Len =0; Len<BuffLen; Len++ )\r
+ {\r
+ *pBuffer = UART_GetChar(uart);\r
+ pBuffer++;\r
+ }\r
+}\r
+\r
+\r
+void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2)\r
+{\r
+\r
+ uart->UART_CMPR = (UART_CMPR_VAL1(Val1) | UART_CMPR_VAL2(Val2));\r
+\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \addtogroup uart_dma_module UART xDMA driver\r
+ * \ingroup lib_uartflash\r
+ * \section Usage\r
+ *\r
+ * <ul>\r
+ * <li> UARTD_Configure() initializes and configures the UART peripheral and xDMA for data transfer.</li>\r
+ * <li> Configures the parameters for the device corresponding to the cs value by UARTD_ConfigureCS(). </li>\r
+ * <li> Starts a UART master transfer. This is a non blocking function UARTD_SendCommand(). It will\r
+ * return as soon as the transfer is started..</li>\r
+ * </ul>\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the UART Flash with xDMA driver.\r
+ *\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/** xDMA Link List size for uart transation*/\r
+#define DMA_UART_LLI 2\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief UART xDMA Rx callback\r
+ * Invoked on UART DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to UARTDma instance. \r
+ */ \r
+static void UARTD_Rx_Cb(uint32_t channel, UartDma* pArg)\r
+{\r
+\r
+ UartChannel *pUartdCh = pArg->pRxChannel;\r
+ if (channel != pUartdCh->ChNum)\r
+ return;\r
+\r
+ // NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum);\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pUartdCh && pUartdCh->callback) {\r
+ pUartdCh->callback(0, pUartdCh->pArgument);\r
+ } \r
+ pUartdCh->sempaphore = 1;\r
+}\r
+\r
+/**\r
+ * \brief USART xDMA Rx callback\r
+ * Invoked on USART DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to USARTDma instance. \r
+ */ \r
+static void UARTD_Tx_Cb(uint32_t channel, UartDma* pArg)\r
+{\r
+ UartChannel *pUartdCh = pArg->pTxChannel;\r
+ if (channel != pUartdCh->ChNum)\r
+ return;\r
+\r
+ // NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum);\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pUartdCh && pUartdCh->callback) {\r
+ pUartdCh->callback(0, pUartdCh->pArgument);\r
+ }\r
+ pUartdCh->sempaphore = 1;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the UART Rx DMA Destination with Linker List mode.\r
+ *\r
+ * \param UartChannel Pointer to UART dma channel\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * USARTD_ERROR_XXX.\r
+ */\r
+static uint8_t _configureRxLinkList(Uart *pUartHw, void *pXdmad, UartChannel *pUartRx)\r
+{\r
+ sXdmadCfg xdmadRxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t uartId;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART0 ) uartId = ID_UART0;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART1 ) uartId = ID_UART1;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART2 ) uartId = ID_UART2;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART3 ) uartId = ID_UART3;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART4 ) uartId = ID_UART4;\r
+\r
+ /* Setup RX Link List */\r
+ xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NDEN_UPDATED |\r
+ pUartRx->BuffSize;\r
+ xdmadRxCfg.mbr_da = (uint32_t)pUartRx->pBuff;\r
+\r
+ xdmadRxCfg.mbr_sa = (uint32_t)&pUartHw->UART_RHR;\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_PER2MEM |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE |\r
+ XDMAC_CC_SIF_AHB_IF1 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_FIXED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_RX ));\r
+\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ xdmadRxCfg.mbr_sus = 0;\r
+ xdmadRxCfg.mbr_dus =0;\r
+ xdmaCndc = 0;\r
+ if (XDMAD_ConfigureTransfer( pXdmad, pUartRx->ChNum, &xdmadRxCfg, xdmaCndc, 0))\r
+ return USARTD_ERROR;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the UART tx DMA source with Linker List mode.\r
+ *\r
+ * \param UartChannel Pointer to UART dma channel\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * USARTD_ERROR_XXX.\r
+ */\r
+static uint8_t _configureTxLinkList(Uart *pUartHw, void *pXdmad, UartChannel *pUartTx)\r
+{\r
+ sXdmadCfg xdmadTxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t uartId;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART0 ) uartId = ID_UART0;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART1 ) uartId = ID_UART1;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART2 ) uartId = ID_UART2;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART3 ) uartId = ID_UART3;\r
+ if ((unsigned int)pUartHw == (unsigned int)UART4 ) uartId = ID_UART4;\r
+\r
+ /* Setup TX Link List */ \r
+ xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NSEN_UPDATED | pUartTx->BuffSize;\r
+\r
+ xdmadTxCfg.mbr_sa = (uint32_t)pUartTx->pBuff;\r
+ xdmadTxCfg.mbr_da = (uint32_t)&pUartHw->UART_THR;\r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_MEM2PER |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF1 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_FIXED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_TX ));\r
+\r
+ xdmadTxCfg.mbr_bc = 0;\r
+ xdmadTxCfg.mbr_sus = 0;\r
+ xdmadTxCfg.mbr_dus =0;\r
+ xdmaCndc = 0;\r
+\r
+ if (XDMAD_ConfigureTransfer( pXdmad, pUartTx->ChNum, &xdmadTxCfg, xdmaCndc, 0))\r
+ return USARTD_ERROR;\r
+ return 0;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initializes the UartDma structure and the corresponding UART & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no UART command processing.\r
+ *\r
+ * \param pUartd Pointer to a UartDma instance.\r
+ * \param pUartHw Associated UART peripheral.\r
+ * \param uartId UART peripheral identifier.\r
+ * \param pXdmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t UARTD_Configure( UartDma *pUartd ,\r
+ Uart *pUartHw ,\r
+ uint8_t uartId,\r
+ uint32_t UartMode,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the UART structure */\r
+ pUartd->pUartHw = pUartHw;\r
+ pUartd->uartId = uartId;\r
+ pUartd->pTxChannel = 0;\r
+ pUartd->pRxChannel = 0;\r
+ pUartd->pXdmad = pXdmad;\r
+\r
+ /* Enable the UART Peripheral ,Execute a software reset of the UART, Configure UART in Master Mode*/\r
+ UART_Configure ( pUartHw, UartMode, 115200, BOARD_MCK);\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pUartd->pXdmad, 0 );\r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_SetPriority( XDMAC_IRQn ,1);\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enables USART Rx DMA channel\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no USART command processing.\r
+ *\r
+ * \param pUSARTd Pointer to a UartDma instance.\r
+ * \param pUartHw Associated USART peripheral.\r
+ * \param uartId USART peripheral identifier.\r
+ * \param UartClk USART clock.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+\r
+uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh)\r
+{\r
+ Uart *pUartHw = pUartd->pUartHw;\r
+ uint32_t Channel;\r
+\r
+ // Initialize the callback\r
+ pUartd->pRxChannel = pRxCh;\r
+\r
+ /* Enables the USART to receive data. */\r
+ UART_SetReceiverEnabled ( pUartHw , 1);\r
+\r
+ XDMAD_FreeChannel( pUartd->pXdmad, pRxCh->ChNum);\r
+\r
+ /* Allocate a DMA channel for UART0/1 RX. */\r
+ Channel = XDMAD_AllocateChannel( pUartd->pXdmad, pUartd->uartId, XDMAD_TRANSFER_MEMORY);\r
+ if ( Channel == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return USARTD_ERROR;\r
+ }\r
+\r
+ pRxCh->ChNum = Channel ;\r
+\r
+ /* Setup callbacks for UART0/1 RX */\r
+ XDMAD_SetCallback(pUartd->pXdmad, pRxCh->ChNum, (XdmadTransferCallback)UARTD_Rx_Cb, pUartd);\r
+ if (XDMAD_PrepareChannel( pUartd->pXdmad, pRxCh->ChNum ))\r
+ return USARTD_ERROR;\r
+\r
+ /* Enable interrupt */ \r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+ if (_configureRxLinkList(pUartHw, pUartd->pXdmad, pRxCh))\r
+ return USARTD_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh)\r
+{\r
+ Uart *pUartHw = pUartd->pUartHw;\r
+ uint32_t Channel;\r
+\r
+ // Initialize the callback\r
+ pUartd->pTxChannel = pTxCh;\r
+\r
+ /* Enables the USART to transfer data. */\r
+ UART_SetTransmitterEnabled ( pUartHw , 1);\r
+\r
+ XDMAD_FreeChannel( pUartd->pXdmad, pTxCh->ChNum);\r
+\r
+ /* Allocate a DMA channel for USART0/1 TX. */\r
+ Channel = XDMAD_AllocateChannel( pUartd->pXdmad, XDMAD_TRANSFER_MEMORY, pUartd->uartId);\r
+ if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return USARTD_ERROR;\r
+ }\r
+\r
+ pTxCh->ChNum = Channel ;\r
+\r
+ /* Setup callbacks for USART0/1 TX */\r
+ XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)UARTD_Tx_Cb, pUartd);\r
+ if ( XDMAD_PrepareChannel( pUartd->pXdmad, pTxCh->ChNum ))\r
+ return USARTD_ERROR;\r
+\r
+ /* Enable interrupt */ \r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+ if (_configureTxLinkList(pUartHw, pUartd->pXdmad, pTxCh))\r
+ return USARTD_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a USART master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pUSARTd Pointer to a USARTDma instance.\r
+ * \param pCommand Pointer to the USART command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t UARTD_SendData( UartDma *pUartd)\r
+{\r
+\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ while(!pUartd->pTxChannel->sempaphore);\r
+ if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pTxChannel->ChNum )) \r
+ return USARTD_ERROR_LOCK;\r
+ pUartd->pTxChannel->sempaphore=0;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a USART master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pUSARTd Pointer to a USARTDma instance.\r
+ * \param pCommand Pointer to the USART command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t UARTD_RcvData( UartDma *pUartd)\r
+{ \r
+\r
+ while(!pUartd->pRxChannel->sempaphore);\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pRxChannel->ChNum )) \r
+ return USARTD_ERROR_LOCK;\r
+ pUartd->pRxChannel->sempaphore=0;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)\r
+ * controller.\r
+ *\r
+ */\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures an USART peripheral with the specified parameters.\r
+ *\r
+ *\r
+ * \param usart Pointer to the USART peripheral to configure.\r
+ * \param mode Desired value for the USART mode register (see the datasheet).\r
+ * \param baudrate Baudrate at which the USART should operate (in Hz).\r
+ * \param masterClock Frequency of the system master clock (in Hz).\r
+ */\r
+void USART_Configure(Usart *pUsart,\r
+ uint32_t mode,\r
+ uint32_t baudrate,\r
+ uint32_t masterClock)\r
+{\r
+ \r
+ unsigned int CD, FP, BaudError, OVER, ActualBaudRate;\r
+ \r
+ /* Reset and disable receiver & transmitter*/\r
+ pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX\r
+ | US_CR_RXDIS | US_CR_TXDIS | US_CR_RSTSTA;\r
+ \r
+ pUsart->US_IDR = 0xFFFFFFFF;\r
+ \r
+ /* Configure baudrate*/ \r
+ BaudError = 10;\r
+ OVER = 0;\r
+ \r
+ // Configure baud rate\r
+ while (BaudError > 5)\r
+ {\r
+ \r
+ CD = (masterClock / (baudrate * 8*(2-OVER)));\r
+ FP = ((masterClock / (baudrate * (2-OVER)) ) - CD * 8); \r
+ ActualBaudRate = (masterClock/(CD*8 + FP))/(2-OVER);\r
+ BaudError = (100-((baudrate*100/ActualBaudRate)));\r
+ \r
+ if (BaudError > 5)\r
+ {\r
+ OVER++;\r
+ if(OVER>=2)\r
+ {\r
+ assert( 0 ) ;\r
+ }\r
+ }\r
+ }\r
+ \r
+ pUsart->US_BRGR = ( US_BRGR_CD(CD) | US_BRGR_FP(FP));\r
+ \r
+ /* Configure mode*/\r
+ pUsart->US_MR = (mode | (OVER << 19) );\r
+\r
+ // Enable receiver and transmitter\r
+ pUsart->US_CR = US_CR_RXEN | US_CR_TXEN;\r
+ \r
+\r
+ /* Disable buffering for printf(). */\r
+#if ( defined (__GNUC__) && !defined (__SAMBA__) )\r
+ setvbuf(stdout, (char *)NULL, _IONBF, 0);\r
+#endif\r
+\r
+}\r
+/**\r
+ * \brief Enables or disables the transmitter of an USART peripheral.\r
+ *\r
+ *\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the transmitter is enabled; otherwise it is\r
+ * disabled.\r
+ */\r
+void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ usart->US_CR = US_CR_TXEN;\r
+ }\r
+ else {\r
+\r
+ usart->US_CR = US_CR_TXDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the receiver of an USART peripheral\r
+ *\r
+ *\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the receiver is enabled; otherwise it is disabled.\r
+ */\r
+void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+\r
+ usart->US_CR = US_CR_RXEN;\r
+ }\r
+ else {\r
+\r
+ usart->US_CR = US_CR_RXDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the Request To Send (RTS) of an USART peripheral\r
+ *\r
+ *\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the RTS is enabled (0); otherwise it is disabled.\r
+ */\r
+void USART_SetRTSEnabled( Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+ \r
+ usart->US_CR = US_CR_RTSEN;\r
+ }\r
+ else {\r
+ \r
+ usart->US_CR = US_CR_RTSDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sends one packet of data through the specified USART peripheral. This\r
+ * function operates synchronously, so it only returns when the data has been\r
+ * actually sent.\r
+ *\r
+ *\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param data Data to send including 9nth bit and sync field if necessary (in\r
+ * the same format as the US_THR register in the datasheet).\r
+ * \param timeOut Time out value (0 = no timeout).\r
+ */\r
+void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut)\r
+{\r
+ if (timeOut == 0) {\r
+\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);\r
+ }\r
+ else {\r
+\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {\r
+\r
+ if (timeOut == 0) {\r
+\r
+ TRACE_ERROR("USART_Write: Timed out.\n\r");\r
+ return;\r
+ }\r
+ timeOut--;\r
+ }\r
+ }\r
+\r
+ usart->US_THR = data;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Reads and return a packet of data on the specified USART peripheral. This\r
+ * function operates asynchronously, so it waits until some data has been\r
+ * received.\r
+ *\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param timeOut Time out value (0 -> no timeout).\r
+ */\r
+uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut)\r
+{\r
+ if (timeOut == 0) {\r
+\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0);\r
+ }\r
+ else {\r
+\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0) {\r
+\r
+ if (timeOut == 0) {\r
+\r
+ TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ;\r
+ return 0;\r
+ }\r
+ timeOut--;\r
+ }\r
+ }\r
+\r
+ return usart->US_RHR;\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if some data has been received and can be read from an USART;\r
+ * otherwise returns 0.\r
+ *\r
+ * \param usart Pointer to an Usart instance.\r
+ */\r
+uint8_t USART_IsDataAvailable(Usart *usart)\r
+{\r
+ if ((usart->US_CSR & US_CSR_RXRDY) != 0) {\r
+\r
+ return 1;\r
+ }\r
+ else {\r
+\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Sets the filter value for the IRDA demodulator.\r
+ *\r
+ * \param pUsart Pointer to an Usart instance.\r
+ * \param filter Filter value.\r
+ */\r
+void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)\r
+{\r
+ assert( pUsart != NULL ) ;\r
+\r
+ pUsart->US_IF = filter;\r
+}\r
+\r
+/**\r
+ * \brief Sends one packet of data through the specified USART peripheral. This\r
+ * function operates synchronously, so it only returns when the data has been\r
+ * actually sent.\r
+ *\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param c Character to send\r
+ */\r
+void USART_PutChar( Usart *usart, uint8_t c)\r
+{\r
+ /* Wait for the transmitter to be ready*/\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);\r
+\r
+ /* Send character*/\r
+ usart->US_THR = c;\r
+\r
+ /* Wait for the transfer to complete*/\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if a character can be read in USART\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t USART_IsRxReady(Usart *usart)\r
+{\r
+ return (usart->US_CSR & US_CSR_RXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Get present status\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t USART_GetStatus(Usart *usart)\r
+{\r
+ return usart->US_CSR;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void USART_EnableIt(Usart *usart,uint32_t mode)\r
+{\r
+ usart->US_IER = mode;\r
+}\r
+\r
+/**\r
+ * \brief Disable interrupt\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void USART_DisableIt(Usart *usart,uint32_t mode)\r
+{\r
+ usart->US_IDR = mode;\r
+}\r
+\r
+/**\r
+ * \brief Return interrupt mask\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t USART_GetItMask(Usart *usart)\r
+{\r
+ return usart->US_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns a character from the USART.\r
+ *\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \return Character received.\r
+ */\r
+uint8_t USART_GetChar(Usart *usart)\r
+{\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0);\r
+ return usart->US_RHR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \addtogroup usart_dma_module USART xDMA driver\r
+ * \section Usage\r
+ *\r
+ * <ul>\r
+ * <li> USARTD_Configure() initializes and configures the USART peripheral and xDMA for data transfer.</li>\r
+ * <li> Configures the parameters for the device corresponding to the cs value by USARTD_ConfigureCS(). </li>\r
+ * </ul>\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation for the USART with xDMA driver.\r
+ *\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/** xDMA Link List size for usart transmition*/\r
+#define DMA_USART_LLI 2\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief USART xDMA Rx callback\r
+ * Invoked on USART DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to USARTDma instance. \r
+ */ \r
+static void USARTD_Rx_Cb(uint32_t channel, UsartDma* pArg)\r
+{\r
+\r
+ UsartChannel *pUsartdCh = pArg->pRxChannel;\r
+ if (channel != pUsartdCh->ChNum)\r
+ return;\r
+\r
+ // NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, pUsartdCh->ChNum);\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pUsartdCh && pUsartdCh->callback) {\r
+ pUsartdCh->callback(0, pUsartdCh->pArgument);\r
+ } \r
+ pUsartdCh->Done = 1;\r
+ memory_barrier();\r
+}\r
+\r
+/**\r
+ * \brief USART xDMA Rx callback\r
+ * Invoked on USART DMA reception done.\r
+ * \param channel DMA channel.\r
+ * \param pArg Pointer to callback argument - Pointer to USARTDma instance. \r
+ */ \r
+static void USARTD_Tx_Cb(uint32_t channel, UsartDma* pArg)\r
+{\r
+ UsartChannel *pUsartdCh = pArg->pTxChannel;\r
+ if (channel != pUsartdCh->ChNum)\r
+ return;\r
+\r
+ // NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+\r
+ /* Release the DMA channels */\r
+ XDMAD_FreeChannel(pArg->pXdmad, pUsartdCh->ChNum);\r
+\r
+ /* Invoke the callback associated with the current command */\r
+ if (pUsartdCh && pUsartdCh->callback) {\r
+ pUsartdCh->callback(0, pUsartdCh->pArgument);\r
+ }\r
+ pUsartdCh->Done = 1;\r
+ memory_barrier();\r
+}\r
+\r
+/**\r
+ * \brief Configure the USART Rx DMA Destination with Linker List mode.\r
+ *\r
+ * \param UsartChannel Pointer to USART dma channel\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * USARTD_ERROR_XXX.\r
+ */\r
+static uint8_t _configureRxLinkList(Usart *pUsartHw, void *pXdmad, UsartChannel *pUsartRx)\r
+{\r
+ sXdmadCfg xdmadRxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t usartId;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART0 ) usartId = ID_USART0;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART1 ) usartId = ID_USART1;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART2 ) usartId = ID_USART2;\r
+\r
+ /* Setup RX Link List */\r
+ xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NDEN_UPDATED |\r
+ pUsartRx->BuffSize;\r
+ xdmadRxCfg.mbr_da = (uint32_t)pUsartRx->pBuff;\r
+\r
+ xdmadRxCfg.mbr_sa = (uint32_t)&pUsartHw->US_RHR;\r
+ xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_PER2MEM |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE |\r
+ XDMAC_CC_SIF_AHB_IF1 |\r
+ XDMAC_CC_DIF_AHB_IF0 |\r
+ XDMAC_CC_SAM_FIXED_AM |\r
+ XDMAC_CC_DAM_INCREMENTED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( usartId, XDMAD_TRANSFER_RX ));\r
+\r
+ xdmadRxCfg.mbr_bc = 0;\r
+ xdmadRxCfg.mbr_sus = 0;\r
+ xdmadRxCfg.mbr_dus =0;\r
+ xdmaCndc = 0;\r
+ if (XDMAD_ConfigureTransfer( pXdmad, pUsartRx->ChNum, &xdmadRxCfg, xdmaCndc, 0))\r
+ return USARTD_ERROR;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure the USART tx DMA source with Linker List mode.\r
+ *\r
+ * \param UsartChannel Pointer to USART dma channel\r
+ * \returns 0 if the dma multibuffer configuration successfully; otherwise returns\r
+ * USARTD_ERROR_XXX.\r
+ */\r
+static uint8_t _configureTxLinkList(Usart *pUsartHw, void *pXdmad, UsartChannel *pUsartTx)\r
+{\r
+ sXdmadCfg xdmadTxCfg;\r
+ uint32_t xdmaCndc;\r
+ uint32_t usartId;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART0 ) usartId = ID_USART0;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART1 ) usartId = ID_USART1;\r
+ if ((unsigned int)pUsartHw == (unsigned int)USART2 ) usartId = ID_USART2;\r
+ /* Setup TX Link List */ \r
+ xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |\r
+ XDMA_UBC_NDE_FETCH_DIS|\r
+ XDMA_UBC_NSEN_UPDATED | pUsartTx->BuffSize;\r
+\r
+ xdmadTxCfg.mbr_sa = (uint32_t)pUsartTx->pBuff;\r
+ xdmadTxCfg.mbr_da = (uint32_t)&pUsartHw->US_THR;\r
+ xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |\r
+ XDMAC_CC_MBSIZE_SINGLE |\r
+ XDMAC_CC_DSYNC_MEM2PER |\r
+ XDMAC_CC_CSIZE_CHK_1 |\r
+ XDMAC_CC_DWIDTH_BYTE|\r
+ XDMAC_CC_SIF_AHB_IF0 |\r
+ XDMAC_CC_DIF_AHB_IF1 |\r
+ XDMAC_CC_SAM_INCREMENTED_AM |\r
+ XDMAC_CC_DAM_FIXED_AM |\r
+ XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( usartId, XDMAD_TRANSFER_TX ));\r
+\r
+ xdmadTxCfg.mbr_bc = 0;\r
+ xdmadTxCfg.mbr_sus = 0;\r
+ xdmadTxCfg.mbr_dus =0;\r
+ xdmaCndc = 0;\r
+\r
+ if (XDMAD_ConfigureTransfer( pXdmad, pUsartTx->ChNum, &xdmadTxCfg, xdmaCndc, 0))\r
+ return USARTD_ERROR;\r
+ return 0;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initializes the USARTDma structure and the corresponding USART & DMA hardware.\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no USART command processing.\r
+ *\r
+ * \param pUSARTd Pointer to a UsartDma instance.\r
+ * \param pUsartHw Associated USART peripheral.\r
+ * \param usartId USART peripheral identifier.\r
+ * \param UsartClk USART clock.\r
+ * \param pXdmad Pointer to a Dmad instance. \r
+ */\r
+uint32_t USARTD_Configure( UsartDma *pUsartd ,\r
+ Usart *pUsartHw ,\r
+ uint8_t usartId,\r
+ uint32_t UsartMode,\r
+ uint32_t UsartClk,\r
+ sXdmad *pXdmad )\r
+{\r
+ /* Initialize the USART structure */\r
+ pUsartd->pUsartHw = pUsartHw;\r
+ pUsartd->usartId = usartId;\r
+ pUsartd->pRxChannel = 0;\r
+ pUsartd->pTxChannel = 0;\r
+ pUsartd->pXdmad = pXdmad;\r
+\r
+ /* Enable the USART Peripheral ,Execute a software reset of the USART, Configure USART in Master Mode*/\r
+ USART_Configure ( pUsartHw, UsartMode, UsartClk, BOARD_MCK);\r
+\r
+ /* Driver initialize */\r
+ XDMAD_Initialize( pUsartd->pXdmad, 0 );\r
+ /* Configure and enable interrupt on RC compare */ \r
+ NVIC_ClearPendingIRQ(XDMAC_IRQn);\r
+ NVIC_SetPriority( XDMAC_IRQn ,1);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enables USART Rx DMA channel\r
+ * select value.\r
+ * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.\r
+ * The DMA channels are freed automatically when no USART command processing.\r
+ *\r
+ * \param pUSARTd Pointer to a UsartDma instance.\r
+ * \param pUsartHw Associated USART peripheral.\r
+ * \param usartId USART peripheral identifier.\r
+ * \param UsartClk USART clock.\r
+ * \param pDmad Pointer to a Dmad instance. \r
+ */\r
+\r
+uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh)\r
+{\r
+ Usart *pUsartHw = pUsartd->pUsartHw;\r
+\r
+ // Initialize the callback\r
+ pUsartd->pRxChannel = pRxCh;\r
+\r
+ /* Enables the USART to receive data. */\r
+ USART_SetReceiverEnabled ( pUsartHw , 1);\r
+\r
+ XDMAD_FreeChannel( pUsartd->pXdmad, pRxCh->ChNum);\r
+\r
+ /* Allocate a DMA channel for USART0/1 RX. */\r
+ pRxCh->ChNum = XDMAD_AllocateChannel( pUsartd->pXdmad, pUsartd->usartId, XDMAD_TRANSFER_MEMORY);\r
+ if ( pRxCh->ChNum == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return USARTD_ERROR;\r
+ }\r
+\r
+ /* Setup callbacks for USART0/1 RX */\r
+ XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, (XdmadTransferCallback)USARTD_Rx_Cb, pUsartd);\r
+ if (XDMAD_PrepareChannel( pUsartd->pXdmad, pRxCh->ChNum ))\r
+ return USARTD_ERROR;\r
+\r
+ /* Enable interrupt */ \r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+ if (_configureRxLinkList(pUsartHw, pUsartd->pXdmad, pRxCh))\r
+ return USARTD_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+uint32_t USARTD_EnableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh)\r
+{\r
+ Usart *pUsartHw = pUsartd->pUsartHw;\r
+\r
+ // Initialize the callback\r
+ pUsartd->pTxChannel = pTxCh;\r
+\r
+ /* Enables the USART to transfer data. */\r
+ USART_SetTransmitterEnabled ( pUsartHw , 1); \r
+\r
+ XDMAD_FreeChannel( pUsartd->pXdmad, pTxCh->ChNum);\r
+\r
+ /* Allocate a DMA channel for USART0/1 TX. */\r
+ pTxCh->ChNum = XDMAD_AllocateChannel( pUsartd->pXdmad, XDMAD_TRANSFER_MEMORY, pUsartd->usartId);\r
+ if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED ) \r
+ {\r
+ return USARTD_ERROR;\r
+ }\r
+\r
+ /* Setup callbacks for USART0/1 TX */\r
+ XDMAD_SetCallback(pUsartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)USARTD_Tx_Cb, pUsartd);\r
+ if ( XDMAD_PrepareChannel( pUsartd->pXdmad, pTxCh->ChNum ))\r
+ return USARTD_ERROR;\r
+\r
+ /* Enable interrupt */ \r
+ NVIC_EnableIRQ(XDMAC_IRQn);\r
+\r
+ if (_configureTxLinkList(pUsartHw, pUsartd->pXdmad, pTxCh))\r
+ return USARTD_ERROR_LOCK;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a USART master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pUSARTd Pointer to a USARTDma instance.\r
+ * \param pCommand Pointer to the USART command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t USARTD_SendData( UsartDma *pUsartd)\r
+{\r
+\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ while(!pUsartd->pTxChannel->Done);\r
+ if (XDMAD_StartTransfer( pUsartd->pXdmad, pUsartd->pTxChannel->ChNum )) \r
+ return USARTD_ERROR_LOCK;\r
+ pUsartd->pTxChannel->Done=0;\r
+ memory_barrier();\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Starts a USART master transfer. This is a non blocking function. It will\r
+ * return as soon as the transfer is started.\r
+ *\r
+ * \param pUSARTd Pointer to a USARTDma instance.\r
+ * \param pCommand Pointer to the USART command to execute.\r
+ * \returns 0 if the transfer has been started successfully; otherwise returns\r
+ * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not\r
+ * valid.\r
+ */\r
+uint32_t USARTD_RcvData( UsartDma *pUsartd)\r
+{ \r
+\r
+ while(!pUsartd->pRxChannel->Done);\r
+ /* Start DMA 0(RX) && 1(TX) */\r
+ if (XDMAD_StartTransfer( pUsartd->pXdmad, pUsartd->pRxChannel->ChNum )) \r
+ return USARTD_ERROR_LOCK;\r
+ pUsartd->pRxChannel->Done=0;\r
+ memory_barrier();\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Watchdog Timer (WDT) controller.\r
+ *\r
+ */\r
+\r
+/** \addtogroup wdt_module Working with WDT\r
+ * \ingroup peripherals_module\r
+ * The WDT driver provides the interface to configure and use the WDT\r
+ * peripheral.\r
+ *\r
+ * The WDT can be used to prevent system lock-up if the software becomes\r
+ * trapped in a deadlock. It can generate a general reset or a processor\r
+ * reset only. It is clocked by slow clock divided by 128.\r
+ *\r
+ * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)\r
+ * and external reset generation enabled. The user must either disable it or\r
+ * reprogram it to meet the application requires.\r
+ *\r
+ * To use the WDT, the user could follow these few steps:\r
+ * <ul>\r
+ * <li>Enable watchdog with given mode using \ref WDT_Enable().\r
+ * <li>Restart the watchdog using \ref WDT_Restart() within the watchdog period.\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the WDT section of the\r
+ * Datasheet.\r
+ *\r
+ * \note\r
+ * The Watchdog Mode Register (WDT_MR) can be written only once.\n\r
+ *\r
+ * Related files :\n\r
+ * \ref wdt.c\n\r
+ * \ref wdt.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enable watchdog with given mode.\r
+ *\r
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.\r
+ * Only a processor reset resets it.\r
+ *\r
+ * \param dwMode WDT mode to be set\r
+ */\r
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode )\r
+{\r
+ pWDT->WDT_MR = dwMode ;\r
+}\r
+\r
+/**\r
+ * \brief Disable watchdog.\r
+ *\r
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.\r
+ * Only a processor reset resets it.\r
+ */\r
+extern void WDT_Disable( Wdt* pWDT )\r
+{\r
+ pWDT->WDT_MR = WDT_MR_WDDIS;\r
+}\r
+\r
+/**\r
+ * \brief Watchdog restart.\r
+ */\r
+extern void WDT_Restart( Wdt* pWDT )\r
+{\r
+ pWDT->WDT_CR = 0xA5000001;\r
+}\r
+\r
+/**\r
+ * \brief Watchdog get status.\r
+ */\r
+extern uint32_t WDT_GetStatus( Wdt* pWDT )\r
+{\r
+ return (pWDT->WDT_SR & 0x3) ;\r
+}\r
+\r
+/**\r
+ * \brief Watchdog get period.\r
+ *\r
+ * \param dwMs desired watchdog period in millisecond.\r
+ */\r
+extern uint32_t WDT_GetPeriod( uint32_t dwMs )\r
+{\r
+ if ( (dwMs < 4) || (dwMs > 16000) )\r
+ {\r
+ return 0 ;\r
+ }\r
+ return ((dwMs << 8) / 1000) ;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup dmad_module\r
+ *\r
+ * \section DmaHw Dma Hardware Interface Usage\r
+ * <ul>\r
+ * <li> The DMA controller can handle the transfer between peripherals and memory \r
+ * and so receives the triggers from the peripherals. The hardware interface number\r
+ * are getting from DMAIF_Get_ChannelNumber().</li>\r
+\r
+ * <li> DMAIF_IsValidatedPeripherOnDma() helps to check if the given DMAC has associated \r
+ * peripheral identifier coded by the given peripheral.</li>\r
+ * \r
+ * </ul>\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/** \file */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <board.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+/** Array of DMA Channel definition for SAMv7 chip*/\r
+static const XdmaHardwareInterface xdmaHwIf[] = {\r
+ /* dmac, peripheral, T/R, Channel Number*/\r
+ {0, ID_HSMCI, 0, 0},\r
+ {0, ID_HSMCI, 1, 0},\r
+ {0, ID_SPI0, 0, 1},\r
+ {0, ID_SPI0, 1, 2},\r
+ {0, ID_SPI1, 0, 3},\r
+ {0, ID_SPI1, 1, 4},\r
+ {0, ID_QSPI, 0, 5},\r
+ {0, ID_QSPI, 1, 6},\r
+ {0, ID_USART0, 0, 7},\r
+ {0, ID_USART0, 1, 8},\r
+ {0, ID_USART1, 0, 9},\r
+ {0, ID_USART1, 1, 10},\r
+ {0, ID_USART2, 0, 11},\r
+ {0, ID_USART2, 1, 12},\r
+ {0, ID_PWM0, 0, 13},\r
+ {0, ID_TWI0, 0, 14},\r
+ {0, ID_TWI0, 1, 15},\r
+ {0, ID_TWI1, 0, 16},\r
+ {0, ID_TWI1, 1, 17},\r
+ {0, ID_TWI2, 0, 18},\r
+ {0, ID_TWI2, 1, 19},\r
+ {0, ID_UART0, 0, 20},\r
+ {0, ID_UART0, 1, 21},\r
+ {0, ID_UART1, 0, 22},\r
+ {0, ID_UART1, 1, 23},\r
+ {0, ID_UART2, 0, 24},\r
+ {0, ID_UART2, 1, 25},\r
+ {0, ID_UART3, 0, 26},\r
+ {0, ID_UART3, 1, 27},\r
+ {0, ID_UART4, 0, 28},\r
+ {0, ID_UART4, 1, 29},\r
+ {0, ID_DACC, 0, 30},\r
+ {0, ID_DACC, 0, 31},\r
+ {0, ID_SSC, 0, 32},\r
+ {0, ID_SSC, 1, 33},\r
+ {0, ID_PIOA, 1, 34},\r
+ {0, ID_AFEC0, 1, 35},\r
+ {0, ID_AFEC1, 1, 36},\r
+ {0, ID_AES, 0, 37},\r
+ {0, ID_AES, 1, 38},\r
+ {0, ID_PWM1, 0, 39},\r
+ {0, ID_TC0, 1, 40},\r
+ {0, ID_TC1, 1, 41},\r
+ {0, ID_TC2, 1, 42},\r
+ {0, ID_TC3, 1, 43},\r
+\r
+\r
+\r
+};\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Get peripheral identifier coded for hardware handshaking interface\r
+ *\r
+ * \param bDmac DMA Controller number.\r
+ * \param bPeriphID Peripheral ID.\r
+ * \param bTransfer Transfer type 0: Tx, 1 :Rx.\r
+ * \return 0-15 peripheral identifier coded.\r
+ * 0xff : no associated peripheral identifier coded.\r
+ */\r
+uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID,\r
+ uint8_t bTransfer)\r
+{\r
+ uint8_t i;\r
+ uint8_t NumOfPeripheral = ((XDMAC_GetType(XDMAC) & 0x00FF0000) >> 16);\r
+ for (i = 0; i <=NumOfPeripheral; i++)\r
+ {\r
+ if ( (xdmaHwIf[i].bPeriphID == bPeriphID) && (xdmaHwIf[i].bTransfer == bTransfer))\r
+ {\r
+ return xdmaHwIf[i].bIfID;\r
+ }\r
+ }\r
+ return 0xff;\r
+}\r
+\r
+/**\r
+ * \brief Check if the given DMAC has associated peripheral identifier coded by\r
+ * the given peripheral.\r
+ *\r
+ * \param bDmac DMA Controller number.\r
+ * \param bPeriphID Peripheral ID (0xff : memory only).\r
+ * \return 1: Is a validated peripher. 0: no associated peripheral identifier coded.\r
+ */\r
+uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bPeriphID)\r
+{\r
+ uint8_t i;\r
+ uint8_t NumOfPeripheral = ((XDMAC_GetType(XDMAC) & 0x00FF0000) >> 16);\r
+ /* It is always validated when transfer to memory */\r
+ if (bPeriphID == 0xFF) {\r
+ return 1;\r
+ }\r
+\r
+ for (i = 0; i <=NumOfPeripheral; i++)\r
+ {\r
+ if ((xdmaHwIf[i].bPeriphID == bPeriphID))\r
+ {\r
+ return 1;\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of xDMA controller (XDMAC).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+/** \addtogroup dmac_functions XDMAC Functions\r
+ *@{\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+uint32_t XDMAC_GetType( Xdmac *pXdmac)\r
+{\r
+ assert(pXdmac);\r
+ return pXdmac->XDMAC_GTYPE;\r
+}\r
+\r
+uint32_t XDMAC_GetConfig( Xdmac *pXdmac)\r
+{\r
+ assert(pXdmac);\r
+ return pXdmac->XDMAC_GCFG;\r
+}\r
+\r
+uint32_t XDMAC_GetArbiter( Xdmac *pXdmac)\r
+{\r
+ assert(pXdmac);\r
+ return pXdmac->XDMAC_GWAC;\r
+}\r
+\r
+/**\r
+ * \brief Enables XDMAC global interrupt.\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param dwInteruptMask IT to be enabled.\r
+ */\r
+void XDMAC_EnableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask )\r
+{\r
+ assert(pXdmac);\r
+ pXdmac->XDMAC_GIE = dwInteruptMask;\r
+}\r
+\r
+/**\r
+ * \brief Disables XDMAC global interrupt\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param dwInteruptMask IT to be enabled\r
+ */\r
+void XDMAC_DisableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask )\r
+{\r
+ assert(pXdmac);\r
+ pXdmac->XDMAC_GID = dwInteruptMask;\r
+}\r
+\r
+uint32_t XDMAC_GetGItMask( Xdmac *pXdmac )\r
+{\r
+ assert(pXdmac);\r
+ return (pXdmac->XDMAC_GIM);\r
+}\r
+\r
+uint32_t XDMAC_GetGIsr( Xdmac *pXdmac )\r
+{\r
+ assert(pXdmac);\r
+ return (pXdmac->XDMAC_GIS);\r
+}\r
+\r
+uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac )\r
+{\r
+ uint32_t _dwStatus;\r
+ assert(pXdmac);\r
+ _dwStatus = pXdmac->XDMAC_GIS;\r
+ _dwStatus &= pXdmac->XDMAC_GIM;\r
+ return _dwStatus;\r
+}\r
+\r
+/**\r
+ * \brief enables the relevant channel of given XDMAC.\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param channel Particular channel number.\r
+ */\r
+void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GE |= XDMAC_GE_EN0 << channel;\r
+}\r
+\r
+/**\r
+ * \brief enables the relevant channels of given XDMAC.\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param bmChannels Channels bitmap.\r
+ */\r
+void XDMAC_EnableChannels( Xdmac *pXdmac, uint8_t bmChannels )\r
+{\r
+ assert(pXdmac);\r
+ pXdmac->XDMAC_GE = bmChannels;\r
+}\r
+\r
+/**\r
+ * \brief Disables the relevant channel of given XDMAC.\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param channel Particular channel number.\r
+ */\r
+void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GD |= XDMAC_GD_DI0 << channel;\r
+}\r
+\r
+/**\r
+ * \brief Disables the relevant channels of given XDMAC.\r
+ *\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ * \param bmChannels Channels bitmap.\r
+ */\r
+void XDMAC_DisableChannels( Xdmac *pXdmac, uint8_t bmChannels )\r
+{\r
+ assert(pXdmac);\r
+ pXdmac->XDMAC_GD = bmChannels;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get Global channel status of given XDMAC.\r
+ * \Note: When set to 1, this bit indicates that the channel x is enabled. If a channel disable request is issued, this bit remains asserted\r
+ until pending transaction is completed.\r
+ * \param pXdmac Pointer to the XDMAC peripheral.\r
+ */\r
+uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac)\r
+{\r
+\r
+ assert(pXdmac);\r
+ return pXdmac->XDMAC_GS;\r
+}\r
+\r
+void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel;\r
+}\r
+\r
+\r
+void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel;\r
+}\r
+\r
+void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GRWS |= XDMAC_GRWS_RWS0 << channel;\r
+}\r
+\r
+void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GRWR |= XDMAC_GRWR_RWR0 << channel;\r
+}\r
+\r
+void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GSWR |= (XDMAC_GSWR_SWREQ0 << channel);\r
+}\r
+\r
+uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac)\r
+{\r
+\r
+ assert(pXdmac);\r
+ return pXdmac->XDMAC_GSWS;\r
+}\r
+\r
+void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_GSWF |= XDMAC_GSWF_SWF0 << channel;\r
+}\r
+\r
+void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask;\r
+}\r
+\r
+void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask )\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask;\r
+}\r
+\r
+uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ return pXdmac->XDMAC_CHID[channel].XDMAC_CIM;\r
+}\r
+\r
+uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ return pXdmac->XDMAC_CHID[channel].XDMAC_CIS;\r
+}\r
+\r
+uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel)\r
+{\r
+ uint32_t status;\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS;\r
+ status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM;\r
+\r
+ return status;\r
+}\r
+\r
+void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr;\r
+}\r
+\r
+void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr;\r
+}\r
+\r
+void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr, uint32_t ndaif)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = ( addr & 0xFFFFFFFC ) | ndaif;\r
+}\r
+\r
+void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint32_t config)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config;\r
+}\r
+\r
+void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = ublen;\r
+}\r
+\r
+void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint32_t blen)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CBC = blen;\r
+}\r
+\r
+void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CC = config;\r
+}\r
+\r
+uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ return pXdmac->XDMAC_CHID[channel].XDMAC_CC;\r
+}\r
+\r
+void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, uint32_t dds_msp)\r
+{\r
+\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp;\r
+}\r
+\r
+void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t subs)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = subs;\r
+}\r
+\r
+void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t dubs)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = dubs;\r
+}\r
+\r
+\r
+uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel)\r
+{\r
+ assert(pXdmac);\r
+ assert(channel < XDMAC_CHANNEL_NUM);\r
+ return pXdmac->XDMAC_CHID[channel].XDMAC_CDA;\r
+}\r
+\r
+/**@}*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup xdmad_module \r
+ *\r
+ * \section Xdma xDma Configuration Usage\r
+ *\r
+ * To configure a XDMA channel, the user has to follow these few steps :\r
+ * <ul>\r
+ * <li> Initialize a XDMA driver instance by XDMAD_Initialize().</li>\r
+ * <li> choose an available (disabled) channel using XDMAD_AllocateChannel().</li>\r
+ * <li> After the XDMAC selected channel has been programmed, XDMAD_PrepareChannel() is to enable \r
+ * clock and dma peripheral of the DMA, and set Configuration register to set up the transfer type \r
+ * (memory or non-memory peripheral for source and destination) and flow control device.</li>\r
+ * <li> Invoke XDMAD_StartTransfer() to start DMA transfer or XDMAD_StopTransfer() to force stop DMA transfer.</li>\r
+ * <li> Once the buffer of data is transferred, XDMAD_IsTransferDone() checks if DMA transfer is finished.</li>\r
+ * <li> XDMAD_Handler() handles XDMA interrupt, and invoking XDMAD_SetCallback() if provided.</li>\r
+ * </ul>\r
+ *\r
+ * Related files:\n\r
+ * \ref xdmad.h\n\r
+ * \ref xdmad.c.\n\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup dmad_functions\r
+ @{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Includes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include <assert.h>\r
+static uint8_t xDmad_Initialized = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Try to allocate a DMA channel for on given controller.\r
+ * \param pDmad Pointer to DMA driver instance. \r
+ * \param bSrcID Source peripheral ID, 0xFF for memory.\r
+ * \param bDstID Destination peripheral ID, 0xFF for memory.\r
+ * \return Channel number if allocation sucessful, return\r
+ * DMAD_ALLOC_FAILED if allocation failed.\r
+ */\r
+static uint32_t XDMAD_AllocateXdmacChannel( sXdmad *pXdmad,\r
+ uint8_t bSrcID,\r
+ uint8_t bDstID)\r
+{\r
+ uint32_t i;\r
+ /* Can't support peripheral to peripheral */\r
+ if ((( bSrcID != XDMAD_TRANSFER_MEMORY ) && ( bDstID != XDMAD_TRANSFER_MEMORY )))\r
+ {\r
+ return XDMAD_ALLOC_FAILED;\r
+ }\r
+ /* dma transfer from peripheral to memory */\r
+ if ( bDstID == XDMAD_TRANSFER_MEMORY)\r
+ {\r
+ if( (!XDMAIF_IsValidatedPeripherOnDma(bSrcID)) )\r
+ {\r
+ return XDMAD_ALLOC_FAILED;\r
+ }\r
+ }\r
+ /* dma transfer from memory to peripheral */\r
+ if ( bSrcID == XDMAD_TRANSFER_MEMORY )\r
+ {\r
+ if( (!XDMAIF_IsValidatedPeripherOnDma(bDstID)) )\r
+ {\r
+ return XDMAD_ALLOC_FAILED;\r
+ }\r
+ }\r
+\r
+ for (i = 0; i < pXdmad->numChannels; i ++)\r
+ {\r
+ if (( pXdmad->XdmaChannels[i].state == XDMAD_STATE_FREE ) || ( pXdmad->XdmaChannels[i].state == XDMAD_STATE_DONE ))\r
+ {\r
+ /* Allocate the channel */\r
+ pXdmad->XdmaChannels[i].state = XDMAD_STATE_ALLOCATED;\r
+ /* Get general informations */\r
+ pXdmad->XdmaChannels[i].bSrcPeriphID = bSrcID;\r
+ pXdmad->XdmaChannels[i].bDstPeriphID = bDstID;\r
+ pXdmad->XdmaChannels[i].bSrcTxIfID =\r
+ XDMAIF_Get_ChannelNumber(bSrcID, 0);\r
+ pXdmad->XdmaChannels[i].bSrcRxIfID =\r
+ XDMAIF_Get_ChannelNumber(bSrcID, 1);\r
+ pXdmad->XdmaChannels[i].bDstTxIfID =\r
+ XDMAIF_Get_ChannelNumber(bDstID, 0);\r
+ pXdmad->XdmaChannels[i].bDstRxIfID =\r
+ XDMAIF_Get_ChannelNumber(bDstID, 1);\r
+ return ((i) & 0xFF);\r
+ }\r
+ }\r
+ return XDMAD_ALLOC_FAILED;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize xDMA driver instance.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param bPollingMode Polling DMA transfer:\r
+ * 1. Via XDMAD_IsTransferDone(); or\r
+ * 2. Via XDMAD_Handler().\r
+ */\r
+void XDMAD_Initialize( sXdmad *pXdmad, uint8_t bPollingMode )\r
+{\r
+ uint32_t j;\r
+\r
+ assert( pXdmad != NULL ) ;\r
+ if (xDmad_Initialized) return;\r
+ pXdmad->pXdmacs = XDMAC;\r
+ pXdmad->pollingMode = bPollingMode;\r
+ pXdmad->numControllers = XDMAC_CONTROLLER_NUM;\r
+ pXdmad->numChannels = (XDMAC_GTYPE_NB_CH( XDMAC_GetType(XDMAC) ) + 1);\r
+\r
+ for (j = 0; j < pXdmad->numChannels; j ++)\r
+ {\r
+ pXdmad->XdmaChannels[j].fCallback = 0;\r
+ pXdmad->XdmaChannels[j].pArg = 0;\r
+ pXdmad->XdmaChannels[j].bIrqOwner = 0;\r
+ pXdmad->XdmaChannels[j].bSrcPeriphID = 0;\r
+ pXdmad->XdmaChannels[j].bDstPeriphID = 0;\r
+ pXdmad->XdmaChannels[j].bSrcTxIfID = 0;\r
+ pXdmad->XdmaChannels[j].bSrcRxIfID = 0;\r
+ pXdmad->XdmaChannels[j].bDstTxIfID = 0;\r
+ pXdmad->XdmaChannels[j].bDstRxIfID = 0;\r
+ pXdmad->XdmaChannels[j].state = XDMAD_STATE_FREE;\r
+ }\r
+ xDmad_Initialized = 1;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Allocate a XDMA channel for upper layer.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param bSrcID Source peripheral ID, 0xFF for memory.\r
+ * \param bDstID Destination peripheral ID, 0xFF for memory.\r
+ * \return Channel number if allocation sucessful, return\r
+ * XDMAD_ALLOC_FAILED if allocation failed.\r
+ */\r
+uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad,\r
+ uint8_t bSrcID,\r
+ uint8_t bDstID)\r
+{ \r
+ uint32_t dwChannel = XDMAD_ALLOC_FAILED;\r
+\r
+ dwChannel = XDMAD_AllocateXdmacChannel( pXdmad, bSrcID, bDstID );\r
+\r
+ return dwChannel;\r
+}\r
+\r
+/**\r
+ * \brief Free the specified xDMA channel.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ */\r
+eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, \r
+ uint32_t dwChannel )\r
+{\r
+\r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+\r
+ assert( pXdmad != NULL ) ;\r
+ switch ( pXdmad->XdmaChannels[iChannel].state )\r
+ {\r
+ case XDMAD_STATE_START: \r
+ case XDMAD_STATE_ALLOCATED: \r
+ return XDMAD_BUSY;\r
+ case XDMAD_STATE_DONE:\r
+ pXdmad->XdmaChannels[iChannel].state = XDMAD_STATE_FREE;\r
+ break;\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Set the callback function for xDMA channel transfer.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ * \param fCallback Pointer to callback function.\r
+ * \param pArg Pointer to optional argument for callback.\r
+ */\r
+eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad, \r
+ uint32_t dwChannel,\r
+ XdmadTransferCallback fCallback, \r
+ void* pArg )\r
+{\r
+\r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+ assert( pXdmad != NULL ) ;\r
+ if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE )\r
+ return XDMAD_ERROR;\r
+ else if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START )\r
+ return XDMAD_BUSY;\r
+\r
+ pXdmad->XdmaChannels[iChannel].fCallback = fCallback;\r
+ pXdmad->XdmaChannels[iChannel].pArg = pArg;\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enable clock of the xDMA peripheral, Enable the dma peripheral,\r
+ * configure configuration register for xDMA transfer.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ * \param dwCfg Configuration value.\r
+ */\r
+eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel)\r
+{\r
+\r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+\r
+\r
+ assert( pXdmad != NULL ) ;\r
+ Xdmac *pXdmac = pXdmad->pXdmacs;\r
+\r
+ if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE )\r
+ return XDMAD_ERROR;\r
+ else if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START )\r
+ return XDMAD_BUSY;\r
+ /* Clear dummy status */\r
+ XDMAC_GetGlobalChStatus( pXdmac );\r
+ XDMAC_GetGIsr (pXdmac);\r
+\r
+ /* Enable clock of the DMA peripheral */\r
+ if (!PMC_IsPeriphEnabled( ID_XDMAC ))\r
+ {\r
+ PMC_EnablePeripheral( ID_XDMAC );\r
+ }\r
+\r
+ /* Clear dummy status */\r
+ XDMAC_GetChannelIsr( pXdmac,iChannel );\r
+ /* Disables XDMAC interrupt for the given channel. */\r
+ XDMAC_DisableGIt (pXdmac, (uint32_t)-1);\r
+ XDMAC_DisableChannelIt (pXdmac, iChannel, (uint32_t)-1);\r
+ /* Disable the given dma channel. */\r
+ XDMAC_DisableChannel( pXdmac, iChannel );\r
+ XDMAC_SetSourceAddr(pXdmac, iChannel, 0);\r
+ XDMAC_SetDestinationAddr(pXdmac, iChannel, 0);\r
+ XDMAC_SetBlockControl(pXdmac, iChannel, 0);\r
+ XDMAC_SetChannelConfig( pXdmac, iChannel, 0x20);\r
+ XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0);\r
+ XDMAC_SetDescriptorControl(pXdmac, iChannel, 0);\r
+ return XDMAD_OK;\r
+}\r
+\r
+/**\r
+ * \brief xDMA interrupt handler\r
+ * \param pxDmad Pointer to DMA driver instance.\r
+ */\r
+void XDMAD_Handler( sXdmad *pDmad)\r
+{\r
+ Xdmac *pXdmac;\r
+ sXdmadChannel *pCh;\r
+ uint32_t xdmaChannelIntStatus, xdmaGlobaIntStatus,xdmaGlobalChStatus;\r
+ uint8_t bExec = 0;\r
+ uint8_t _iChannel;\r
+ assert( pDmad != NULL ) ;\r
+\r
+\r
+ pXdmac = pDmad->pXdmacs;\r
+ xdmaGlobaIntStatus = XDMAC_GetGIsr(pXdmac);\r
+ if ((xdmaGlobaIntStatus & 0xFFFFFF) != 0)\r
+ {\r
+ xdmaGlobalChStatus = XDMAC_GetGlobalChStatus(pXdmac);\r
+ for (_iChannel = 0; _iChannel < pDmad->numChannels; _iChannel ++) \r
+ {\r
+ if (!(xdmaGlobaIntStatus & (1<<_iChannel))) continue;\r
+ pCh = &pDmad->XdmaChannels[_iChannel];\r
+ if ( pCh->state == XDMAD_STATE_FREE) return ;\r
+ if ((xdmaGlobalChStatus & ( XDMAC_GS_ST0 << _iChannel)) == 0) \r
+ {\r
+ bExec = 0;\r
+ xdmaChannelIntStatus = XDMAC_GetChannelIsr( pXdmac, _iChannel);\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_BIS) { \r
+ if((XDMAC_GetChannelItMask(pXdmac, _iChannel) & XDMAC_CIM_LIM) == 0 ) {\r
+ pCh->state = XDMAD_STATE_DONE ;\r
+ bExec = 1;\r
+ }\r
+ //printf("XDMAC_CIS_BIS\n\r");\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_FIS) {\r
+ // printf("XDMAC_CIS_FIS\n\r");\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_RBEIS) {\r
+ //printf("XDMAC_CIS_RBEIS\n\r");\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_WBEIS) {\r
+ // printf("XDMAC_CIS_WBEIS\n\r");\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_ROIS) {\r
+ // printf("XDMAC_CIS_ROIS\n\r");\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_LIS) {\r
+ //printf("XDMAC_CIS_LIS\n\r");\r
+\r
+ pCh->state = XDMAD_STATE_DONE ;\r
+ bExec = 1;\r
+ }\r
+ if (xdmaChannelIntStatus & XDMAC_CIS_DIS ) \r
+ {\r
+ pCh->state = XDMAD_STATE_DONE ;\r
+ bExec = 1;\r
+ }\r
+ }\r
+ /* Execute callback */\r
+ if (bExec && pCh->fCallback) {\r
+ //XDMAC_DisableGIt( pXdmac,1 << _iChannel);\r
+ pCh->fCallback(_iChannel, pCh->pArg);\r
+ }\r
+ }\r
+ } // if condtion\r
+}\r
+\r
+/**\r
+ * \brief Check if DMA transfer is finished.\r
+ * In polling mode XDMAD_Handler() is polled.\r
+ * \param pDmad Pointer to DMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ */\r
+eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel )\r
+{ \r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+ uint8_t state;\r
+ state = pXdmad->XdmaChannels[iChannel].state;\r
+ assert( pXdmad != NULL ) ;\r
+ if ( state == XDMAD_STATE_ALLOCATED ) return XDMAD_OK;\r
+ if ( state == XDMAD_STATE_FREE )\r
+ return XDMAD_ERROR;\r
+ else if ( state != XDMAD_STATE_DONE )\r
+ {\r
+ if(pXdmad->pollingMode) XDMAD_Handler( pXdmad);\r
+ return XDMAD_BUSY;\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configure DMA for a single transfer.\r
+ * \param pXdmad Pointer to xDMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ */\r
+eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad,\r
+ uint32_t dwChannel,\r
+ sXdmadCfg *pXdmaParam,\r
+ uint32_t dwXdmaDescCfg,\r
+ uint32_t dwXdmaDescAddr)\r
+{\r
+\r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+ Xdmac *pXdmac = pXdmad->pXdmacs;\r
+ XDMAC_GetGIsr(pXdmac);\r
+ XDMAC_GetChannelIsr( pXdmac, iChannel);\r
+ if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE )\r
+ return XDMAD_ERROR;\r
+ if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START )\r
+ return XDMAD_BUSY;\r
+ /* Linked List is enabled */\r
+ if ((dwXdmaDescCfg & XDMAC_CNDC_NDE) == XDMAC_CNDC_NDE_DSCR_FETCH_EN)\r
+ {\r
+ if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV0) {\r
+ XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );\r
+ XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa);\r
+ XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da);\r
+ }\r
+ if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV1) {\r
+ XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );\r
+ }\r
+ XDMAC_SetDescriptorAddr(pXdmac, iChannel, dwXdmaDescAddr, 0);\r
+ XDMAC_SetDescriptorControl(pXdmac, iChannel, dwXdmaDescCfg);\r
+ XDMAC_DisableChannelIt (pXdmac, iChannel, (uint32_t)-1);\r
+ XDMAC_EnableChannelIt (pXdmac,iChannel, XDMAC_CIE_LIE );\r
+ }\r
+ /* LLI is disabled. */\r
+ else\r
+ {\r
+ XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa);\r
+ XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da);\r
+ XDMAC_SetMicroblockControl(pXdmac, iChannel, pXdmaParam->mbr_ubc);\r
+ XDMAC_SetBlockControl(pXdmac, iChannel, pXdmaParam->mbr_bc);\r
+ XDMAC_SetDataStride_MemPattern(pXdmac, iChannel, pXdmaParam->mbr_ds);\r
+ XDMAC_SetSourceMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_sus);\r
+ XDMAC_SetDestinationMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_dus);\r
+ XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg );\r
+ XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0);\r
+ XDMAC_SetDescriptorControl(pXdmac, iChannel, 0);\r
+ XDMAC_EnableChannelIt (pXdmac,\r
+ iChannel,\r
+ XDMAC_CIE_BIE |\r
+ XDMAC_CIE_DIE |\r
+ XDMAC_CIE_FIE |\r
+ XDMAC_CIE_RBIE |\r
+ XDMAC_CIE_WBIE |\r
+ XDMAC_CIE_ROIE);\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+/**\r
+ * \brief Start xDMA transfer.\r
+ * \param pXdmad Pointer to XDMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ */\r
+eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel )\r
+{\r
+\r
+ uint8_t iChannel = (dwChannel) & 0xFF;\r
+ Xdmac *pXdmac = pXdmad->pXdmacs;\r
+ if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE )\r
+ {\r
+ printf("-E- XDMAD_STATE_FREE \n\r");\r
+ return XDMAD_ERROR;\r
+ }\r
+ else if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START )\r
+ {\r
+ printf("-E- XDMAD_STATE_START \n\r");\r
+ return XDMAD_BUSY;\r
+ }\r
+ /* Change state to transferring */\r
+ pXdmad->XdmaChannels[iChannel].state = XDMAD_STATE_START; \r
+ XDMAC_EnableChannel(pXdmac, iChannel);\r
+ if ( pXdmad->pollingMode == 0 )\r
+ {\r
+ XDMAC_EnableGIt( pXdmac,1 << iChannel);\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Stop DMA transfer.\r
+ * \param pDmad Pointer to DMA driver instance.\r
+ * \param dwChannel ControllerNumber << 8 | ChannelNumber.\r
+ */\r
+eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel )\r
+{ \r
+ uint8_t _iChannel = (dwChannel) & 0xFF;\r
+ Xdmac *pXdmac = pXdmad->pXdmacs;\r
+\r
+ pXdmad->XdmaChannels[_iChannel].state = XDMAD_STATE_ALLOCATED;\r
+ /* Disable channel */\r
+ XDMAC_DisableChannel(pXdmac, _iChannel);\r
+ /* Disable interrupts */\r
+ XDMAC_DisableChannelIt(pXdmac, _iChannel, (uint32_t)-1);\r
+ /* Clear pending status */\r
+ XDMAC_GetChannelIsr( pXdmac, _iChannel);\r
+ XDMAC_GetGlobalChStatus(pXdmac);\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+/**@}*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and standard FreeRTOS hook functions.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "TaskNotify.h"\r
+\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Disable watchdog. */\r
+ WDT_Disable( WDT0 );\r
+ WDT_Disable( WDT1 );\r
+\r
+ SCB_EnableICache();\r
+ SCB_EnableDCache();\r
+\r
+ LED_Configure( 0 );\r
+ LED_Configure( 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Call the code that uses a mutex from an ISR. */\r
+ vInterruptSemaphorePeriodicTest();\r
+\r
+ /* Call the code that 'gives' a task notification from an ISR. */\r
+ xNotifyTaskFromISR();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Just to keep the linker happy. */\r
+int __write( int x );\r
+int __write( int x )\r
+{\r
+ return x;\r
+}\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained\libboard_samv7-ek\resources\IAR\samv7-ek-sram.mac" --backend -B "--endian=little" "--cpu=Cortex-M7" "--fpu=VFPv5_sp" "--drv_verify_download" "--semihosting=none" "--drv_communication=USB0" "--drv_interface_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=0,0,2000000" \r
+\r
+\r
--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED is used to show the demo status. */\r
+#define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOG, GPIO_PIN_6 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ mainTOGGLE_LED();\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f746xx.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f746xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F746xx_H\r
+#define __STM32F746xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ RNG_IRQn = 80, /*!< RNG global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */\r
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */\r
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */\r
+ SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */ \r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals \r
+ */\r
+#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */\r
+#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+ \r
+ \r
+#include "system_stm32f7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief HDMI-CEC \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+\r
+/** \r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+ \r
+/** \r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef; \r
+\r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief System configuration controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ \r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef; \r
+\r
+/** \r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+ \r
+typedef struct\r
+{ \r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */\r
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */\r
+\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t reserved; /*!< Reserved */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Serial Audio Interface\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+/** \r
+ * @brief SPDIF-RX Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */\r
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ \r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */\r
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ \r
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */\r
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */\r
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */\r
+} SPDIFRX_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ \r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ \r
+} QUADSPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */\r
+\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */\r
+} LPTIM_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ \r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ \r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ \r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+} USART_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+ * @brief RNG\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */ \r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */\r
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ \r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ \r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */ \r
+#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ \r
+#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */\r
+#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */\r
+#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */\r
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */\r
+#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */\r
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */\r
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */\r
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASHAXI_BASE\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r
+#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)\r
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)\r
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)\r
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) \r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)\r
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)\r
+/*!< AHB2 peripherals */\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE ((uint32_t )0xE0042000)\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)\r
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)\r
+\r
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)\r
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)\r
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)\r
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)\r
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)\r
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)\r
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)\r
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)\r
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)\r
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)\r
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)\r
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) \r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE) \r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE) \r
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */\r
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */\r
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */\r
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */\r
+ \r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */\r
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */\r
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */\r
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */\r
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */\r
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */\r
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/\r
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */\r
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */\r
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)\r
+#define DCMI_CR_CM ((uint32_t)0x00000002)\r
+#define DCMI_CR_CROP ((uint32_t)0x00000004)\r
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)\r
+#define DCMI_CR_ESS ((uint32_t)0x00000010)\r
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)\r
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)\r
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)\r
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)\r
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)\r
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)\r
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)\r
+#define DCMI_CR_CRE ((uint32_t)0x00001000)\r
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)\r
+#define DCMI_CR_BSM ((uint32_t)0x00030000)\r
+#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)\r
+#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)\r
+#define DCMI_CR_OEBS ((uint32_t)0x00040000)\r
+#define DCMI_CR_LSM ((uint32_t)0x00080000)\r
+#define DCMI_CR_OELS ((uint32_t)0x00100000)\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)\r
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)\r
+#define DCMI_SR_FNE ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for DCMI_RISR register ****************/\r
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)\r
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)\r
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)\r
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)\r
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)\r
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)\r
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)\r
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)\r
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_MISR register ****************/\r
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)\r
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)\r
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)\r
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)\r
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)\r
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)\r
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)\r
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)\r
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/ \r
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)\r
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)\r
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)\r
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) \r
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)\r
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)\r
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)\r
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)\r
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)\r
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)\r
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)\r
+#define DMA_SxCR_CT ((uint32_t)0x00080000) \r
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)\r
+#define DMA_SxCR_PL ((uint32_t)0x00030000)\r
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)\r
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)\r
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)\r
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)\r
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)\r
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)\r
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)\r
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)\r
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)\r
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)\r
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)\r
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)\r
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)\r
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)\r
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)\r
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)\r
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)\r
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)\r
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)\r
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)\r
+#define DMA_SxCR_EN ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)\r
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)\r
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)\r
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)\r
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)\r
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)\r
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)\r
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)\r
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)\r
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)\r
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)\r
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)\r
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)\r
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)\r
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)\r
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)\r
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/ \r
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)\r
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)\r
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)\r
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)\r
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)\r
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)\r
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)\r
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)\r
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/ \r
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/ \r
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/ \r
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/ \r
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */\r
+#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFSR register ****************/\r
+\r
+#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */\r
+#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ \r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */\r
+#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */\r
+#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */\r
+#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */\r
+\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+ \r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)\r
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)\r
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)\r
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)\r
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)\r
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)\r
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)\r
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)\r
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)\r
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)\r
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)\r
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)\r
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)\r
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)\r
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)\r
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)\r
+#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)\r
+#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP ((uint32_t)0x00000001)\r
+#define FLASH_SR_OPERR ((uint32_t)0x00000002)\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)\r
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)\r
+#define FLASH_SR_ERSERR ((uint32_t)0x00000080)\r
+#define FLASH_SR_BSY ((uint32_t)0x00010000)\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG ((uint32_t)0x00000001)\r
+#define FLASH_CR_SER ((uint32_t)0x00000002)\r
+#define FLASH_CR_MER ((uint32_t)0x00000004)\r
+#define FLASH_CR_SNB ((uint32_t)0x00000078)\r
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)\r
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)\r
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)\r
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)\r
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)\r
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)\r
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)\r
+#define FLASH_CR_STRT ((uint32_t)0x00010000)\r
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)\r
+#define FLASH_CR_ERRIE ((uint32_t)0x02000000)\r
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)\r
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)\r
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
+#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010)\r
+#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)\r
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)\r
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)\r
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)\r
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)\r
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)\r
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)\r
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)\r
+#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)\r
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000)\r
+#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)\r
+#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)\r
+\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */\r
+#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_ECCR register ******************/\r
+#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */\r
+ \r
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */\r
+\r
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */\r
+\r
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+\r
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */\r
+\r
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */\r
+\r
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */\r
+\r
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */\r
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */\r
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */\r
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */\r
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */\r
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */\r
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */\r
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */\r
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */\r
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */\r
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */\r
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */\r
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */\r
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */\r
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */\r
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */\r
+#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */\r
+ \r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */\r
+#define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */\r
+#define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */\r
+#define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */\r
+\r
+#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */\r
+\r
+#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ \r
+\r
+#define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */\r
+#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */\r
+#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */\r
+#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */\r
+#define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */\r
+#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */\r
+#define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */\r
+#define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */\r
+#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */\r
+\r
+#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */\r
+#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */\r
+#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */\r
+#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */\r
+#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */\r
+#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */\r
+#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */\r
+#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */\r
+\r
+#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */\r
+#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */\r
+#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */\r
+#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */\r
+#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */\r
+#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */\r
+\r
+/******************* Bit definition for PWR_CSR2 register ********************/\r
+#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */\r
+#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */\r
+#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */\r
+#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */\r
+#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */\r
+#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */\r
+\r
+#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */\r
+#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */\r
+#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */\r
+#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */\r
+#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */\r
+#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */\r
+#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */\r
+#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */\r
+#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */\r
+#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */\r
+#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */\r
+#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */\r
+#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */ \r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001)\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)\r
+\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)\r
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */\r
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */\r
+\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)\r
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000)\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000)\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000)\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)\r
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)\r
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)\r
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)\r
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)\r
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)\r
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)\r
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)\r
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)\r
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)\r
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)\r
+\r
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)\r
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)\r
+\r
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)\r
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)\r
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)\r
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)\r
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)\r
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)\r
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)\r
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)\r
+\r
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)\r
+\r
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)\r
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)\r
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)\r
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)\r
+\r
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)\r
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)\r
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)\r
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)\r
+\r
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)\r
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)\r
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)\r
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)\r
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)\r
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)\r
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)\r
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)\r
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)\r
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)\r
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)\r
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)\r
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)\r
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)\r
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)\r
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)\r
+#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)\r
+#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)\r
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)\r
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)\r
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)\r
+#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)\r
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)\r
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)\r
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+\r
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)\r
+#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)\r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)\r
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)\r
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)\r
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)\r
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)\r
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)\r
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)\r
+#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)\r
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)\r
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)\r
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)\r
+#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)\r
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)\r
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)\r
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)\r
+#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)\r
+#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)\r
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)\r
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)\r
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)\r
+#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)\r
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)\r
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)\r
+#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)\r
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)\r
+#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)\r
+#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)\r
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)\r
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)\r
+#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)\r
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+\r
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)\r
+#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)\r
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)\r
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)\r
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)\r
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)\r
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)\r
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)\r
+#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)\r
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)\r
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)\r
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)\r
+#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)\r
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)\r
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)\r
+#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)\r
+#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)\r
+#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)\r
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)\r
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)\r
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)\r
+#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)\r
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)\r
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)\r
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)\r
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)\r
+#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)\r
+#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)\r
+\r
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)\r
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)\r
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)\r
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)\r
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)\r
+#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)\r
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)\r
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)\r
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)\r
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)\r
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)\r
+#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)\r
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)\r
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)\r
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)\r
+#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)\r
+#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)\r
+#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)\r
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)\r
+#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)\r
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)\r
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)\r
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)\r
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001)\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)\r
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)\r
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)\r
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)\r
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)\r
+#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)\r
+#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)\r
+#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)\r
+#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)\r
+\r
+#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)\r
+#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)\r
+#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)\r
+\r
+#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)\r
+\r
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/\r
+#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)\r
+#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)\r
+#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)\r
+#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)\r
+#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)\r
+#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)\r
+#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)\r
+#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)\r
+#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)\r
+#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)\r
+#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)\r
+#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)\r
+#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)\r
+#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)\r
+#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)\r
+#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)\r
+#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)\r
+#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)\r
+#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)\r
+#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)\r
+#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)\r
+#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)\r
+#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)\r
+#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)\r
+#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)\r
+#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)\r
+#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)\r
+#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)\r
+#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)\r
+#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)\r
+#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)\r
+#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)\r
+#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)\r
+#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)\r
+#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)\r
+#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)\r
+#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)\r
+#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)\r
+#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)\r
+#define RNG_CR_IE ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY ((uint32_t)0x00000001)\r
+#define RNG_SR_CECS ((uint32_t)0x00000002)\r
+#define RNG_SR_SECS ((uint32_t)0x00000004)\r
+#define RNG_SR_CEIS ((uint32_t)0x00000020)\r
+#define RNG_SR_SEIS ((uint32_t)0x00000040)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE ((uint32_t)0x01000000) \r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF ((uint32_t)0x00020000)\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)\r
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ****************/\r
+#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)\r
+#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)\r
+#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)\r
+#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)\r
+#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)\r
+#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)\r
+#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)\r
+#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)\r
+#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)\r
+#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)\r
+#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)\r
+#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
+#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
+#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)\r
+#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
+#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)\r
+#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
+#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
+#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
+#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)\r
+#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)\r
+#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)\r
+#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)\r
+#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)\r
+#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)\r
+#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_OR register ****************/\r
+#define RTC_OR_TSINSEL ((uint32_t)0x00000006)\r
+#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)\r
+#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)\r
+#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)\r
+\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER ((uint32_t)0x00000020)\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+\r
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */\r
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+\r
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
+\r
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+\r
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+ \r
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */\r
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SPDIF-RX Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SPDIF_CR register *******************/\r
+#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */\r
+#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */\r
+#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */\r
+#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */\r
+#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */\r
+#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */\r
+#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */\r
+#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */\r
+#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */\r
+#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */\r
+#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */\r
+#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */\r
+#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */\r
+\r
+/******************* Bit definition for SPDIFRX_IMR register *******************/\r
+#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */\r
+#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */\r
+#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */\r
+#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */\r
+#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */\r
+#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */\r
+#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_SR register *******************/\r
+#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */\r
+#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */\r
+#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */\r
+#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */\r
+#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */\r
+#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */\r
+#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */\r
+#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */\r
+#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */\r
+#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */\r
+\r
+/******************* Bit definition for SPDIFRX_IFCR register *******************/\r
+#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */\r
+#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */\r
+#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */\r
+#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/\r
+#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */\r
+#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */\r
+#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */\r
+#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */\r
+#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */\r
+#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/\r
+#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */\r
+#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */\r
+#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */\r
+#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */\r
+#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */\r
+#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/\r
+#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */\r
+#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */\r
+\r
+/******************* Bit definition for SPDIFRX_CSR register *******************/\r
+#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */\r
+#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */\r
+#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */\r
+\r
+/******************* Bit definition for SPDIFRX_DIR register *******************/\r
+#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */\r
+#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */\r
+#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */\r
+#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */\r
+ \r
+#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */\r
+#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */\r
+ \r
+#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */\r
+ \r
+#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */\r
+#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */\r
+ \r
+#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */\r
+#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA register ********************/\r
+#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
+#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
+#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
+#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
+#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
+#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
+#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
+#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
+#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */\r
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */\r
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */\r
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */\r
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */\r
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */\r
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */ \r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
+#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */\r
+#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) \r
+#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) \r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */\r
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+\r
+\r
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */\r
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+\r
+\r
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */\r
+\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */\r
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */\r
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */\r
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register ********************/\r
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register *******************/\r
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */ \r
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ \r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */\r
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */\r
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */\r
+#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */\r
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */\r
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */\r
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */\r
+#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */\r
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */\r
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */\r
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */\r
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */\r
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */\r
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */\r
+#define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */\r
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */\r
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */\r
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */\r
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */\r
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */\r
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */\r
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */\r
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */\r
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */\r
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */\r
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */\r
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */\r
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */\r
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */\r
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */\r
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */\r
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */\r
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */\r
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */\r
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */\r
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */\r
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */\r
+\r
+/******************** Bit definition forUSB_OTG_HCFG register ********************/\r
+\r
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition forUSB_OTG_DCFG register ********************/\r
+\r
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */\r
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */\r
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */\r
+\r
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */\r
+\r
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */\r
+#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */\r
+\r
+/******************** Bit definition forUSB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */\r
+\r
+/******************** Bit definition forUSB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */\r
+\r
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */\r
+\r
+/******************** Bit definition forUSB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */\r
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/\r
+\r
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */\r
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */\r
+\r
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */\r
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */\r
+\r
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */\r
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+\r
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */\r
+#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */\r
+#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */\r
+#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */\r
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */\r
+#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */\r
+#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/\r
+#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/\r
+#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */\r
+#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */\r
+\r
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/\r
+#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */\r
+#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */\r
+ \r
+/******************** Bit definition forUSB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */\r
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */\r
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */\r
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */\r
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */\r
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\r
+ ((__INSTANCE__) == ADC2) || \\r
+ ((__INSTANCE__) == ADC3))\r
+\r
+/******************************* CAN Instances ********************************/\r
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\r
+ ((__INSTANCE__) == CAN2))\r
+ \r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)\r
+\r
+/******************************* DCMI Instances *******************************/\r
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r
+\r
+/******************************* DMA2D Instances *******************************/\r
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\r
+ ((__INSTANCE__) == DMA1_Stream1) || \\r
+ ((__INSTANCE__) == DMA1_Stream2) || \\r
+ ((__INSTANCE__) == DMA1_Stream3) || \\r
+ ((__INSTANCE__) == DMA1_Stream4) || \\r
+ ((__INSTANCE__) == DMA1_Stream5) || \\r
+ ((__INSTANCE__) == DMA1_Stream6) || \\r
+ ((__INSTANCE__) == DMA1_Stream7) || \\r
+ ((__INSTANCE__) == DMA2_Stream0) || \\r
+ ((__INSTANCE__) == DMA2_Stream1) || \\r
+ ((__INSTANCE__) == DMA2_Stream2) || \\r
+ ((__INSTANCE__) == DMA2_Stream3) || \\r
+ ((__INSTANCE__) == DMA2_Stream4) || \\r
+ ((__INSTANCE__) == DMA2_Stream5) || \\r
+ ((__INSTANCE__) == DMA2_Stream6) || \\r
+ ((__INSTANCE__) == DMA2_Stream7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+ \r
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+\r
+/****************************** CEC Instances *********************************/\r
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r
+\r
+/****************************** QSPI Instances *********************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+ \r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3) || \\r
+ ((__INSTANCE__) == I2C4))\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3))\r
+\r
+/******************************* LPTIM Instances ********************************/\r
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r
+\r
+/****************************** LTDC Instances ********************************/\r
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)\r
+\r
+/******************************* SAI Instances ********************************/\r
+#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\r
+ ((__PERIPH__) == SAI1_Block_B) || \\r
+ ((__PERIPH__) == SAI2_Block_A) || \\r
+ ((__PERIPH__) == SAI2_Block_B))\r
+\r
+\r
+/******************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)\r
+\r
+\r
+/****************************** SPDIFRX Instances *********************************/\r
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r
+ \r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3) || \\r
+ ((__INSTANCE__) == SPI4) || \\r
+ ((__INSTANCE__) == SPI5) || \\r
+ ((__INSTANCE__) == SPI6))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+ \r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : DMA requests generation (UDE) *************/\r
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (COMDE) *****************/\r
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/********************** TIM Instances : 32 bit Counter ************************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/***************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM11))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM2) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM3) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM4) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM5) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM9) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM10) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM11) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM12) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM13) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM14) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))))\r
+\r
+/************ TIM Instances : complementary output(s) available ***************/\r
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))))\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+ \r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/********************* UART Instances : Smart card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8)) \r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)\r
+\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32F7xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */\r
+/* product lines within the same STM32F7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define HASH_RNG_IRQn RNG_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define HASH_RNG_IRQHandler RNG_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F746xx_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f756xx.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS STM32F756xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f756xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F756xx_H\r
+#define __STM32F756xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */\r
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */\r
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */\r
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */\r
+ SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */ \r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals \r
+ */\r
+#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p0 */\r
+#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+ \r
+ \r
+#include "system_stm32f7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief HDMI-CEC \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+\r
+/** \r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+ \r
+/** \r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef; \r
+\r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief System configuration controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ \r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef; \r
+\r
+/** \r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+ \r
+typedef struct\r
+{ \r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */\r
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */\r
+\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t reserved; /*!< Reserved */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Serial Audio Interface\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+/** \r
+ * @brief SPDIF-RX Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */\r
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ \r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */\r
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ \r
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */\r
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */\r
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */\r
+} SPDIFRX_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ \r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ \r
+} QUADSPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */\r
+\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */\r
+} LPTIM_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ \r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ \r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ \r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+} USART_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Crypto Processor\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */\r
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */\r
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */\r
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */\r
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */\r
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */\r
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */\r
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */\r
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */\r
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */\r
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */\r
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */\r
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */\r
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */\r
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */\r
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */\r
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */\r
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */\r
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */\r
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */\r
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */\r
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */\r
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */\r
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */\r
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */\r
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */\r
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */\r
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */\r
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */\r
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */\r
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */\r
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */\r
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */\r
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */\r
+} CRYP_TypeDef;\r
+\r
+/** \r
+ * @brief HASH\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */\r
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */\r
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */\r
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */\r
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */\r
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */\r
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */\r
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */\r
+} HASH_TypeDef;\r
+\r
+/** \r
+ * @brief HASH_DIGEST\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ \r
+} HASH_DIGEST_TypeDef;\r
+\r
+/** \r
+ * @brief RNG\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */ \r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ __IO uint32_t GPWRDN; /*!< Power Down Register 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */\r
+ uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ \r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ \r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct \r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/** \r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */ \r
+#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ \r
+#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */\r
+#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */\r
+#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */\r
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */\r
+#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */\r
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */\r
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */\r
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASHAXI_BASE\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r
+#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)\r
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)\r
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)\r
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) \r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)\r
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)\r
+/*!< AHB2 peripherals */\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)\r
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)\r
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE ((uint32_t )0xE0042000)\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)\r
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)\r
+\r
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)\r
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)\r
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)\r
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)\r
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)\r
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)\r
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)\r
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)\r
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)\r
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)\r
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)\r
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) \r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE) \r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE) \r
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)\r
+#define HASH ((HASH_TypeDef *) HASH_BASE)\r
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */\r
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */\r
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */\r
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */\r
+ \r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */\r
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */\r
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */\r
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */\r
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */\r
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */\r
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/\r
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */\r
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */\r
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Crypto Processor */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for CRYP_CR register ********************/\r
+#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)\r
+\r
+#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)\r
+#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)\r
+#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)\r
+#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)\r
+#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)\r
+\r
+#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)\r
+#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)\r
+#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)\r
+#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)\r
+#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)\r
+#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)\r
+#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)\r
+#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)\r
+\r
+#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)\r
+#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)\r
+#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)\r
+#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) \r
+\r
+/****************** Bits definition for CRYP_SR register *********************/\r
+#define CRYP_SR_IFEM ((uint32_t)0x00000001)\r
+#define CRYP_SR_IFNF ((uint32_t)0x00000002)\r
+#define CRYP_SR_OFNE ((uint32_t)0x00000004)\r
+#define CRYP_SR_OFFU ((uint32_t)0x00000008)\r
+#define CRYP_SR_BUSY ((uint32_t)0x00000010)\r
+/****************** Bits definition for CRYP_DMACR register ******************/\r
+#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)\r
+#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)\r
+/***************** Bits definition for CRYP_IMSCR register ******************/\r
+#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)\r
+#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_RISR register *******************/\r
+#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)\r
+#define CRYP_RISR_INRIS ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_MISR register *******************/\r
+#define CRYP_MISR_INMIS ((uint32_t)0x00000001)\r
+#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)\r
+#define DCMI_CR_CM ((uint32_t)0x00000002)\r
+#define DCMI_CR_CROP ((uint32_t)0x00000004)\r
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)\r
+#define DCMI_CR_ESS ((uint32_t)0x00000010)\r
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)\r
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)\r
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)\r
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)\r
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)\r
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)\r
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)\r
+#define DCMI_CR_CRE ((uint32_t)0x00001000)\r
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)\r
+#define DCMI_CR_BSM ((uint32_t)0x00030000)\r
+#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)\r
+#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)\r
+#define DCMI_CR_OEBS ((uint32_t)0x00040000)\r
+#define DCMI_CR_LSM ((uint32_t)0x00080000)\r
+#define DCMI_CR_OELS ((uint32_t)0x00100000)\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)\r
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)\r
+#define DCMI_SR_FNE ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for DCMI_RISR register ****************/\r
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)\r
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)\r
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)\r
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)\r
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)\r
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)\r
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)\r
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)\r
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_MISR register ****************/\r
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)\r
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)\r
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)\r
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)\r
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)\r
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)\r
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)\r
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)\r
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/ \r
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)\r
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)\r
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)\r
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) \r
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)\r
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)\r
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)\r
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)\r
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)\r
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)\r
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)\r
+#define DMA_SxCR_CT ((uint32_t)0x00080000) \r
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)\r
+#define DMA_SxCR_PL ((uint32_t)0x00030000)\r
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)\r
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)\r
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)\r
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)\r
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)\r
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)\r
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)\r
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)\r
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)\r
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)\r
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)\r
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)\r
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)\r
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)\r
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)\r
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)\r
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)\r
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)\r
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)\r
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)\r
+#define DMA_SxCR_EN ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)\r
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)\r
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)\r
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)\r
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)\r
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)\r
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)\r
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)\r
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)\r
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)\r
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)\r
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)\r
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)\r
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)\r
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)\r
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)\r
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/ \r
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)\r
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)\r
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)\r
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)\r
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)\r
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)\r
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)\r
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)\r
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/ \r
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/ \r
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/ \r
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/ \r
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */\r
+#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFSR register ****************/\r
+\r
+#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */\r
+#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ \r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */\r
+#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */\r
+#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */\r
+#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */\r
+\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+ \r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)\r
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)\r
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)\r
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)\r
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)\r
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)\r
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)\r
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)\r
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)\r
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)\r
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)\r
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)\r
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)\r
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)\r
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)\r
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)\r
+#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)\r
+#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP ((uint32_t)0x00000001)\r
+#define FLASH_SR_OPERR ((uint32_t)0x00000002)\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)\r
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)\r
+#define FLASH_SR_ERSERR ((uint32_t)0x00000080)\r
+#define FLASH_SR_BSY ((uint32_t)0x00010000)\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG ((uint32_t)0x00000001)\r
+#define FLASH_CR_SER ((uint32_t)0x00000002)\r
+#define FLASH_CR_MER ((uint32_t)0x00000004)\r
+#define FLASH_CR_SNB ((uint32_t)0x00000078)\r
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)\r
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)\r
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)\r
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)\r
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)\r
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)\r
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)\r
+#define FLASH_CR_STRT ((uint32_t)0x00010000)\r
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)\r
+#define FLASH_CR_ERRIE ((uint32_t)0x02000000)\r
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)\r
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)\r
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
+#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010)\r
+#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)\r
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)\r
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)\r
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)\r
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)\r
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)\r
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)\r
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)\r
+#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)\r
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000)\r
+#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)\r
+#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)\r
+\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */\r
+#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */\r
+#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_ECCR register ******************/\r
+#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */\r
+ \r
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */\r
+\r
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */\r
+\r
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+\r
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */\r
+\r
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */\r
+\r
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */\r
+\r
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HASH */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for HASH_CR register ********************/\r
+#define HASH_CR_INIT ((uint32_t)0x00000004)\r
+#define HASH_CR_DMAE ((uint32_t)0x00000008)\r
+#define HASH_CR_DATATYPE ((uint32_t)0x00000030)\r
+#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)\r
+#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)\r
+#define HASH_CR_MODE ((uint32_t)0x00000040)\r
+#define HASH_CR_ALGO ((uint32_t)0x00040080)\r
+#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)\r
+#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)\r
+#define HASH_CR_NBW ((uint32_t)0x00000F00)\r
+#define HASH_CR_NBW_0 ((uint32_t)0x00000100)\r
+#define HASH_CR_NBW_1 ((uint32_t)0x00000200)\r
+#define HASH_CR_NBW_2 ((uint32_t)0x00000400)\r
+#define HASH_CR_NBW_3 ((uint32_t)0x00000800)\r
+#define HASH_CR_DINNE ((uint32_t)0x00001000)\r
+#define HASH_CR_MDMAT ((uint32_t)0x00002000)\r
+#define HASH_CR_LKEY ((uint32_t)0x00010000)\r
+\r
+/****************** Bits definition for HASH_STR register *******************/\r
+#define HASH_STR_NBW ((uint32_t)0x0000001F)\r
+#define HASH_STR_NBW_0 ((uint32_t)0x00000001)\r
+#define HASH_STR_NBW_1 ((uint32_t)0x00000002)\r
+#define HASH_STR_NBW_2 ((uint32_t)0x00000004)\r
+#define HASH_STR_NBW_3 ((uint32_t)0x00000008)\r
+#define HASH_STR_NBW_4 ((uint32_t)0x00000010)\r
+#define HASH_STR_DCAL ((uint32_t)0x00000100)\r
+\r
+/****************** Bits definition for HASH_IMR register *******************/\r
+#define HASH_IMR_DINIM ((uint32_t)0x00000001)\r
+#define HASH_IMR_DCIM ((uint32_t)0x00000002)\r
+\r
+/****************** Bits definition for HASH_SR register ********************/\r
+#define HASH_SR_DINIS ((uint32_t)0x00000001)\r
+#define HASH_SR_DCIS ((uint32_t)0x00000002)\r
+#define HASH_SR_DMAS ((uint32_t)0x00000004)\r
+#define HASH_SR_BUSY ((uint32_t)0x00000008)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */\r
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */\r
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */\r
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */\r
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */\r
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */\r
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */\r
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */\r
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */\r
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */\r
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */\r
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */\r
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */\r
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */\r
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */\r
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */\r
+#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */\r
+ \r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */\r
+#define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */\r
+#define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */\r
+#define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */\r
+\r
+#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */\r
+\r
+#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ \r
+\r
+#define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */\r
+#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */\r
+#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */\r
+#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */\r
+#define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */\r
+#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */\r
+#define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */\r
+#define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */\r
+#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */\r
+\r
+#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */\r
+#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */\r
+#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */\r
+#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */\r
+#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */\r
+#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */\r
+#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */\r
+#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */\r
+\r
+#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */\r
+#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */\r
+#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */\r
+#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */\r
+#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */\r
+#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */\r
+\r
+/******************* Bit definition for PWR_CSR2 register ********************/\r
+#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */\r
+#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */\r
+#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */\r
+#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */\r
+#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */\r
+#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */\r
+\r
+#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */\r
+#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */\r
+#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */\r
+#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */\r
+#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */\r
+#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */\r
+#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */\r
+#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */\r
+#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */\r
+#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */\r
+#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */\r
+#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */\r
+#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */ \r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001)\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)\r
+\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)\r
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */\r
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */\r
+\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)\r
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000)\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000)\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000)\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)\r
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)\r
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)\r
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)\r
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)\r
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)\r
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)\r
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)\r
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)\r
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)\r
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)\r
+\r
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)\r
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)\r
+\r
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)\r
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)\r
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)\r
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)\r
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)\r
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)\r
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)\r
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)\r
+\r
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)\r
+\r
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)\r
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)\r
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)\r
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)\r
+\r
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)\r
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)\r
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)\r
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)\r
+\r
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)\r
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)\r
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)\r
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)\r
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)\r
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)\r
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)\r
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)\r
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)\r
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)\r
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)\r
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)\r
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)\r
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)\r
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)\r
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)\r
+#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)\r
+#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)\r
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)\r
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)\r
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)\r
+#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)\r
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)\r
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)\r
+#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)\r
+#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)\r
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+\r
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)\r
+#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)\r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)\r
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)\r
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)\r
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)\r
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)\r
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)\r
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)\r
+#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)\r
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)\r
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)\r
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)\r
+#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)\r
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)\r
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)\r
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)\r
+#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)\r
+#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)\r
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)\r
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)\r
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)\r
+#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)\r
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)\r
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)\r
+#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)\r
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)\r
+#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)\r
+#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)\r
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)\r
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)\r
+#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)\r
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+\r
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)\r
+#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)\r
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)\r
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)\r
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)\r
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)\r
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)\r
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)\r
+#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)\r
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)\r
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)\r
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)\r
+#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)\r
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)\r
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)\r
+#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)\r
+#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)\r
+#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)\r
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)\r
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)\r
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)\r
+#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)\r
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)\r
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)\r
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)\r
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)\r
+#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)\r
+#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)\r
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)\r
+\r
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)\r
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)\r
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)\r
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)\r
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)\r
+#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)\r
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)\r
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)\r
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)\r
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)\r
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)\r
+#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)\r
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)\r
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)\r
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)\r
+#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)\r
+#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)\r
+#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)\r
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)\r
+#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)\r
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)\r
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)\r
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)\r
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001)\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)\r
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)\r
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)\r
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)\r
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)\r
+#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)\r
+#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)\r
+\r
+#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)\r
+#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)\r
+#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)\r
+#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)\r
+\r
+#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)\r
+#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)\r
+#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)\r
+\r
+#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)\r
+\r
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/\r
+#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)\r
+#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)\r
+#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)\r
+#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)\r
+#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)\r
+#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)\r
+#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)\r
+#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)\r
+#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)\r
+#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)\r
+#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)\r
+#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)\r
+#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)\r
+#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)\r
+#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)\r
+#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)\r
+#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)\r
+#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)\r
+#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)\r
+#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)\r
+#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)\r
+#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)\r
+#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)\r
+#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)\r
+#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)\r
+#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)\r
+#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)\r
+#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)\r
+#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)\r
+#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)\r
+#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)\r
+#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)\r
+#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)\r
+#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)\r
+#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)\r
+#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)\r
+#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)\r
+#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)\r
+#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)\r
+#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)\r
+#define RNG_CR_IE ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY ((uint32_t)0x00000001)\r
+#define RNG_SR_CECS ((uint32_t)0x00000002)\r
+#define RNG_SR_SECS ((uint32_t)0x00000004)\r
+#define RNG_SR_CEIS ((uint32_t)0x00000020)\r
+#define RNG_SR_SEIS ((uint32_t)0x00000040)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE ((uint32_t)0x01000000) \r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF ((uint32_t)0x00020000)\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)\r
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ****************/\r
+#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)\r
+#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)\r
+#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)\r
+#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)\r
+#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)\r
+#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)\r
+#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)\r
+#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)\r
+#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)\r
+#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)\r
+#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)\r
+#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
+#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
+#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)\r
+#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
+#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)\r
+#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
+#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
+#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
+#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)\r
+#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)\r
+#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)\r
+#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)\r
+#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)\r
+#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)\r
+#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_OR register ****************/\r
+#define RTC_OR_TSINSEL ((uint32_t)0x00000006)\r
+#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)\r
+#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)\r
+#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)\r
+\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER ((uint32_t)0x00000020)\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+\r
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */\r
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+\r
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
+\r
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+\r
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+ \r
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */\r
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SPDIF-RX Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SPDIF_CR register *******************/\r
+#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */\r
+#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */\r
+#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */\r
+#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */\r
+#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */\r
+#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */\r
+#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */\r
+#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */\r
+#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */\r
+#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */\r
+#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */\r
+#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */\r
+#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */\r
+\r
+/******************* Bit definition for SPDIFRX_IMR register *******************/\r
+#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */\r
+#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */\r
+#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */\r
+#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */\r
+#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */\r
+#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */\r
+#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_SR register *******************/\r
+#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */\r
+#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */\r
+#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */\r
+#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */\r
+#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */\r
+#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */\r
+#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */\r
+#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */\r
+#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */\r
+#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */\r
+\r
+/******************* Bit definition for SPDIFRX_IFCR register *******************/\r
+#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */\r
+#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */\r
+#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */\r
+#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/\r
+#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */\r
+#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */\r
+#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */\r
+#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */\r
+#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */\r
+#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/\r
+#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */\r
+#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */\r
+#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */\r
+#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */\r
+#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */\r
+#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/\r
+#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */\r
+#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */\r
+\r
+/******************* Bit definition for SPDIFRX_CSR register *******************/\r
+#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */\r
+#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */\r
+#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */\r
+\r
+/******************* Bit definition for SPDIFRX_DIR register *******************/\r
+#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */\r
+#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */\r
+#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */\r
+#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */\r
+ \r
+#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */\r
+#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */\r
+ \r
+#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */\r
+ \r
+#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */\r
+#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */\r
+ \r
+#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */\r
+#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA register ********************/\r
+#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
+#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
+#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
+#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
+#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
+#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
+#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
+#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
+#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */\r
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */\r
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */\r
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */\r
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */\r
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */\r
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */\r
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */ \r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
+#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */\r
+#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) \r
+#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) \r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */\r
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+\r
+\r
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */\r
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+\r
+\r
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */\r
+\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */\r
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */\r
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */\r
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register ********************/\r
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register *******************/\r
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */\r
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */\r
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */\r
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */\r
+\r
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */ \r
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ \r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */\r
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */\r
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */\r
+#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */\r
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */\r
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */\r
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */\r
+#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */\r
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */\r
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */\r
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */\r
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */\r
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */\r
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */\r
+\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */\r
+#define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */\r
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */\r
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */\r
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */\r
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */\r
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */\r
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */\r
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */\r
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */\r
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */\r
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */\r
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */\r
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */\r
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */\r
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */\r
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */\r
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */\r
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */\r
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */\r
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */\r
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */\r
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */\r
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */\r
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */\r
+\r
+/******************** Bit definition forUSB_OTG_HCFG register ********************/\r
+\r
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition forUSB_OTG_DCFG register ********************/\r
+\r
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */\r
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */\r
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */\r
+\r
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */\r
+\r
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */\r
+#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */\r
+\r
+/******************** Bit definition forUSB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */\r
+\r
+/******************** Bit definition forUSB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */\r
+\r
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */\r
+\r
+/******************** Bit definition forUSB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */\r
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/\r
+\r
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */\r
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */\r
+\r
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */\r
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */\r
+\r
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */\r
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */\r
+\r
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+\r
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */\r
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */\r
+#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */\r
+#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */\r
+#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */\r
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */\r
+#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */\r
+#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/\r
+#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/\r
+#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */\r
+#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */\r
+\r
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/\r
+#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */\r
+#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */\r
+\r
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */\r
+ \r
+/******************** Bit definition forUSB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */\r
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */\r
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */\r
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */\r
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */\r
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */\r
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */\r
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */\r
+\r
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */\r
+\r
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\r
+ ((__INSTANCE__) == ADC2) || \\r
+ ((__INSTANCE__) == ADC3))\r
+\r
+/******************************* CAN Instances ********************************/\r
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\r
+ ((__INSTANCE__) == CAN2))\r
+ \r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)\r
+\r
+/******************************* DCMI Instances *******************************/\r
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r
+\r
+/******************************* DMA2D Instances *******************************/\r
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\r
+ ((__INSTANCE__) == DMA1_Stream1) || \\r
+ ((__INSTANCE__) == DMA1_Stream2) || \\r
+ ((__INSTANCE__) == DMA1_Stream3) || \\r
+ ((__INSTANCE__) == DMA1_Stream4) || \\r
+ ((__INSTANCE__) == DMA1_Stream5) || \\r
+ ((__INSTANCE__) == DMA1_Stream6) || \\r
+ ((__INSTANCE__) == DMA1_Stream7) || \\r
+ ((__INSTANCE__) == DMA2_Stream0) || \\r
+ ((__INSTANCE__) == DMA2_Stream1) || \\r
+ ((__INSTANCE__) == DMA2_Stream2) || \\r
+ ((__INSTANCE__) == DMA2_Stream3) || \\r
+ ((__INSTANCE__) == DMA2_Stream4) || \\r
+ ((__INSTANCE__) == DMA2_Stream5) || \\r
+ ((__INSTANCE__) == DMA2_Stream6) || \\r
+ ((__INSTANCE__) == DMA2_Stream7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+ \r
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+\r
+/****************************** CEC Instances *********************************/\r
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r
+\r
+/****************************** QSPI Instances *********************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+ \r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3) || \\r
+ ((__INSTANCE__) == I2C4))\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3))\r
+\r
+/******************************* LPTIM Instances ********************************/\r
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r
+\r
+/****************************** LTDC Instances ********************************/\r
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)\r
+\r
+/******************************* SAI Instances ********************************/\r
+#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\r
+ ((__PERIPH__) == SAI1_Block_B) || \\r
+ ((__PERIPH__) == SAI2_Block_A) || \\r
+ ((__PERIPH__) == SAI2_Block_B))\r
+\r
+\r
+/******************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)\r
+\r
+\r
+/****************************** SPDIFRX Instances *********************************/\r
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r
+ \r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3) || \\r
+ ((__INSTANCE__) == SPI4) || \\r
+ ((__INSTANCE__) == SPI5) || \\r
+ ((__INSTANCE__) == SPI6))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+ \r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : DMA requests generation (UDE) *************/\r
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (COMDE) *****************/\r
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/********************** TIM Instances : 32 bit Counter ************************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/***************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM11))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM2) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM3) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM4) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM5) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM9) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM10) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM11) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM12) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM13) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM14) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))))\r
+\r
+/************ TIM Instances : complementary output(s) available ***************/\r
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))))\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+ \r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/********************* UART Instances : Smart card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8)) \r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)\r
+\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32F7xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */\r
+/* product lines within the same STM32F7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define RNG_IRQn HASH_RNG_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define RNG_IRQHandler HASH_RNG_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F756xx_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File. \r
+ * \r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32F7xx device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral\92s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_HAL_DRIVER"\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F7xx_H\r
+#define __STM32F7xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32F7)\r
+#define STM32F7\r
+#endif /* STM32F7 */\r
+\r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application \r
+ */\r
+#if !defined (STM32F756xx) && !defined (STM32F746xx)\r
+ /* #define STM32F756xx */ /*!< STM32F756VI, STM32F756VG, STM32F756ZG, STM32F756ZI, STM32F756IG, STM32F756II,\r
+ STM32F756BG, STM32F756BI, STM32F756NI, STM32F756NG Devices */\r
+ /* #define STM32F746xx */ /*!< STM32F746VI, STM32F746VG, STM32F746ZG, STM32F746ZI, STM32F746IG, STM32F746II,\r
+ STM32F746BG, STM32F746BI, STM32F746NI, STM32F746NG Devices */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number V0.2.0\r
+ */\r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_MAIN (0x00) /*!< [31:24] main version */\r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_CMSIS_DEVICE_VERSION ((__STM32F7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\\r
+ |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\\r
+ |(__STM32F7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7xx_CMSIS_DEVICE_VERSION))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx)\r
+ #include "stm32f756xx.h"\r
+#elif defined(STM32F746xx)\r
+ #include "stm32f746xx.h"\r
+#else\r
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+typedef enum \r
+{\r
+ RESET = 0, \r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum \r
+{\r
+ DISABLE = 0, \r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum \r
+{\r
+ ERROR = 0, \r
+ SUCCESS = !ERROR\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef USE_HAL_DRIVER\r
+ #include "stm32f7xx_hal_conf.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F7xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. \r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F7XX_H\r
+#define __SYSTEM_STM32F7XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F7xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_types\r
+ * @{\r
+ */\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F7XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 31. July 2014\r
+* $Revision: V1.4.4\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_common_tables.h\r
+*\r
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\r
+*\r
+* Target Processor: Cortex-M4/Cortex-M3\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+* -------------------------------------------------------------------- */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+//extern const q31_t realCoefAQ31[1024];\r
+//extern const q31_t realCoefBQ31[1024];\r
+extern const float32_t twiddleCoef_16[32];\r
+extern const float32_t twiddleCoef_32[64];\r
+extern const float32_t twiddleCoef_64[128];\r
+extern const float32_t twiddleCoef_128[256];\r
+extern const float32_t twiddleCoef_256[512];\r
+extern const float32_t twiddleCoef_512[1024];\r
+extern const float32_t twiddleCoef_1024[2048];\r
+extern const float32_t twiddleCoef_2048[4096];\r
+extern const float32_t twiddleCoef_4096[8192];\r
+#define twiddleCoef twiddleCoef_4096\r
+extern const q31_t twiddleCoef_16_q31[24];\r
+extern const q31_t twiddleCoef_32_q31[48];\r
+extern const q31_t twiddleCoef_64_q31[96];\r
+extern const q31_t twiddleCoef_128_q31[192];\r
+extern const q31_t twiddleCoef_256_q31[384];\r
+extern const q31_t twiddleCoef_512_q31[768];\r
+extern const q31_t twiddleCoef_1024_q31[1536];\r
+extern const q31_t twiddleCoef_2048_q31[3072];\r
+extern const q31_t twiddleCoef_4096_q31[6144];\r
+extern const q15_t twiddleCoef_16_q15[24];\r
+extern const q15_t twiddleCoef_32_q15[48];\r
+extern const q15_t twiddleCoef_64_q15[96];\r
+extern const q15_t twiddleCoef_128_q15[192];\r
+extern const q15_t twiddleCoef_256_q15[384];\r
+extern const q15_t twiddleCoef_512_q15[768];\r
+extern const q15_t twiddleCoef_1024_q15[1536];\r
+extern const q15_t twiddleCoef_2048_q15[3072];\r
+extern const q15_t twiddleCoef_4096_q15[6144];\r
+extern const float32_t twiddleCoef_rfft_32[32];\r
+extern const float32_t twiddleCoef_rfft_64[64];\r
+extern const float32_t twiddleCoef_rfft_128[128];\r
+extern const float32_t twiddleCoef_rfft_256[256];\r
+extern const float32_t twiddleCoef_rfft_512[512];\r
+extern const float32_t twiddleCoef_rfft_1024[1024];\r
+extern const float32_t twiddleCoef_rfft_2048[2048];\r
+extern const float32_t twiddleCoef_rfft_4096[4096];\r
+\r
+\r
+/* floating-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )\r
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )\r
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )\r
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\r
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\r
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\r
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\r
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\r
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\r
+\r
+/* fixed-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )\r
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )\r
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )\r
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )\r
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )\r
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )\r
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )\r
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r
+\r
+/* Tables for Fast Math Sine and Cosine */\r
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 31. July 2014\r
+* $Revision: V1.4.4\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_const_structs.h\r
+*\r
+* Description: This file has constant structs that are initialized for\r
+* user convenience. For example, some can be given as\r
+* arguments to the arm_cfft_f32() function.\r
+*\r
+* Target Processor: Cortex-M4/Cortex-M3\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+* -------------------------------------------------------------------- */\r
+\r
+#ifndef _ARM_CONST_STRUCTS_H\r
+#define _ARM_CONST_STRUCTS_H\r
+\r
+#include "arm_math.h"\r
+#include "arm_common_tables.h"\r
+\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
+\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r
+\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+*\r
+* $Date: 12. March 2014\r
+* $Revision: V1.4.4\r
+*\r
+* Project: CMSIS DSP Library\r
+* Title: arm_math.h\r
+*\r
+* Description: Public header file for CMSIS DSP Library\r
+*\r
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\r
+*\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions\r
+* are met:\r
+* - Redistributions of source code must retain the above copyright\r
+* notice, this list of conditions and the following disclaimer.\r
+* - Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in\r
+* the documentation and/or other materials provided with the\r
+* distribution.\r
+* - Neither the name of ARM LIMITED nor the names of its contributors\r
+* may be used to endorse or promote products derived from this\r
+* software without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+* POSSIBILITY OF SUCH DAMAGE.\r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * Introduction\r
+ * ------------\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of functions each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * Using the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
+ *\r
+ * Examples\r
+ * --------\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * Toolchain Support\r
+ * ------------\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.60.\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * Building the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM_math.uvproj\r
+ *\r
+ *\r
+ * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * Pre-processor Macros\r
+ * ------------\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * - UNALIGNED_SUPPORT_DISABLE:\r
+ *\r
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
+ *\r
+ * - ARM_MATH_BIG_ENDIAN:\r
+ *\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * - ARM_MATH_MATRIX_CHECK:\r
+ *\r
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
+ *\r
+ * - ARM_MATH_ROUNDING:\r
+ *\r
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
+ *\r
+ * - ARM_MATH_CMx:\r
+ *\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.\r
+ *\r
+ * - __FPU_PRESENT:\r
+ *\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
+ *\r
+ * <hr>\r
+ * CMSIS-DSP in ARM::CMSIS Pack\r
+ * -----------------------------\r
+ * \r
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
+ * |File/Folder |Content |\r
+ * |------------------------------|------------------------------------------------------------------------|\r
+ * |\b CMSIS\\Documentation\\DSP | This documentation |\r
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
+ * \r
+ * <hr>\r
+ * Revision History of CMSIS-DSP\r
+ * ------------\r
+ * Please refer to \ref ChangeLog_pg.\r
+ *\r
+ * Copyright Notice\r
+ * ------------\r
+ *\r
+ * Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined(ARM_MATH_CM7)\r
+ #include "core_cm7.h"\r
+#elif defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+#define ARM_MATH_CM0_FAMILY\r
+ #elif defined (ARM_MATH_CM0PLUS)\r
+#include "core_cm0plus.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#else\r
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+#include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#ifndef PI\r
+#define PI 3.14159265358979f\r
+#endif\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define FAST_MATH_TABLE_SIZE 512\r
+#define FAST_MATH_Q31_SHIFT (32 - 10)\r
+#define FAST_MATH_Q15_SHIFT (16 - 10)\r
+#define CONTROLLER_Q31_SHIFT (32 - 9)\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x400000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+ /**\r
+ * @brief Macro for Unaligned Support\r
+ */\r
+#ifndef UNALIGNED_SUPPORT_DISABLE\r
+ #define ALIGN4\r
+#else\r
+ #if defined (__GNUC__)\r
+ #define ALIGN4 __attribute__((aligned(4)))\r
+ #else\r
+ #define ALIGN4 __align(4)\r
+ #endif\r
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#if defined __CC_ARM\r
+#define __SIMD32_TYPE int32_t __packed\r
+#define CMSIS_UNUSED __attribute__((unused))\r
+#elif defined __ICCARM__\r
+#define CMSIS_UNUSED\r
+#define __SIMD32_TYPE int32_t __packed\r
+#elif defined __GNUC__\r
+#define __SIMD32_TYPE int32_t\r
+#define CMSIS_UNUSED __attribute__((unused))\r
+#elif defined __CSMC__ /* Cosmic */\r
+#define CMSIS_UNUSED\r
+#define __SIMD32_TYPE int32_t\r
+#else\r
+#error Unknown compiler\r
+#endif\r
+\r
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
+\r
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
+\r
+#define __SIMD64(addr) (*(int64_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ static __INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ static __INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ static __INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif\r
+\r
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
+\r
+ static __INLINE uint32_t __CLZ(\r
+ q31_t data);\r
+\r
+\r
+ static __INLINE uint32_t __CLZ(\r
+ q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return (count);\r
+\r
+ }\r
+\r
+#endif\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ static __INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
+ */\r
+ static __INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0_FAMILY)\r
+\r
+ static __INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0_FAMILY */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (q7_t) x;\r
+ s = (q7_t) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum =\r
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (q7_t) x;\r
+ s = (q7_t) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &\r
+ 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum =\r
+ ((sum +\r
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum =\r
+ ((sum +\r
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (q15_t) x;\r
+ s = (q15_t) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -\r
+ ((q15_t) (x >> 16) * (q15_t) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +\r
+ ((q15_t) (x >> 16) * (q15_t) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
+ ((q15_t) x * (q15_t) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
+ ((q15_t) x * (q15_t) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +\r
+ ((q15_t) x * (q15_t) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SXTB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SXTB16(\r
+ q31_t x)\r
+ {\r
+\r
+ return ((((x << 24) >> 24) & 0x0000FFFF) |\r
+ (((x << 8) >> 8) & 0xFFFF0000));\r
+ }\r
+\r
+\r
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float64_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f64;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pScratch);\r
+\r
+ /**\r
+ * @brief Q31, complex, matrix multiplication.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_cmplx_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t * pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t * pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t * pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+#ifdef ARM_MATH_CM0_FAMILY\r
+ q15_t A1;\r
+ q15_t A2;\r
+#else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+#endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q15(\r
+ arm_cfft_radix2_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q15(\r
+ const arm_cfft_radix2_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q31;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q31(\r
+ arm_cfft_radix2_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q31(\r
+ const arm_cfft_radix2_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix2_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_f32(\r
+ arm_cfft_radix2_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_f32(\r
+ const arm_cfft_radix2_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q15;\r
+\r
+void arm_cfft_q15( \r
+ const arm_cfft_instance_q15 * S, \r
+ q15_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag); \r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q31;\r
+\r
+void arm_cfft_q31( \r
+ const arm_cfft_instance_q31 * S, \r
+ q31_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag); \r
+ \r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_f32;\r
+\r
+ void arm_cfft_f32(\r
+ const arm_cfft_instance_f32 * S,\r
+ float32_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+typedef struct\r
+ {\r
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
+ uint16_t fftLenRFFT; /**< length of the real sequence */\r
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
+ } arm_rfft_fast_instance_f32 ;\r
+\r
+arm_status arm_rfft_fast_init_f32 (\r
+ arm_rfft_fast_instance_f32 * S,\r
+ uint16_t fftLen);\r
+\r
+void arm_rfft_fast_f32(\r
+ arm_rfft_fast_instance_f32 * S,\r
+ float32_t * p, float32_t * pOut,\r
+ uint8_t ifftFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+\r
+ void arm_conv_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_stereo_df2T_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f64;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_stereo_df2T_f32(\r
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f64(\r
+ const arm_biquad_cascade_df2T_instance_f64 * S,\r
+ float64_t * pSrc,\r
+ float64_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_stereo_df2T_init_f32(\r
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f64(\r
+ arm_biquad_cascade_df2T_instance_f64 * S,\r
+ uint8_t numStages,\r
+ float64_t * pCoeffs,\r
+ float64_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pkCoeffs,\r
+ float32_t * pvCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pkCoeffs,\r
+ q31_t * pvCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pkCoeffs,\r
+ q15_t * pvCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @return none.\r
+ */\r
+ void arm_correlate_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cos output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t * pSinVal,\r
+ float32_t * pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] *pSinVal points to the processed sine output.\r
+ * @param[out] *pCosVal points to the processed cosine output.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t * pSinVal,\r
+ q31_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+\r
+ static __INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ static __INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+#ifndef ARM_MATH_CM0_FAMILY\r
+ __SIMD32_TYPE *vstate;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ vstate = __SIMD32_CONST(S->state);\r
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);\r
+\r
+#else\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0) * in;\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0];\r
+ acc += (q31_t) S->A2 * S->state[1];\r
+\r
+#endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f64(\r
+ const arm_matrix_instance_f64 * src,\r
+ arm_matrix_instance_f64 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta =\r
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ static __INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ static __INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (int32_t) ((x - S->x1) / xSpacing);\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if((uint32_t)i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues - 1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i + 1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q31_t arm_linear_interp_q31(\r
+ q31_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q15_t arm_linear_interp_q15(\r
+ q15_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+ if(index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ static __INLINE q7_t arm_linear_interp_q7(\r
+ q7_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ uint32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ if (x < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ index = (x >> 20) & 0xfff;\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate, and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ static __INLINE arm_status arm_sqrt_f32(\r
+ float32_t in,\r
+ float32_t * pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+#else\r
+ *pOut = sqrtf(in);\r
+#endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in,\r
+ q31_t * pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in,\r
+ q15_t * pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none.\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] *pSrc points to the floating-point input vector\r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0\r
+ || yIndex > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex - 1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+ \r
+\r
+//SMMLAR\r
+#define multAcc_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+//SMMLSR\r
+#define multSub_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+//SMMULR\r
+#define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
+\r
+//SMMLA\r
+#define multAcc_32x32_keep32(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+//SMMLS\r
+#define multSub_32x32_keep32(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+//SMMUL\r
+#define mult_32x32_keep32(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+\r
+#if defined ( __CC_ARM ) //Keil\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #ifdef ARM_MATH_CM4\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("push") \\r
+ _Pragma ("O1")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER \r
+ #endif\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #ifdef ARM_MATH_CM4\r
+ #define LOW_OPTIMIZATION_EXIT \\r
+ _Pragma ("pop")\r
+ #else\r
+ #define LOW_OPTIMIZATION_EXIT \r
+ #endif\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__ICCARM__) //IAR\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #ifdef ARM_MATH_CM4\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER \r
+ #endif\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+//Enter low optimization region - place directly above function definition\r
+ #ifdef ARM_MATH_CM4\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \r
+ #endif\r
+\r
+//Exit low optimization region - place directly after end of function definition\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__GNUC__)\r
+\r
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))\r
+\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined(__CSMC__) // Cosmic\r
+\r
+#define LOW_OPTIMIZATION_ENTER\r
+#define LOW_OPTIMIZATION_EXIT\r
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0P definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if (__VTOR_PRESENT == 1)\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if (__VTOR_PRESENT == 1)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0+ Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 01. September 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x07) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x07)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x07)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93];\r
+ __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15];\r
+ __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
+ uint32_t RESERVED5[1];\r
+ __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1];\r
+ __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6];\r
+ __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1];\r
+ __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* Cache Level ID register */\r
+#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* Cache Type register */\r
+#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* Cache Size ID Register */\r
+#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* Cache Size Selection Register */\r
+#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register */\r
+#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register*/\r
+#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Registers */\r
+#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register */\r
+#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register */\r
+#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS control register */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )\r
+\r
+\r
+/** \brief Enable I-Cache\r
+\r
+ The function turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0; // invalidate I-Cache\r
+ SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Disable I-Cache\r
+\r
+ The function turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache\r
+ SCB->ICIALLU = 0; // invalidate I-Cache\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Invalidate I-Cache\r
+\r
+ The function invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache(void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Enable D-Cache\r
+\r
+ The function turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+ __DSB();\r
+\r
+ SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Disable D-Cache\r
+\r
+ The function turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache\r
+\r
+ do { // clean & invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Invalidate D-Cache\r
+\r
+ The function invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Clean D-Cache\r
+\r
+ The function cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // clean D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCSW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/** \brief Clean & Invalidate D-Cache\r
+\r
+ The function cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ uint32_t ccsidr, sshift, wshift, sw;\r
+ uint32_t sets, ways;\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+ sets = CCSIDR_SETS(ccsidr);\r
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
+ ways = CCSIDR_WAYS(ccsidr);\r
+ wshift = __CLZ(ways) & 0x1f;\r
+\r
+ __DSB();\r
+\r
+ do { // clean & invalidate D-Cache\r
+ int32_t tmpways = ways;\r
+ do {\r
+ sw = ((tmpways << wshift) | (sets << sshift));\r
+ SCB->DCCISW = sw;\r
+ } while(tmpways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.00\r
+ * @date 28. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+\r
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/\r
+/* Cosmic specific functions */\r
+#include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.00\r
+ * @date 28. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function executes a exclusive STR instruction for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function executes a exclusive STR instruction for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function executes a exclusive STR instruction for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+/** \brief Rotate Right with Extend (32 bit)\r
+\r
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.\r
+\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief LDRT Unprivileged (8 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/** \brief LDRT Unprivileged (16 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/** \brief LDRT Unprivileged (32 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/** \brief STRT Unprivileged (8 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/** \brief STRT Unprivileged (16 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/** \brief STRT Unprivileged (32 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constrant "l"\r
+ * Otherwise, use general registers, specified by constrant "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32 - op2)); \r
+}\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function executes a exclusive LDR instruction for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function executes a exclusive STR instruction for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function executes a exclusive STR instruction for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function executes a exclusive STR instruction for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/** \brief Rotate Right with Extend (32 bit)\r
+\r
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.\r
+\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDRT Unprivileged (8 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/** \brief LDRT Unprivileged (16 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/** \brief LDRT Unprivileged (32 bit)\r
+\r
+ This function executes a Unprivileged LDRT instruction for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STRT Unprivileged (8 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/** \brief STRT Unprivileged (16 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/** \brief STRT Unprivileged (32 bit)\r
+\r
+ This function executes a Unprivileged STRT instruction for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+\r
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/\r
+/* Cosmic specific functions */\r
+#include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32) ) >> 32))\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ // Little endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else // Big endian\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+/* not yet supported */\r
+\r
+\r
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/\r
+/* Cosmic specific functions */\r
+#include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (000) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154];\r
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/* SCB Security Features Register Definitions */\r
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */\r
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */\r
+\r
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */\r
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of SC000 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V4.00\r
+ * @date 22. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300) /*!< Cortex secure core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ ) /* Cosmic */\r
+ #if ( __CSMC__ & 0x400) // FPU present for parser\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
+\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ The function reads the active register in NVIC and returns the active bit.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************/\r
+/* RAM.INI: RAM Initialization File */\r
+/******************************************************************************/\r
+/* This file is part of the uVision/ARM development tools. */\r
+/* Copyright (c) 2014 Keil - An ARM Company. All rights reserved. */\r
+/* This software may only be used under the terms of a valid, current, */\r
+/* end user licence from KEIL for a compatible version of KEIL software */\r
+/* development tools. Nothing else gives you the right to use this software. */\r
+/******************************************************************************/\r
+\r
+FUNC void Setup (void) {\r
+ SP = _RDWORD(0x20000000); // Setup Stack Pointer\r
+ PC = _RDWORD(0x20000004); // Setup Program Counter\r
+ _WDWORD(0xE000ED08, 0x20000000); // Setup Vector Table Offset Register\r
+ _WDWORD(0x00000000, _RDWORD(0x20000000)); // Setup Vector Table Offset Register\r
+ _WDWORD(0x00000004, _RDWORD(0x20000004)); // Setup Vector Table Offset Register\r
+}\r
+\r
+LOAD %L INCREMENTAL // Download\r
+\r
+Setup(); // Setup for Running\r
+\r
+g, main\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 46 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* The full demo always has tasks to run so the tick will never be turned off.\r
+The blinky demo will use the default tickless idle implementation to turn the\r
+tick off. */\r
+#define configUSE_TICKLESS_IDLE 0\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Prevent the inclusion of items the assembler will not understand in assembly\r
+files. */\r
+#ifndef __IAR_SYSTEMS_ASM__\r
+\r
+ /* Library includes. */\r
+ #include "stm32f7xx_hal.h"\r
+\r
+ extern uint32_t SystemCoreClock;\r
+\r
+ /* Normal assert() semantics without relying on the provision of an assert.h\r
+ header file. */\r
+ extern void vAssertCalled( uint32_t ulLine, const char *pcFile );\r
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ )\r
+\r
+#endif /* __IAR_SYSTEMS_ASM__ */\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * TIM2 and TIM3 provide the interrupts that are used with the IntQ\r
+ * standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. The timers generate interrupts at slightly different\r
+ * frequencies and use different priorities, resulting in a nesting depth of\r
+ * three (including the tick and PendSV interrupts, which run at lower\r
+ * priorities).\r
+ *\r
+ * TIM4 provides a much higher frequency timer that tests the nesting\r
+ * of interrupts that don't use the FreeRTOS API. For convenience, the high\r
+ * frequency timer also keeps a count of the number of times it executes, and\r
+ * the count can be used as the time base for the run time stats.\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 4.\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_2_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_3_FREQUENCY ( 2003UL )\r
+#define tmrTIMER_4_FREQUENCY ( 20000UL )\r
+\r
+/* The high frequency interrupt given a priority above the maximum at which\r
+interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
+timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1\r
+#define tmrMEDIUM_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY\r
+#define tmrHIGHER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/* For convenience the high frequency timer increments a variable that is then\r
+used as the time base for the run time stats. */\r
+volatile uint32_t ulHighFrequencyTimerCounts = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+TIM_HandleTypeDef xTimHandle;\r
+const uint32_t ulPrescale = 0; /* No prescale. */\r
+\r
+ /* Clock the utilised timers. */\r
+ __TIM2_CLK_ENABLE();\r
+ __TIM3_CLK_ENABLE();\r
+ __TIM4_CLK_ENABLE();\r
+\r
+ /* Configure TIM2 to generate an interrupt at the required frequency. */\r
+ xTimHandle.Instance = TIM2;\r
+ xTimHandle.Init.Period = ( SystemCoreClock / 2UL ) / ( tmrTIMER_2_FREQUENCY - 1 );\r
+ xTimHandle.Init.Prescaler = ulPrescale;\r
+ xTimHandle.Init.ClockDivision = 0;\r
+ xTimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ HAL_TIM_Base_Init( &xTimHandle );\r
+ HAL_TIM_Base_Start_IT( &xTimHandle );\r
+\r
+ /* Configure and enable TIM2 interrupt. */\r
+ NVIC_SetPriority( TIM2_IRQn, tmrLOWER_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TIM2_IRQn );\r
+ NVIC_EnableIRQ( TIM2_IRQn );\r
+\r
+ /* Repeat for TIM3 and TIM4. */\r
+ xTimHandle.Instance = TIM3;\r
+ xTimHandle.Init.Period = ( SystemCoreClock / 2UL ) / ( tmrTIMER_3_FREQUENCY - 1 );\r
+ HAL_TIM_Base_Init( &xTimHandle );\r
+ HAL_TIM_Base_Start_IT( &xTimHandle );\r
+ NVIC_SetPriority( TIM3_IRQn, tmrMEDIUM_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TIM3_IRQn );\r
+ NVIC_EnableIRQ( TIM3_IRQn );\r
+\r
+ xTimHandle.Instance = TIM4;\r
+ xTimHandle.Init.Period = ( SystemCoreClock / 2UL ) / ( tmrTIMER_4_FREQUENCY - 1 );\r
+ HAL_TIM_Base_Init( &xTimHandle );\r
+ HAL_TIM_Base_Start_IT( &xTimHandle );\r
+ NVIC_SetPriority( TIM4_IRQn, tmrHIGHER_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TIM4_IRQn );\r
+ NVIC_EnableIRQ( TIM4_IRQn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM2_IRQHandler( void )\r
+{\r
+ /* Clear the interrupt and call the IntQTimer test function. */\r
+ TIM2->SR = 0;\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM3_IRQHandler( void )\r
+{\r
+ /* Clear the interrupt and call the IntQTimer test function. */\r
+ TIM3->SR = 0;\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM4_IRQHandler( void )\r
+{\r
+ TIM4->SR = 0;\r
+\r
+ /* Keep a count of the number of interrupts to use as a time base for the\r
+ run-time stats. */\r
+ ulHighFrequencyTimerCounts++;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+BaseType_t xTimer0Handler( void );\r
+BaseType_t xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#include <FreeRTOSConfig.h>\r
+\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Implementation\r
+ PUBLIC vRegTest2Implementation\r
+ PUBLIC vRegTestClearFlopRegistersToParameterValue\r
+ PUBLIC ulRegTestCheckFlopRegistersContainParameterValue\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest1Implementation\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop:\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+vRegTest2Implementation\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop:\r
+\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+\r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+\r
+ /* Yield to increase test coverage. */\r
+ movs r0, #0x01\r
+ ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+ lsl r0, r0, #28 /* Shift to PendSV bit */\r
+ str r0, [r1]\r
+ dsb\r
+\r
+ pop { r0-r1 }\r
+\r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop:\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTestClearFlopRegistersToParameterValue\r
+\r
+ /* Clobber the auto saved registers. */\r
+ vmov d0, r0, r0\r
+ vmov d1, r0, r0\r
+ vmov d2, r0, r0\r
+ vmov d3, r0, r0\r
+ vmov d4, r0, r0\r
+ vmov d5, r0, r0\r
+ vmov d6, r0, r0\r
+ vmov d7, r0, r0\r
+ bx lr\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ulRegTestCheckFlopRegistersContainParameterValue\r
+\r
+ vmov r1, s0\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s1\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s2\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s3\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s4\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s5\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s6\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s7\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s8\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s9\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s10\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s11\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s12\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s13\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s14\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s15\r
+ cmp r0, r1\r
+ bne return_error\r
+\r
+return_pass\r
+ mov r0, #1\r
+ bx lr\r
+\r
+return_error\r
+ mov r0, #0\r
+ bx lr\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+__asm void vRegTest1Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vRegTest2Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ \r
+ /* Yield to increase test coverage. */\r
+ movs r0, #0x01\r
+ ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+ lsl r0, r0, #28 /* Shift to PendSV bit */\r
+ str r0, [r1]\r
+ dsb\r
+ \r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "QueueSet.h"\r
+#include "TaskNotify.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The initial priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/* The LED is used to show the demo status. */\r
+#define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOG, GPIO_PIN_6 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main() to run the full demo (as opposed to the blinky demo) when\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file, but the\r
+ * entry points are kept in the C file for the convenience of checking the task\r
+ * parameter.\r
+ */\r
+static void prvRegTestTaskEntry1( void *pvParameters );\r
+extern void vRegTest1Implementation( void );\r
+static void prvRegTestTaskEntry2( void *pvParameters );\r
+extern void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * Register commands that can be used with FreeRTOS+CLI. The commands are\r
+ * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.\r
+ */\r
+extern void vRegisterSampleCLICommands( void );\r
+\r
+/*\r
+ * The task that manages the FreeRTOS+CLI input and output.\r
+ */\r
+extern void vUSBCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks has not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartInterruptSemaphoreTasks();\r
+ vStartQueueSetTasks();\r
+ vStartTaskNotifyTask();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 0UL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 1UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 10UL;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 11UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 13UL;\r
+ }\r
+\r
+ if( xAreQueueSetTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 14UL;\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 15UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 16UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 17UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ mainTOGGLE_LED();\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry1( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest1Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry2( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest2Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check timer will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>26</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F7xxx.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>7.30.3.8061</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>7.30.4.8186</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F7xxx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCores</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreMaster</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticorePort</name>\r
+ <state>53461</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreWorkspace</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveProject</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveConfiguration</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>26</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>7.30.3.8061</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>ARMSIM_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCores</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreMaster</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticorePort</name>\r
+ <state>53461</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreWorkspace</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveProject</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveConfiguration</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>22</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>21</version>\r
+ <state>41</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>6</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>3</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>7.30.3.8061</state>\r
+ </option>\r
+ <option>\r
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+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
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+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
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+ <name>CrcAlgorithm</name>\r
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+ <name>IlinkThreadsSlave</name>\r
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+ <settings>\r
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+ <configuration>\r
+ <name>Release</name>\r
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+ <name>GFPUCoreSlave</name>\r
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+ <name>GBECoreSlave</name>\r
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+ <name>GRuntimeLibThreads</name>\r
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+ <name>CCGuardCalls</name>\r
+ <state>1</state>\r
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+ </data>\r
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+ <settings>\r
+ <name>AARM</name>\r
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+ <archiveVersion>1</archiveVersion>\r
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+ <prebuild></prebuild>\r
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+ <name>ILINK</name>\r
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+ <state>1</state>\r
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+ <state>1</state>\r
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+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBufferedTerminalOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgorithm</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkThreadsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Blinky_Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Blinky_Demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS_Source</name>\r
+ <group>\r
+ <name>Portable</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1\portasm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1\portmacro.h</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Full_Demo</name>\r
+ <group>\r
+ <name>Common_Demo_Tasks</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flop.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\IntSemTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\QueueSet.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\TaskNotify.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\IntQueueTimer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\main_full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\RegTest_IAR.s</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>ST_Library</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_cortex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_dma.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_rcc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_tim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ST_Library\stm32f7xx_hal_tim_ex.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\System_IAR\startup_stm32f756xx.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\System_IAR\stm32f7xx_hal_msp.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\System_IAR\stm32f7xx_it.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\System_IAR\system_stm32f7xx.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>STM32756G_EVAL</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\STM32F7xx\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>0</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>0</sLdApp>
+ <sGomain>0</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>11</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMRTXEVENTFLAGS</Key>
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>JL2CM3</Key>
+ <Name>-U59101789 -O111 -S6 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO23 -FD20000000 -FC800 -FN1 -FF0STM32F5x -FS08000000 -FL0100000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ULP2CM3</Key>
+ <Name>-UP1018195 -O15 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06415041) -L01(5) -TO18 -TC10000000 -TP11 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L4xx -FS08000000 -FL0100000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ST-LINKIII-KEIL_SWO</Key>
+ <Name>-U51FF71064986495151250987 -I0 -O8431 -S3 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO23 -FD20000000 -FC800 -FN1 -FF0STM32F5x -FS08000000 -FL0100000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ST-LINKIII-KEIL</Key>
+ <Name>-S</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-O207 -S8 -C0 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x -FS08000000 -FL100000)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <WatchWindow2>
+ <Ww>
+ <count>0</count>
+ <WinNumber>2</WinNumber>
+ <ItemText>tick</ItemText>
+ </Ww>
+ </WatchWindow2>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>1</SubType>
+ <ItemText>0x020006A8</ItemText>
+ <AccSizeX>0</AccSizeX>
+ </Mm>
+ </MemoryWindow1>
+ <MemoryWindow2>
+ <Mm>
+ <WinNumber>2</WinNumber>
+ <SubType>2</SubType>
+ <ItemText>0x08000000</ItemText>
+ <AccSizeX>0</AccSizeX>
+ </Mm>
+ </MemoryWindow2>
+ <MemoryWindow3>
+ <Mm>
+ <WinNumber>3</WinNumber>
+ <SubType>1</SubType>
+ <ItemText>0x0</ItemText>
+ <AccSizeX>0</AccSizeX>
+ </Mm>
+ </MemoryWindow3>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>User</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\Blinky_Demo\main_blinky.c</PathWithFileName>
+ <FilenameWithoutPath>main_blinky.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\Full_Demo\main_full.c</PathWithFileName>
+ <FilenameWithoutPath>main_full.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>5</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
+ <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
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+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>11</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Pelican"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x100000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x8000000</StartAddress>
+ <Size>0x100000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0xffff</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>STM32F756xx, CORE_CM7,USE_HAL_DRIVER</Define>
+ <Undefine></Undefine>
+ <IncludePath>.\CMSIS\Device\ST\STM32F7xx\Include;.\CMSIS\Include;.\ST_Library\include;.;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM7\r0p1;..\Common\include;.\Full_Demo</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x08000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>.\STM32L4xx\Project.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>User</GroupName>
+ <Files>
+ <File>
+ <FileName>main_blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Blinky_Demo\main_blinky.c</FilePath>
+ </File>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueueTimer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\IntQueueTimer.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest_Keil.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Full_Demo\RegTest_Keil.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>ST Library</GroupName>
+ <Files>
+ <File>
+ <FileName>stm32f7xx_hal.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_cortex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_cortex.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_gpio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_gpio.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_rcc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_rcc.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_tim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_tim.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_dma.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_dma.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_tim_ex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ST_Library\stm32f7xx_hal_tim_ex.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_stm32f7xx.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\system_stm32f7xx.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_it.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\stm32f7xx_it.c</FilePath>
+ </File>
+ <File>
+ <FileName>stm32f7xx_hal_msp.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_Keil\stm32f7xx_hal_msp.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_stm32f756xx.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\System_Keil\startup_stm32f756xx.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS Source</GroupName>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM7\r0p1\port.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common Demo Tasks</GroupName>
+ <Files>
+ <File>
+ <FileName>BlockQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\death.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>EventGroupsDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\EventGroupsDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>integer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\integer.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\IntQueue.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntSemTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\IntSemTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>PollQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>QPeek.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\QPeek.c</FilePath>
+ </File>
+ <File>
+ <FileName>QueueOverwrite.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\QueueOverwrite.c</FilePath>
+ </File>
+ <File>
+ <FileName>QueueSet.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\QueueSet.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>TaskNotify.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\TaskNotify.c</FilePath>
+ </File>
+ <File>
+ <FileName>TimerDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_hal_legacy.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file contains aliases definition for the STM32Cube HAL constants \r
+ * macros and functions maintained for legacy purpose.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_HAL_LEGACY\r
+#define __STM32_HAL_LEGACY\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
+#define REGULAR_GROUP ADC_REGULAR_GROUP\r
+#define INJECTED_GROUP ADC_INJECTED_GROUP\r
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
+#define AWD_EVENT ADC_AWD_EVENT\r
+#define AWD1_EVENT ADC_AWD1_EVENT\r
+#define AWD2_EVENT ADC_AWD2_EVENT\r
+#define AWD3_EVENT ADC_AWD3_EVENT\r
+#define OVR_EVENT ADC_OVR_EVENT\r
+#define JQOVF_EVENT ADC_JQOVF_EVENT\r
+#define ALL_CHANNELS ADC_ALL_CHANNELS\r
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO \r
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 \r
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO \r
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 \r
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */ \r
+ \r
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)\r
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)\r
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) \r
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
+#define OBEX_PCROP OPTIONBYTE_PCROP\r
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
+#define PAGESIZE FLASH_PAGE_SIZE\r
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
+#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
+#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
+#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
+#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
+#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
+#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
+#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
+ * @{\r
+ */\r
+#if defined(STM32L4) || defined(STM32F7)\r
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
+#else\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
+#define GET_GPIO_INDEX GPIO_GET_INDEX\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
+\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define NAND_AddressTypedef NAND_AddressTypeDef\r
+\r
+#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
+#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
+\r
+#define __NOR_WRITE NOR_WRITE\r
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
+ \r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 \r
+\r
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 \r
+\r
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
+ \r
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO \r
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 \r
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/* Compact Flash-ATA registers description */\r
+#define CF_DATA ATA_DATA \r
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT \r
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER \r
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW \r
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH \r
+#define CF_CARD_HEAD ATA_CARD_HEAD \r
+#define CF_STATUS_CMD ATA_STATUS_CMD \r
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA \r
+\r
+/* Compact Flash-ATA commands */\r
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD \r
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
+\r
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define FORMAT_BIN RTC_FORMAT_BIN\r
+#define FORMAT_BCD RTC_FORMAT_BCD\r
+\r
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+\r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE \r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE \r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
+\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
+\r
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
+\r
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
+\r
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
+ \r
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
+#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
+#define TIM_DMABase_SR TIM_DMABASE_SR\r
+#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
+#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
+#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
+#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
+#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
+#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
+#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
+#define TIM_DMABase_OR TIM_DMABASE_OR\r
+\r
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
+\r
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
+\r
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
+\r
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
+\r
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
+\r
+#define USARTNACK_ENABLED USART_NACK_ENABLE\r
+#define USARTNACK_DISABLED USART_NACK_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CFR_BASE WWDG_CFR_BASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)\r
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)\r
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define VLAN_TAG ETH_VLAN_TAG\r
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
+\r
+#define ETH_MMCCR ((uint32_t)0x00000100) \r
+#define ETH_MMCRIR ((uint32_t)0x00000104) \r
+#define ETH_MMCTIR ((uint32_t)0x00000108) \r
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) \r
+#define ETH_MMCTIMR ((uint32_t)0x00000110) \r
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) \r
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) \r
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) \r
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) \r
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) \r
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */ \r
+ \r
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
+\r
+/*HASH Algorithm Selection*/\r
+\r
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 \r
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
+\r
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH \r
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
+\r
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
+\r
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
+\r
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
+\r
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
+\r
+#define DBP_BitNumber DBP_BIT_NUMBER\r
+#define PVDE_BitNumber PVDE_BIT_NUMBER\r
+#define PMODE_BitNumber PMODE_BIT_NUMBER\r
+#define EWUP_BitNumber EWUP_BIT_NUMBER\r
+#define FPDS_BitNumber FPDS_BIT_NUMBER\r
+#define ODEN_BitNumber ODEN_BIT_NUMBER\r
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
+#define BRE_BitNumber BRE_BIT_NUMBER\r
+\r
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback \r
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
+#define HAL_TIM_DMAError TIM_DMAError\r
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */ \r
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_IT_CC CRYP_IT_CC\r
+#define AES_IT_ERR CRYP_IT_ERR\r
+#define AES_FLAG_CCF CRYP_FLAG_CCF\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM \r
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
+\r
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __ADC_ENABLE __HAL_ADC_ENABLE\r
+#define __ADC_DISABLE __HAL_ADC_DISABLE\r
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
+\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
+\r
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
+\r
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
+\r
+#define __HAL_ADC_SQR1 ADC_SQR1\r
+#define __HAL_ADC_SMPR1 ADC_SMPR1\r
+#define __HAL_ADC_SMPR2 ADC_SMPR2\r
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR ADC_JSQR\r
+\r
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
+\r
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
+\r
+\r
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
+ ((WAVE) == DAC_WAVE_NOISE)|| \\r
+ ((WAVE) == DAC_WAVE_TRIANGLE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_WRPAREA IS_OB_WRPAREA\r
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
+#define __HAL_I2C_SPEED I2C_SPEED\r
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
+\r
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+\r
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()\r
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()\r
+#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
+\r
+#if defined (STM32F4)\r
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() \r
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG \r
+#endif /* STM32F4 */\r
+/** \r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
+\r
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
+\r
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE \r
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE \r
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE\r
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE\r
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE\r
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE \r
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET\r
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET\r
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE\r
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE\r
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE\r
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE \r
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET\r
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET\r
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE\r
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE\r
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET\r
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET\r
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE\r
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE\r
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET\r
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET\r
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
+\r
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE \r
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE \r
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE \r
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE \r
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE \r
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE \r
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE \r
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE \r
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE \r
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE \r
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE \r
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE \r
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE \r
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE \r
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE \r
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE \r
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE \r
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE \r
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE \r
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE \r
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE \r
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE \r
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE \r
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE \r
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE \r
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE \r
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE \r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET \r
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE \r
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE \r
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE \r
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE \r
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE \r
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE \r
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE \r
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
+\r
+/* alias define maintained for legacy */\r
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+\r
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
+\r
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
+\r
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
+\r
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
+#define RCC_MCO_NODIV RCC_MCODIV_1\r
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
+\r
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
+\r
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
+\r
+#define CR_HSION_BB RCC_CR_HSION_BB\r
+#define CR_CSSON_BB RCC_CR_CSSON_BB\r
+#define CR_PLLON_BB RCC_CR_PLLON_BB\r
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
+#define CR_MSION_BB RCC_CR_MSION_BB\r
+#define CSR_LSION_BB RCC_CSR_LSION_BB\r
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
+\r
+#if defined (STM32F1)\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
+#endif /* STM32F1 */\r
+\r
+#define IS_ALARM IS_RTC_ALARM\r
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
+#define IS_TAMPER IS_RTC_TAMPER\r
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER \r
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
+\r
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
+\r
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+\r
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+\r
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
+\r
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE \r
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
+#define __USART_ENABLE __HAL_USART_ENABLE\r
+#define __USART_DISABLE __HAL_USART_DISABLE\r
+\r
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
+\r
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+\r
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
+\r
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
+\r
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
+\r
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+\r
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
+\r
+#define TIM_TS_ITR0 ((uint32_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint32_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint32_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint32_t)0x0030)\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+\r
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)\r
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)\r
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2))\r
+\r
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)\r
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)\r
+\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \\r
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))\r
+\r
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)\r
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)\r
+\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
+\r
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE \r
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_LTDC_LAYER LTDC_LAYER\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
+#define SAI_STREOMODE SAI_STEREOMODE\r
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY \r
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL \r
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL \r
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL \r
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL \r
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL \r
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32_HAL_LEGACY */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file contains all the functions prototypes for the HAL \r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_H\r
+#define __STM32F7xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @brief Freeze/Unfreeze Peripherals in Debug mode \r
+ */\r
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+\r
+/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))\r
+ \r
+\r
+/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\\r
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\\r
+ }while(0);\r
+\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(__IO uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+void HAL_EnableDBGSleepMode(void);\r
+void HAL_DisableDBGSleepMode(void);\r
+void HAL_EnableDBGStopMode(void);\r
+void HAL_DisableDBGStopMode(void);\r
+void HAL_EnableDBGStandbyMode(void);\r
+void HAL_DisableDBGStandbyMode(void);\r
+void HAL_EnableCompensationCell(void);\r
+void HAL_DisableCompensationCell(void);\r
+void HAL_EnableFMCMemorySwapping(void);\r
+void HAL_DisableFMCMemorySwapping(void);\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of ADC HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_ADC_H\r
+#define __STM32F7xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Types ADC Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */\r
+ HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */\r
+ HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ \r
+ HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */\r
+ HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */\r
+ HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */\r
+ HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */\r
+ HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */\r
+ HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */\r
+ HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */\r
+ HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */\r
+ HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */\r
+\r
+}HAL_ADC_StateTypeDef;\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for \r
+ all the ADCs.\r
+ This parameter can be a value of @ref ADC_ClockPrescaler */\r
+ uint32_t Resolution; /*!< Configures the ADC resolution dual mode. \r
+ This parameter can be a value of @ref ADC_Resolution */\r
+ uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. \r
+ This parameter can be a value of @ref ADC_data_align */\r
+ uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or \r
+ Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */ \r
+ uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set \r
+ at the end of single channel conversion or at the end of all conversions.\r
+ This parameter can be a value of @ref ADC_EOCSelection */\r
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */ \r
+ uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for\r
+ regular channel group.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */\r
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not \r
+ for regular channels.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done \r
+ using the sequencer for regular channel group.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */\r
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.\r
+ If set to ADC_SOFTWARE_START, external triggers are disabled.\r
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular\r
+ Note: This parameter can be modified only if there is no conversion is ongoing. */\r
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.\r
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.\r
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular\r
+ Note: This parameter can be modified only if there is no conversion is ongoing. */\r
+}ADC_InitTypeDef;\r
+\r
+/** \r
+ * @brief ADC handle Structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ ADC_TypeDef *Instance; /*!< Register base address */\r
+\r
+ ADC_InitTypeDef Init; /*!< ADC required parameters */\r
+\r
+ __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */\r
+\r
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */\r
+\r
+ HAL_LockTypeDef Lock; /*!< ADC locking object */\r
+\r
+ __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< ADC Error code */\r
+}ADC_HandleTypeDef;\r
+\r
+/** \r
+ * @brief ADC Configuration regular Channel structure definition\r
+ */ \r
+typedef struct \r
+{\r
+ uint32_t Channel; /*!< The ADC channel to configure. \r
+ This parameter can be a value of @ref ADC_channels */\r
+ uint32_t Rank; /*!< The rank in the regular group sequencer. \r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
+ uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.\r
+ This parameter can be a value of @ref ADC_sampling_times */\r
+ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */\r
+}ADC_ChannelConfTypeDef;\r
+\r
+/** \r
+ * @brief ADC Configuration multi-mode structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.\r
+ This parameter can be a value of @ref ADC_analog_watchdog_selection */\r
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.\r
+ This parameter must be a 12-bit value. */ \r
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.\r
+ This parameter must be a 12-bit value. */\r
+ uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. \r
+ This parameter has an effect only if watchdog mode is configured on single channel \r
+ This parameter can be a value of @ref ADC_channels */ \r
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured\r
+ is interrupt mode or in polling mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */\r
+}ADC_AnalogWDGConfTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants ADC Exported Constants\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup ADC_Error_Code ADC Error Code\r
+ * @{\r
+ */ \r
+\r
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */\r
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */\r
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler\r
+ * @{\r
+ */ \r
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases\r
+ * @{\r
+ */ \r
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)\r
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)\r
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)\r
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)\r
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)\r
+#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))\r
+#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))\r
+#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r
+#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r
+#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Resolution ADC Resolution\r
+ * @{\r
+ */ \r
+#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)\r
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)\r
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)\r
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular\r
+ * @{\r
+ */ \r
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)\r
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)\r
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)\r
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular\r
+ * @{\r
+ */\r
+/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */\r
+/* compatibility with other STM32 devices. */\r
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)\r
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)\r
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)\r
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r
+#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)\r
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))\r
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)\r
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))\r
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))\r
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))\r
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r
+\r
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)\r
+#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align ADC Data Align \r
+ * @{\r
+ */ \r
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)\r
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels ADC Common Channels\r
+ * @{\r
+ */ \r
+#define ADC_CHANNEL_0 ((uint32_t)0x00000000)\r
+#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)\r
+#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)\r
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)\r
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)\r
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))\r
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))\r
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)\r
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))\r
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))\r
+\r
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)\r
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)\r
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_sampling_times ADC Sampling Times\r
+ * @{\r
+ */ \r
+#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)\r
+#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)\r
+#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)\r
+#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))\r
+#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)\r
+#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))\r
+#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))\r
+#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup ADC_EOCSelection ADC EOC Selection\r
+ * @{\r
+ */ \r
+#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)\r
+#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)\r
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Event_type ADC Event Type\r
+ * @{\r
+ */ \r
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)\r
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection\r
+ * @{\r
+ */ \r
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))\r
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))\r
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)\r
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)\r
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition\r
+ * @{\r
+ */ \r
+#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) \r
+#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) \r
+#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)\r
+#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup ADC_flags_definition ADC Flags Definition\r
+ * @{\r
+ */ \r
+#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)\r
+#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)\r
+#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)\r
+#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)\r
+#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)\r
+#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels_type ADC Channels Type\r
+ * @{\r
+ */ \r
+#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)\r
+#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */\r
+#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Macros ADC Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset ADC handle state\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the ADC peripheral.\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)\r
+\r
+/**\r
+ * @brief Disable the ADC peripheral.\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)\r
+\r
+/**\r
+ * @brief Enable the ADC end of conversion interrupt.\r
+ * @param __HANDLE__: specifies the ADC Handle.\r
+ * @param __INTERRUPT__: ADC Interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the ADC end of conversion interrupt.\r
+ * @param __HANDLE__: specifies the ADC Handle.\r
+ * @param __INTERRUPT__: ADC interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))\r
+\r
+/** @brief Check if the specified ADC interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: specifies the ADC Handle.\r
+ * @param __INTERRUPT__: specifies the ADC interrupt source to check.\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clear the ADC's pending flags.\r
+ * @param __HANDLE__: specifies the ADC Handle.\r
+ * @param __FLAG__: ADC flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))\r
+\r
+/**\r
+ * @brief Get the selected ADC's flag status.\r
+ * @param __HANDLE__: specifies the ADC Handle.\r
+ * @param __FLAG__: ADC flag.\r
+ * @retval None\r
+ */\r
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include ADC HAL Extension module */\r
+#include "stm32f7xx_hal_adc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup ADC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions ***********************************/\r
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);\r
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ******************************************************/\r
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r
+\r
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);\r
+\r
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);\r
+\r
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);\r
+\r
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);\r
+\r
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);\r
+\r
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);\r
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control functions *************************************************/\r
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);\r
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Peripheral State functions ***************************************************/\r
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);\r
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup ADC_Private_Constants ADC Private Constants\r
+ * @{\r
+ */\r
+/* Delay for ADC stabilization time. */\r
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */\r
+/* Unit: us */\r
+#define ADC_STAB_DELAY_US ((uint32_t) 3)\r
+/* Delay for temperature sensor stabilization time. */\r
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */\r
+/* Unit: us */\r
+#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup ADC_Private_Macros ADC Private Macros\r
+ * @{\r
+ */\r
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \\r
+ ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV8))\r
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \\r
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))\r
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \\r
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B)) \r
+#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))\r
+#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \\r
+ ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \\r
+ ((__REGTRIG__) == ADC_SOFTWARE_START))\r
+#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \\r
+ ((__ALIGN__) == ADC_DATAALIGN_LEFT)) \r
+#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \\r
+ ((__CHANNEL__) == ADC_CHANNEL_18)) \r
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \\r
+ ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) \r
+#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \\r
+ ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \\r
+ ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) \r
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \\r
+ ((__EVENT__) == ADC_OVR_EVENT)) \r
+#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \\r
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))\r
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \\r
+ ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \\r
+ ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))\r
+#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))\r
+#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))\r
+#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))\r
+#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))\r
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \\r
+ ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \\r
+ (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \\r
+ (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \\r
+ (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))\r
+\r
+/**\r
+ * @brief Set ADC Regular channel sequence length.\r
+ * @param _NbrOfConversion_: Regular channel sequence length. \r
+ * @retval None\r
+ */\r
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)\r
+\r
+/**\r
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.\r
+ * @param _SAMPLETIME_: Sample time parameter.\r
+ * @param _CHANNELNB_: Channel number. \r
+ * @retval None\r
+ */\r
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))\r
+\r
+/**\r
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.\r
+ * @param _SAMPLETIME_: Sample time parameter.\r
+ * @param _CHANNELNB_: Channel number. \r
+ * @retval None\r
+ */\r
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))\r
+\r
+/**\r
+ * @brief Set the selected regular channel rank for rank between 1 and 6.\r
+ * @param _CHANNELNB_: Channel number.\r
+ * @param _RANKNB_: Rank number. \r
+ * @retval None\r
+ */\r
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))\r
+\r
+/**\r
+ * @brief Set the selected regular channel rank for rank between 7 and 12.\r
+ * @param _CHANNELNB_: Channel number.\r
+ * @param _RANKNB_: Rank number. \r
+ * @retval None\r
+ */\r
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))\r
+\r
+/**\r
+ * @brief Set the selected regular channel rank for rank between 13 and 16.\r
+ * @param _CHANNELNB_: Channel number.\r
+ * @param _RANKNB_: Rank number. \r
+ * @retval None\r
+ */\r
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))\r
+\r
+/**\r
+ * @brief Enable ADC continuous conversion mode.\r
+ * @param _CONTINUOUS_MODE_: Continuous mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)\r
+\r
+/**\r
+ * @brief Configures the number of discontinuous conversions for the regular group channels.\r
+ * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.\r
+ * @retval None\r
+ */\r
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))\r
+\r
+/**\r
+ * @brief Enable ADC scan mode.\r
+ * @param _SCANCONV_MODE_: Scan conversion mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)\r
+\r
+/**\r
+ * @brief Enable the ADC end of conversion selection.\r
+ * @param _EOCSelection_MODE_: End of conversion selection mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)\r
+\r
+/**\r
+ * @brief Enable the ADC DMA continuous request.\r
+ * @param _DMAContReq_MODE_: DMA continuous request mode.\r
+ * @retval None\r
+ */\r
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)\r
+\r
+/**\r
+ * @brief Return resolution bits in CR1 register.\r
+ * @param __HANDLE__: ADC handle\r
+ * @retval None\r
+ */\r
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup ADC_Private_Functions ADC Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F7xx_ADC_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of ADC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_ADC_EX_H\r
+#define __STM32F7xx_ADC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADCEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ADCEx_Exported_Types ADC Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief ADC Configuration injected Channel structure definition\r
+ */ \r
+typedef struct \r
+{\r
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel.\r
+ This parameter can be a value of @ref ADC_channels */ \r
+ uint32_t InjectedRank; /*!< The rank in the injected group sequencer\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ \r
+ uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.\r
+ This parameter can be a value of @ref ADC_sampling_times */\r
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.\r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for\r
+ injected channel group.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */\r
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group \r
+ conversion after regular one */\r
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels. \r
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */\r
+ uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.\r
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */\r
+}ADC_InjectionConfTypeDef;\r
+\r
+/** \r
+ * @brief ADC Configuration multi-mode structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. \r
+ This parameter can be a value of @ref ADCEx_Common_mode */\r
+ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.\r
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */\r
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.\r
+ This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */\r
+}ADC_MultiModeTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ADCEx_Exported_Constants ADC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADCEx_Common_mode ADC Common Mode\r
+ * @{\r
+ */\r
+#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) \r
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)\r
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)\r
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))\r
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))\r
+#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r
+#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r
+#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r
+#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode\r
+ * @{\r
+ */ \r
+#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */\r
+#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\r
+#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\r
+#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected\r
+ * @{\r
+ */\r
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)\r
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)\r
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)\r
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected\r
+ * @{\r
+ */\r
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)\r
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)\r
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)\r
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)\r
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r
+\r
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)\r
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))\r
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))\r
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))\r
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection\r
+ * @{\r
+ */ \r
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)\r
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)\r
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)\r
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Macros ADC Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup ADCEx_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup ADCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* I/O operation functions ******************************************************/\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);\r
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);\r
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);\r
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);\r
+\r
+/* Peripheral Control functions *************************************************/\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup ADCEx_Private_Constants ADC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup ADCEx_Private_Macros ADC Private Macros\r
+ * @{\r
+ */\r
+#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \\r
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \\r
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \\r
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_INTERL) || \\r
+ ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))\r
+#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \\r
+ ((__MODE__) == ADC_DMAACCESSMODE_1) || \\r
+ ((__MODE__) == ADC_DMAACCESSMODE_2) || \\r
+ ((__MODE__) == ADC_DMAACCESSMODE_3))\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \\r
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))\r
+#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \\r
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO))\r
+#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))\r
+#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))\r
+\r
+/**\r
+ * @brief Set the selected injected Channel rank.\r
+ * @param _CHANNELNB_: Channel number.\r
+ * @param _RANKNB_: Rank number. \r
+ * @param _JSQR_JL_: Sequence length. \r
+ * @retval None\r
+ */\r
+#define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup ADCEx_Private_Functions ADC Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F7xx_ADC_EX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_can.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CAN HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CAN_H\r
+#define __STM32F7xx_HAL_CAN_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CAN\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Types CAN Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */\r
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */\r
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */\r
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */\r
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */\r
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */\r
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */\r
+\r
+}HAL_CAN_StateTypeDef;\r
+\r
+/**\r
+ * @brief CAN init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r
+\r
+ uint32_t Mode; /*!< Specifies the CAN operating mode.\r
+ This parameter can be a value of @ref CAN_operating_mode */\r
+\r
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta\r
+ the CAN hardware is allowed to lengthen or\r
+ shorten a bit to perform resynchronization.\r
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
+\r
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r
+\r
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
+\r
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+}CAN_InitTypeDef;\r
+\r
+/**\r
+ * @brief CAN filter configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
+ configuration, first one for a 16-bit configuration).\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
+ configuration, second one for a 16-bit configuration).\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (MSBs for a 32-bit configuration,\r
+ first one for a 16-bit configuration).\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (LSBs for a 32-bit configuration,\r
+ second one for a 16-bit configuration).\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
+ This parameter can be a value of @ref CAN_filter_FIFO */\r
+\r
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */\r
+\r
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.\r
+ This parameter can be a value of @ref CAN_filter_mode */\r
+\r
+ uint32_t FilterScale; /*!< Specifies the filter scale.\r
+ This parameter can be a value of @ref CAN_filter_scale */\r
+\r
+ uint32_t FilterActivation; /*!< Enable or disable the filter.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t BankNumber; /*!< Select the start slave bank filter.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */\r
+\r
+}CAN_FilterConfTypeDef;\r
+\r
+/**\r
+ * @brief CAN Tx message structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */\r
+\r
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_Identifier_Type */\r
+\r
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r
+\r
+ uint32_t Data[8]; /*!< Contains the data to be transmitted.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r
+\r
+}CanTxMsgTypeDef;\r
+\r
+/**\r
+ * @brief CAN Rx message structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */\r
+\r
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.\r
+ This parameter can be a value of @ref CAN_Identifier_Type */\r
+\r
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r
+\r
+ uint32_t Data[8]; /*!< Contains the data to be received.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r
+\r
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r
+\r
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.\r
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */\r
+\r
+}CanRxMsgTypeDef;\r
+\r
+/**\r
+ * @brief CAN handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ CAN_TypeDef *Instance; /*!< Register base address */\r
+\r
+ CAN_InitTypeDef Init; /*!< CAN required parameters */\r
+\r
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */\r
+\r
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */\r
+\r
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */\r
+\r
+ HAL_LockTypeDef Lock; /*!< CAN locking object */\r
+\r
+ __IO uint32_t ErrorCode; /*!< CAN Error code */\r
+\r
+}CAN_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Constants CAN Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code\r
+ * @{\r
+ */\r
+#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */\r
+#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */\r
+#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */\r
+#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */\r
+#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */\r
+#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */\r
+#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */\r
+#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */\r
+#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */\r
+#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_InitStatus CAN InitStatus\r
+ * @{\r
+ */\r
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */\r
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_operating_mode CAN Operating Mode\r
+ * @{\r
+ */\r
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */\r
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */\r
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */\r
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width\r
+ * @{\r
+ */\r
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */\r
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */\r
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */\r
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1\r
+ * @{\r
+ */\r
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */\r
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */\r
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */\r
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */\r
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */\r
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */\r
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */\r
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */\r
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */\r
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */\r
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */\r
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */\r
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */\r
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */\r
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */\r
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2\r
+ * @{\r
+ */\r
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */\r
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */\r
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */\r
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */\r
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */\r
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */\r
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */\r
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_mode CAN Filter Mode\r
+ * @{\r
+ */\r
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */\r
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_scale CAN Filter Scale\r
+ * @{\r
+ */\r
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */\r
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO\r
+ * @{\r
+ */\r
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
+/* Legacy defines */\r
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Identifier_Type CAN Identifier Type\r
+ * @{\r
+ */\r
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */\r
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request\r
+ * @{\r
+ */\r
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */\r
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants\r
+ * @{\r
+ */\r
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */\r
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_flags CAN Flags\r
+ * @{\r
+ */\r
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r
+ and CAN_ClearFlag() functions. */\r
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with\r
+ CAN_GetFlagStatus() function. */\r
+\r
+/* Transmit Flags */\r
+#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */\r
+#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */\r
+#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */\r
+#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */\r
+#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */\r
+#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */\r
+#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */\r
+#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */\r
+#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */\r
+\r
+/* Receive Flags */\r
+#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */\r
+#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */\r
+\r
+#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */\r
+#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */\r
+\r
+/* Operating Mode Flags */\r
+#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */\r
+#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */\r
+#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */\r
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.\r
+ In this case the SLAK bit can be polled.*/\r
+\r
+/* Error Flags */\r
+#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */\r
+#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */\r
+#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Interrupts CAN Interrupts\r
+ * @{\r
+ */\r
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */\r
+\r
+/* Receive Interrupts */\r
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */\r
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */\r
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */\r
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */\r
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */\r
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */\r
+\r
+/* Operating Mode Interrupts */\r
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */\r
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */\r
+\r
+/* Error Interrupts */\r
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */\r
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */\r
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */\r
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */\r
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */\r
+\r
+/* Flags named as Interrupts : kept only for FW compatibility */\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition\r
+ * @{\r
+ */\r
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)\r
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)\r
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Macros CAN Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset CAN handle state\r
+ * @param __HANDLE__: specifies the CAN Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the specified CAN interrupts.\r
+ * @param __HANDLE__: CAN handle\r
+ * @param __INTERRUPT__: CAN Interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified CAN interrupts.\r
+ * @param __HANDLE__: CAN handle\r
+ * @param __INTERRUPT__: CAN Interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Return the number of pending received messages.\r
+ * @param __HANDLE__: CAN handle\r
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval The number of pending message.\r
+ */\r
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \\r
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))\r
+\r
+/** @brief Check whether the specified CAN flag is set or not.\r
+ * @param __HANDLE__: CAN Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag\r
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag\r
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag\r
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag\r
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag\r
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag\r
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag\r
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag\r
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag\r
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag\r
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag\r
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag\r
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag\r
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag\r
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag\r
+ * @arg CAN_FLAG_WKU: Wake up Flag\r
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag\r
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag\r
+ * @arg CAN_FLAG_EWG: Error Warning Flag\r
+ * @arg CAN_FLAG_EPV: Error Passive Flag\r
+ * @arg CAN_FLAG_BOF: Bus-Off Flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \\r
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))\r
+\r
+/** @brief Clear the specified CAN pending flag.\r
+ * @param __HANDLE__: CAN Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag\r
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag\r
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag\r
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag\r
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag\r
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag\r
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag\r
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag\r
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag\r
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag\r
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag\r
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag\r
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag\r
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag\r
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag\r
+ * @arg CAN_FLAG_WKU: Wake up Flag\r
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag\r
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag\r
+ * @arg CAN_FLAG_EWG: Error Warning Flag\r
+ * @arg CAN_FLAG_EPV: Error Passive Flag\r
+ * @arg CAN_FLAG_BOF: Bus-Off Flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\r
+ (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))\r
+\r
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: CAN Handle\r
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable\r
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable\r
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Check the transmission status of a CAN Frame.\r
+ * @param __HANDLE__: CAN Handle\r
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.\r
+ * @retval The new status of transmission (TRUE or FALSE).\r
+ */\r
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\\r
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\\r
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\\r
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))\r
+\r
+/**\r
+ * @brief Release the specified receive FIFO.\r
+ * @param __HANDLE__: CAN handle\r
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \\r
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))\r
+\r
+/**\r
+ * @brief Cancel a transmit request.\r
+ * @param __HANDLE__: CAN Handle\r
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\\r
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\\r
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\\r
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))\r
+\r
+/**\r
+ * @brief Enable or disable the DBG Freeze for CAN.\r
+ * @param __HANDLE__: CAN Handle\r
+ * @param __NEWSTATE__: new state of the CAN peripheral.\r
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen\r
+ * during debug. Reception FIFOs can still be accessed/controlled normally)\r
+ * or DISABLE (CAN is working during debug).\r
+ * @retval None\r
+ */\r
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \\r
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CAN_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CAN_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions ***********************************/\r
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);\r
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);\r
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);\r
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);\r
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CAN_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ******************************************************/\r
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);\r
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);\r
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);\r
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);\r
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);\r
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);\r
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);\r
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CAN_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ***************************************************/\r
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);\r
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup CAN_Private_Types CAN Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup CAN_Private_Variables CAN Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup CAN_Private_Constants CAN Private Constants\r
+ * @{\r
+ */\r
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */\r
+#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */\r
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */\r
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CAN_Private_Macros CAN Private Macros\r
+ * @{\r
+ */\r
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \\r
+ ((MODE) == CAN_MODE_LOOPBACK)|| \\r
+ ((MODE) == CAN_MODE_SILENT) || \\r
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))\r
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \\r
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))\r
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)\r
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)\r
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \\r
+ ((MODE) == CAN_FILTERMODE_IDLIST))\r
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \\r
+ ((SCALE) == CAN_FILTERSCALE_32BIT))\r
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \\r
+ ((FIFO) == CAN_FILTER_FIFO1))\r
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)\r
+\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
+\r
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \\r
+ ((IDTYPE) == CAN_ID_EXT))\r
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
+\r
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \\r
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \\r
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))\r
+ \r
+\r
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \\r
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
+ ((FLAG) == CAN_FLAG_WKU))\r
+\r
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup CAN_Private_Functions CAN Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_CAN_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cec.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CEC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CEC_H\r
+#define __STM32F7xx_HAL_CEC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CEC\r
+ * @{\r
+ */\r
+ \r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup CEC_Exported_Types CEC Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief CEC Init Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.\r
+ It can be one of @ref CEC_Signal_Free_Time \r
+ and belongs to the set {0,...,7} where \r
+ 0x0 is the default configuration \r
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */\r
+\r
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,\r
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE \r
+ or CEC_EXTENDED_TOLERANCE */\r
+\r
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. \r
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped. \r
+ CEC_RX_STOP_ON_BRE: reception is stopped. */\r
+\r
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the\r
+ CEC line upon Bit Rising Error detection.\r
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.\r
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */\r
+ \r
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the\r
+ CEC line upon Long Bit Period Error detection.\r
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. \r
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ \r
+ \r
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line\r
+ upon an error detected on a broadcast message. \r
+ \r
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:\r
+ \r
+ 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.\r
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE \r
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.\r
+ b) LBPE detection: error-bit generation on the CEC line \r
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.\r
+ \r
+ 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.\r
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,\r
+ there is no error-bit generation in case of Short Bit Period Error detection in \r
+ a broadcast message while LSTN bit is set. */\r
+ \r
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.\r
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.\r
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */\r
+\r
+ uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */\r
+ \r
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:\r
+ \r
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its \r
+ own address (OAR). Messages addressed to different destination are ignored. \r
+ Broadcast messages are always received.\r
+ \r
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own \r
+ address (OAR) with positive acknowledge. Messages addressed to different destination \r
+ are received, but without interfering with the CEC bus: no acknowledge sent. */\r
+\r
+ uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */\r
+\r
+}CEC_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL CEC State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */\r
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */\r
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */\r
+ HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */\r
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */\r
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */\r
+}HAL_CEC_StateTypeDef;\r
+\r
+/** \r
+ * @brief CEC handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ CEC_TypeDef *Instance; /* CEC registers base address */\r
+ \r
+ CEC_InitTypeDef Init; /* CEC communication parameters */\r
+ \r
+ uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */\r
+ \r
+ uint16_t TxXferCount; /* CEC Tx Transfer Counter */\r
+ \r
+ uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */\r
+ \r
+ uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */\r
+ \r
+ uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register \r
+ in case error is reported */\r
+ \r
+ HAL_LockTypeDef Lock; /* Locking object */\r
+ \r
+ HAL_CEC_StateTypeDef State; /* CEC communication state */\r
+ \r
+}CEC_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup CEC_Exported_Constants CEC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Error_Code CEC Error Code\r
+ * @{\r
+ */ \r
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */\r
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */\r
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */\r
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */\r
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */\r
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */\r
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */\r
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */\r
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */\r
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter\r
+ * @{\r
+ */\r
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)\r
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)\r
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)\r
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)\r
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)\r
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)\r
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)\r
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance\r
+ * @{\r
+ */\r
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)\r
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error\r
+ * @{\r
+ */\r
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)\r
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported\r
+ * @{\r
+ */ \r
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)\r
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported\r
+ * @{\r
+ */ \r
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)\r
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message\r
+ * @{\r
+ */ \r
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)\r
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option\r
+ * @{\r
+ */ \r
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)\r
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_Listening_Mode CEC Listening mode option\r
+ * @{\r
+ */ \r
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)\r
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register \r
+ * @{\r
+ */\r
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header \r
+ * @{\r
+ */\r
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition\r
+ * @{\r
+ */\r
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE\r
+#define CEC_IT_TXERR CEC_IER_TXERRIE\r
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE\r
+#define CEC_IT_TXEND CEC_IER_TXENDIE\r
+#define CEC_IT_TXBR CEC_IER_TXBRIE\r
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE\r
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE\r
+#define CEC_IT_LBPE CEC_IER_LBPEIE\r
+#define CEC_IT_SBPE CEC_IER_SBPEIE\r
+#define CEC_IT_BRE CEC_IER_BREIE\r
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE\r
+#define CEC_IT_RXEND CEC_IER_RXENDIE\r
+#define CEC_IT_RXBR CEC_IER_RXBRIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Flags_Definitions CEC Flags definition\r
+ * @{\r
+ */\r
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE\r
+#define CEC_FLAG_TXERR CEC_ISR_TXERR\r
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR\r
+#define CEC_FLAG_TXEND CEC_ISR_TXEND\r
+#define CEC_FLAG_TXBR CEC_ISR_TXBR\r
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST\r
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE\r
+#define CEC_FLAG_LBPE CEC_ISR_LBPE\r
+#define CEC_FLAG_SBPE CEC_ISR_SBPE\r
+#define CEC_FLAG_BRE CEC_ISR_BRE\r
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR\r
+#define CEC_FLAG_RXEND CEC_ISR_RXEND\r
+#define CEC_FLAG_RXBR CEC_ISR_RXBR\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags \r
+ * @{\r
+ */\r
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\\r
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag \r
+ * @{\r
+ */\r
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag \r
+ * @{\r
+ */\r
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup CEC_Exported_Macros CEC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset CEC handle state\r
+ * @param __HANDLE__: CEC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)\r
+\r
+/** @brief Checks whether or not the specified CEC interrupt flag is set.\r
+ * @param __HANDLE__: specifies the CEC Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_FLAG_TXERR: Tx Error.\r
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.\r
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost\r
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r
+ * @arg CEC_FLAG_LBPE: Rx Long period Error\r
+ * @arg CEC_FLAG_SBPE: Rx Short period Error\r
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error\r
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.\r
+ * @arg CEC_FLAG_RXEND: End Of Reception.\r
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received. \r
+ * @retval ITStatus\r
+ */\r
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) \r
+\r
+/** @brief Clears the interrupt or status flag when raised (write at 1)\r
+ * @param __HANDLE__: specifies the CEC Handle.\r
+ * @param __FLAG__: specifies the interrupt/status flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_FLAG_TXERR: Tx Error.\r
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.\r
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost\r
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r
+ * @arg CEC_FLAG_LBPE: Rx Long period Error\r
+ * @arg CEC_FLAG_SBPE: Rx Short period Error\r
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error\r
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.\r
+ * @arg CEC_FLAG_RXEND: End Of Reception.\r
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received. \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \r
+\r
+/** @brief Enables the specified CEC interrupt.\r
+ * @param __HANDLE__: specifies the CEC Handle.\r
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r
+ * @arg CEC_IT_TXERR: Tx Error IT Enable \r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r
+ * @arg CEC_IT_TXEND: End of transmission IT Enable \r
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable \r
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable \r
+ * @retval none\r
+ */\r
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) \r
+\r
+/** @brief Disables the specified CEC interrupt.\r
+ * @param __HANDLE__: specifies the CEC Handle.\r
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r
+ * @arg CEC_IT_TXERR: Tx Error IT Enable \r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r
+ * @arg CEC_IT_TXEND: End of transmission IT Enable \r
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable \r
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable \r
+ * @retval none\r
+ */ \r
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) \r
+\r
+/** @brief Checks whether or not the specified CEC interrupt is enabled.\r
+ * @param __HANDLE__: specifies the CEC Handle.\r
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r
+ * @arg CEC_IT_TXERR: Tx Error IT Enable \r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r
+ * @arg CEC_IT_TXEND: End of transmission IT Enable \r
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable \r
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable \r
+ * @retval FlagStatus \r
+ */\r
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))\r
+\r
+/** @brief Enables the CEC device\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)\r
+\r
+/** @brief Disables the CEC device\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)\r
+\r
+/** @brief Set Transmission Start flag\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)\r
+\r
+/** @brief Set Transmission End flag\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval none \r
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. \r
+ */\r
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)\r
+\r
+/** @brief Get Transmission Start flag\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval FlagStatus \r
+ */\r
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)\r
+\r
+/** @brief Get Transmission End flag\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval FlagStatus \r
+ */\r
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) \r
+\r
+/** @brief Clear OAR register\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)\r
+\r
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)\r
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand\r
+ * @param __HANDLE__: specifies the CEC Handle. \r
+ * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) \r
+ * @retval none \r
+ */\r
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CEC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CEC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);\r
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CEC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ***************************************************/\r
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);\r
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);\r
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);\r
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CEC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);\r
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Types CEC Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Variables CEC Private Variables\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Constants CEC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Macros CEC Private Macros\r
+ * @{\r
+ */\r
+ \r
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) \r
+\r
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \\r
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))\r
+ \r
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \\r
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))\r
+ \r
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \\r
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))\r
+\r
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \\r
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))\r
+ \r
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \\r
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))\r
+ \r
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \\r
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))\r
+ \r
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \\r
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))\r
+ \r
+/** @brief Check CEC device Own Address Register (OAR) setting.\r
+ * OAR address is written in a 15-bit field within CEC_CFGR register. \r
+ * @param __ADDRESS__: CEC own address. \r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF) \r
+\r
+/** @brief Check CEC initiator or destination logical address setting.\r
+ * Initiator and destination addresses are coded over 4 bits. \r
+ * @param __ADDRESS__: CEC initiator or logical address. \r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) \r
+\r
+/** @brief Check CEC message size.\r
+ * The message size is the payload size: without counting the header, \r
+ * it varies from 0 byte (ping operation, one header only, no payload) to \r
+ * 15 bytes (1 opcode and up to 14 operands following the header). \r
+ * @param __SIZE__: CEC message size. \r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Functions CEC Private Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CEC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_conf_template.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HAL configuration template file. \r
+ * This file should be copied to the application folder and renamed\r
+ * to stm32f7xx_hal_conf.h.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CONF_H\r
+#define __STM32F7xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver \r
+ */\r
+#define HAL_MODULE_ENABLED \r
+#define HAL_ADC_MODULE_ENABLED \r
+#define HAL_CAN_MODULE_ENABLED\r
+#define HAL_CEC_MODULE_ENABLED \r
+#define HAL_CRC_MODULE_ENABLED \r
+#define HAL_CRYP_MODULE_ENABLED \r
+#define HAL_DAC_MODULE_ENABLED \r
+#define HAL_DCMI_MODULE_ENABLED \r
+#define HAL_DMA_MODULE_ENABLED\r
+#define HAL_DMA2D_MODULE_ENABLED \r
+#define HAL_ETH_MODULE_ENABLED \r
+#define HAL_FLASH_MODULE_ENABLED \r
+#define HAL_NAND_MODULE_ENABLED\r
+#define HAL_NOR_MODULE_ENABLED\r
+#define HAL_SRAM_MODULE_ENABLED\r
+#define HAL_SDRAM_MODULE_ENABLED\r
+#define HAL_HASH_MODULE_ENABLED \r
+#define HAL_GPIO_MODULE_ENABLED\r
+#define HAL_I2C_MODULE_ENABLED\r
+#define HAL_I2S_MODULE_ENABLED \r
+#define HAL_IWDG_MODULE_ENABLED \r
+#define HAL_LPTIM_MODULE_ENABLED\r
+#define HAL_LTDC_MODULE_ENABLED \r
+#define HAL_PWR_MODULE_ENABLED\r
+#define HAL_QSPI_MODULE_ENABLED \r
+#define HAL_RCC_MODULE_ENABLED \r
+#define HAL_RNG_MODULE_ENABLED \r
+#define HAL_RTC_MODULE_ENABLED\r
+#define HAL_SAI_MODULE_ENABLED \r
+#define HAL_SD_MODULE_ENABLED \r
+#define HAL_SPDIFRX_MODULE_ENABLED\r
+#define HAL_SPI_MODULE_ENABLED \r
+#define HAL_TIM_MODULE_ENABLED \r
+#define HAL_UART_MODULE_ENABLED \r
+#define HAL_USART_MODULE_ENABLED \r
+#define HAL_IRDA_MODULE_ENABLED \r
+#define HAL_SMARTCARD_MODULE_ENABLED \r
+#define HAL_WWDG_MODULE_ENABLED \r
+#define HAL_CORTEX_MODULE_ENABLED\r
+#define HAL_PCD_MODULE_ENABLED\r
+#define HAL_HCD_MODULE_ENABLED\r
+\r
+\r
+/* ########################## HSE/HSI Values adaptation ##################### */\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief Internal Low Speed oscillator (LSI) value.\r
+ */\r
+#if !defined (LSI_VALUE) \r
+ #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+#endif /* LSE_VALUE */\r
+\r
+/**\r
+ * @brief External clock source for I2S peripheral\r
+ * This value is used by the I2S HAL module to compute the I2S clock source \r
+ * frequency, this source is inserted directly through I2S_CKIN pad. \r
+ */\r
+#if !defined (EXTERNAL_CLOCK_VALUE)\r
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* EXTERNAL_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */ \r
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */\r
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */\r
+#define USE_RTOS 0\r
+#define PREFETCH_ENABLE 1\r
+#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* ################## Ethernet peripheral configuration ##################### */\r
+\r
+/* Section 1 : Ethernet peripheral configuration */\r
+\r
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r
+#define MAC_ADDR0 2\r
+#define MAC_ADDR1 0\r
+#define MAC_ADDR2 0\r
+#define MAC_ADDR3 0\r
+#define MAC_ADDR4 0\r
+#define MAC_ADDR5 0\r
+\r
+/* Definition of the Ethernet driver buffers size and count */ \r
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */\r
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */\r
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */\r
+\r
+/* Section 2: PHY configuration section */\r
+\r
+/* DP83848 PHY Address*/ \r
+#define DP83848_PHY_ADDRESS 0x01\r
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)\r
+/* PHY Configuration delay */\r
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)\r
+\r
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)\r
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)\r
+\r
+/* Section 3: Common PHY Registers */\r
+\r
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */\r
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */\r
+ \r
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */\r
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */\r
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */\r
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */\r
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */\r
+\r
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */\r
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */\r
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */\r
+ \r
+/* Section 4: Extended PHY Registers */\r
+\r
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */\r
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */\r
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */\r
+ \r
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */\r
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */\r
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */\r
+\r
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */\r
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */\r
+\r
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */\r
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file \r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CAN_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_can.h"\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cec.h"\r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cryp.h" \r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_eth.h"\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sdram.h"\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_spdifrx.h"\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CONF_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CORTEX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CORTEX_H\r
+#define __STM32F7xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX\r
+ * @{\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+ * @brief MPU Region initialization structure \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Enable; /*!< Specifies the status of the region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
+ uint8_t Number; /*!< Specifies the number of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
+ uint8_t Size; /*!< Specifies the size of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ \r
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ \r
+ uint8_t AccessPermission; /*!< Specifies the region access permission type. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
+ uint8_t DisableExec; /*!< Specifies the instruction access status. \r
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
+ * @{\r
+ */\r
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r
+ * @{\r
+ */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)\r
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
+ * @{\r
+ */\r
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) \r
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)\r
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)\r
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+ * @{\r
+ */\r
+#define MPU_REGION_ENABLE ((uint8_t)0x01)\r
+#define MPU_REGION_DISABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+ * @{\r
+ */\r
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)\r
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)\r
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
+ * @{\r
+ */\r
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)\r
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)\r
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+ * @{\r
+ */\r
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)\r
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)\r
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06) \r
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07) \r
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08) \r
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) \r
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)\r
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) \r
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) \r
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) \r
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) \r
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) \r
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)\r
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)\r
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)\r
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) \r
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) \r
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) \r
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) \r
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)\r
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)\r
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)\r
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)\r
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)\r
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)\r
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) \r
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) \r
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r
+ * @{\r
+ */\r
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) \r
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01) \r
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) \r
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) \r
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05) \r
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+ * @{\r
+ */\r
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00) \r
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01) \r
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02) \r
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03) \r
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04) \r
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)\r
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)\r
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported Macros -----------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Configures the SysTick clock source.\r
+ * @param __CLKSRC__: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \\r
+ do { \\r
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \\r
+ { \\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \\r
+ } \\r
+ else \\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CORTEX_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+ ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
+ ((TYPE) == MPU_TEX_LEVEL1) || \\r
+ ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7))\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/** \r
+ * @} \r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/ \r
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions\r
+ * @brief CORTEX private functions \r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Disables the MPU\r
+ * @param None \r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void HAL_MPU_Disable(void)\r
+{\r
+ /* Disable fault exceptions */\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+ \r
+ /* Disable the MPU */\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MPU\r
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault, \r
+ * NMI, FAULTMASK and privileged accessto the default memory \r
+ * This parameter can be one of the following values:\r
+ * @arg MPU_HFNMI_PRIVDEF_NONE\r
+ * @arg MPU_HARDFAULT_NMI\r
+ * @arg MPU_PRIVILEGED_DEFAULT\r
+ * @arg MPU_HFNMI_PRIVDEF\r
+ * @retval None\r
+ */\r
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ /* Enable the MPU */\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+ \r
+ /* Enable fault exceptions */\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CORTEX_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CRC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CRC_H\r
+#define __STM32F7xx_HAL_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC CRC\r
+ * @brief CRC HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CRC_Exported_Types CRC Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */\r
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */\r
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */\r
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */\r
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */\r
+}HAL_CRC_StateTypeDef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. \r
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default \r
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. \r
+ In that case, there is no need to set GeneratingPolynomial field.\r
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */\r
+\r
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. \r
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default\r
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field. \r
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */\r
+\r
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree\r
+ respectively equal to 7, 8, 16 or 32. This field is written in normal representation, \r
+ e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.\r
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */ \r
+\r
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.\r
+ Value can be either one of\r
+ CRC_POLYLENGTH_32B (32-bit CRC)\r
+ CRC_POLYLENGTH_16B (16-bit CRC)\r
+ CRC_POLYLENGTH_8B (8-bit CRC)\r
+ CRC_POLYLENGTH_7B (7-bit CRC) */\r
+ \r
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse \r
+ is set to DEFAULT_INIT_VALUE_ENABLE */ \r
+ \r
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. \r
+ Can be either one of the following values \r
+ CRC_INPUTDATA_INVERSION_NONE no input data inversion\r
+ CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2\r
+ CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C\r
+ CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ \r
+ \r
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.\r
+ Can be either \r
+ CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or\r
+ CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */\r
+}CRC_InitTypeDef;\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ CRC_TypeDef *Instance; /*!< Register base address */ \r
+ \r
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */\r
+ \r
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */\r
+ \r
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. \r
+ Can be either \r
+ CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)\r
+ CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)\r
+ CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data) \r
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error\r
+ must occur if InputBufferFormat is not one of the three values listed above */ \r
+}CRC_HandleTypeDef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup CRC_Exported_Constants CRC exported constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial\r
+ * @{\r
+ */\r
+#define DEFAULT_CRC32_POLY 0x04C11DB7\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value\r
+ * @{\r
+ */\r
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used\r
+ * @{\r
+ */\r
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)\r
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used\r
+ * @{\r
+ */ \r
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)\r
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP\r
+ * @{\r
+ */\r
+#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)\r
+#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)\r
+#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)\r
+#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions\r
+ * @{\r
+ */\r
+#define HAL_CRC_LENGTH_32B 32\r
+#define HAL_CRC_LENGTH_16B 16\r
+#define HAL_CRC_LENGTH_8B 8\r
+#define HAL_CRC_LENGTH_7B 7\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CRC_Input_Buffer_Format CRC input buffer format\r
+ * @{\r
+ */\r
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but\r
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set \r
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for \r
+ * the CRC APIs to provide a correct result */ \r
+#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)\r
+#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)\r
+#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)\r
+#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)\r
+/** \r
+ * @}\r
+ */ \r
+\r
+/** \r
+ * @}\r
+ */ \r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Macros CRC exported macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset CRC handle state\r
+ * @param __HANDLE__: CRC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)\r
+\r
+/**\r
+ * @brief Reset CRC Data Register.\r
+ * @param __HANDLE__: CRC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)\r
+\r
+/**\r
+ * @brief Set CRC INIT non-default value\r
+ * @param __HANDLE__ : CRC handle\r
+ * @param __INIT__ : 32-bit initial value \r
+ * @retval None.\r
+ */\r
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) \r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param __HANDLE__: CRC handle\r
+ * @param __VALUE__: 8-bit value to be stored in the ID register\r
+ * @retval None\r
+ */\r
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r
+ * @param __HANDLE__: CRC handle\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Include CRC HAL Extension module */\r
+#include "stm32f7xx_hal_crc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CRC_Exported_Functions CRC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);\r
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);\r
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);\r
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Aliases for inter STM32 series compatibility */\r
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse\r
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse\r
+\r
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions\r
+ * @{\r
+ */\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Types CRC Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Defines CRC Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Variables CRC Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Constants CRC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Macros CRC Private Macros\r
+ * @{\r
+ */\r
+#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \\r
+ ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))\r
+#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \\r
+ ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))\r
+#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \\r
+ ((__LENGTH__) == CRC_POLYLENGTH_16B) || \\r
+ ((__LENGTH__) == CRC_POLYLENGTH_8B) || \\r
+ ((__LENGTH__) == CRC_POLYLENGTH_7B))\r
+#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \\r
+ ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \\r
+ ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup CRC_Private_Functions CRC Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CRC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CRC HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CRC_EX_H\r
+#define __STM32F7xx_HAL_CRC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRCEx CRCEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes\r
+ * @{\r
+ */\r
+#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)\r
+#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)\r
+#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)\r
+#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)\r
+\r
+#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \\r
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \\r
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \\r
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes\r
+ * @{\r
+ */\r
+#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)\r
+\r
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \\r
+ ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))\r
+/** \r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Set CRC output reversal\r
+ * @param __HANDLE__ : CRC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) \r
+\r
+/**\r
+ * @brief Unset CRC output reversal\r
+ * @param __HANDLE__ : CRC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) \r
+\r
+/**\r
+ * @brief Set CRC non-default polynomial\r
+ * @param __HANDLE__ : CRC handle\r
+ * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial \r
+ * @retval None.\r
+ */\r
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions\r
+ * @{\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);\r
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);\r
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);\r
+\r
+/* Peripheral Control functions ***********************************************/\r
+/* Peripheral State and Error functions ***************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CRC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CRYP HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CRYP_H\r
+#define __STM32F7xx_HAL_CRYP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx)\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRYP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup CRYP_Exported_Types CRYP Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r
+ This parameter can be a value of @ref CRYP CRYP_Data_Type */\r
+\r
+ uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length. \r
+ This parameter can be a value of @ref CRYP CRYP_Key_Size */\r
+\r
+ uint8_t* pKey; /*!< The key used for encryption/decryption */\r
+\r
+ uint8_t* pInitVect; /*!< The initialization vector used also as initialization\r
+ counter in CTR mode */\r
+\r
+ uint8_t IVSize; /*!< The size of initialization vector. \r
+ This parameter (called nonce size in CCM) is used only \r
+ in AES-128/192/256 encryption/decryption CCM mode */\r
+\r
+ uint8_t TagSize; /*!< The size of returned authentication TAG. \r
+ This parameter is used only in AES-128/192/256 \r
+ encryption/decryption CCM mode */\r
+\r
+ uint8_t* Header; /*!< The header used in GCM and CCM modes */\r
+\r
+ uint32_t HeaderSize; /*!< The size of header buffer in bytes */\r
+\r
+ uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.\r
+ This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */\r
+}CRYP_InitTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition\r
+ * @{\r
+ */\r
+ \r
+\r
+typedef enum\r
+{\r
+ HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */\r
+ HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */\r
+ HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */\r
+ HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */\r
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */\r
+}HAL_CRYP_STATETypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition\r
+ * @{\r
+ */\r
+ \r
+\r
+typedef enum\r
+{\r
+ HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */\r
+ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */\r
+ HAL_CRYP_PHASE_FINAL = 0x03 /*!< CRYP peripheral is in final phase\r
+ This is relevant only with CCM and GCM modes */\r
+}HAL_PhaseTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition\r
+ * @{\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ CRYP_InitTypeDef Init; /*!< CRYP required parameters */\r
+\r
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r
+\r
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r
+\r
+ __IO uint16_t CrypInCount; /*!< Counter of inputed data */\r
+\r
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */\r
+\r
+ HAL_StatusTypeDef Status; /*!< CRYP peripheral status */\r
+\r
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */\r
+\r
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */\r
+\r
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */\r
+}CRYP_HandleTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size\r
+ * @{\r
+ */\r
+#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)\r
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0\r
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type\r
+ * @{\r
+ */\r
+#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)\r
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0\r
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1\r
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection\r
+ * @{\r
+ */\r
+#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000C)\r
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014)\r
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018)\r
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001C)\r
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024)\r
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028)\r
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002C)\r
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030)\r
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt\r
+ * @{\r
+ */\r
+#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */\r
+#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags\r
+ * @{\r
+ */\r
+#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently \r
+ processing a block of data \r
+ or a key preparation (for \r
+ AES decryption). */\r
+#define CRYP_FLAG_IFEM ((uint32_t)0x00000001) /*!< Input FIFO is empty */\r
+#define CRYP_FLAG_IFNF ((uint32_t)0x00000002) /*!< Input FIFO is not Full */\r
+#define CRYP_FLAG_OFNE ((uint32_t)0x00000004) /*!< Output FIFO is not empty */\r
+#define CRYP_FLAG_OFFU ((uint32_t)0x00000008) /*!< Output FIFO is Full */\r
+#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002) /*!< Output FIFO service raw \r
+ interrupt status */\r
+#define CRYP_FLAG_INRIS ((uint32_t)0x01000001) /*!< Input FIFO service raw \r
+ interrupt status */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset CRYP handle state\r
+ * @param __HANDLE__: specifies the CRYP handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable/Disable the CRYP peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)\r
+#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)\r
+\r
+/**\r
+ * @brief Flush the data FIFO.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)\r
+\r
+/**\r
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.\r
+ * @param MODE: The algorithm mode.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)\r
+\r
+/** @brief Check whether the specified CRYP flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data \r
+ * or a key preparation (for AES decryption). \r
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty\r
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full\r
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending\r
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty\r
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full\r
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+\r
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \\r
+ (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))\r
+\r
+/** @brief Check whether the specified CRYP interrupt is set or not.\r
+ * @param __INTERRUPT__: specifies the interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending\r
+ * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enable the CRYP interrupt.\r
+ * @param __INTERRUPT__: CRYP Interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the CRYP interrupt.\r
+ * @param __INTERRUPT__: CRYP interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Include CRYP HAL Extension module */\r
+#include "stm32f7xx_hal_cryp_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);\r
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);\r
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);\r
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+/* AES encryption/decryption using polling ***********************************/\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+\r
+/* AES encryption/decryption using interrupt *********************************/\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+\r
+/* AES encryption/decryption using DMA ***************************************/\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group3\r
+ * @{\r
+ */ \r
+/* DES encryption/decryption using polling ***********************************/\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+\r
+/* DES encryption/decryption using interrupt *********************************/\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+\r
+/* DES encryption/decryption using DMA ***************************************/\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group4\r
+ * @{\r
+ */ \r
+/* TDES encryption/decryption using polling **********************************/\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+\r
+/* TDES encryption/decryption using interrupt ********************************/\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+\r
+/* TDES encryption/decryption using DMA **************************************/\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group5\r
+ * @{\r
+ */ \r
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);\r
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);\r
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group6\r
+ * @{\r
+ */ \r
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup CRYP_Exported_Functions_Group7\r
+ * @{\r
+ */ \r
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup CRYP_Private_Types CRYP Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup CRYP_Private_Variables CRYP Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup CRYP_Private_Constants CRYP Private Constants\r
+ * @{\r
+ */\r
+#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CRYP_Private_Macros CRYP Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \\r
+ ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \\r
+ ((__KEYSIZE__) == CRYP_KEYSIZE_256B))\r
+\r
+\r
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \\r
+ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \\r
+ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \\r
+ ((__DATATYPE__) == CRYP_DATATYPE_1B)) \r
+\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup CRYP_Private_Functions CRYP Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* STM32F756xx */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CRYP_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of CRYP HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CRYP_EX_H\r
+#define __STM32F7xx_HAL_CRYP_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx)\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRYPEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection\r
+ * @{\r
+ */ \r
+#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000)\r
+#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004)\r
+#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008)\r
+#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig\r
+ * @brief The phases are relevant only to AES-GCM and AES-CCM\r
+ * @{\r
+ */ \r
+#define CRYP_PHASE_INIT ((uint32_t)0x00000000)\r
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0\r
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1\r
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Set the phase: Init, header, payload, final. \r
+ * This is relevant only for GCM and CCM modes.\r
+ * @param __PHASE__: The phase.\r
+ * @retval None\r
+ */\r
+#define __HAL_CRYP_SET_PHASE(__PHASE__) do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\\r
+ CRYP->CR |= (uint32_t)(__PHASE__);\\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRYPEx_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+ \r
+/* AES encryption/decryption using polling ***********************************/\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);\r
+\r
+/* AES encryption/decryption using interrupt *********************************/\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+\r
+/* AES encryption/decryption using DMA ***************************************/\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @addtogroup CRYPEx_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+ \r
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+\r
+ /* Private types -------------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* STM32F756xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CRYP_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DAC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DAC_H\r
+#define __STM32F7xx_HAL_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DAC_Exported_Types DAC Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */\r
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */\r
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */\r
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */\r
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */\r
+}HAL_DAC_StateTypeDef;\r
+ \r
+/** \r
+ * @brief DAC handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ DAC_TypeDef *Instance; /*!< Register base address */\r
+\r
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */\r
+\r
+ HAL_LockTypeDef Lock; /*!< DAC locking object */\r
+\r
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */\r
+\r
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DAC Error code */\r
+\r
+}DAC_HandleTypeDef;\r
+\r
+/** \r
+ * @brief DAC Configuration regular Channel structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_ChannelConfTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DAC_Exported_Constants DAC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Error_Code DAC Error Code\r
+ * @{\r
+ */\r
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */\r
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */\r
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */\r
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection DAC Trigger Selection\r
+ * @{\r
+ */\r
+\r
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ \r
+\r
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer DAC Output Buffer\r
+ * @{\r
+ */\r
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)\r
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Channel_selection DAC Channel Selection\r
+ * @{\r
+ */\r
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)\r
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignment DAC Data Alignment\r
+ * @{\r
+ */\r
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)\r
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)\r
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_flags_definition DAC Flags Definition\r
+ * @{\r
+ */ \r
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)\r
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_IT_definition DAC IT Definition\r
+ * @{\r
+ */ \r
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)\r
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup DAC_Exported_Macros DAC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DAC handle state\r
+ * @param __HANDLE__: specifies the DAC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)\r
+\r
+/** @brief Enable the DAC channel\r
+ * @param __HANDLE__: specifies the DAC handle.\r
+ * @param __DAC_CHANNEL__: specifies the DAC channel\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \\r
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))\r
+\r
+/** @brief Disable the DAC channel\r
+ * @param __HANDLE__: specifies the DAC handle\r
+ * @param __DAC_CHANNEL__: specifies the DAC channel.\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \\r
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))\r
+\r
+\r
+/** @brief Enable the DAC interrupt\r
+ * @param __HANDLE__: specifies the DAC handle\r
+ * @param __INTERRUPT__: specifies the DAC interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the DAC interrupt\r
+ * @param __HANDLE__: specifies the DAC handle\r
+ * @param __INTERRUPT__: specifies the DAC interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))\r
+\r
+/** @brief Checks if the specified DAC interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: DAC handle\r
+ * @param __INTERRUPT__: DAC interrupt source to check\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt\r
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt\r
+ * @retval State of interruption (SET or RESET)\r
+ */\r
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Get the selected DAC's flag status.\r
+ * @param __HANDLE__: specifies the DAC handle.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the DAC's flag.\r
+ * @param __HANDLE__: specifies the DAC handle.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r
+ * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r
+ * @retval None\r
+ */\r
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include DAC HAL Extension module */\r
+#include "stm32f7xx_hal_dac_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DAC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions *********************************/\r
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);\r
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);\r
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);\r
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DAC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ****************************************************/\r
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);\r
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);\r
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DAC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DAC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Peripheral State functions *************************************************/\r
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);\r
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);\r
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);\r
+\r
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);\r
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup DAC_Private_Constants DAC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DAC_Private_Macros DAC Private Macros\r
+ * @{\r
+ */\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \\r
+ ((ALIGN) == DAC_ALIGN_12B_L) || \\r
+ ((ALIGN) == DAC_ALIGN_8B_R))\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \\r
+ ((CHANNEL) == DAC_CHANNEL_2))\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \\r
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \\r
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))\r
+\r
+/** @brief Set DHR12R1 alignment\r
+ * @param __ALIGNMENT__: specifies the DAC alignment\r
+ * @retval None\r
+ */\r
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))\r
+\r
+/** @brief Set DHR12R2 alignment\r
+ * @param __ALIGNMENT__: specifies the DAC alignment\r
+ * @retval None\r
+ */\r
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))\r
+\r
+/** @brief Set DHR12RD alignment\r
+ * @param __ALIGNMENT__: specifies the DAC alignment\r
+ * @retval None\r
+ */\r
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DAC_Private_Functions DAC Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F7xx_HAL_DAC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DAC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DAC_EX_H\r
+#define __STM32F7xx_HAL_DAC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DACEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DACEx_Exported_Constants DAC Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude\r
+ * @{\r
+ */\r
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DACEx_wave_Format DAC Wave Format\r
+ * @{\r
+ */\r
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)\r
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DACEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DACEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Extension features functions ***********************************************/\r
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);\r
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);\r
+\r
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);\r
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup DACEx_Private_Constants DAC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DACEx_Private_Macros DAC Private Macros\r
+ * @{\r
+ */\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \\r
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \\r
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DACEx_Private_Functions DAC Private Functions\r
+ * @{\r
+ */\r
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);\r
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);\r
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); \r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F7xx_HAL_DAC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DCMI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DCMI_H\r
+#define __STM32F7xx_HAL_DCMI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/* Include DCMI HAL Extended module */\r
+/* (include on top of file since DCMI structures are defined in extended file) */\r
+#include "stm32f7xx_hal_dcmi_ex.h"\r
+ \r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DCMI DCMI\r
+ * @brief DCMI HAL module driver\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DCMI_Exported_Types DCMI Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief DCMI Error source\r
+ */\r
+typedef enum\r
+{ \r
+ DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */\r
+ DCMI_OVERRUN = 2, /*!< DCMI Overrun */\r
+}DCMI_ErrorTypeDef;\r
+\r
+/** \r
+ * @brief HAL DCMI State structures definition\r
+ */ \r
+typedef enum\r
+{\r
+ HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */\r
+ HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */\r
+ HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */\r
+ HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */\r
+ HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */\r
+}HAL_DCMI_StateTypeDef;\r
+\r
+/** \r
+ * @brief DCMI handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ DCMI_TypeDef *Instance; /*!< DCMI Register base address */\r
+\r
+ DCMI_InitTypeDef Init; /*!< DCMI parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< DCMI locking object */\r
+\r
+ __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */\r
+\r
+ __IO uint32_t XferCount; /*!< DMA transfer counter */\r
+\r
+ __IO uint32_t XferSize; /*!< DMA transfer size */\r
+\r
+ uint32_t XferTransferNumber; /*!< DMA transfer number */\r
+\r
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */\r
+\r
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */\r
+\r
+}DCMI_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMI_Error_Code DCMI Error Code\r
+ * @{\r
+ */\r
+#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */\r
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */\r
+#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode\r
+ * @{\r
+ */ \r
+#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously \r
+ into the destination memory through the DMA */\r
+#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of \r
+ frame and then transfers a single frame through the DMA */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode\r
+ * @{\r
+ */ \r
+#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)\r
+ is synchronized with the HSYNC/VSYNC signals */\r
+#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with \r
+ synchronization codes embedded in the data flow */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity\r
+ * @{\r
+ */\r
+#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */\r
+#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity\r
+ * @{\r
+ */\r
+#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */\r
+#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity\r
+ * @{\r
+ */ \r
+#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */\r
+#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG\r
+ * @{\r
+ */\r
+#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */\r
+#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate\r
+ * @{\r
+ */\r
+#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */\r
+#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */\r
+#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode\r
+ * @{\r
+ */\r
+#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */\r
+#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */\r
+#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */\r
+#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate \r
+ * @{\r
+ */\r
+#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Window_Height DCMI Window Height\r
+ * @{\r
+ */ \r
+#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_interrupt_sources DCMI interrupt sources\r
+ * @{\r
+ */\r
+#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)\r
+#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)\r
+#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)\r
+#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)\r
+#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Flags DCMI Flags\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DCMI SR register\r
+ */ \r
+#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)\r
+#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)\r
+#define DCMI_FLAG_FNE ((uint32_t)0x2004)\r
+/** \r
+ * @brief DCMI RISR register \r
+ */ \r
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)\r
+#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)\r
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)\r
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)\r
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)\r
+/** \r
+ * @brief DCMI MISR register \r
+ */ \r
+#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)\r
+#define DCMI_FLAG_OVFMI ((uint32_t)0x1002)\r
+#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)\r
+#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)\r
+#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset DCMI handle state\r
+ * @param __HANDLE__: specifies the DCMI handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the DCMI.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)\r
+\r
+/**\r
+ * @brief Disable the DCMI.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))\r
+\r
+/* Interrupt & Flag management */\r
+/**\r
+ * @brief Get the DCMI pending flags.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask\r
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r
+ * @arg DCMI_FLAG_LINERI: Line flag mask\r
+ * @retval The state of FLAG.\r
+ */\r
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\\r
+((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\\r
+ (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DCMI pending flags.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask\r
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r
+ * @arg DCMI_FLAG_LINERI: Line flag mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Enable the specified DCMI interrupts.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r
+ * @arg DCMI_IT_OVF: Overflow interrupt mask\r
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r
+ * @arg DCMI_IT_LINE: Line interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified DCMI interrupts.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r
+ * @arg DCMI_IT_OVF: Overflow interrupt mask\r
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r
+ * @arg DCMI_IT_LINE: Line interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified DCMI interrupt has occurred or not.\r
+ * @param __HANDLE__: DCMI handle\r
+ * @param __INTERRUPT__: specifies the DCMI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r
+ * @arg DCMI_IT_OVF: Overflow interrupt mask\r
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask\r
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r
+ * @arg DCMI_IT_LINE: Line interrupt mask\r
+ * @retval The state of INTERRUPT.\r
+ */\r
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);\r
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);\r
+void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);\r
+void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup DCMI_Exported_Functions_Group2 Operations functions\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);\r
+void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);\r
+void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);\r
+void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);\r
+void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);\r
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);\r
+HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);\r
+HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+/* Peripheral State functions *************************************************/\r
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);\r
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/ \r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup DCMI_Private_Macros DCMI Private Macros\r
+ * @{\r
+ */\r
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \\r
+ ((MODE) == DCMI_MODE_SNAPSHOT))\r
+ \r
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \\r
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))\r
+ \r
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \\r
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))\r
+ \r
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \\r
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))\r
+ \r
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \\r
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))\r
+ \r
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \\r
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))\r
+ \r
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \\r
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \\r
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))\r
+ \r
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \\r
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \\r
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \\r
+ ((DATA) == DCMI_EXTEND_DATA_14B))\r
+ \r
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)\r
+\r
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DCMI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DCMI Extension HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DCMI_EX_H\r
+#define __STM32F7xx_HAL_DCMI_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DCMIEx DCMI Extended\r
+ * @brief DCMI HAL module driver\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DCMIEx_Exported_Types DCMI Extende Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief DCMIEx Embedded Synchronisation CODE Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */\r
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */\r
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */\r
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */\r
+}DCMI_CodesInitTypeDef;\r
+\r
+/** \r
+ * @brief DCMI Init structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.\r
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */\r
+\r
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.\r
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */\r
+\r
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.\r
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */\r
+\r
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.\r
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */\r
+\r
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.\r
+ This parameter can be a value of @ref DCMI_Capture_Rate */\r
+\r
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.\r
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */\r
+\r
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */\r
+\r
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. \r
+ This parameter can be a value of @ref DCMI_MODE_JPEG */\r
+#if defined(STM32F746xx) || defined(STM32F756xx)\r
+ uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface \r
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */\r
+ \r
+ uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd\r
+ This parameter can be a value of @ref DCMIEx_Byte_Select_Start */\r
+\r
+ uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface \r
+ This parameter can be a value of @ref DCMIEx_Line_Select_Mode */\r
+ \r
+ uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd\r
+ This parameter can be a value of @ref DCMIEx_Line_Select_Start */\r
+ \r
+#endif /* STM32F746xx || STM32F756xx */\r
+}DCMI_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32F746xx) || defined(STM32F756xx)\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode\r
+ * @{\r
+ */\r
+#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */\r
+#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */\r
+#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */\r
+#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start\r
+ * @{\r
+ */ \r
+#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */\r
+#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode\r
+ * @{\r
+ */\r
+#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */\r
+#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start\r
+ * @{\r
+ */ \r
+#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */\r
+#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/ \r
+/* Exported functions --------------------------------------------------------*/\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/ \r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros\r
+ * @{\r
+ */\r
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \\r
+ ((MODE) == DCMI_BSM_OTHER) || \\r
+ ((MODE) == DCMI_BSM_ALTERNATE_4) || \\r
+ ((MODE) == DCMI_BSM_ALTERNATE_2))\r
+ \r
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \\r
+ ((POLARITY) == DCMI_OEBS_EVEN))\r
+ \r
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \\r
+ ((MODE) == DCMI_LSM_ALTERNATE_2))\r
+ \r
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \\r
+ ((POLARITY) == DCMI_OELS_EVEN))\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F746xx || STM32F756xx */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DCMI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_def.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file contains HAL common defines, enumeration, macros and \r
+ * structures definitions. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DEF\r
+#define __STM32F7xx_HAL_DEF\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx.h"\r
+#include "Legacy/stm32_hal_legacy.h"\r
+#include <stdio.h>\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief HAL Status structures definition \r
+ */ \r
+typedef enum \r
+{\r
+ HAL_OK = 0x00,\r
+ HAL_ERROR = 0x01,\r
+ HAL_BUSY = 0x02,\r
+ HAL_TIMEOUT = 0x03\r
+} HAL_StatusTypeDef;\r
+\r
+/** \r
+ * @brief HAL Lock structures definition \r
+ */\r
+typedef enum \r
+{\r
+ HAL_UNLOCKED = 0x00,\r
+ HAL_LOCKED = 0x01 \r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#define HAL_MAX_DELAY 0xFFFFFFFF\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)\r
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \\r
+ } while(0)\r
+\r
+#define UNUSED(x) ((void)(x))\r
+\r
+/** @brief Reset the Handle's State field.\r
+ * @param __HANDLE__: specifies the Peripheral Handle.\r
+ * @note This macro can be used for the following purpose: \r
+ * - When the Handle is declared as local variable; before passing it as parameter\r
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r
+ * to set to 0 the Handle's "State" field.\r
+ * Otherwise, "State" field may have any random value and the first time the function \r
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+ * (i.e. HAL_PPP_MspInit() will not be executed).\r
+ * - When there is a need to reconfigure the low level hardware: instead of calling\r
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+ * @retval None\r
+ */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)\r
+\r
+#if (USE_RTOS == 1)\r
+ /* Reserved for future use */\r
+ #error \93USE_RTOS should be 0 in the current HAL release\94\r
+#else\r
+ #define __HAL_LOCK(__HANDLE__) \\r
+ do{ \\r
+ if((__HANDLE__)->Lock == HAL_LOCKED) \\r
+ { \\r
+ return HAL_BUSY; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Lock = HAL_LOCKED; \\r
+ } \\r
+ }while (0)\r
+\r
+ #define __HAL_UNLOCK(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
+ }while (0)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ )\r
+ #ifndef __weak\r
+ #define __weak __attribute__((weak))\r
+ #endif /* __weak */\r
+ #ifndef __packed\r
+ #define __packed __attribute__((__packed__))\r
+ #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined (__GNUC__) /* GNU Compiler */\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END __attribute__ ((aligned (4)))\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #define __ALIGN_BEGIN\r
+ #endif /* __ALIGN_BEGIN */\r
+#else\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #if defined (__CC_ARM) /* ARM Compiler */\r
+ #define __ALIGN_BEGIN __align(4) \r
+ #elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define __ALIGN_BEGIN \r
+ #endif /* __CC_ARM */\r
+ #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/** \r
+ * @brief __RAM_FUNC definition\r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source module.\r
+ Using the 'Options for File' dialog you can simply change the 'Code / Const' \r
+ area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+ dialog. \r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+/** \r
+ * @brief __NOINLINE definition\r
+ */ \r
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )\r
+/* ARM & GNUCompiler \r
+ ---------------- \r
+*/\r
+#define __NOINLINE __attribute__ ( (noinline) )\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+*/\r
+#define __NOINLINE _Pragma("optimize = no_inline")\r
+\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32F7xx_HAL_DEF */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_H\r
+#define __STM32F7xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @brief DMA Exported Types \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream. \r
+ This parameter can be a value of @ref DMA_Channel_selection */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, \r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+\r
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r
+ This parameter can be a value of @ref DMA_FIFO_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the \r
+ memory-to-memory data transfer is configured on the selected stream */\r
+\r
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */\r
+\r
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Memory_burst \r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction. \r
+ This parameter can be a value of @ref DMA_Peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+}DMA_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */\r
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */\r
+ HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */\r
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */\r
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */\r
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */\r
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+/** \r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */ \r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */ \r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */ \r
+\r
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */\r
+\r
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @brief DMA Error Code \r
+ * @{\r
+ */ \r
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */\r
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */\r
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */\r
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Channel_selection DMA Channel selection\r
+ * @brief DMA channel selection \r
+ * @{\r
+ */ \r
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */\r
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */\r
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */\r
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */\r
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */\r
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */\r
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */\r
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @brief DMA data transfer direction \r
+ * @{\r
+ */ \r
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @brief DMA peripheral incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */\r
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @brief DMA memory incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */\r
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @brief DMA peripheral data size \r
+ * @{\r
+ */ \r
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */\r
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\r
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @brief DMA memory data size \r
+ * @{ \r
+ */\r
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */\r
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\r
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @brief DMA mode \r
+ * @{\r
+ */ \r
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */\r
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */\r
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @brief DMA priority levels \r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */\r
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */\r
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */\r
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r
+ * @brief DMA FIFO direct mode\r
+ * @{\r
+ */\r
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */\r
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r
+ * @brief DMA FIFO level \r
+ * @{\r
+ */\r
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */\r
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */\r
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */\r
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_burst DMA Memory burst\r
+ * @brief DMA memory burst \r
+ * @{\r
+ */ \r
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000) \r
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) \r
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) \r
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r
+ * @brief DMA peripheral burst \r
+ * @{\r
+ */ \r
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000) \r
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) \r
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) \r
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @brief DMA interrupts definition \r
+ * @{\r
+ */\r
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)\r
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)\r
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)\r
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)\r
+#define DMA_IT_FE ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @brief DMA flag definitions \r
+ * @{\r
+ */ \r
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)\r
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)\r
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)\r
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)\r
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)\r
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)\r
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)\r
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)\r
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)\r
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)\r
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)\r
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)\r
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)\r
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)\r
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)\r
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)\r
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)\r
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)\r
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)\r
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @brief Reset DMA handle state\r
+ * @param __HANDLE__: specifies the DMA handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO filled level.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The FIFO filling state.\r
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r
+ * and not empty.\r
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r
+ * - DMA_FIFOStatus_Empty: when FIFO is empty\r
+ * - DMA_FIFOStatus_Full: when FIFO is full\r
+ */\r
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ DMA_FLAG_TCIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream half transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */ \r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ DMA_FLAG_HTIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ DMA_FLAG_TEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified FIFO error flag index.\r
+ */\r
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ DMA_FLAG_FEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream direct mode error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified direct mode error flag index.\r
+ */\r
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ DMA_FLAG_DMEIF3_7)\r
+\r
+/**\r
+ * @brief Get the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Stream interrupt has occurred or not.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval The state of DMA_IT.\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\r
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Writes the number of data units to be transferred on the DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) \r
+ * Number of data items depends only on the Peripheral data format.\r
+ * \r
+ * @note If Peripheral data format is Bytes: number of data units is equal \r
+ * to total number of bytes to be transferred.\r
+ * \r
+ * @note If Peripheral data format is Half-Word: number of data units is \r
+ * equal to total number of bytes to be transferred / 2.\r
+ * \r
+ * @note If Peripheral data format is Word: number of data units is equal \r
+ * to total number of bytes to be transferred / 4.\r
+ * \r
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.\r
+ */\r
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r
+ * @param __HANDLE__: DMA handle\r
+ * \r
+ * @retval The number of remaining data units in the current DMA Stream transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r
+\r
+\r
+/* Include DMA HAL Extension module */\r
+#include "stm32f7xx_hal_dma_ex.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @brief DMA Exported functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r
+ * @brief I/O operation functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ * @{\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+/* Private Constants -------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Constants DMA Private Constants\r
+ * @brief DMA private defines and constants \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @brief DMA private macros \r
+ * @{\r
+ */\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7))\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR) || \\r
+ ((MODE) == DMA_PFCTRL)) \r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\r
+ ((STATE) == DMA_FIFOMODE_ENABLE))\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\r
+ ((BURST) == DMA_MBURST_INC4) || \\r
+ ((BURST) == DMA_MBURST_INC8) || \\r
+ ((BURST) == DMA_MBURST_INC16))\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\r
+ ((BURST) == DMA_PBURST_INC4) || \\r
+ ((BURST) == DMA_PBURST_INC8) || \\r
+ ((BURST) == DMA_PBURST_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @brief DMA private functions \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma2d.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DMA2D HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA2D_H\r
+#define __STM32F7xx_HAL_DMA2D_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA2D DMA2D\r
+ * @brief DMA2D HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types\r
+ * @{\r
+ */\r
+#define MAX_DMA2D_LAYER 2\r
+\r
+/** \r
+ * @brief DMA2D color Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Blue; /*!< Configures the blue value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint32_t Green; /*!< Configures the green value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint32_t Red; /*!< Configures the red value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+} DMA2D_ColorTypeDef;\r
+\r
+/** \r
+ * @brief DMA2D CLUT Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/\r
+\r
+ uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.\r
+ This parameter can be one value of @ref DMA2D_CLUT_CM */\r
+\r
+ uint32_t Size; /*!< configures the DMA2D CLUT size. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/\r
+} DMA2D_CLUTCfgTypeDef;\r
+\r
+/** \r
+ * @brief DMA2D Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< configures the DMA2D transfer mode.\r
+ This parameter can be one value of @ref DMA2D_Mode */\r
+\r
+ uint32_t ColorMode; /*!< configures the color format of the output image.\r
+ This parameter can be one value of @ref DMA2D_Color_Mode */\r
+\r
+ uint32_t OutputOffset; /*!< Specifies the Offset value. \r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ \r
+} DMA2D_InitTypeDef;\r
+\r
+/** \r
+ * @brief DMA2D Layer structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t InputOffset; /*!< configures the DMA2D foreground offset.\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */\r
+\r
+ uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode . \r
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode */\r
+\r
+ uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode. \r
+ This parameter can be one value of @ref DMA2D_ALPHA_MODE */\r
+\r
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode. \r
+ This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF \r
+ in case of A8 or A4 color mode (ARGB). \r
+ Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/\r
+\r
+} DMA2D_LayerCfgTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA2D State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */\r
+ HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */\r
+ HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */\r
+}HAL_DMA2D_StateTypeDef;\r
+\r
+/** \r
+ * @brief DMA2D handle Structure definition\r
+ */\r
+typedef struct __DMA2D_HandleTypeDef\r
+{\r
+ DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */\r
+\r
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */ \r
+\r
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */\r
+\r
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */\r
+\r
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ \r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA2D Lock */ \r
+\r
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA2D Error code */ \r
+} DMA2D_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA2D_Error_Code DMA2D Error Code\r
+ * @{\r
+ */\r
+#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */\r
+#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */\r
+#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Mode DMA2D Mode \r
+ * @{\r
+ */\r
+#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */\r
+#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */\r
+#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */\r
+#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Color_Mode DMA2D Color Mode \r
+ * @{\r
+ */\r
+#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */\r
+#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */\r
+#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */\r
+#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */\r
+#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE\r
+ * @{\r
+ */\r
+#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA2D_SIZE DMA2D SIZE \r
+ * @{\r
+ */\r
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */\r
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Offset DMA2D Offset \r
+ * @{\r
+ */\r
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode\r
+ * @{\r
+ */\r
+#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */\r
+#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */\r
+#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */\r
+#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */\r
+#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */\r
+#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */\r
+#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */\r
+#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */\r
+#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */\r
+#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */\r
+#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE\r
+ * @{\r
+ */\r
+#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */\r
+#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */\r
+#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value\r
+ with original alpha channel value */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM\r
+ * @{\r
+ */\r
+#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */\r
+#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Size_Clut DMA2D Size Clut\r
+ * @{\r
+ */\r
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_DeadTime DMA2D DeadTime \r
+ * @{\r
+ */\r
+#define LINE_WATERMARK DMA2D_LWR_LW\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts \r
+ * @{\r
+ */\r
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */\r
+#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */\r
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */\r
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */\r
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */\r
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Flag DMA2D Flag \r
+ * @{\r
+ */\r
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */\r
+#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */\r
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DMA2D handle state\r
+ * @param __HANDLE__: specifies the DMA2D handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the DMA2D.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)\r
+\r
+/**\r
+ * @brief Disable the DMA2D.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)\r
+\r
+/* Interrupt & Flag management */\r
+/**\r
+ * @brief Get the DMA2D pending flags.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA2D_FLAG_CE: Configuration error flag\r
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag\r
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag\r
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag\r
+ * @arg DMA2D_FLAG_TC: Transfer complete flag\r
+ * @arg DMA2D_FLAG_TE: Transfer error flag \r
+ * @retval The state of FLAG.\r
+ */\r
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r
+\r
+/**\r
+ * @brief Clears the DMA2D pending flags.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA2D_FLAG_CE: Configuration error flag\r
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag\r
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag\r
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag\r
+ * @arg DMA2D_FLAG_TC: Transfer complete flag\r
+ * @arg DMA2D_FLAG_TE: Transfer error flag \r
+ * @retval None\r
+ */\r
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA2D interrupts.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask\r
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask\r
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask\r
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask\r
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified DMA2D interrupts.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask\r
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask\r
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask\r
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask\r
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified DMA2D interrupt has occurred or not.\r
+ * @param __HANDLE__: DMA2D handle\r
+ * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask\r
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask\r
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask\r
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask\r
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask\r
+ * @retval The state of INTERRUPT.\r
+ */\r
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/ \r
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *******************************/\r
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); \r
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);\r
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);\r
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);\r
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);\r
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);\r
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);\r
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);\r
+\r
+/* Peripheral Control functions *************************************************/\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);\r
+\r
+/* Peripheral State functions ***************************************************/\r
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);\r
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Types DMA2D Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private defines -------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Defines DMA2D Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Variables DMA2D Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros\r
+ * @{\r
+ */\r
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)\r
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \\r
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))\r
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \\r
+ ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \\r
+ ((MODE_ARGB) == DMA2D_ARGB4444))\r
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)\r
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)\r
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)\r
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)\r
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \\r
+ ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \\r
+ ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \\r
+ ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \\r
+ ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \\r
+ ((INPUT_CM) == CM_A4))\r
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \\r
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \\r
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))\r
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))\r
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)\r
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)\r
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \\r
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \\r
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))\r
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \\r
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \\r
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ---------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA2D_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DMA HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_EX_H\r
+#define __STM32F7xx_HAL_DMA_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMAEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
+ * @brief DMAEx Exported types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL DMA Memory definition \r
+ */ \r
+typedef enum\r
+{\r
+ MEMORY0 = 0x00, /*!< Memory 0 */\r
+ MEMORY1 = 0x01, /*!< Memory 1 */\r
+\r
+}HAL_DMA_MemoryTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
+ * @brief DMAEx Exported functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r
+ * @brief DMAEx Private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_eth.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of ETH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_ETH_H\r
+#define __STM32F7xx_HAL_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup ETH_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
+ ((SPEED) == ETH_SPEED_100M))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE)) \r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
+ ((CMD) == ETH_WATCHDOG_DISABLE))\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
+ ((CMD) == ETH_JABBER_DISABLE))\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEAll_DISABLE))\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
+ ((CMD) == ETH_FIXEDBURST_DISABLE))\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMATXDESC_IC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LS) || \\r
+ ((FLAG) == ETH_DMATXDESC_FS) || \\r
+ ((FLAG) == ETH_DMATXDESC_DC) || \\r
+ ((FLAG) == ETH_DMATXDESC_DP) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
+ ((FLAG) == ETH_DMATXDESC_TER) || \\r
+ ((FLAG) == ETH_DMATXDESC_TCH) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
+ ((FLAG) == ETH_DMATXDESC_IHE) || \\r
+ ((FLAG) == ETH_DMATXDESC_ES) || \\r
+ ((FLAG) == ETH_DMATXDESC_JT) || \\r
+ ((FLAG) == ETH_DMATXDESC_FF) || \\r
+ ((FLAG) == ETH_DMATXDESC_PCE) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCA) || \\r
+ ((FLAG) == ETH_DMATXDESC_NC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCO) || \\r
+ ((FLAG) == ETH_DMATXDESC_EC) || \\r
+ ((FLAG) == ETH_DMATXDESC_VF) || \\r
+ ((FLAG) == ETH_DMATXDESC_CC) || \\r
+ ((FLAG) == ETH_DMATXDESC_ED) || \\r
+ ((FLAG) == ETH_DMATXDESC_UF) || \\r
+ ((FLAG) == ETH_DMATXDESC_DB))\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMARXDESC_AFM) || \\r
+ ((FLAG) == ETH_DMARXDESC_ES) || \\r
+ ((FLAG) == ETH_DMARXDESC_DE) || \\r
+ ((FLAG) == ETH_DMARXDESC_SAF) || \\r
+ ((FLAG) == ETH_DMARXDESC_LE) || \\r
+ ((FLAG) == ETH_DMARXDESC_OE) || \\r
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
+ ((FLAG) == ETH_DMARXDESC_FS) || \\r
+ ((FLAG) == ETH_DMARXDESC_LS) || \\r
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARXDESC_LC) || \\r
+ ((FLAG) == ETH_DMARXDESC_FT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RWT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RE) || \\r
+ ((FLAG) == ETH_DMARXDESC_DBE) || \\r
+ ((FLAG) == ETH_DMARXDESC_CE) || \\r
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) \r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Defines\r
+ * @{\r
+ */\r
+/* Delay to wait when writing to some Ethernet registers */\r
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)\r
+\r
+/* ETHERNET Errors */\r
+#define ETH_SUCCESS ((uint32_t)0)\r
+#define ETH_ERROR ((uint32_t)1)\r
+\r
+/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)\r
+\r
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Frame length Shift */\r
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */\r
+\r
+/* ETHERNET MACMIIAR register Mask */\r
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)\r
+\r
+/* ETHERNET MACCR register Mask */\r
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) \r
+\r
+/* ETHERNET MACFCR register Mask */\r
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)\r
+\r
+/* ETHERNET DMAOMR register Mask */\r
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)\r
+\r
+/* ETHERNET Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8\r
+\r
+/* ETHERNET Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup ETH_Exported_Types ETH Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */\r
+ HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */\r
+ HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */\r
+}HAL_ETH_StateTypeDef;\r
+\r
+/** \r
+ * @brief ETH Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */\r
+ \r
+ uint16_t PhyAddress; /*!< Ethernet PHY address.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+ \r
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
+ \r
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
+ This parameter can be a value of @ref ETH_Rx_Mode */\r
+ \r
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. \r
+ This parameter can be a value of @ref ETH_Checksum_Mode */\r
+ \r
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. \r
+ This parameter can be a value of @ref ETH_Media_Interface */\r
+\r
+} ETH_InitTypeDef;\r
+\r
+\r
+ /** \r
+ * @brief ETH MAC Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Watchdog */ \r
+\r
+ uint32_t Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */ \r
+\r
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode.\r
+ This parameter can be a value of @ref ETH_Receive_Own */ \r
+\r
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */ \r
+\r
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */ \r
+\r
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a collision occurs (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r
+\r
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Deferral_Check */ \r
+\r
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
+ This parameter can be a value of @ref ETH_Receive_All */ \r
+\r
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. \r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */ \r
+\r
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) \r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r
+\r
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r
+\r
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r
+\r
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r
+\r
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ \r
+\r
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. \r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ \r
+\r
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame.\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+ \r
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address).\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ \r
+\r
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */ \r
+\r
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering.\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r
+\r
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+} ETH_MACInitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief ETH DMA Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r
+\r
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r
+\r
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r
+\r
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r
+\r
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+ \r
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r
+\r
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
+ \r
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
+\r
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ \r
+\r
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */ \r
+} ETH_DMAInitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief ETH DMA Descriptors data structure definition\r
+ */ \r
+\r
+typedef struct \r
+{\r
+ __IO uint32_t Status; /*!< Status */\r
+ \r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+ \r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+ \r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+ \r
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */\r
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
+ \r
+ uint32_t Reserved1; /*!< Reserved */\r
+ \r
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
+ \r
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
+\r
+} ETH_DMADescTypeDef;\r
+\r
+\r
+/** \r
+ * @brief Received Frame Informations structure definition\r
+ */ \r
+typedef struct \r
+{\r
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
+ \r
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
+ \r
+ uint32_t SegCount; /*!< Segment count */\r
+ \r
+ uint32_t length; /*!< Frame length */\r
+ \r
+ uint32_t buffer; /*!< Frame buffer */\r
+\r
+} ETH_DMARxFrameInfos;\r
+\r
+\r
+/** \r
+ * @brief ETH Handle Structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ ETH_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
+ \r
+ uint32_t LinkStatus; /*!< Ethernet link status */\r
+ \r
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
+ \r
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
+ \r
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
+ \r
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< ETH Lock */\r
+\r
+} ETH_HandleTypeDef;\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
+ * @{\r
+ */ \r
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */\r
+#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */ \r
+#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */\r
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */\r
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */\r
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */ \r
+\r
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
+ to the driver receive buffers memory.\r
+\r
+ Depending on the size of the received ethernet packet and the size of \r
+ each ethernet driver receive buffer, the received packet can take one or more\r
+ ethernet driver receive buffer. \r
+\r
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE \r
+ and the total count of the driver receive buffers ETH_RXBUFNB.\r
+\r
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as \r
+ example, they can be reconfigured in the application layer to fit the application \r
+ needs */ \r
+\r
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_RX_BUF_SIZE\r
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE \r
+#endif\r
+\r
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ \r
+#ifndef ETH_RXBUFNB\r
+ #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#endif\r
+\r
+\r
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the \r
+ driver transmit buffers memory to the TxFIFO.\r
+\r
+ Depending on the size of the Ethernet packet to be transmitted and the size of \r
+ each ethernet driver transmit buffer, the packet to be transmitted can take \r
+ one or more ethernet driver transmit buffer. \r
+\r
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE \r
+ and the total count of the driver transmit buffers ETH_TXBUFNB.\r
+\r
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as \r
+ example, they can be reconfigured in the application layer to fit the application \r
+ needs */ \r
+\r
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_TX_BUF_SIZE \r
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ \r
+#ifndef ETH_TXBUFNB\r
+ #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
+#endif\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Tx Descriptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */ \r
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */\r
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */\r
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */\r
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */\r
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ \r
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ \r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */\r
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */\r
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */\r
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */\r
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */\r
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */\r
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */\r
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */\r
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */\r
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */\r
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */\r
+\r
+/** \r
+ * @brief Bit definition of TDES1 register\r
+ */ \r
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of TDES2 register\r
+ */ \r
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of TDES3 register\r
+ */ \r
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+ /*---------------------------------------------------------------------------------------------\r
+ TDES6 | Transmit Time Stamp Low [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES7 | Transmit Time Stamp High [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES6 register */\r
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */\r
+\r
+/* Bit definition of TDES7 register */\r
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Rx Descriptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */ \r
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */\r
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */\r
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */\r
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */\r
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ \r
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ \r
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */\r
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */\r
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/** \r
+ * @brief Bit definition of RDES1 register\r
+ */ \r
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */\r
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */\r
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of RDES2 register \r
+ */ \r
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of RDES3 register \r
+ */ \r
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES5 | Reserved[31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES6 | Receive Time Stamp Low [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES7 | Receive Time Stamp High [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES4 register */\r
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */\r
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ \r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ \r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ \r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ \r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ \r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ \r
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */\r
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */\r
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */\r
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */\r
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ \r
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */\r
+\r
+/* Bit definition of RDES6 register */\r
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */\r
+\r
+/* Bit definition of RDES7 register */\r
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */\r
+/**\r
+ * @}\r
+ */\r
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation \r
+ * @{\r
+ */ \r
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)\r
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Speed ETH Speed \r
+ * @{\r
+ */ \r
+#define ETH_SPEED_10M ((uint32_t)0x00000000)\r
+#define ETH_SPEED_100M ((uint32_t)0x00004000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r
+ * @{\r
+ */ \r
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)\r
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Rx_Mode ETH Rx Mode\r
+ * @{\r
+ */ \r
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)\r
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r
+ * @{\r
+ */ \r
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)\r
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Media_Interface ETH Media Interface\r
+ * @{\r
+ */ \r
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)\r
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Watchdog ETH Watchdog \r
+ * @{\r
+ */ \r
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber ETH Jabber\r
+ * @{\r
+ */ \r
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap \r
+ * @{\r
+ */ \r
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r
+ * @{\r
+ */ \r
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own ETH Receive Own \r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode \r
+ * @{\r
+ */ \r
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)\r
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r
+ * @{\r
+ */ \r
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)\r
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r
+ * @{\r
+ */ \r
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r
+ * @{\r
+ */ \r
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r
+ * @{\r
+ */ \r
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)\r
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)\r
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)\r
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check ETH Deferral Check\r
+ * @{\r
+ */\r
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)\r
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All ETH Receive All\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)\r
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r
+ * @{\r
+ */ \r
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)\r
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)\r
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r
+ * @{\r
+ */ \r
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r
+ * @{\r
+ */ \r
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r
+ * @{\r
+ */ \r
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)\r
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r
+ * @{\r
+ */ \r
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)\r
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r
+ * @{\r
+ */ \r
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)\r
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)\r
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r
+ * @{\r
+ */ \r
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)\r
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)\r
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause \r
+ * @{\r
+ */ \r
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r
+ * @{\r
+ */ \r
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r
+ * @{\r
+ */ \r
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)\r
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)\r
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r
+ * @{\r
+ */ \r
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)\r
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses ETH MAC addresses\r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)\r
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)\r
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)\r
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA \r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)\r
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags\r
+ * @{\r
+ */ \r
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r
+ * @{\r
+ */ \r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)\r
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r
+ * @{\r
+ */ \r
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)\r
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r
+ * @{\r
+ */ \r
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r
+ * @{\r
+ */ \r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r
+ * @{\r
+ */ \r
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)\r
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats \r
+ * @{\r
+ */ \r
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)\r
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r
+ * @{\r
+ */ \r
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)\r
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r
+ * @{\r
+ */ \r
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r
+ * @{\r
+ */ \r
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r
+ * @{\r
+ */ \r
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r
+ * @{\r
+ */ \r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)\r
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r
+ * @{\r
+ */ \r
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r
+ * @{\r
+ */ \r
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */\r
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers \r
+ * @{\r
+ */ \r
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags ETH PMT Flags\r
+ * @{\r
+ */ \r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r
+ * @{\r
+ */ \r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags ETH MAC Flags\r
+ * @{\r
+ */ \r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags ETH DMA Flags\r
+ * @{\r
+ */ \r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */\r
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state \r
+ * @{\r
+ */ \r
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */\r
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */\r
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state \r
+ * @{\r
+ */ \r
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */\r
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow ETH DMA overflow\r
+ * @{\r
+ */ \r
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r
+ * @{\r
+ */ \r
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Macros ETH Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset ETH handle state\r
+ * @param __HANDLE__: specifies the ETH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r
+\r
+/** \r
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of TDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of RDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r
+\r
+/**\r
+ * @brief Disables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r
+\r
+/**\r
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r
+\r
+/** \r
+ * @brief Enables the specified ETHERNET MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag \r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag \r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag \r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag \r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag \r
+ * @retval The state of ETHERNET MAC flag.\r
+ */\r
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/** \r
+ * @brief Enables the specified ETHERNET DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be\r
+ * enabled @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be\r
+ * disabled. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the ETHERNET DMA IT pending bit.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+* @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r
+\r
+/**\r
+ * @brief Set the DMA Receive status watchdog timer register value\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __VALUE__: DMA Receive status watchdog timer register value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r
+\r
+/** \r
+ * @brief Enables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Enables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Disables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r
+\r
+/**\r
+ * @brief Disables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Disables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset \r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received \r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/** \r
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\r
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Enables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Disables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r
+\r
+/**\r
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enable event on ETH External event line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disable event on ETH External event line\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Get flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Clear flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r
+ \r
+/**\r
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) \r
+\r
+/**\r
+ * @brief Enables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */ \r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\r
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\r
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup ETH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* IO operation functions ****************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r
+/* Communication with PHY functions*/\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r
+/* Callback in non blocking modes (Interrupt) */\r
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Peripheral State functions ************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_ETH_H */\r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of FLASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_H\r
+#define __STM32F7xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief FLASH Procedure structure definition\r
+ */\r
+typedef enum \r
+{\r
+ FLASH_PROC_NONE = 0, \r
+ FLASH_PROC_SECTERASE,\r
+ FLASH_PROC_MASSERASE,\r
+ FLASH_PROC_PROGRAM\r
+} FLASH_ProcedureTypeDef;\r
+\r
+\r
+/** \r
+ * @brief FLASH handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */\r
+ \r
+ __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */\r
+ \r
+ __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */\r
+ \r
+ __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */\r
+ \r
+ __IO uint32_t Address; /* Internal variable to save address selected for program */\r
+ \r
+ HAL_LockTypeDef Lock; /* FLASH locking object */\r
+\r
+ __IO uint32_t ErrorCode; /* FLASH error code */\r
+\r
+}FLASH_ProcessTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Error_Code FLASH Error Code\r
+ * @brief FLASH Error Code \r
+ * @{\r
+ */ \r
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002) /*!< Programming Sequence error */\r
+#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004) /*!< Programming Parallelism error */\r
+#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) /*!< Programming Alignment error */\r
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010) /*!< Write protection error */\r
+#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020) /*!< Operation Error */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Type_Program FLASH Type Program\r
+ * @{\r
+ */ \r
+#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flag_definition FLASH Flag definition\r
+ * @brief Flag definition\r
+ * @{\r
+ */ \r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */\r
+#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r
+ * @brief FLASH Interrupt definition\r
+ * @{\r
+ */\r
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r
+ * @{\r
+ */\r
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)\r
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)\r
+#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)\r
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)\r
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys FLASH Keys\r
+ * @{\r
+ */ \r
+#define FLASH_KEY1 ((uint32_t)0x45670123)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)\r
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Set the FLASH Latency.\r
+ * @param __LATENCY__: FLASH Latency \r
+ * The value of this parameter depend on device used within the same series\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\r
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r
+\r
+ \r
+/**\r
+ * @brief Enable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\r
+\r
+/**\r
+ * @brief Enable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note The ART accelerator is available only for flash access on ITCM interface.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Resets the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note This function must be used only when the Adaptive Real-Time memory accelerator\r
+ * is disabled. \r
+ * @retval None\r
+ */\r
+#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)\r
+\r
+/**\r
+ * @brief Enable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ : FLASH interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt \r
+ * @retval none\r
+ */ \r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Get the specified FLASH flag status. \r
+ * @param __FLAG__: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag \r
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the specified FLASH flag.\r
+ * @param __FLAG__: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag \r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include FLASH HAL Extension module */\r
+#include "stm32f7xx_hal_flash_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Program operation functions ***********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+/* FLASH IRQ handler method */\r
+void HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */ \r
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
+/* Option bytes control */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+uint32_t HAL_FLASH_GetError(void);\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of FLASH HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_EX_H\r
+#define __STM32F7xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.\r
+ This parameter can be a value of @ref FLASHEx_Type_Erase */\r
+\r
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled\r
+ This parameter must be a value of @ref FLASHEx_Sectors */\r
+\r
+ uint32_t NbSectors; /*!< Number of sectors to be erased.\r
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r
+\r
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */\r
+\r
+} FLASH_EraseInitTypeDef;\r
+\r
+/**\r
+ * @brief FLASH Option Bytes Program structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< Option byte to be configured.\r
+ This parameter can be a value of @ref FLASHEx_Option_Type */\r
+\r
+ uint32_t WRPState; /*!< Write protection activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_WRP_State */\r
+\r
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.\r
+ The value of this parameter depend on device used within the same series */\r
+\r
+ uint32_t RDPLevel; /*!< Set the read protection level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r
+\r
+ uint32_t BORLevel; /*!< Set the BOR Level.\r
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r
+\r
+ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / \r
+ IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */\r
+ \r
+ uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+ uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r
+ * @{\r
+ */ \r
+#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */\r
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r
+ * @{\r
+ */ \r
+#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */\r
+#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */\r
+#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */\r
+#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_WRP_State FLASH WRP State\r
+ * @{\r
+ */ \r
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */\r
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Option_Type FLASH Option Type\r
+ * @{\r
+ */ \r
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */\r
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */\r
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */\r
+#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */\r
+#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10) /*!< Boot 0 Address configuration */\r
+#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20) /*!< Boot 1 Address configuration */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r
+ * @{\r
+ */\r
+#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00)\r
+#define OB_RDP_LEVEL_1 ((uint32_t)0x5500)\r
+/*#define OB_RDP_LEVEL_2 ((uint32_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 \r
+ it s no more possible to go back to level 1 or 0 */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r
+ * @{\r
+ */ \r
+#define OB_WWDG_SW ((uint32_t)0x10) /*!< Software WWDG selected */\r
+#define OB_WWDG_HW ((uint32_t)0x00) /*!< Hardware WWDG selected */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r
+ * @{\r
+ */ \r
+#define OB_IWDG_SW ((uint32_t)0x20) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint32_t)0x00) /*!< Hardware IWDG selected */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r
+ * @{\r
+ */ \r
+#define OB_STOP_NO_RST ((uint32_t)0x40) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint32_t)0x00) /*!< Reset generated when entering in STOP */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r
+ * @{\r
+ */ \r
+#define OB_STDBY_NO_RST ((uint32_t)0x80) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint32_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r
+ * @{\r
+ */\r
+#define OB_IWDG_STOP_FREEZE ((uint32_t)0x40000000) /*!< Freeze IWDG counter in STOP mode */\r
+#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STOP mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r
+ * @{\r
+ */\r
+#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x80000000) /*!< Freeze IWDG counter in STANDBY mode */\r
+#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STANDBY mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r
+ * @{\r
+ */\r
+#define OB_BOR_LEVEL3 ((uint32_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */\r
+#define OB_BOR_LEVEL2 ((uint32_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */\r
+#define OB_BOR_LEVEL1 ((uint32_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */\r
+#define OB_BOR_OFF ((uint32_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r
+ * @{\r
+ */\r
+#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000) /*!< Boot from ITCM RAM (0x00000000) */\r
+#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040) /*!< Boot from System memory bootloader (0x00100000) */\r
+#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080) /*!< Boot from Flash on ITCM interface (0x00200000) */\r
+#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000) /*!< Boot from Flash on AXIM interface (0x08000000) */\r
+#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */\r
+#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */\r
+#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Latency FLASH Latency\r
+ * @{\r
+ */\r
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */\r
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */\r
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */\r
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */\r
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */\r
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */\r
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */\r
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */\r
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */\r
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */\r
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */\r
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */\r
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */\r
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */\r
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */\r
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\r
+ * @{\r
+ */\r
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< MER bit to clear */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */\r
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */\r
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */\r
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */\r
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */\r
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */\r
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000) /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000) /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000) /*!< Write protection of Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000) /*!< Write protection of Sector3 */\r
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000) /*!< Write protection of Sector4 */\r
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000) /*!< Write protection of Sector5 */\r
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000) /*!< Write protection of Sector6 */\r
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Extension Program operation functions *************************************/\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+#define FLASH_SECTOR_TOTAL 8\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\r
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE)) \r
+\r
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4)) \r
+\r
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\r
+ ((VALUE) == OB_WRPSTATE_ENABLE)) \r
+\r
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))\r
+\r
+#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM) || \\r
+ ((ADDRESS) == OB_BOOTADDR_SYSTEM) || \\r
+ ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \\r
+ ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \\r
+ ((ADDRESS) == OB_BOOTADDR_DTCM_RAM) || \\r
+ ((ADDRESS) == OB_BOOTADDR_SRAM1) || \\r
+ ((ADDRESS) == OB_BOOTADDR_SRAM2))\r
+\r
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\\r
+ ((LEVEL) == OB_RDP_LEVEL_2))*/\r
+\r
+#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r
+\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r
+\r
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\r
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \\r
+ ((LATENCY) == FLASH_LATENCY_1) || \\r
+ ((LATENCY) == FLASH_LATENCY_2) || \\r
+ ((LATENCY) == FLASH_LATENCY_3) || \\r
+ ((LATENCY) == FLASH_LATENCY_4) || \\r
+ ((LATENCY) == FLASH_LATENCY_5) || \\r
+ ((LATENCY) == FLASH_LATENCY_6) || \\r
+ ((LATENCY) == FLASH_LATENCY_7) || \\r
+ ((LATENCY) == FLASH_LATENCY_8) || \\r
+ ((LATENCY) == FLASH_LATENCY_9) || \\r
+ ((LATENCY) == FLASH_LATENCY_10) || \\r
+ ((LATENCY) == FLASH_LATENCY_11) || \\r
+ ((LATENCY) == FLASH_LATENCY_12) || \\r
+ ((LATENCY) == FLASH_LATENCY_13) || \\r
+ ((LATENCY) == FLASH_LATENCY_14) || \\r
+ ((LATENCY) == FLASH_LATENCY_15))\r
+\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))\r
+\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))\r
+\r
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of GPIO HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_H\r
+#define __STM32F7xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIO_mode_define */\r
+\r
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+ This parameter can be a value of @ref GPIO_pull_define */\r
+\r
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIO_speed_define */\r
+\r
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. \r
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */\r
+}GPIO_InitTypeDef;\r
+\r
+/** \r
+ * @brief GPIO Bit SET and Bit RESET enumeration \r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PIN_RESET = 0,\r
+ GPIO_PIN_SET\r
+}GPIO_PinState;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_pins_define GPIO pins define\r
+ * @{\r
+ */\r
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */\r
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */\r
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */\r
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */\r
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */\r
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */\r
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */\r
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */\r
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */\r
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */\r
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */\r
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */\r
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */\r
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */\r
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */\r
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */\r
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_mode_define GPIO mode define\r
+ * @brief GPIO Configuration Mode \r
+ * Elements values convention: 0xX0yz00YZ\r
+ * - X : GPIO mode or EXTI Mode\r
+ * - y : External IT or Event trigger detection \r
+ * - z : IO configuration on External IT or Event\r
+ * - Y : Output type (Push Pull or Open Drain)\r
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
+ * @{\r
+ */ \r
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */\r
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */\r
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */\r
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */\r
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */\r
+\r
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */\r
+ \r
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+ \r
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_speed_define GPIO speed define\r
+ * @brief GPIO Output Maximum frequency\r
+ * @{\r
+ */ \r
+#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */\r
+#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */\r
+#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */\r
+#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup GPIO_pull_define GPIO pull define\r
+ * @brief GPIO Pull-Up or Pull-Down Activation\r
+ * @{\r
+ */ \r
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */\r
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */\r
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param __EXTI_LINE__: specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include GPIO HAL Extension module */\r
+#include "stm32f7xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
+ ((MODE) == GPIO_MODE_AF_PP) ||\\r
+ ((MODE) == GPIO_MODE_AF_OD) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_ANALOG))\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \\r
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))\r
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
+ ((PULL) == GPIO_PULLDOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of GPIO HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_EX_H\r
+#define __STM32F7xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO \r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */\r
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */\r
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */\r
+\r
+\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */\r
+#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */\r
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */\r
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */\r
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */\r
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */\r
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */\r
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */\r
+\r
+\r
+/** \r
+ * @brief AF 9 selection \r
+ */ \r
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */\r
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */\r
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */\r
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */\r
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */\r
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC ((uint8_t)0xC) /* SDMMC Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 13 selection \r
+ */ \r
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 14 selection \r
+ */\r
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/ \r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @brief GPIO pin available on the platform\r
+ */\r
+/* Defines the available pins per GPIOs */\r
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOB_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOC_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOD_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOE_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOF_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOG_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOI_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOH_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \\r
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Macros\r
+ * @{\r
+ */\r
+/** @defgroup GPIO_Get_Port_Index GPIO Get Port Index\r
+ * @{\r
+ */\r
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U :\\r
+ ((__GPIOx__) == (GPIOF))? 5U :\\r
+ ((__GPIOx__) == (GPIOG))? 6U :\\r
+ ((__GPIOx__) == (GPIOH))? 7U :\\r
+ ((__GPIOx__) == (GPIOI))? 8U :\\r
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \\r
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r
+/** @defgroup GPIO_IS_Alternate_function_selection GPIO Check Alternate Function\r
+ * @{\r
+ */ \r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of HASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_HASH_H\r
+#define __STM32F7xx_HAL_HASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx)\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASH \r
+ * @brief HASH HAL module driver \r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup HASH_Exported_Types HASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r
+ This parameter can be a value of @ref HASH DataType */\r
+\r
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation */\r
+\r
+ uint8_t* pKey; /*!< The key is used only in HMAC operation */\r
+}HASH_InitTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition\r
+ * @{\r
+ */\r
+\r
+typedef enum\r
+{\r
+ HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */\r
+ HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */\r
+ HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */\r
+ HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */\r
+ HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */\r
+}HAL_HASH_STATETypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition\r
+ * @{\r
+ */\r
+ \r
+typedef enum\r
+{\r
+ HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */\r
+ HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */\r
+}HAL_HASHPhaseTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition\r
+ * @{\r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ HASH_InitTypeDef Init; /*!< HASH required parameters */\r
+\r
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */\r
+\r
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */\r
+\r
+ __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */\r
+\r
+ __IO uint32_t HashInCount; /*!< Counter of inputed data */\r
+\r
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */\r
+\r
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */\r
+\r
+ HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */\r
+\r
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< HASH locking object */\r
+\r
+ __IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */\r
+} HASH_HandleTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup HASH_Exported_Constants HASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection\r
+ * @{\r
+ */\r
+#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */\r
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */\r
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */\r
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode\r
+ * @{\r
+ */\r
+#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ \r
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group3 HASH DataType\r
+ * @{\r
+ */\r
+#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */\r
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */\r
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */\r
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key \r
+ * @brief HASH HMAC Long key used only for HMAC mode\r
+ * @{\r
+ */\r
+#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */\r
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition \r
+ * @{\r
+ */\r
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */\r
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */\r
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */\r
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */\r
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition \r
+ * @{\r
+ */\r
+#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */\r
+#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup HASH_Exported_Macros HASH Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset HASH handle state\r
+ * @param __HANDLE__: specifies the HASH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)\r
+\r
+/** @brief Check whether the specified HASH flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. \r
+ * @arg HASH_FLAG_DCIS: Digest calculation complete\r
+ * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing\r
+ * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data\r
+ * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Macros for HMAC finish.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
+\r
+/**\r
+ * @brief Enable the multiple DMA mode. \r
+ * This feature is available only in STM32F429x and STM32F439x devices.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT\r
+\r
+/**\r
+ * @brief Disable the multiple DMA mode.\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)\r
+\r
+/**\r
+ * @brief Start the digest computation\r
+ * @retval None\r
+ */\r
+#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL\r
+\r
+/**\r
+ * @brief Set the number of valid bits in last word written in Data register\r
+ * @param SIZE: size in byte of last data written in Data register.\r
+ * @retval None\r
+*/\r
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\\r
+ HASH->STR |= 8 * ((SIZE) % 4);\\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Include HASH HAL Extension module */\r
+#include "stm32f7xx_hal_hash_ex.h"\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HASH_Exported_Functions HASH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASH_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);\r
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @addtogroup HASH_Exported_Functions_Group3\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group4\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group5\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group6\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group7\r
+ * @{\r
+ */ \r
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group8\r
+ * @{\r
+ */\r
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);\r
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+ \r
+ /* Private types -------------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Types HASH Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Variables HASH Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Constants HASH Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Macros HASH Private Macros\r
+ * @{\r
+ */\r
+#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \\r
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \\r
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \\r
+ ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))\r
+\r
+\r
+#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \\r
+ ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))\r
+\r
+\r
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \\r
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \\r
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \\r
+ ((__DATATYPE__) == HASH_DATATYPE_1B))\r
+\r
+\r
+#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \\r
+ ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup HASH_Private_Functions HASH Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* STM32F756xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_HASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of HASH HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_HASH_EX_H\r
+#define __STM32F7xx_HAL_HASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx)\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HASHEx \r
+ * @brief HASHEx HAL Extension module driver \r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions\r
+ * @{\r
+ */ \r
+\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions\r
+ * @{\r
+ */ \r
+ \r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions\r
+ * @{\r
+ */ \r
+ \r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA\r
+ * @{\r
+ */\r
+ \r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA\r
+ * @{\r
+ */\r
+ \r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions\r
+ * @{\r
+ */\r
+ \r
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /* Private types -------------------------------------------------------------*/\r
+/** @defgroup HASHEx_Private_Types HASHEx Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup HASHEx_Private_Variables HASHEx Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup HASHEx_Private_Constants HASHEx Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup HASHEx_Private_Macros HASHEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup HASHEx_Private_Functions HASHEx Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* STM32F756xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_HASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hcd.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of HCD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_HCD_H\r
+#define __STM32F7xx_HAL_HCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_usb.h"\r
+ \r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HCD HCD\r
+ * @brief HCD HAL module driver\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup HCD_Exported_Types HCD Exported Types\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition \r
+ * @{\r
+ */\r
+typedef enum \r
+{\r
+ HAL_HCD_STATE_RESET = 0x00,\r
+ HAL_HCD_STATE_READY = 0x01,\r
+ HAL_HCD_STATE_ERROR = 0x02,\r
+ HAL_HCD_STATE_BUSY = 0x03,\r
+ HAL_HCD_STATE_TIMEOUT = 0x04\r
+} HCD_StateTypeDef;\r
+\r
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;\r
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;\r
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef ; \r
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;\r
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition \r
+ * @{\r
+ */ \r
+typedef struct\r
+{\r
+ HCD_TypeDef *Instance; /*!< Register base address */ \r
+ HCD_InitTypeDef Init; /*!< HCD required parameters */\r
+ HCD_HCTypeDef hc[15]; /*!< Host channels parameters */\r
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */\r
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */\r
+ void *pData; /*!< Pointer Stack Handler */\r
+} HCD_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup HCD_Exported_Constants HCD Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup HCD_Speed HCD Speed\r
+ * @{\r
+ */\r
+#define HCD_SPEED_HIGH 0\r
+#define HCD_SPEED_LOW 2 \r
+#define HCD_SPEED_FULL 3\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HCD_PHY_Module HCD PHY Module\r
+ * @{\r
+ */\r
+#define HCD_PHY_ULPI 1\r
+#define HCD_PHY_EMBEDDED 2\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup HCD_Exported_Macros HCD Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
+\r
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))\r
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) \r
+\r
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) \r
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) \r
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) \r
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) \r
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup HCD_Exported_Functions HCD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);\r
+HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);\r
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps);\r
+\r
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);\r
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);\r
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r
+ uint8_t pipe, \r
+ uint8_t direction ,\r
+ uint8_t ep_type, \r
+ uint8_t token, \r
+ uint8_t* pbuff, \r
+ uint16_t length,\r
+ uint8_t do_ping);\r
+\r
+ /* Non-Blocking mode: Interrupt */\r
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);\r
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);\r
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);\r
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);\r
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, \r
+ uint8_t chnum, \r
+ HCD_URBStateTypeDef urb_state);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);\r
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);\r
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);\r
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);\r
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup HCD_Private_Macros HCD Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup HCD_Instance_definition HCD Instance definition\r
+ * @{\r
+ */\r
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup HCD_Private_Functions HCD Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_HCD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of I2C HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_I2C_H\r
+#define __STM32F7xx_HAL_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup I2C_Exported_Types I2C Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
+ * @brief I2C Configuration Structure definition \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.\r
+ This parameter calculated by referring to I2C initialization \r
+ section in Reference manual */\r
+\r
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_addressing_mode */\r
+\r
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_dual_addressing_mode */\r
+\r
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected\r
+ This parameter can be a 7-bit address. */\r
+\r
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected\r
+ This parameter can be a value of @ref I2C_own_address2_masks */\r
+\r
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.\r
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */\r
+\r
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.\r
+ This parameter can be a value of @ref I2C_nostretch_mode */\r
+\r
+}I2C_InitTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_state_structure_definition HAL state structure definition\r
+ * @brief HAL State structure definition \r
+ * @{\r
+ */ \r
+\r
+typedef enum\r
+{\r
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */\r
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */\r
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */\r
+ HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */\r
+ HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */\r
+ HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */\r
+ HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */\r
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */\r
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */\r
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */\r
+}HAL_I2C_StateTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
+ * @brief I2C Error Code definition \r
+ * @{\r
+ */ \r
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */\r
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */\r
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */\r
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */\r
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */\r
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */\r
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition \r
+ * @brief I2C handle Structure definition \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ I2C_TypeDef *Instance; /*!< I2C registers base address */\r
+\r
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */\r
+\r
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */\r
+\r
+ uint16_t XferSize; /*!< I2C transfer size */\r
+\r
+ __IO uint16_t XferCount; /*!< I2C transfer counter */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< I2C locking object */\r
+\r
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< I2C Error code */\r
+\r
+}I2C_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_addressing_mode I2C addressing mode\r
+ * @{\r
+ */\r
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)\r
+#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)\r
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address2_masks I2C own address2 masks\r
+ * @{\r
+ */\r
+#define I2C_OA2_NOMASK ((uint8_t)0x00)\r
+#define I2C_OA2_MASK01 ((uint8_t)0x01)\r
+#define I2C_OA2_MASK02 ((uint8_t)0x02)\r
+#define I2C_OA2_MASK03 ((uint8_t)0x03)\r
+#define I2C_OA2_MASK04 ((uint8_t)0x04)\r
+#define I2C_OA2_MASK05 ((uint8_t)0x05)\r
+#define I2C_OA2_MASK06 ((uint8_t)0x06)\r
+#define I2C_OA2_MASK07 ((uint8_t)0x07)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode\r
+ * @{\r
+ */\r
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)\r
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_nostretch_mode I2C nostretch mode\r
+ * @{\r
+ */\r
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)\r
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size\r
+ * @{\r
+ */\r
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)\r
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition\r
+ * @{\r
+ */\r
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD\r
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND\r
+#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition\r
+ * @{\r
+ */\r
+#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)\r
+#define I2C_GENERATE_STOP I2C_CR2_STOP\r
+#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define I2C_GENERATE_START_WRITE I2C_CR2_START\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
+ * @brief I2C Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define I2C_IT_ERRI I2C_CR1_ERRIE\r
+#define I2C_IT_TCI I2C_CR1_TCIE\r
+#define I2C_IT_STOPI I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI I2C_CR1_RXIE\r
+#define I2C_IT_TXI I2C_CR1_TXIE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Flag_definition I2C Flag definition\r
+ * @{\r
+ */ \r
+#define I2C_FLAG_TXE I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR I2C_ISR_ADDR\r
+#define I2C_FLAG_AF I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF I2C_ISR_STOPF\r
+#define I2C_FLAG_TC I2C_ISR_TC\r
+#define I2C_FLAG_TCR I2C_ISR_TCR\r
+#define I2C_FLAG_BERR I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY I2C_ISR_BUSY\r
+#define I2C_FLAG_DIR I2C_ISR_DIR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+ \r
+/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset I2C handle state\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
+\r
+/** @brief Enable the specified I2C interrupts.\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @param __INTERRUPT__: specifies the interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_ERRI: Errors interrupt enable\r
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable\r
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable\r
+ * @arg I2C_IT_NACKI: NACK received interrupt enable\r
+ * @arg I2C_IT_ADDRI: Address match interrupt enable\r
+ * @arg I2C_IT_RXI: RX interrupt enable\r
+ * @arg I2C_IT_TXI: TX interrupt enable\r
+ * \r
+ * @retval None\r
+ */\r
+ \r
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified I2C interrupts.\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @param __INTERRUPT__: specifies the interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_ERRI: Errors interrupt enable\r
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable\r
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable\r
+ * @arg I2C_IT_NACKI: NACK received interrupt enable\r
+ * @arg I2C_IT_ADDRI: Address match interrupt enable\r
+ * @arg I2C_IT_RXI: RX interrupt enable\r
+ * @arg I2C_IT_TXI: TX interrupt enable\r
+ * \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
+ \r
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_ERRI: Errors interrupt enable\r
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable\r
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable\r
+ * @arg I2C_IT_NACKI: NACK received interrupt enable\r
+ * @arg I2C_IT_ADDRI: Address match interrupt enable\r
+ * @arg I2C_IT_RXI: RX interrupt enable\r
+ * @arg I2C_IT_TXI: TX interrupt enable\r
+ * \r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Checks whether the specified I2C flag is set or not.\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_TXE: Transmit data register empty\r
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status\r
+ * @arg I2C_FLAG_RXNE: Receive data register not empty\r
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure received flag\r
+ * @arg I2C_FLAG_STOPF: STOP detection flag\r
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)\r
+ * @arg I2C_FLAG_TCR: Transfer complete reload\r
+ * @arg I2C_FLAG_BERR: Bus error\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag \r
+ * @arg I2C_FLAG_ALERT: SMBus alert\r
+ * @arg I2C_FLAG_BUSY: Bus busy\r
+ * @arg I2C_FLAG_DIR: Transfer direction (slave mode)\r
+ *\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF)\r
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))\r
+\r
+/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.\r
+ * @param __HANDLE__: specifies the I2C Handle.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure received flag\r
+ * @arg I2C_FLAG_STOPF: STOP detection flag\r
+ * @arg I2C_FLAG_BERR: Bus error\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun \r
+ * @arg I2C_FLAG_PECERR: PEC error in reception\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag \r
+ * @arg I2C_FLAG_ALERT: SMBus alert\r
+ * \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))\r
+ \r
+/** @brief Enable the specified I2C peripheral.\r
+ * @param __HANDLE__: specifies the I2C Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Disable the specified I2C peripheral.\r
+ * @param __HANDLE__: specifies the I2C Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Include I2C HAL Extension module */\r
+#include "stm32f7xx_hal_i2c_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions******************************/\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions ****************************************************/\r
+ /******* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
+\r
+ /******* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+ /******* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */ \r
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @{\r
+ */\r
+/* Peripheral State and Errors functions *************************************/\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
+\r
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \\r
+ ((MASK) == I2C_OA2_MASK01) || \\r
+ ((MASK) == I2C_OA2_MASK02) || \\r
+ ((MASK) == I2C_OA2_MASK03) || \\r
+ ((MASK) == I2C_OA2_MASK04) || \\r
+ ((MASK) == I2C_OA2_MASK05) || \\r
+ ((MASK) == I2C_OA2_MASK06) || \\r
+ ((MASK) == I2C_OA2_MASK07)) \r
+\r
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
+ ((CALL) == I2C_GENERALCALL_ENABLE))\r
+\r
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
+\r
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
+ \r
+\r
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \\r
+ ((MODE) == I2C_AUTOEND_MODE) || \\r
+ ((MODE) == I2C_SOFTEND_MODE))\r
+\r
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \\r
+ ((REQUEST) == I2C_GENERATE_START_READ) || \\r
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
+ ((REQUEST) == I2C_NO_STARTSTOP))\r
+ \r
+\r
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)\r
+\r
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))\r
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))\r
+\r
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c.c file */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_I2C_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of I2C HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_I2C_EX_H\r
+#define __STM32F7xx_HAL_I2C_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter\r
+ * @{\r
+ */\r
+#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)\r
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Peripheral Control methods ************************************************/\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_I2C_EX_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2s.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of I2S HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_I2S_H\r
+#define __STM32F7xx_HAL_I2S_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2S\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup I2S_Exported_Types I2S Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref I2S_Mode */\r
+\r
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Standard */\r
+\r
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Data_Format */\r
+\r
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref I2S_MCLK_Output */\r
+\r
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Audio_Frequency */\r
+\r
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref I2S_Clock_Polarity */\r
+ \r
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.\r
+ This parameter can be a value of @ref I2S_Clock_Source */\r
+}I2S_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */\r
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */\r
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ \r
+ HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ \r
+ HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */\r
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */ \r
+ HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */ \r
+ \r
+}HAL_I2S_StateTypeDef;\r
+\r
+/** \r
+ * @brief I2S handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ SPI_TypeDef *Instance; /* I2S registers base address */\r
+\r
+ I2S_InitTypeDef Init; /* I2S communication parameters */\r
+ \r
+ uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */\r
+ \r
+ __IO uint16_t TxXferSize; /* I2S Tx transfer size */\r
+ \r
+ __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */\r
+ \r
+ uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */\r
+ \r
+ __IO uint16_t RxXferSize; /* I2S Rx transfer size */\r
+ \r
+ __IO uint16_t RxXferCount; /* I2S Rx transfer counter \r
+ (This field is initialized at the \r
+ same value as transfer size at the \r
+ beginning of the transfer and \r
+ decremented when a sample is received. \r
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */\r
+ \r
+ __IO HAL_LockTypeDef Lock; /* I2S locking object */\r
+ \r
+ __IO HAL_I2S_StateTypeDef State; /* I2S communication state */\r
+\r
+ __IO uint32_t ErrorCode; /* I2S Error code */\r
+\r
+}I2S_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup I2S_Exported_Constants I2S Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2S_Error_Defintion I2S_Error_Defintion\r
+ *@brief I2S Error Code\r
+ * @{\r
+ */\r
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */\r
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */\r
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */\r
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */\r
+#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup I2S_Clock_Source I2S Clock Source\r
+ * @{\r
+ */\r
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)\r
+#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Mode I2S Mode\r
+ * @{\r
+ */\r
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)\r
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)\r
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)\r
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup I2S_Standard I2S Standard\r
+ * @{\r
+ */\r
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)\r
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010)\r
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020)\r
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)\r
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup I2S_Data_Format I2S Data Format\r
+ * @{\r
+ */\r
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)\r
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)\r
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)\r
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_MCLK_Output I2S Mclk Output\r
+ * @{\r
+ */\r
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)\r
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency\r
+ * @{\r
+ */\r
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)\r
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)\r
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)\r
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)\r
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)\r
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)\r
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)\r
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)\r
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)\r
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity\r
+ * @{\r
+ */\r
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)\r
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition\r
+ * @{\r
+ */\r
+#define I2S_IT_TXE SPI_CR2_TXEIE\r
+#define I2S_IT_RXNE SPI_CR2_RXNEIE\r
+#define I2S_IT_ERR SPI_CR2_ERRIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Flags_Definition I2S Flags Definition\r
+ * @{\r
+ */ \r
+#define I2S_FLAG_TXE SPI_SR_TXE\r
+#define I2S_FLAG_RXNE SPI_SR_RXNE\r
+\r
+#define I2S_FLAG_UDR SPI_SR_UDR\r
+#define I2S_FLAG_OVR SPI_SR_OVR\r
+#define I2S_FLAG_FRE SPI_SR_FRE\r
+\r
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE\r
+#define I2S_FLAG_BSY SPI_SR_BSY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup I2S_Exported_Macros I2S Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset I2S handle state\r
+ * @param __HANDLE__: specifies the I2S handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)\r
+\r
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).\r
+ * @param __HANDLE__: specifies the I2S Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)\r
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)\r
+\r
+/** @brief Enable or disable the specified I2S interrupts.\r
+ * @param __HANDLE__: specifies the I2S Handle.\r
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg I2S_IT_ERR: Error interrupt enable\r
+ * @retval None\r
+ */ \r
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))\r
+ \r
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: specifies the I2S Handle.\r
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.\r
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg I2S_IT_ERR: Error interrupt enable\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Checks whether the specified I2S flag is set or not.\r
+ * @param __HANDLE__: specifies the I2S Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag\r
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag\r
+ * @arg I2S_FLAG_UDR: Underrun flag\r
+ * @arg I2S_FLAG_OVR: Overrun flag\r
+ * @arg I2S_FLAG_FRE: Frame error flag\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag\r
+ * @arg I2S_FLAG_BSY: Busy flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the I2S OVR pending flag.\r
+ * @param __HANDLE__: specifies the I2S Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->DR; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+/** @brief Clears the I2S UDR pending flag.\r
+ * @param __HANDLE__: specifies the I2S Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);\r
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions \r
+ * @{\r
+ */\r
+/* I/O operation functions ***************************************************/\r
+ /* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r
+\r
+ /* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);\r
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);\r
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);\r
+\r
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);\r
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @{\r
+ */\r
+/* Peripheral Control and State functions ************************************/\r
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);\r
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2S_Private_Constants I2S Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2S_Private_Macros I2S Private Macros\r
+ * @{\r
+ */\r
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \\r
+ ((CLOCK) == I2S_CLOCK_SYSCLK))\r
+ \r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \\r
+ ((MODE) == I2S_MODE_SLAVE_RX) || \\r
+ ((MODE) == I2S_MODE_MASTER_TX)|| \\r
+ ((MODE) == I2S_MODE_MASTER_RX))\r
+ \r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \\r
+ ((STANDARD) == I2S_STANDARD_MSB) || \\r
+ ((STANDARD) == I2S_STANDARD_LSB) || \\r
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \\r
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))\r
+\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \\r
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \\r
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \\r
+ ((FORMAT) == I2S_DATAFORMAT_32B))\r
+\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \\r
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))\r
+ \r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \\r
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \\r
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))\r
+ \r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \\r
+ ((CPOL) == I2S_CPOL_HIGH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_I2S_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_irda.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of IRDA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_IRDA_H\r
+#define __STM32F7xx_HAL_IRDA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IRDA\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup IRDA_Exported_Types IRDA Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief IRDA Init Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.\r
+ The baud rate register is computed using the following formula:\r
+ Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref IRDAEx_Word_Length */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref IRDA_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref IRDA_Mode */\r
+ \r
+ uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock\r
+ to achieve low-power frequency.\r
+ @note Prescaler value 0 is forbidden */\r
+ \r
+ uint16_t PowerMode; /*!< Specifies the IRDA power mode.\r
+ This parameter can be a value of @ref IRDA_Low_Power */\r
+}IRDA_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */\r
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< An internal process is ongoing */\r
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */\r
+}HAL_IRDA_StateTypeDef;\r
+\r
+/**\r
+ * @brief IRDA clock sources definition\r
+ */\r
+typedef enum\r
+{\r
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */\r
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */\r
+ IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */\r
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */\r
+ IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */\r
+}IRDA_ClockSourceTypeDef;\r
+\r
+/** \r
+ * @brief IRDA handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ USART_TypeDef *Instance; /* IRDA registers base address */\r
+\r
+ IRDA_InitTypeDef Init; /* IRDA communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /* IRDA Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /* IRDA Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /* IRDA Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /* IRDA Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /* IRDA RX RDR register mask */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /* Locking object */\r
+\r
+ __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */\r
+\r
+ __IO uint32_t ErrorCode; /* IRDA Error code */\r
+\r
+}IRDA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** \r
+ * @brief IRDA Configuration enumeration values definition \r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup IRDA_Exported_Constants IRDA Exported constants\r
+ * @{\r
+ */\r
+/** @defgroup IRDA_Error_Code IRDA Error Code\r
+ * @brief IRDA Error Code \r
+ * @{\r
+ */ \r
+\r
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */\r
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */\r
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */\r
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */\r
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Parity IRDA Parity\r
+ * @{\r
+ */ \r
+#define IRDA_PARITY_NONE ((uint32_t)0x0000)\r
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode\r
+ * @{\r
+ */ \r
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Low_Power IRDA Low Power\r
+ * @{\r
+ */\r
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)\r
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /** @defgroup IRDA_State IRDA State\r
+ * @{\r
+ */ \r
+#define IRDA_STATE_DISABLE ((uint32_t)0x0000)\r
+#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup IRDA_Mode IRDA Mode\r
+ * @{\r
+ */ \r
+#define IRDA_MODE_DISABLE ((uint32_t)0x0000)\r
+#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_One_Bit IRDA One Bit\r
+ * @{\r
+ */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx\r
+ * @{\r
+ */\r
+#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)\r
+#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx\r
+ * @{\r
+ */\r
+#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)\r
+#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup IRDA_Flags IRDA Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define IRDA_FLAG_REACK ((uint32_t)0x00400000)\r
+#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) \r
+#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)\r
+#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) \r
+#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)\r
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080)\r
+#define IRDA_FLAG_TC ((uint32_t)0x00000040)\r
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)\r
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008)\r
+#define IRDA_FLAG_NE ((uint32_t)0x00000004)\r
+#define IRDA_FLAG_FE ((uint32_t)0x00000002)\r
+#define IRDA_FLAG_PE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{ \r
+ */ \r
+#define IRDA_IT_PE ((uint16_t)0x0028)\r
+#define IRDA_IT_TXE ((uint16_t)0x0727)\r
+#define IRDA_IT_TC ((uint16_t)0x0626)\r
+#define IRDA_IT_RXNE ((uint16_t)0x0525)\r
+#define IRDA_IT_IDLE ((uint16_t)0x0424)\r
+\r
+\r
+ \r
+/** Elements values convention: 000000000XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ */\r
+#define IRDA_IT_ERR ((uint16_t)0x0060)\r
+\r
+/** Elements values convention: 0000ZZZZ00000000b\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ */\r
+#define IRDA_IT_ORE ((uint16_t)0x0300)\r
+#define IRDA_IT_NE ((uint16_t)0x0200)\r
+#define IRDA_IT_FE ((uint16_t)0x0100)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags\r
+ * @{\r
+ */\r
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ \r
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ \r
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ \r
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ \r
+#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+\r
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters\r
+ * @{\r
+ */\r
+#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ \r
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ \r
+#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset IRDA handle state\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)\r
+\r
+/** @brief Check whether the specified IRDA flag is set or not.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * UART peripheral\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag\r
+ * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag\r
+ * @arg IRDA_FLAG_BUSY: Busy flag\r
+ * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag\r
+ * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag\r
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag\r
+ * @arg IRDA_FLAG_TC: Transmission Complete flag\r
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag\r
+ * @arg IRDA_FLAG_ORE: OverRun Error flag\r
+ * @arg IRDA_FLAG_NE: Noise Error flag\r
+ * @arg IRDA_FLAG_FE: Framing Error flag\r
+ * @arg IRDA_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) \r
+\r
+/** @brief Enable the specified IRDA interrupt.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * UART peripheral\r
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg IRDA_IT_TC: Transmission complete interrupt\r
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt\r
+ * @arg IRDA_IT_PE: Parity Error interrupt\r
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r
+\r
+/** @brief Disable the specified IRDA interrupt.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg IRDA_IT_TC: Transmission complete interrupt\r
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt\r
+ * @arg IRDA_IT_PE: Parity Error interrupt\r
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r
+\r
+/** @brief Check whether the specified IRDA interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT__: specifies the IRDA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg IRDA_IT_TC: Transmission complete interrupt\r
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt\r
+ * @arg IRDA_IT_ORE: OverRun Error interrupt\r
+ * @arg IRDA_IT_NE: Noise Error interrupt\r
+ * @arg IRDA_IT_FE: Framing Error interrupt\r
+ * @arg IRDA_IT_PE: Parity Error interrupt \r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) \r
+\r
+/** @brief Check whether the specified IRDA interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT__: specifies the IRDA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg IRDA_IT_TC: Transmission complete interrupt\r
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt\r
+ * @arg IRDA_IT_ORE: OverRun Error interrupt\r
+ * @arg IRDA_IT_NE: Noise Error interrupt\r
+ * @arg IRDA_IT_FE: Framing Error interrupt\r
+ * @arg IRDA_IT_PE: Parity Error interrupt \r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))\r
+\r
+/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag\r
+ * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag\r
+ * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag\r
+ * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag\r
+ * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag \r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))\r
+\r
+/** @brief Set a specific IRDA request flag.\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __REQ__: specifies the request flag to set\r
+ * This parameter can be one of the following values:\r
+ * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request \r
+ * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r
+ * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r
+\r
+/** @brief Enable UART/USART associated to IRDA Handle\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable UART/USART associated to IRDA Handle\r
+ * @param __HANDLE__: specifies the IRDA Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include IRDA HAL Extension module */\r
+#include "stm32f7xx_hal_irda_ex.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);\r
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);\r
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);\r
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IRDA_Exported_Functions_Group3 Control functions\r
+ * @{\r
+ */\r
+/* Peripheral State methods **************************************************/\r
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);\r
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup IRDA_Private_Constants IRDA Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask\r
+ * @{\r
+ */ \r
+#define IRDA_IT_MASK ((uint16_t)0x001F) \r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup IRDA_Private_Macros IRDA Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value\r
+ * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.\r
+ * @retval True or False\r
+ */ \r
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)\r
+\r
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0\r
+ * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.\r
+ * @retval True or False\r
+ */ \r
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)\r
+\r
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \\r
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \\r
+ ((__PARITY__) == IRDA_PARITY_ODD))\r
+ \r
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))\r
+\r
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \\r
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))\r
+ \r
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \\r
+ ((__STATE__) == IRDA_STATE_ENABLE))\r
+ \r
+#define IS_IRDA_MODE(__STATE__) (((__STATE__) == IRDA_MODE_DISABLE) || \\r
+ ((__STATE__) == IRDA_MODE_ENABLE))\r
+ \r
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \\r
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))\r
+\r
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \\r
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE)) \r
+\r
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \\r
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))\r
+\r
+#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \\r
+ ((PARAM) == IRDA_SENDBREAK_REQUEST) || \\r
+ ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \\r
+ ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \\r
+ ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup IRDA_Private_Functions IRDA Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_IRDA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_irda_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of IRDA HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ * \r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_IRDA_EX_H\r
+#define __STM32F7xx_HAL_IRDA_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IRDAEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup IRDAEx_Word_Length IRDAEx Word Length\r
+ * @{\r
+ */\r
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)\r
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)\r
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros\r
+ * @{\r
+ */\r
+/** @brief Reports the IRDA clock source.\r
+ * @param __HANDLE__: specifies the IRDA Handle\r
+ * @param __CLOCKSOURCE__ : output variable\r
+ * @retval IRDA clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/** @brief Reports the mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * @param __HANDLE__: specifies the IRDA Handle\r
+ * @retval mask to apply to USART RDR register value.\r
+ */ \r
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003F ; \\r
+ } \\r
+ } \\r
+} while(0)\r
+\r
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \\r
+ ((LENGTH) == IRDA_WORDLENGTH_8B) || \\r
+ ((LENGTH) == IRDA_WORDLENGTH_9B))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_IRDA_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of IWDG HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_IWDG_H\r
+#define __STM32F7xx_HAL_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup IWDG_Exported_Types IWDG Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief IWDG HAL State Structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */\r
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */\r
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */\r
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */\r
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */\r
+\r
+}HAL_IWDG_StateTypeDef;\r
+\r
+/** \r
+ * @brief IWDG Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.\r
+ This parameter can be a value of @ref IWDG_Prescaler */\r
+\r
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r
+\r
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r
+\r
+} IWDG_InitTypeDef;\r
+\r
+/** \r
+ * @brief IWDG Handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ IWDG_TypeDef *Instance; /*!< Register base address */\r
+\r
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */\r
+\r
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */\r
+\r
+}IWDG_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Prescaler IWDG Prescaler\r
+ * @{\r
+ */\r
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */\r
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */\r
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */\r
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */\r
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */\r
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */\r
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Window IWDG Window\r
+ * @{\r
+ */\r
+#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset IWDG handle state\r
+ * @param __HANDLE__: IWDG handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enables the IWDG peripheral.\r
+ * @param __HANDLE__: IWDG handle\r
+ * @retval None\r
+ */\r
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param __HANDLE__: IWDG handle\r
+ * @retval None\r
+ */\r
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)\r
+\r
+/**\r
+ * @brief Gets the selected IWDG's flag status.\r
+ * @param __HANDLE__: IWDG handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag\r
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag\r
+ * @arg IWDG_FLAG_WVU: Watchdog counter window value flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE) .\r
+ */\r
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup IWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);\r
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ****************************************************/\r
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);\r
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup IWDG_Private_Defines\r
+ * @{\r
+ */\r
+/**\r
+ * @brief IWDG Key Register BitMask\r
+ */\r
+#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */\r
+#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */\r
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */\r
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */\r
+\r
+/**\r
+ * @brief IWDG Flag definition\r
+ */\r
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */\r
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */\r
+#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup IWDG_Private_Macro IWDG Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r
+ * @param __HANDLE__: IWDG handle\r
+ * @retval None\r
+ */\r
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)\r
+\r
+/**\r
+ * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r
+ * @param __HANDLE__: IWDG handle\r
+ * @retval None\r
+ */\r
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)\r
+\r
+/**\r
+ * @brief Check IWDG prescaler value.\r
+ * @param __PRESCALER__: IWDG prescaler value\r
+ * @retval None\r
+ */\r
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \\r
+ ((__PRESCALER__) == IWDG_PRESCALER_256))\r
+\r
+/**\r
+ * @brief Check IWDG reload value.\r
+ * @param __RELOAD__: IWDG reload value\r
+ * @retval None\r
+ */\r
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)\r
+\r
+/**\r
+ * @brief Check IWDG window value.\r
+ * @param __WINDOW__: IWDG window value\r
+ * @retval None\r
+ */\r
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_IWDG_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_lptim.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of LPTIM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_LPTIM_H\r
+#define __STM32F7xx_HAL_LPTIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM LPTIM\r
+ * @brief LPTIM HAL module driver\r
+ * @{\r
+ */\r
+ \r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief LPTIM Clock configuration definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Source; /*!< Selects the clock source.\r
+ This parameter can be a value of @ref LPTIM_Clock_Source */\r
+\r
+ uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.\r
+ This parameter can be a value of @ref LPTIM_Clock_Prescaler */\r
+ \r
+}LPTIM_ClockConfigTypeDef;\r
+\r
+/** \r
+ * @brief LPTIM Clock configuration definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit\r
+ if the ULPTIM input is selected.\r
+ Note: This parameter is used only when Ultra low power clock source is used.\r
+ Note: If the polarity is configured on 'both edges', an auxiliary clock\r
+ (one of the Low power oscillator) must be active.\r
+ This parameter can be a value of @ref LPTIM_Clock_Polarity */ \r
+ \r
+ uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.\r
+ Note: This parameter is used only when Ultra low power clock source is used.\r
+ This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ \r
+ \r
+}LPTIM_ULPClockConfigTypeDef;\r
+\r
+/** \r
+ * @brief LPTIM Trigger configuration definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Source; /*!< Selects the Trigger source.\r
+ This parameter can be a value of @ref LPTIM_Trigger_Source */\r
+ \r
+ uint32_t ActiveEdge; /*!< Selects the Trigger active edge.\r
+ Note: This parameter is used only when an external trigger is used.\r
+ This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */\r
+ \r
+ uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.\r
+ Note: This parameter is used only when an external trigger is used.\r
+ This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ \r
+}LPTIM_TriggerConfigTypeDef;\r
+\r
+/** \r
+ * @brief LPTIM Initialization Structure definition \r
+ */\r
+typedef struct\r
+{ \r
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */\r
+ \r
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */\r
+ \r
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */\r
+ \r
+ uint32_t OutputPolarity; /*!< Specifies the Output polarity.\r
+ This parameter can be a value of @ref LPTIM_Output_Polarity */\r
+ \r
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare\r
+ values is done immediately or after the end of current period.\r
+ This parameter can be a value of @ref LPTIM_Updating_Mode */\r
+\r
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event\r
+ or each external event.\r
+ This parameter can be a value of @ref LPTIM_Counter_Source */ \r
+ \r
+}LPTIM_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL LPTIM State structure definition \r
+ */ \r
+typedef enum __HAL_LPTIM_StateTypeDef\r
+{\r
+ HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */\r
+ HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ \r
+ HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ \r
+ HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ \r
+}HAL_LPTIM_StateTypeDef;\r
+\r
+/** \r
+ * @brief LPTIM handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ LPTIM_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */\r
+ \r
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ \r
+ \r
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */\r
+ \r
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */\r
+ \r
+}LPTIM_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source\r
+ * @{\r
+ */\r
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)\r
+#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL \r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler\r
+ * @{\r
+ */\r
+#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)\r
+#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0\r
+#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1\r
+#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))\r
+#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2\r
+#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))\r
+#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))\r
+#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)\r
+#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time\r
+ * @{\r
+ */\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)\r
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0\r
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source\r
+ * @{\r
+ */\r
+#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)\r
+#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)\r
+#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)\r
+#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1\r
+#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)\r
+#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2\r
+#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity\r
+ * @{\r
+ */\r
+#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0\r
+#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1\r
+#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time\r
+ * @{\r
+ */\r
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)\r
+#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)\r
+#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN\r
+#define LPTIM_FLAG_UP LPTIM_ISR_UP\r
+#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK\r
+#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK\r
+#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG\r
+#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM\r
+#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE\r
+#define LPTIM_IT_UP LPTIM_IER_UPIE\r
+#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE\r
+#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE\r
+#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE\r
+#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE\r
+#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset LPTIM handle state\r
+ * @param __HANDLE__: LPTIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable/Disable the LPTIM peripheral.\r
+ * @param __HANDLE__: LPTIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))\r
+#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))\r
+\r
+/**\r
+ * @brief Starts the LPTIM peripheral in Continuous or in single mode.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)\r
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)\r
+ \r
+ \r
+/**\r
+ * @brief Writes the passed parameter in the Autoreload register.\r
+ * @param __HANDLE__: LPTIM handle\r
+ * @param __VALUE__ : Autoreload value\r
+ * @retval None\r
+ */\r
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))\r
+\r
+/**\r
+ * @brief Writes the passed parameter in the Compare register.\r
+ * @param __HANDLE__: LPTIM handle\r
+ * @param __VALUE__ : Compare value\r
+ * @retval None\r
+ */\r
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified LPTIM flag is set or not.\r
+ * @param __HANDLE__: LPTIM handle\r
+ * @param __FLAG__ : LPTIM flag to check\r
+ * This parameter can be a value of:\r
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.\r
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.\r
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.\r
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.\r
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.\r
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.\r
+ * @retval The state of the specified flag (SET or RESET).\r
+ */\r
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clears the specified LPTIM flag.\r
+ * @param __HANDLE__: LPTIM handle.\r
+ * @param __FLAG__ : LPTIM flag to clear.\r
+ * This parameter can be a value of:\r
+ * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.\r
+ * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.\r
+ * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.\r
+ * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.\r
+ * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r
+ * @arg LPTIM_FLAG_ARRM : Autoreload match Flag.\r
+ * @arg LPTIM_FLAG_CMPM : Compare match Flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Enable the specified LPTIM interrupt.\r
+ * @param __HANDLE__ : LPTIM handle.\r
+ * @param __INTERRUPT__ : LPTIM interrupt to set.\r
+ * This parameter can be a value of:\r
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.\r
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.\r
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.\r
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.\r
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.\r
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.\r
+ * @retval None.\r
+ */\r
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r
+\r
+ /**\r
+ * @brief Disable the specified LPTIM interrupt.\r
+ * @param __HANDLE__ : LPTIM handle.\r
+ * @param __INTERRUPT__ : LPTIM interrupt to set.\r
+ * This parameter can be a value of:\r
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.\r
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.\r
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.\r
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.\r
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.\r
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.\r
+ * @retval None.\r
+ */\r
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))\r
+\r
+ /**\r
+ * @brief Checks whether the specified LPTIM interrupt is set or not.\r
+ * @param __HANDLE__ : LPTIM handle.\r
+ * @param __INTERRUPT__ : LPTIM interrupt to check.\r
+ * This parameter can be a value of:\r
+ * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.\r
+ * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.\r
+ * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.\r
+ * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.\r
+ * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r
+ * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.\r
+ * @arg LPTIM_IT_CMPM : Compare match Interrupt.\r
+ * @retval Interrupt status.\r
+ */\r
+ \r
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);\r
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* MSP functions *************************************************************/\r
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* Start/Stop operation functions *********************************************/\r
+/* ################################# PWM Mode ################################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* ############################# One Pulse Mode ##############################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* ############################## Set once Mode ##############################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* ############################### Encoder Mode ##############################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* ############################# Time out Mode ##############################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* ############################## Counter Mode ###############################*/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* Reading operation functions ************************************************/\r
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);\r
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);\r
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* LPTIM IRQ functions *******************************************************/\r
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* CallBack functions ********************************************************/\r
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);\r
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/* Peripheral State functions ************************************************/\r
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Types LPTIM Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros\r
+ * @{\r
+ */\r
+ \r
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \\r
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))\r
+ \r
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \\r
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))\r
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) \r
+\r
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \\r
+ ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))\r
+ \r
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \\r
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \\r
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \\r
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))\r
+\r
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \\r
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))\r
+\r
+#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \\r
+ ((__TRIG__) == LPTIM_TRIGSOURCE_5))\r
+\r
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \\r
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \\r
+ ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))\r
+\r
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \\r
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \\r
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \\r
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) \r
+\r
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \\r
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))\r
+\r
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \\r
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))\r
+\r
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)\r
+\r
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)\r
+ \r
+#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)\r
+\r
+#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_LPTIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_ltdc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of LTDC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_LTDC_H\r
+#define __STM32F7xx_HAL_LTDC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LTDC LTDC\r
+ * @brief LTDC HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup LTDC_Exported_Types LTDC Exported Types\r
+ * @{\r
+ */\r
+#define MAX_LAYER 2\r
+\r
+/** \r
+ * @brief LTDC color structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Blue; /*!< Configures the blue value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint8_t Green; /*!< Configures the green value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint8_t Red; /*!< Configures the red value. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint8_t Reserved; /*!< Reserved 0xFF */\r
+} LTDC_ColorTypeDef;\r
+\r
+/** \r
+ * @brief LTDC Init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.\r
+ This parameter can be one value of @ref LTDC_HS_POLARITY */\r
+\r
+ uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.\r
+ This parameter can be one value of @ref LTDC_VS_POLARITY */\r
+\r
+ uint32_t DEPolarity; /*!< configures the data enable polarity. \r
+ This parameter can be one of value of @ref LTDC_DE_POLARITY */\r
+\r
+ uint32_t PCPolarity; /*!< configures the pixel clock polarity. \r
+ This parameter can be one of value of @ref LTDC_PC_POLARITY */\r
+\r
+ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.\r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r
+\r
+ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. \r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r
+\r
+ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.\r
+ This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */\r
+\r
+ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.\r
+ This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */\r
+\r
+ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. \r
+ This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */\r
+\r
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.\r
+ This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */\r
+\r
+ uint32_t TotalWidth; /*!< configures the total width.\r
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */\r
+\r
+ uint32_t TotalHeigh; /*!< configures the total height.\r
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */\r
+\r
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */\r
+} LTDC_InitTypeDef;\r
+\r
+/** \r
+ * @brief LTDC Layer structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.\r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r
+\r
+ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.\r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r
+\r
+ uint32_t WindowY0; /*!< Configures the Window vertical Start Position.\r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r
+\r
+ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.\r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t PixelFormat; /*!< Specifies the pixel format. \r
+ This parameter can be one of value of @ref LTDC_Pixelformat */\r
+\r
+ uint32_t Alpha; /*!< Specifies the constant alpha used for blending.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint32_t Alpha0; /*!< Configures the default alpha value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r
+\r
+ uint32_t BlendingFactor1; /*!< Select the blending factor 1. \r
+ This parameter can be one of value of @ref LTDC_BlendingFactor1 */\r
+\r
+ uint32_t BlendingFactor2; /*!< Select the blending factor 2. \r
+ This parameter can be one of value of @ref LTDC_BlendingFactor2 */\r
+\r
+ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */\r
+\r
+ uint32_t ImageWidth; /*!< Configures the color frame buffer line length. \r
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */\r
+\r
+ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. \r
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r
+\r
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */\r
+} LTDC_LayerCfgTypeDef;\r
+\r
+/** \r
+ * @brief HAL LTDC State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */\r
+ HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */\r
+ HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */\r
+ HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */\r
+ HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */\r
+}HAL_LTDC_StateTypeDef;\r
+\r
+/** \r
+ * @brief LTDC handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ LTDC_TypeDef *Instance; /*!< LTDC Register base address */\r
+\r
+ LTDC_InitTypeDef Init; /*!< LTDC parameters */\r
+\r
+ LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< LTDC Lock */\r
+\r
+ __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< LTDC Error code */\r
+\r
+} LTDC_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LTDC_Error_Code LTDC Error Code\r
+ * @{\r
+ */\r
+#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */\r
+#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */\r
+#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */\r
+#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY\r
+ * @{\r
+ */\r
+#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */\r
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY\r
+ * @{\r
+ */\r
+#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */\r
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY\r
+ * @{\r
+ */\r
+#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */\r
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY\r
+ * @{\r
+ */\r
+#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */\r
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_SYNC LTDC SYNC\r
+ * @{\r
+ */\r
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */ \r
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR\r
+ * @{\r
+ */\r
+#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1\r
+ * @{\r
+ */\r
+#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */\r
+#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2\r
+ * @{\r
+ */\r
+#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */\r
+#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_Pixelformat LTDC Pixel format\r
+ * @{\r
+ */\r
+#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */\r
+#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Alpha LTDC Alpha\r
+ * @{\r
+ */\r
+#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config\r
+ * @{\r
+ */\r
+#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */\r
+#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */\r
+\r
+#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ \r
+#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Interrupts LTDC Interrupts\r
+ * @{\r
+ */\r
+#define LTDC_IT_LI LTDC_IER_LIE\r
+#define LTDC_IT_FU LTDC_IER_FUIE\r
+#define LTDC_IT_TE LTDC_IER_TERRIE\r
+#define LTDC_IT_RR LTDC_IER_RRIE\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_Flag LTDC Flag\r
+ * @{\r
+ */\r
+#define LTDC_FLAG_LI LTDC_ISR_LIF\r
+#define LTDC_FLAG_FU LTDC_ISR_FUIF\r
+#define LTDC_FLAG_TE LTDC_ISR_TERRIF\r
+#define LTDC_FLAG_RR LTDC_ISR_RRIF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset LTDC handle state\r
+ * @param __HANDLE__: specifies the LTDC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the LTDC.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)\r
+\r
+/**\r
+ * @brief Disable the LTDC.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))\r
+\r
+/**\r
+ * @brief Enable the LTDC Layer.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __LAYER__: Specify the layer to be enabled\r
+ * This parameter can be 0 or 1\r
+ * @retval None.\r
+ */\r
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)\r
+\r
+/**\r
+ * @brief Disable the LTDC Layer.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __LAYER__: Specify the layer to be disabled\r
+ * This parameter can be 0 or 1\r
+ * @retval None.\r
+ */\r
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)\r
+\r
+/**\r
+ * @brief Reload Layer Configuration.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @retval None.\r
+ */\r
+#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)\r
+\r
+/* Interrupt & Flag management */\r
+/**\r
+ * @brief Get the LTDC pending flags.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LTDC_FLAG_LI: Line Interrupt flag \r
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r
+\r
+/**\r
+ * @brief Clears the LTDC pending flags.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg LTDC_FLAG_LI: Line Interrupt flag \r
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r
+ * @retval None\r
+ */\r
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified LTDC interrupts.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg LTDC_IT_LI: Line Interrupt flag \r
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag\r
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified LTDC interrupts.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg LTDC_IT_LI: Line Interrupt flag \r
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag\r
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified LTDC interrupt has occurred or not.\r
+ * @param __HANDLE__: LTDC handle\r
+ * @param __INTERRUPT__: specifies the LTDC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg LTDC_IT_LI: Line Interrupt flag \r
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag\r
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag\r
+ * @retval The state of INTERRUPT (SET or RESET).\r
+ */\r
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup LTDC_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup LTDC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);\r
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);\r
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);\r
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);\r
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);\r
+void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup LTDC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup LTDC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);\r
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);\r
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup LTDC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Peripheral State functions *************************************************/\r
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);\r
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup LTDC_Private_Types LTDC Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup LTDC_Private_Variables LTDC Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup LTDC_Private_Constants LTDC Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup LTDC_Private_Macros LTDC Private Macros\r
+ * @{\r
+ */\r
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))\r
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)\r
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \\r
+ ((HSPOL) == LTDC_HSPOLARITY_AH))\r
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \\r
+ ((VSPOL) == LTDC_VSPOLARITY_AH))\r
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \\r
+ ((DEPOL) == LTDC_DEPOLARITY_AH))\r
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \\r
+ ((PCPOL) == LTDC_PCPOLARITY_IIPC))\r
+#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)\r
+#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)\r
+#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)\r
+#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)\r
+#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)\r
+#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)\r
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)\r
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)\r
+#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)\r
+#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)\r
+#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)\r
+#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \\r
+ ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))\r
+#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \\r
+ ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))\r
+#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \\r
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \\r
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \\r
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))\r
+#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)\r
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)\r
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)\r
+#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)\r
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)\r
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)\r
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)\r
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)\r
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup LTDC_Private_Functions LTDC Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_LTDC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nand.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of NAND HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_NAND_H\r
+#define __STM32F7xx_HAL_NAND_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_fmc.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup NAND\r
+ * @{\r
+ */ \r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+/* Exported typedef ----------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup NAND_Exported_Types NAND Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL NAND State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */\r
+ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */\r
+ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */\r
+ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */\r
+}HAL_NAND_StateTypeDef;\r
+ \r
+/** \r
+ * @brief NAND Memory electronic signature Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ /*<! NAND memory electronic signature maker and device IDs */\r
+\r
+ uint8_t Maker_Id; \r
+\r
+ uint8_t Device_Id;\r
+\r
+ uint8_t Third_Id;\r
+\r
+ uint8_t Fourth_Id;\r
+}NAND_IDTypeDef;\r
+\r
+/** \r
+ * @brief NAND Memory address Structure definition\r
+ */\r
+typedef struct \r
+{\r
+ uint16_t Page; /*!< NAND memory Page address */\r
+\r
+ uint16_t Zone; /*!< NAND memory Zone address */\r
+\r
+ uint16_t Block; /*!< NAND memory Block address */\r
+\r
+}NAND_AddressTypeDef;\r
+\r
+/** \r
+ * @brief NAND Memory info Structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */\r
+\r
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */\r
+\r
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */\r
+\r
+ uint32_t BlockNbr; /*!< NAND memory number of blocks */\r
+\r
+ uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */\r
+}NAND_InfoTypeDef;\r
+\r
+/** \r
+ * @brief NAND handle Structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< NAND locking object */\r
+\r
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */\r
+\r
+ NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */\r
+}NAND_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup NAND_Exported_Macros NAND Exported Macros\r
+ * @{\r
+ */ \r
+\r
+/** @brief Reset NAND handle state\r
+ * @param __HANDLE__: specifies the NAND handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);\r
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);\r
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);\r
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);\r
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);\r
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions \r
+ * @{\r
+ */\r
+\r
+/* IO operation functions ****************************************************/\r
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);\r
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);\r
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);\r
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);\r
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);\r
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);\r
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);\r
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions \r
+ * @{\r
+ */\r
+\r
+/* NAND Control functions ****************************************************/\r
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);\r
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);\r
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions \r
+ * @{\r
+ */\r
+/* NAND State functions *******************************************************/\r
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);\r
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup NAND_Private_Constants NAND Private Constants\r
+ * @{\r
+ */\r
+#define NAND_DEVICE ((uint32_t)0x80000000) \r
+#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)\r
+\r
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */\r
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */\r
+\r
+#define NAND_CMD_AREA_A ((uint8_t)0x00)\r
+#define NAND_CMD_AREA_B ((uint8_t)0x01)\r
+#define NAND_CMD_AREA_C ((uint8_t)0x50)\r
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)\r
+\r
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)\r
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)\r
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)\r
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0) \r
+#define NAND_CMD_READID ((uint8_t)0x90)\r
+#define NAND_CMD_STATUS ((uint8_t)0x70)\r
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)\r
+#define NAND_CMD_RESET ((uint8_t)0xFF)\r
+\r
+/* NAND memory status */\r
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)\r
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)\r
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)\r
+#define NAND_BUSY ((uint32_t)0x00000000)\r
+#define NAND_ERROR ((uint32_t)0x00000001)\r
+#define NAND_READY ((uint32_t)0x00000040)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup NAND_Private_Macros NAND Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief NAND memory address computation.\r
+ * @param __ADDRESS__: NAND memory address.\r
+ * @param __HANDLE__ : NAND handle.\r
+ * @retval NAND Raw address value\r
+ */\r
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \\r
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))\r
+\r
+/**\r
+ * @brief NAND memory address cycling.\r
+ * @param __ADDRESS__: NAND memory address.\r
+ * @retval NAND address cycling value.\r
+ */\r
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */\r
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */\r
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */\r
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_NAND_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nor.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of NOR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_NOR_H\r
+#define __STM32F7xx_HAL_NOR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_fmc.h"\r
+\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup NOR\r
+ * @{\r
+ */ \r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+/* Exported typedef ----------------------------------------------------------*/\r
+/** @defgroup NOR_Exported_Types NOR Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL SRAM State structures definition \r
+ */ \r
+typedef enum\r
+{ \r
+ HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */\r
+ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */\r
+ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */\r
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */\r
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */\r
+}HAL_NOR_StateTypeDef;\r
+\r
+/**\r
+ * @brief FMC NOR Status typedef\r
+ */\r
+typedef enum\r
+{\r
+ HAL_NOR_STATUS_SUCCESS = 0,\r
+ HAL_NOR_STATUS_ONGOING,\r
+ HAL_NOR_STATUS_ERROR,\r
+ HAL_NOR_STATUS_TIMEOUT\r
+}HAL_NOR_StatusTypeDef;\r
+\r
+/**\r
+ * @brief FMC NOR ID typedef\r
+ */\r
+typedef struct\r
+{\r
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */\r
+\r
+ uint16_t Device_Code1;\r
+\r
+ uint16_t Device_Code2;\r
+\r
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. \r
+ These codes can be accessed by performing read operations with specific \r
+ control signals and addresses set.They can also be accessed by issuing \r
+ an Auto Select command */\r
+}NOR_IDTypeDef;\r
+\r
+/**\r
+ * @brief FMC NOR CFI typedef\r
+ */\r
+typedef struct\r
+{\r
+ /*!< Defines the information stored in the memory's Common flash interface\r
+ which contains a description of various electrical and timing parameters, \r
+ density information and functions supported by the memory */\r
+\r
+ uint16_t CFI_1;\r
+\r
+ uint16_t CFI_2;\r
+\r
+ uint16_t CFI_3;\r
+\r
+ uint16_t CFI_4;\r
+}NOR_CFITypeDef;\r
+\r
+/** \r
+ * @brief NOR handle Structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */\r
+\r
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */\r
+\r
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< NOR locking object */\r
+\r
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */\r
+\r
+}NOR_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup NOR_Exported_Macros NOR Exported Macros\r
+ * @{\r
+ */\r
+/** @brief Reset NOR handle state\r
+ * @param __HANDLE__: specifies the NOR handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);\r
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);\r
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);\r
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions \r
+ * @{\r
+ */\r
+\r
+/* I/O operation functions ***************************************************/\r
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);\r
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);\r
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r
+\r
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r
+\r
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);\r
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);\r
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions \r
+ * @{\r
+ */\r
+\r
+/* NOR Control functions *****************************************************/\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions \r
+ * @{\r
+ */\r
+\r
+/* NOR State functions ********************************************************/\r
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);\r
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup NOR_Private_Constants NOR Private Constants\r
+ * @{\r
+ */\r
+/* NOR device IDs addresses */\r
+#define MC_ADDRESS ((uint16_t)0x0000)\r
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)\r
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)\r
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)\r
+\r
+/* NOR CFI IDs addresses */\r
+#define CFI1_ADDRESS ((uint16_t)0x61)\r
+#define CFI2_ADDRESS ((uint16_t)0x62)\r
+#define CFI3_ADDRESS ((uint16_t)0x63)\r
+#define CFI4_ADDRESS ((uint16_t)0x64)\r
+\r
+/* NOR operation wait timeout */\r
+#define NOR_TMEOUT ((uint16_t)0xFFFF)\r
+ \r
+/* NOR memory data width */\r
+#define NOR_MEMORY_8B ((uint8_t)0x0)\r
+#define NOR_MEMORY_16B ((uint8_t)0x1)\r
+\r
+/* NOR memory device read/write start address */\r
+#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)\r
+#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)\r
+#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)\r
+#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup NOR_Private_Macros NOR Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief NOR memory address shifting.\r
+ * @param __NOR_ADDRESS: NOR base address \r
+ * @param __NOR_MEMORY_WIDTH_: NOR memory width\r
+ * @param __ADDRESS__: NOR memory address \r
+ * @retval NOR shifted address value\r
+ */\r
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \\r
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? \\r
+ ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \\r
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))\r
+ \r
+/**\r
+ * @brief NOR memory write data to specified address.\r
+ * @param __ADDRESS__: NOR memory address \r
+ * @param __DATA__: Data to write\r
+ * @retval None\r
+ */\r
+#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \\r
+ (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \\r
+ __DSB(); \\r
+ } while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_NOR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of PCD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PCD_H\r
+#define __STM32F7xx_HAL_PCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_usb.h"\r
+ \r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PCD\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup PCD_Exported_Types PCD Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief PCD State structure definition\r
+ */ \r
+typedef enum \r
+{\r
+ HAL_PCD_STATE_RESET = 0x00,\r
+ HAL_PCD_STATE_READY = 0x01,\r
+ HAL_PCD_STATE_ERROR = 0x02,\r
+ HAL_PCD_STATE_BUSY = 0x03,\r
+ HAL_PCD_STATE_TIMEOUT = 0x04\r
+} PCD_StateTypeDef;\r
+\r
+/* Device LPM suspend state */\r
+typedef enum \r
+{\r
+ LPM_L0 = 0x00, /* on */\r
+ LPM_L1 = 0x01, /* LPM L1 sleep */\r
+ LPM_L2 = 0x02, /* suspend */\r
+ LPM_L3 = 0x03, /* off */\r
+}PCD_LPM_StateTypeDef;\r
+\r
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;\r
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;\r
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef ; \r
+\r
+/** \r
+ * @brief PCD Handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ PCD_TypeDef *Instance; /*!< Register base address */ \r
+ PCD_InitTypeDef Init; /*!< PCD required parameters */\r
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */\r
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ \r
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */\r
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */\r
+ uint32_t Setup[12]; /*!< Setup packet buffer */\r
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */\r
+ uint32_t BESL;\r
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . \r
+ This parameter can be set to ENABLE or DISABLE */\r
+ void *pData; /*!< Pointer to upper stack Handler */ \r
+} PCD_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Include PCD HAL Extension module */\r
+#include "stm32f7xx_hal_pcd_ex.h"\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCD_Speed PCD Speed\r
+ * @{\r
+ */\r
+#define PCD_SPEED_HIGH 0\r
+#define PCD_SPEED_HIGH_IN_FULL 1\r
+#define PCD_SPEED_FULL 2\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PCD_PHY_Module PCD PHY Module\r
+ * @{\r
+ */\r
+#define PCD_PHY_ULPI 1\r
+#define PCD_PHY_EMBEDDED 2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Macros PCD Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)\r
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)\r
+ \r
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))\r
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)\r
+\r
+\r
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \\r
+ ~(USB_OTG_PCGCCTL_STOPCLK)\r
+\r
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\r
+ \r
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)\r
+ \r
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) \r
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) \r
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) \r
+\r
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) \r
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) \r
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) \r
+\r
+#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */\r
+#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */\r
+\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)\r
+\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\\r
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE\r
+ \r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\\r
+ EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\r
+\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\\r
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\\r
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\\r
+ EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) \r
+ \r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\r
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+ \r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\\r
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r
+\r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\r
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\r
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\\r
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE \r
+ \r
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* I/O operation functions ***************************************************/\r
+/* Non-Blocking mode: Interrupt */\r
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\r
+\r
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\r
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);\r
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions ************************************************/\r
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PCD_Instance_definition PCD Instance definition\r
+ * @{\r
+ */\r
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PCD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of PCD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PCD_EX_H\r
+#define __STM32F7xx_HAL_PCD_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+ \r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PCDEx\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef enum \r
+{\r
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */\r
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */\r
+}PCD_LPM_MsgTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\r
+ * @{\r
+ */\r
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\r
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\r
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PCD_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of PWR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_H\r
+#define __STM32F7xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief PWR PVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
+ This parameter can be a value of @ref PWR_PVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWR_PVD_Mode */\r
+}PWR_PVDTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
+ * @{\r
+ */ \r
+#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0\r
+#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1\r
+#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2\r
+#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3\r
+#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4\r
+#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5\r
+#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6\r
+#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
+ * @{\r
+ */\r
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)\r
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
+ * @{\r
+ */\r
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
+ * @{\r
+ */\r
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)\r
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r
+ * @{\r
+ */\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1\r
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag PWR Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_WU PWR_CSR1_WUIF\r
+#define PWR_FLAG_SB PWR_CSR1_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR1_PVDO\r
+#define PWR_FLAG_BRR PWR_CSR1_BRR\r
+#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macro PWR Exported Macro\r
+ * @{\r
+ */\r
+\r
+/** @brief macros configure the main internal regulator output voltage.\r
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption when the device does\r
+ * not operate at the maximum frequency (refer to the datasheets for more details).\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \\r
+ __IO uint32_t tmpreg; \\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),\r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r
+ * when the device wakes up from Standby mode or by a system reset \r
+ * or power reset. \r
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r
+ * scaling output selection is ready.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the PWR's pending flags.\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)\r
+\r
+/**\r
+ * @brief Enable the PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable the PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r
+ * @retval EXTI PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Clear the PVD Exti flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on PVD EXTI line.\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include PWR HAL Extension module */\r
+#include "stm32f7xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+/* PVD configuration */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+/* WakeUp pins configuration */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes entry */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+/* Power PVD IRQ Handler */\r
+void HAL_PWR_PVD_IRQHandler(void);\r
+void HAL_PWR_PVDCallback(void);\r
+\r
+/* Cortex System Control functions *******************************************/\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Constants PWR Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r
+ * @{\r
+ */\r
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Macros PWR Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_WAKEUP_POLARITY(POLARITY) (((POLARITY) == PWR_POLARITY_RISINGEDGE) || \\r
+ ((POLARITY) == PWR_POLARITY_FALLINGEDGE))\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_NORMAL))\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of PWR HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_EX_H\r
+#define __STM32F7xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)\r
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)\r
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)\r
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)\r
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)\r
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS\r
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY\r
+#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY\r
+#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1\r
+#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2\r
+#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3\r
+#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4\r
+#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5\r
+#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r
+ * @{\r
+ */\r
+/** @brief Macros to enable or disable the Over drive mode.\r
+ */\r
+#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)\r
+#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))\r
+\r
+/** @brief Macros to enable or disable the Over drive switching.\r
+ */\r
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)\r
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))\r
+\r
+/** @brief Macros to enable or disable the Under drive mode.\r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode. \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ */\r
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)\r
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\r
+ * is ready \r
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\r
+ * switching is ready \r
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\r
+ * is enabled in Stop mode\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the Under-Drive Ready flag.\r
+ */\r
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)\r
+\r
+/** @brief Check Wake Up flag is set or not.\r
+ * @param __WUFLAG__: specifies the Wake Up flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))\r
+\r
+/** @brief Clear the WakeUp pins flags.\r
+ * @param __WUFLAG__: specifies the Wake Up pin flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWREx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
+\r
+void HAL_PWREx_EnableFlashPowerDown(void);\r
+void HAL_PWREx_DisableFlashPowerDown(void); \r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \r
+\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);\r
+\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Private_Macros PWREx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\r
+#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_qspi.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of QSPI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_QSPI_H\r
+#define __STM32F7xx_HAL_QSPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup QSPI\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup QSPI_Exported_Types QSPI Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief QSPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.\r
+ This parameter can be a number between 0 and 255 */ \r
+ \r
+ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r
+ This parameter can be a value between 1 and 16 */\r
+ \r
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to \r
+ take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r
+ This parameter can be a value of @ref QSPI_SampleShifting */\r
+ \r
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits \r
+ required to address the flash memory. The flash capacity can be up to 4GB \r
+ (addressed using 32 bits) in indirect mode, but the addressable space in \r
+ memory-mapped mode is limited to 256MB\r
+ This parameter can be a number between 0 and 31 */\r
+ \r
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number \r
+ of clock cycles which the chip select must remain high between commands.\r
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */ \r
+ \r
+ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r
+ This parameter can be a value of @ref QSPI_ClockMode */\r
+ \r
+ uint32_t FlashID; /* Specifies the Flash which will be used,\r
+ This parameter can be a value of @ref QSPI_Flash_Select */\r
+ \r
+ uint32_t DualFlash; /* Specifies the Dual Flash Mode State\r
+ This parameter can be a value of @ref QSPI_DualFlash_Mode */ \r
+}QSPI_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL QSPI State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */\r
+ HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */\r
+ HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ \r
+ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ \r
+ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */\r
+ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */\r
+ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */\r
+ HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */\r
+}HAL_QSPI_StateTypeDef;\r
+\r
+/** \r
+ * @brief QSPI Handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ QUADSPI_TypeDef *Instance; /* QSPI registers base address */\r
+ QSPI_InitTypeDef Init; /* QSPI communication parameters */\r
+ uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */\r
+ __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */\r
+ __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */\r
+ uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */\r
+ __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */\r
+ __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */\r
+ DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */\r
+ __IO HAL_LockTypeDef Lock; /* Locking object */\r
+ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */\r
+ __IO uint32_t ErrorCode; /* QSPI Error code */\r
+ uint32_t Timeout; /* Timeout for the QSPI memory access */ \r
+}QSPI_HandleTypeDef;\r
+\r
+/** \r
+ * @brief QSPI Command structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Instruction; /* Specifies the Instruction to be sent\r
+ This parameter can be a value (8-bit) between 0x00 and 0xFF */\r
+ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r
+ uint32_t AddressSize; /* Specifies the Address Size\r
+ This parameter can be a value of @ref QSPI_AddressSize */\r
+ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r
+ This parameter can be a value of @ref QSPI_AlternateBytesSize */\r
+ uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.\r
+ This parameter can be a number between 0 and 31 */\r
+ uint32_t InstructionMode; /* Specifies the Instruction Mode\r
+ This parameter can be a value of @ref QSPI_InstructionMode */\r
+ uint32_t AddressMode; /* Specifies the Address Mode\r
+ This parameter can be a value of @ref QSPI_AddressMode */\r
+ uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode\r
+ This parameter can be a value of @ref QSPI_AlternateBytesMode */\r
+ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)\r
+ This parameter can be a value of @ref QSPI_DataMode */\r
+ uint32_t NbData; /* Specifies the number of data to transfer. \r
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length \r
+ until end of memory)*/\r
+ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase\r
+ This parameter can be a value of @ref QSPI_DdrMode */\r
+ uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of \r
+ system clock in DDR mode.\r
+ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode\r
+ This parameter can be a value of @ref QSPI_SIOOMode */\r
+}QSPI_CommandTypeDef;\r
+\r
+/** \r
+ * @brief QSPI Auto Polling mode configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.\r
+ This parameter can be any value between 0 and 0xFFFFFFFF */\r
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. \r
+ This parameter can be any value between 0 and 0xFFFFFFFF */\r
+ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.\r
+ This parameter can be any value between 0 and 0xFFFF */\r
+ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.\r
+ This parameter can be any value between 1 and 4 */\r
+ uint32_t MatchMode; /* Specifies the method used for determining a match.\r
+ This parameter can be a value of @ref QSPI_MatchMode */\r
+ uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.\r
+ This parameter can be a value of @ref QSPI_AutomaticStop */\r
+}QSPI_AutoPollingTypeDef;\r
+ \r
+/** \r
+ * @brief QSPI Memory Mapped mode configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r
+ This parameter can be any value between 0 and 0xFFFF */\r
+ uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. \r
+ This parameter can be a value of @ref QSPI_TimeOutActivation */\r
+}QSPI_MemoryMappedTypeDef; \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup QSPI_ErrorCode QSPI Error Code\r
+ * @{\r
+ */ \r
+#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */\r
+#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */\r
+#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r
+ * @{\r
+ */\r
+#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/\r
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time\r
+ * @{\r
+ */\r
+#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/\r
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_ClockMode QSPI Clock Mode\r
+ * @{\r
+ */\r
+#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/\r
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup QSPI_Flash_Select QSPI Flash Select\r
+ * @{\r
+ */\r
+#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)\r
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode\r
+ * @{\r
+ */\r
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)\r
+#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_AddressSize QSPI Address Size \r
+ * @{\r
+ */\r
+#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/\r
+#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r
+#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r
+#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r
+ * @{\r
+ */\r
+#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r
+* @{\r
+*/\r
+#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/\r
+#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r
+#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r
+#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_AddressMode QSPI Address Mode\r
+* @{\r
+*/\r
+#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/\r
+#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r
+#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r
+#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode\r
+* @{ \r
+*/\r
+#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/\r
+#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r
+#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r
+#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_DataMode QSPI Data Mode\r
+ * @{\r
+ */\r
+#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/\r
+#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r
+#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r
+#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_DdrMode QSPI Ddr Mode\r
+ * @{\r
+ */\r
+#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/\r
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle\r
+ * @{\r
+ */\r
+#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/\r
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_SIOOMode QSPI SIOO Mode\r
+ * @{\r
+ */\r
+#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/\r
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_MatchMode QSPI Match Mode\r
+ * @{\r
+ */\r
+#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/\r
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r
+ * @{\r
+ */\r
+#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/\r
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation\r
+ * @{\r
+ */\r
+#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/\r
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup QSPI_Flags QSPI Flags\r
+ * @{\r
+ */\r
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/\r
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Interrupts QSPI Interrupts\r
+ * @{\r
+ */ \r
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r
+ * @{\r
+ */ \r
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset QSPI handle state\r
+ * @param __HANDLE__: QSPI handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r
+\r
+/** @brief Enable QSPI\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @retval None\r
+ */ \r
+#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief Disable QSPI\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r
+\r
+/** @brief Enables the specified QSPI interrupt.\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Time out interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+\r
+/** @brief Disables the specified QSPI interrupt.\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r
+\r
+/** @brief Checks whether the specified QSPI interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @param __INTERRUPT__: specifies the QSPI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_IT_TO: QSPI Time out interrupt\r
+ * @arg QSPI_IT_SM: QSPI Status match interrupt\r
+ * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r
+ * @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r
+ * @arg QSPI_IT_TE: QSPI Transfer error interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) \r
+\r
+/**\r
+ * @brief Get the selected QSPI's flag status.\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @param __FLAG__: specifies the QSPI flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_FLAG_BUSY: QSPI Busy flag\r
+ * @arg QSPI_FLAG_TO: QSPI Time out flag\r
+ * @arg QSPI_FLAG_SM: QSPI Status match flag\r
+ * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag\r
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)\r
+\r
+/** @brief Clears the specified QSPI's flag status.\r
+ * @param __HANDLE__: specifies the QSPI Handle.\r
+ * @param __FLAG__: specifies the QSPI clear register flag that needs to be set\r
+ * This parameter can be one of the following values:\r
+ * @arg QSPI_FLAG_TO: QSPI Time out flag\r
+ * @arg QSPI_FLAG_SM: QSPI Status match flag\r
+ * @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r
+ * @arg QSPI_FLAG_TE: QSPI Transfer error flag\r
+ * @retval None\r
+ */\r
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup QSPI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+/* IO operation functions *****************************************************/\r
+/* QSPI IRQ handler method */\r
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r
+\r
+/* QSPI status flag polling mode */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r
+\r
+/* QSPI memory-mapped mode */\r
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group3\r
+ * @{\r
+ */ \r
+/* Callback functions in non-blocking modes ***********************************/\r
+void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI indirect mode */\r
+void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI status flag polling mode */\r
+void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);\r
+\r
+/* QSPI memory-mapped mode */\r
+void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup QSPI_Exported_Functions_Group4\r
+ * @{\r
+ */ \r
+/* Peripheral Control and State functions ************************************/\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);\r
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);\r
+HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);\r
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Constants QSPI Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Macros QSPI Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler\r
+ * @{\r
+ */ \r
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold \r
+ * @{\r
+ */\r
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\r
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) \r
+\r
+/** @defgroup QSPI_FlashSize QSPI Flash Size\r
+ * @{\r
+ */\r
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\r
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) \r
+\r
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\r
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))\r
+\r
+#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \\r
+ ((FLA) == QSPI_FLASH_ID_2)) \r
+ \r
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \\r
+ ((MODE) == QSPI_DUALFLASH_DISABLE))\r
+ \r
+ \r
+/** @defgroup QSPI_Instruction QSPI Instruction\r
+ * @{\r
+ */\r
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\r
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\r
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) \r
+\r
+\r
+/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles\r
+ * @{\r
+ */\r
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \\r
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \\r
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\r
+ ((MODE) == QSPI_INSTRUCTION_4_LINES)) \r
+\r
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \\r
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \\r
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \\r
+ ((MODE) == QSPI_ADDRESS_4_LINES))\r
+\r
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\r
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r
+\r
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \\r
+ ((MODE) == QSPI_DATA_1_LINE) || \\r
+ ((MODE) == QSPI_DATA_2_LINES) || \\r
+ ((MODE) == QSPI_DATA_4_LINES))\r
+\r
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\r
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r
+\r
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\r
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r
+\r
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\r
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r
+\r
+/** @defgroup QSPI_Interval QSPI Interval \r
+ * @{\r
+ */\r
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size\r
+ * @{\r
+ */\r
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) \r
+/**\r
+ * @}\r
+ */\r
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \\r
+ ((MODE) == QSPI_MATCH_MODE_OR)) \r
+ \r
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\r
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) \r
+\r
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\r
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) \r
+\r
+/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period\r
+ * @{\r
+ */\r
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) \r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \\r
+ ((FLAG) == QSPI_FLAG_TO) || \\r
+ ((FLAG) == QSPI_FLAG_SM) || \\r
+ ((FLAG) == QSPI_FLAG_FT) || \\r
+ ((FLAG) == QSPI_FLAG_TC) || \\r
+ ((FLAG) == QSPI_FLAG_TE)) \r
+\r
+#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup QSPI_Private_Functions QSPI Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_QSPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of RCC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_H\r
+#define __STM32F7xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief RCC PLL configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLState; /*!< The new state of the PLL.\r
+ This parameter can be a value of @ref RCC_PLL_Config */\r
+\r
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.\r
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */ \r
+\r
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ \r
+\r
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */\r
+\r
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).\r
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
+\r
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15 */\r
+\r
+}RCC_PLLInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OscillatorType; /*!< The oscillators to be configured.\r
+ This parameter can be a value of @ref RCC_Oscillator_Type */\r
+\r
+ uint32_t HSEState; /*!< The new state of the HSE.\r
+ This parameter can be a value of @ref RCC_HSE_Config */\r
+\r
+ uint32_t LSEState; /*!< The new state of the LSE.\r
+ This parameter can be a value of @ref RCC_LSE_Config */\r
+ \r
+ uint32_t HSIState; /*!< The new state of the HSI.\r
+ This parameter can be a value of @ref RCC_HSI_Config */\r
+\r
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
+ \r
+ uint32_t LSIState; /*!< The new state of the LSI.\r
+ This parameter can be a value of @ref RCC_LSI_Config */\r
+\r
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ \r
+\r
+}RCC_OscInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC System, AHB and APB busses clock configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockType; /*!< The clock to be configured.\r
+ This parameter can be a value of @ref RCC_System_Clock_Type */\r
+ \r
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
+ This parameter can be a value of @ref RCC_System_Clock_Source */\r
+\r
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
+\r
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+}RCC_ClkInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Oscillator_Type Oscillator Type\r
+ * @{\r
+ */\r
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)\r
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)\r
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)\r
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)\r
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Config RCC HSE Config\r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF ((uint32_t)0x00000000)\r
+#define RCC_HSE_ON RCC_CR_HSEON\r
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Config RCC LSE Config\r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF ((uint32_t)0x00000000)\r
+#define RCC_LSE_ON RCC_BDCR_LSEON\r
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Config RCC HSI Config\r
+ * @{\r
+ */\r
+#define RCC_HSI_OFF ((uint32_t)0x00000000)\r
+#define RCC_HSI_ON RCC_CR_HSION\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Config RCC LSI Config\r
+ * @{\r
+ */\r
+#define RCC_LSI_OFF ((uint32_t)0x00000000)\r
+#define RCC_LSI_ON RCC_CSR_LSION\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Config RCC PLL Config\r
+ * @{\r
+ */\r
+#define RCC_PLL_NONE ((uint32_t)0x00000000)\r
+#define RCC_PLL_OFF ((uint32_t)0x00000001)\r
+#define RCC_PLL_ON ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)\r
+#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)\r
+#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)\r
+#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
+ * @{\r
+ */\r
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI\r
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r
+ * @{\r
+ */\r
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)\r
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)\r
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)\r
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)\r
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup RCC_MCO_Index RCC MCO Index\r
+ * @{\r
+ */\r
+#define RCC_MCO1 ((uint32_t)0x00000000)\r
+#define RCC_MCO2 ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)\r
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0\r
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1\r
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)\r
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0\r
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1\r
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)\r
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2\r
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt RCC Interrupt \r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)\r
+#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Flag RCC Flags\r
+ * Elements values convention: 0XXYYYYYb\r
+ * - YYYYY : Flag position in the register\r
+ * - 0XX : Register index\r
+ * - 01: CR register\r
+ * - 10: BDCR register\r
+ * - 11: CSR register\r
+ * @{\r
+ */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)\r
+#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)\r
+\r
+/* Flags in the BDCR register */\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
+#define RCC_FLAG_BORRST ((uint8_t)0x79)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations\r
+ * @{\r
+ */\r
+#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)\r
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1\r
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0\r
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\r
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable \r
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) \r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
+ * @brief EGet the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r
+ * @brief Force or release AHB peripheral reset.\r
+ * @{\r
+ */ \r
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)\r
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r
+\r
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)\r
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset \r
+ * @brief Force or release APB1 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) \r
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r
+\r
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) \r
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset \r
+ * @brief Force or release APB2 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) \r
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r
+\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) != RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_HSI_Configuration HSI Configuration\r
+ * @{ \r
+ */ \r
+ \r
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after startup\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled). \r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI. \r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source. \r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))\r
+#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))\r
+\r
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\\r
+ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Configuration LSI Configuration\r
+ * @{ \r
+ */ \r
+\r
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))\r
+#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Configuration HSE Configuration\r
+ * @{ \r
+ */ \r
+/**\r
+ * @brief Macro to configure the External High Speed oscillator (__HSE__).\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. \r
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function. \r
+ * @param __STATE__: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.\r
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
+ do { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ if((__STATE__) == RCC_HSE_ON) \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else if((__STATE__) == RCC_HSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Configuration LSE Configuration\r
+ * @{ \r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE).\r
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass. \r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using \r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param __STATE__: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.\r
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
+ do { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ if((__STATE__) == RCC_LSE_ON) \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))\r
+#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))\r
+\r
+/** @brief Macros to configure the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using the Power Backup Access macro before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the \r
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r
+ * a Power On Reset (POR).\r
+ * @param __RTCCLKSource__: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r
+ * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes. \r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ */\r
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r
+ \r
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \\r
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \\r
+ } while (0)\r
+\r
+/** @brief Macros to force or release the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset. \r
+ */\r
+#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Configuration PLL Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
+\r
+\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. \r
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 192 and 432 MHz.\r
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 200 MHz on\r
+ * the System clock frequency.\r
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\\r
+ (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \\r
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \\r
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macro to configure the I2S clock source (I2SCLK).\r
+ * @note This function must be called before enabling the I2S APB clock.\r
+ * @param __SOURCE__: specifies the I2S clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\r
+ * used as I2S clock source.\r
+ */\r
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \\r
+ RCC->CFGR |= (__SOURCE__); \\r
+ }while(0)\r
+\r
+/** @brief Macros to enable or disable the PLLI2S. \r
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))\r
+#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Get_Clock_source Get Clock source\r
+ * @{ \r
+ */\r
+/**\r
+ * @brief Macro to configure the system clock source.\r
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.\r
+ * This parameter can be one of the following values:\r
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
+ */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r
+\r
+/** @brief Macro to get the clock source used as system clock.\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
+ */ \r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))\r
+\r
+/**\r
+ * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r
+ * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \\r
+ (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))\r
+\r
+/** @brief Macro to get the oscillator used as PLL clock source.\r
+ * @retval The oscillator used as PLL clock source. The returned value can be one\r
+ * of the following:\r
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
+ */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+ * @brief macros to manage the specified RCC Flags and interrupts.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable \r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))\r
+\r
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\r
+ * bits to clear the selected interrupt pending bits.\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r
+\r
+/** @brief Check the RCC's interrupt has occurred or not.\r
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r
+\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\r
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\r
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\r
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\r
+ * @arg RCC_FLAG_PINRST: Pin reset.\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.\r
+ * @arg RCC_FLAG_SFTRST: Software reset.\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC HAL Extension module */\r
+#include "stm32f7xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+ /** @addtogroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+/* Initialization and de-initialization functions ******************************/\r
+void HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void HAL_RCC_EnableCSS(void);\r
+void HAL_RCC_DisableCSS(void);\r
+uint32_t HAL_RCC_GetSysClockFreq(void);\r
+uint32_t HAL_RCC_GetHCLKFreq(void);\r
+uint32_t HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t HAL_RCC_GetPCLK2Freq(void);\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+\r
+/* CSS NMI IRQ handler */\r
+void HAL_RCC_NMI_IRQHandler(void);\r
+\r
+/* User Callbacks in non blocking mode (IT mode) */ \r
+void HAL_RCC_CSSCallback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+ * @{\r
+ */\r
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */\r
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */\r
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */\r
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ \r
+\r
+/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias\r
+ * @brief RCC registers bit address alias\r
+ * @{\r
+ */\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r
+\r
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)\r
+#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */ \r
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)\r
+\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_BYPASS))\r
+\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_BYPASS))\r
+\r
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\r
+\r
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r
+\r
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\r
+\r
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_HSE))\r
+\r
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r
+#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))\r
+\r
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))\r
+\r
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \\r
+ ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))\r
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV512))\r
+\r
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))\r
+\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\r
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\r
+ ((PCLK) == RCC_HCLK_DIV16))\r
+\r
+#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))\r
+\r
+\r
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\r
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\r
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \\r
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\r
+ ((DIV) == RCC_MCODIV_5)) \r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+\r
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))\r
+\r
+\r
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_HIGH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of RCC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_EX_H\r
+#define __STM32F7xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief PLLI2S Clock structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 49 and Max_Data = 432.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 8. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+}RCC_PLLI2SInitTypeDef;\r
+\r
+/** \r
+ * @brief PLLSAI Clock structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 49 and Max_Data = 432.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ \r
+ \r
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r
+ \r
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r
+\r
+ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 8. \r
+ This parameter will be used only when PLLSAI is disabled */\r
+}RCC_PLLSAIInitTypeDef;\r
+\r
+/** \r
+ * @brief RCC extended clocks structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+\r
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. \r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\r
+\r
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.\r
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\r
+\r
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. \r
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
+ \r
+ uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. \r
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */\r
+\r
+ uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. \r
+ This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r
+ \r
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
+\r
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r
+ \r
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source \r
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r
+ \r
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source \r
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r
+\r
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source \r
+ This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ \r
+ \r
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source \r
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r
+ \r
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source \r
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r
+ \r
+ uint32_t Usart6ClockSelection; /*!< USART6 clock source \r
+ This parameter can be a value of @ref RCCEx_USART6_Clock_Source */\r
+ \r
+ uint32_t Uart7ClockSelection; /*!< UART7 clock source \r
+ This parameter can be a value of @ref RCCEx_UART7_Clock_Source */\r
+ \r
+ uint32_t Uart8ClockSelection; /*!< UART8 clock source \r
+ This parameter can be a value of @ref RCCEx_UART8_Clock_Source */\r
+ \r
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r
+\r
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r
+\r
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r
+ \r
+ uint32_t I2c4ClockSelection; /*!< I2C4 clock source \r
+ This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
+ \r
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
+ \r
+ uint32_t CecClockSelection; /*!< CEC clock source \r
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r
+ \r
+ uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC\r
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\r
+ \r
+ uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source \r
+ This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r
+\r
+}RCC_PeriphCLKInitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\r
+ * @{\r
+ */\r
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)\r
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)\r
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)\r
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)\r
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)\r
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)\r
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)\r
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)\r
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)\r
+#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)\r
+#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)\r
+#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)\r
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)\r
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)\r
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)\r
+#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)\r
+#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)\r
+#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)\r
+#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)\r
+#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)\r
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)\r
+#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)\r
+#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)\r
+#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)\r
+#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)\r
+#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)\r
+#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0\r
+#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1\r
+#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)\r
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ \r
+/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)\r
+#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0\r
+#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)\r
+#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0\r
+#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)\r
+#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)\r
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0\r
+#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1\r
+#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0\r
+#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1\r
+#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0\r
+#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1\r
+#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0\r
+#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1\r
+#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0\r
+#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1\r
+#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)\r
+#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0\r
+#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1\r
+#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0\r
+#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1\r
+#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0\r
+#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1\r
+#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0\r
+#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0\r
+#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0\r
+#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)\r
+#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0\r
+#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)\r
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0\r
+#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1\r
+#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)\r
+#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r
+ * @{\r
+ */\r
+#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)\r
+#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @{\r
+ */\r
+ \r
+/** @brief Enables or disables the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\r
+#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))\r
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\r
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\r
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\r
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \\r
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \\r
+ } while(0)\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\r
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \\r
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \\r
+ } while(0)\r
+ \r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ UNUSED(tmpreg); \\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\\r
+ } while(0) \r
+ \r
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\r
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) \r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\\r
+ __HAL_RCC_SYSCFG_CLK_DISABLE();\\r
+ }while(0)\r
+#if defined(STM32F756xx)\r
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) \r
+#endif /* STM32F756x */\r
+/** @brief Enables or disables the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ */\r
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\r
+\r
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ */\r
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\r
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\r
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\r
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))\r
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\r
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\r
+\r
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\r
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))\r
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\r
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\r
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it. \r
+ */\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) \r
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\r
+\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\r
+\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it. \r
+ */\r
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\r
+\r
+ \r
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) \r
+#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\r
+\r
+#if defined(STM32F756xx)\r
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\r
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) \r
+#endif /* STM32F756x */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */ \r
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\r
+\r
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r
+ * @brief Forces or releases AHB/APB peripheral reset.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Force or release AHB1 peripheral reset.\r
+ */ \r
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\r
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\r
+\r
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\r
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\r
+ \r
+/** @brief Force or release AHB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) \r
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r
+\r
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)\r
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#if defined(STM32F756xx)\r
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\r
+#endif /* STM32F756xx */\r
+\r
+/** @brief Force or release AHB3 peripheral reset\r
+ */ \r
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) \r
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r
+\r
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)\r
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\r
+ \r
+/** @brief Force or release APB1 peripheral reset.\r
+ */ \r
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\r
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\r
+\r
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\r
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\r
+\r
+/** @brief Force or release APB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r
+\r
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */ \r
+ \r
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ */ \r
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\r
+\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\r
+ \r
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\r
+\r
+#if defined(STM32F756xx)\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+ \r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\r
+#endif /* STM32F756xx */\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\r
+\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+ \r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode. \r
+ */\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)\r
+ \r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)\r
+\r
+#if defined(STM32F756xx)\r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)\r
+ \r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)\r
+#endif /* STM32F756xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */ \r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/*---------------------------------------------------------------------------------------------*/\r
+\r
+/** @brief Macro to configure the Timers clocks prescalers \r
+ * @param __PRESC__ : specifies the Timers clocks prescalers selection\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is \r
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2, \r
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to \r
+ * division by 4 or more. \r
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is \r
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, \r
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding \r
+ * to division by 8 or more.\r
+ */ \r
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\\r
+ RCC->DCKCFGR1 |= (__PRESC__);\\r
+ }while(0)\r
+\r
+/** @brief Macros to Enable or Disable the PLLISAI. \r
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. \r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))\r
+#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))\r
+\r
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.\r
+ * @note This function must be used only when the PLLSAI is disabled.\r
+ * @note PLLSAI clock source is common with the main PLL (configured in \r
+ * RCC_PLLConfig function )\r
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.\r
+ * This parameter must be a number between Min_Data = 49 and Max_Data = 432.\r
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO \r
+ * output frequency is between Min_Data = 49 and Max_Data = 432 MHz.\r
+ * @param __PLLSAIQ__: specifies the division factor for SAI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks\r
+ * This parameter can be a divider by 2, 4, 6 or 8.\r
+ */ \r
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))\r
+\r
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.\r
+ * @note This macro must be used only when the PLLI2S is disabled.\r
+ * @note PLLI2S clock source is common with the main PLL (configured in \r
+ * HAL_RCC_ClockConfig() API) \r
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.\r
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.\r
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO \r
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.\r
+ * @param __PLLI2SQ__: specifies the division factor for SAI clock.\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r
+ * @param __PLLI2SR__: specifies the division factor for I2S clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
+ * on the I2S clock frequency.\r
+ * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.\r
+ * This parameter can be a divider by 2, 4, 6 or 8. \r
+ */\r
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))\r
+ \r
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.\r
+ * @note This function must be called before enabling the PLLI2S. \r
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .\r
+ * This parameter must be a number between 1 and 32.\r
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ \r
+ */\r
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))\r
+\r
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.\r
+ * @note This function must be called before enabling the PLLSAI.\r
+ * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .\r
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.\r
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ \r
+ */\r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))\r
+\r
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.\r
+ * \r
+ * @note This function must be called before enabling the PLLSAI. \r
+ * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 16.\r
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ \r
+ */ \r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))\r
+\r
+/** @brief Macro to configure SAI1 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and \r
+ * the SAI clock.\r
+ * @param __SOURCE__: specifies the SAI1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI1 clock. \r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ */\r
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))\r
+\r
+/** @brief Macro to get the SAI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI1 clock. \r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ */\r
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))\r
+\r
+\r
+/** @brief Macro to configure SAI2 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and \r
+ * the SAI clock.\r
+ * @param __SOURCE__: specifies the SAI2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ */\r
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))\r
+\r
+\r
+/** @brief Macro to get the SAI2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r
+ * as SAI2 clock. \r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ */\r
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))\r
+\r
+\r
+/** @brief Enable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Disable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Clear the PLLSAI RDY interrupt pending bits.\r
+ */\r
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\r
+\r
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Check PLLSAI RDY flag is set or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\r
+\r
+/** @brief Macro to Get I2S clock source selection.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source\r
+ */\r
+#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))\r
+\r
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).\r
+ *\r
+ * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))\r
+\r
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).\r
+ *\r
+ * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))\r
+\r
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).\r
+ *\r
+ * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))\r
+\r
+/** @brief Macro to configure the I2C4 clock (I2C4CLK).\r
+ *\r
+ * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))\r
+\r
+/** @brief Macro to configure the USART1 clock (USART1CLK).\r
+ *\r
+ * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))\r
+\r
+/** @brief Macro to configure the USART2 clock (USART2CLK).\r
+ *\r
+ * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))\r
+\r
+/** @brief Macro to configure the USART3 clock (USART3CLK).\r
+ *\r
+ * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))\r
+\r
+ /** @brief Macro to configure the UART4 clock (UART4CLK).\r
+ *\r
+ * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))\r
+\r
+ /** @brief Macro to configure the UART5 clock (UART5CLK).\r
+ *\r
+ * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))\r
+\r
+ /** @brief Macro to configure the USART6 clock (USART6CLK).\r
+ *\r
+ * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))\r
+\r
+ /** @brief Macro to configure the UART7 clock (UART7CLK).\r
+ *\r
+ * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART7 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))\r
+\r
+/** @brief Macro to configure the UART8 clock (UART8CLK).\r
+ *\r
+ * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART8 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))\r
+\r
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).\r
+ *\r
+ * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the LPTIM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))\r
+\r
+/** @brief Macro to configure the CEC clock (CECCLK).\r
+ *\r
+ * @param __CEC_CLKSOURCE__: specifies the CEC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r
+ */\r
+#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))\r
+\r
+/** @brief macro to get the CEC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r
+ */\r
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))\r
+\r
+/** @brief Macro to configure the CLK48 source (CLK48CLK).\r
+ *\r
+ * @param __CLK48_SOURCE__: specifies the CLK48 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source\r
+ */\r
+#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))\r
+\r
+/** @brief macro to get the CLK48 source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source\r
+ */\r
+#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))\r
+\r
+/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).\r
+ *\r
+ * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock\r
+ */\r
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the SDMMC1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) \r
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))\r
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+\r
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))\r
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) \r
+\r
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_16))\r
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))\r
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))\r
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))\r
+\r
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))\r
+#define IS_RCC_USART1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r
+#define IS_RCC_USART3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART5CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART6CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART7CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART8CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r
+#define IS_RCC_I2C1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))\r
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))\r
+#define IS_RCC_I2C4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))\r
+#define IS_RCC_LPTIM1CLK(SOURCE) \\r
+ (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\r
+#define IS_RCC_CLK48SOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \\r
+ ((SOURCE) == RCC_CLK48SOURCE_PLL))\r
+#define IS_RCC_TIMPRES(VALUE) \\r
+ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\r
+ ((VALUE) == RCC_TIMPRES_ACTIVATED))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rng.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of RNG HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RNG_H\r
+#define __STM32F7xx_HAL_RNG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+ \r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RNG RNG\r
+ * @brief RNG HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup RNG_Exported_Types RNG Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */\r
+ HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */\r
+ HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ \r
+ HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */\r
+ HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */\r
+ \r
+}HAL_RNG_StateTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition \r
+ * @{\r
+ */ \r
+typedef struct\r
+{\r
+ RNG_TypeDef *Instance; /*!< Register base address */\r
+\r
+ uint32_t RandomNumber; /*!< Last Generated random number */ \r
+ \r
+ HAL_LockTypeDef Lock; /*!< RNG locking object */\r
+ \r
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */\r
+ \r
+}RNG_HandleTypeDef;\r
+\r
+/** \r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RNG_Exported_Constants RNG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition\r
+ * @{\r
+ */\r
+#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */\r
+#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */\r
+#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition\r
+ * @{\r
+ */\r
+#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */\r
+#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */\r
+#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup RNG_Exported_Macros RNG Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset RNG handle state\r
+ * @param __HANDLE__: RNG Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enables the RNG peripheral.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)\r
+\r
+/**\r
+ * @brief Disables the RNG peripheral.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)\r
+\r
+/**\r
+ * @brief Check the selected RNG flag status.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @param __FLAG__: RNG flag\r
+ * This parameter can be one of the following values:\r
+ * @arg RNG_FLAG_DRDY: Data ready \r
+ * @arg RNG_FLAG_CECS: Clock error current status\r
+ * @arg RNG_FLAG_SECS: Seed error current status \r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clears the selected RNG flag status.\r
+ * @param __HANDLE__: RNG handle\r
+ * @param __FLAG__: RNG flag to clear \r
+ * @note WARNING: This is a dummy macro for HAL code alignment,\r
+ * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */\r
+\r
+\r
+\r
+/**\r
+ * @brief Enables the RNG interrupts.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)\r
+ \r
+/**\r
+ * @brief Disables the RNG interrupts.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)\r
+\r
+/**\r
+ * @brief Checks whether the specified RNG interrupt has occurred or not.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RNG_IT_DRDY: Data ready interrupt \r
+ * @arg RNG_IT_CEI: Clock error interrupt\r
+ * @arg RNG_IT_SEI: Seed error interrupt\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) \r
+\r
+/**\r
+ * @brief Clear the RNG interrupt status flags.\r
+ * @param __HANDLE__: RNG Handle\r
+ * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.\r
+ * This parameter can be one of the following values: \r
+ * @arg RNG_IT_CEI: Clock error interrupt\r
+ * @arg RNG_IT_SEI: Seed error interrupt\r
+ * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. \r
+ * @retval None\r
+ */\r
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup RNG_Exported_Functions RNG Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */ \r
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);\r
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);\r
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);\r
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions\r
+ * @{\r
+ */\r
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */\r
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */\r
+\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);\r
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);\r
+\r
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);\r
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);\r
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions\r
+ * @{\r
+ */\r
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Types RNG Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Defines RNG Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Variables RNG Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Constants RNG Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Macros RNG Private Macros\r
+ * @{\r
+ */\r
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \\r
+ ((IT) == RNG_IT_SEI))\r
+\r
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \\r
+ ((FLAG) == RNG_FLAG_CECS) || \\r
+ ((FLAG) == RNG_FLAG_SECS))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup RNG_Private_Functions RNG Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#endif /* STM32F756xx || STM32F746xx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RNG_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of RTC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RTC_H\r
+#define __STM32F7xx_HAL_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RTC_Exported_Types RTC Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */\r
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */\r
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ \r
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ \r
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ \r
+ \r
+}HAL_RTCStateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Configuration Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */ \r
+\r
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ \r
+ \r
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ \r
+ \r
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. \r
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ \r
+ \r
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. \r
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ \r
+ \r
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. \r
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ \r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */\r
+\r
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r
+ \r
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r
+ \r
+ uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r
+\r
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */ \r
+ \r
+ uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.\r
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */\r
+ \r
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit \r
+ in CR register to store the operation.\r
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */\r
+}RTC_TimeTypeDef; \r
+ \r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t Date; /*!< Specifies the RTC Date.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */\r
+ \r
+ uint8_t Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */\r
+ \r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */\r
+ \r
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+ \r
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.\r
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ \r
+\r
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.\r
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint32_t Alarm; /*!< Specifies the alarm .\r
+ This parameter can be a value of @ref RTC_Alarms_Definitions */ \r
+}RTC_AlarmTypeDef;\r
+\r
+/** \r
+ * @brief RTC Handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ RTC_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ RTC_InitTypeDef Init; /*!< RTC required parameters */ \r
+ \r
+ HAL_LockTypeDef Lock; /*!< RTC locking object */\r
+ \r
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */\r
+ \r
+}RTC_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RTC_Exported_Constants RTC Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RTC_Hour_Formats RTC Hour Formats\r
+ * @{\r
+ */ \r
+#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)\r
+#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)\r
+#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT\r
+ * @{\r
+ */ \r
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)\r
+#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions\r
+ * @{\r
+ */ \r
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)\r
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions\r
+ * @{\r
+ */ \r
+#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions\r
+ * @{\r
+ */ \r
+#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)\r
+#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions\r
+ * @{\r
+ */ \r
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)\r
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions\r
+ * @{\r
+ */\r
+/* Coded in BCD format */\r
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)\r
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)\r
+#define RTC_MONTH_MARCH ((uint8_t)0x03)\r
+#define RTC_MONTH_APRIL ((uint8_t)0x04)\r
+#define RTC_MONTH_MAY ((uint8_t)0x05)\r
+#define RTC_MONTH_JUNE ((uint8_t)0x06)\r
+#define RTC_MONTH_JULY ((uint8_t)0x07)\r
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)\r
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)\r
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)\r
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)\r
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions\r
+ * @{\r
+ */ \r
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)\r
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)\r
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)\r
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)\r
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)\r
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)\r
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions\r
+ * @{\r
+ */ \r
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)\r
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions \r
+ * @{\r
+ */ \r
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)\r
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4\r
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3\r
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2\r
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1\r
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions \r
+ * @{\r
+ */ \r
+#define RTC_ALARM_A RTC_CR_ALRAE\r
+#define RTC_ALARM_B RTC_CR_ALRBE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions\r
+ * @{\r
+ */\r
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \r
+ There is no comparison on sub seconds \r
+ for Alarm */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \r
+ comparison. Only SS[0] is compared. */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \r
+ comparison. Only SS[1:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \r
+ comparison. Only SS[2:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \r
+ comparison. Only SS[3:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \r
+ comparison. Only SS[4:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \r
+ comparison. Only SS[5:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \r
+ comparison. Only SS[6:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \r
+ comparison. Only SS[7:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \r
+ comparison. Only SS[8:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \r
+ comparison. Only SS[9:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \r
+ comparison. Only SS[10:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \r
+ comparison.Only SS[11:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \r
+ comparison. Only SS[12:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \r
+ comparison.Only SS[13:0] are compared */\r
+#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \r
+ to activate alarm. */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)\r
+#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)\r
+#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)\r
+#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)\r
+#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)\r
+#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)\r
+#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)\r
+#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)\r
+#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)\r
+#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)\r
+#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)\r
+#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)\r
+#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)\r
+#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)\r
+#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)\r
+#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)\r
+#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)\r
+#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)\r
+#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)\r
+#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)\r
+#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)\r
+#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)\r
+#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RTC_Exported_Macros RTC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset RTC handle state\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)\r
+\r
+/**\r
+ * @brief Disable the write protection for RTC registers.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->WPR = 0xCA; \\r
+ (__HANDLE__)->Instance->WPR = 0x53; \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable the write protection for RTC registers.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->WPR = 0xFF; \\r
+ } while(0) \r
+ \r
+/**\r
+ * @brief Enable the RTC ALARMA peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))\r
+\r
+/**\r
+ * @brief Disable the RTC ALARMA peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))\r
+\r
+/**\r
+ * @brief Enable the RTC ALARMB peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))\r
+\r
+/**\r
+ * @brief Disable the RTC ALARMB peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))\r
+\r
+/**\r
+ * @brief Enable the RTC Alarm interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @retval None\r
+ */ \r
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the RTC Alarm interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt \r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)\r
+\r
+/**\r
+ * @brief Get the selected RTC Alarm's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Alarm Flag to check.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_ALRAF\r
+ * @arg RTC_FLAG_ALRBF\r
+ * @arg RTC_FLAG_ALRAWF \r
+ * @arg RTC_FLAG_ALRBWF \r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)\r
+\r
+/**\r
+ * @brief Clear the RTC Alarm's pending flags.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_ALRAF\r
+ * @arg RTC_FLAG_ALRBF \r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r
+ \r
+/**\r
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt\r
+ * @arg RTC_IT_ALRB: Alarm B interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r
+\r
+/**\r
+ * @brief Enable event on the RTC Alarm associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Disable event on the RTC Alarm associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r
+\r
+/**\r
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.\r
+ * @retval Line Status.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Clear the RTC Alarm associated Exti line flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RTC HAL Extension module */\r
+#include "stm32f7xx_hal_rtc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RTC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* RTC Time and Date functions ************************************************/\r
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTC_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* RTC Alarm functions ********************************************************/\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);\r
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);\r
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTC_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTC_Exported_Functions_Group5\r
+ * @{\r
+ */\r
+/* Peripheral State functions *************************************************/\r
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RTC_Private_Constants RTC Private Constants\r
+ * @{\r
+ */\r
+/* Masks Definition */\r
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
+\r
+#define RTC_TIMEOUT_VALUE 1000\r
+\r
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup RTC_Private_Macros RTC Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \\r
+ ((__FORMAT__) == RTC_HOURFORMAT_24))\r
+#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \\r
+ ((__POL__) == RTC_OUTPUT_POLARITY_LOW))\r
+#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \\r
+ ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))\r
+#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F) \r
+#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7FFF)\r
+#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))\r
+#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23)\r
+#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59)\r
+#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59)\r
+#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))\r
+#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \\r
+ ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \\r
+ ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))\r
+#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \\r
+ ((__OPERATION__) == RTC_STOREOPERATION_SET))\r
+#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))\r
+#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99)\r
+#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))\r
+#define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))\r
+#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \\r
+ ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \\r
+ ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))\r
+#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))\r
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)\r
+#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \\r
+ ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup RTC_Private_Functions RTC Private Functions\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);\r
+uint8_t RTC_ByteToBcd2(uint8_t Value);\r
+uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RTC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of RTC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RTC_EX_H\r
+#define __STM32F7xx_HAL_RTC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTCEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief RTC Tamper structure definition \r
+ */\r
+typedef struct \r
+{\r
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.\r
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */\r
+ \r
+ uint32_t Interrupt; /*!< Specifies the Tamper Interrupt.\r
+ This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ \r
+ \r
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.\r
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */\r
+ \r
+ uint32_t NoErase; /*!< Specifies the Tamper no erase mode.\r
+ This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */\r
+\r
+ uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.\r
+ This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */\r
+\r
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.\r
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */\r
+ \r
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.\r
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */\r
+ \r
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .\r
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ \r
+ \r
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .\r
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ \r
+ \r
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.\r
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ \r
+}RTC_TamperTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)\r
+#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)\r
+#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)\r
+#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions\r
+ * @{\r
+ */\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)\r
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)\r
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)\r
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)\r
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)\r
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)\r
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)\r
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)\r
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)\r
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)\r
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)\r
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)\r
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)\r
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)\r
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)\r
+#define RTC_BKP_DR20 ((uint32_t)0x00000014)\r
+#define RTC_BKP_DR21 ((uint32_t)0x00000015)\r
+#define RTC_BKP_DR22 ((uint32_t)0x00000016)\r
+#define RTC_BKP_DR23 ((uint32_t)0x00000017)\r
+#define RTC_BKP_DR24 ((uint32_t)0x00000018)\r
+#define RTC_BKP_DR25 ((uint32_t)0x00000019)\r
+#define RTC_BKP_DR26 ((uint32_t)0x0000001A)\r
+#define RTC_BKP_DR27 ((uint32_t)0x0000001B)\r
+#define RTC_BKP_DR28 ((uint32_t)0x0000001C)\r
+#define RTC_BKP_DR29 ((uint32_t)0x0000001D)\r
+#define RTC_BKP_DR30 ((uint32_t)0x0000001E)\r
+#define RTC_BKP_DR31 ((uint32_t)0x0000001F)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions \r
+ * @{\r
+ */ \r
+#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)\r
+#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E\r
+#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E\r
+#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions\r
+ * @{\r
+ */\r
+#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE\r
+#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE\r
+#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE\r
+#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection\r
+ * @{\r
+ */ \r
+#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)\r
+#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00000002)\r
+#define RTC_TIMESTAMPPIN_PC1 ((uint32_t)0x00000004)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)\r
+#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)\r
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE\r
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE \r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions\r
+* @{\r
+*/\r
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)\r
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions\r
+ * @{\r
+ */\r
+#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)\r
+#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */\r
+\r
+#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 \r
+ consecutive samples at the active level */\r
+#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 \r
+ consecutive samples at the active level */\r
+#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 \r
+ consecutive samples at the active leve. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions \r
+ * @{\r
+ */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 32768 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 16384 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 8192 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 4096 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 2048 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 1024 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 512 */\r
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 256 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before \r
+ sampling during 1 RTCCLK cycle */\r
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before \r
+ sampling during 2 RTCCLK cycles */\r
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before \r
+ sampling during 4 RTCCLK cycles */\r
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before \r
+ sampling during 8 RTCCLK cycles */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions\r
+ * @{\r
+ */ \r
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */\r
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions\r
+ * @{\r
+ */ \r
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */\r
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions \r
+ * @{\r
+ */ \r
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)\r
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)\r
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)\r
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)\r
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)\r
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration\r
+ period is 32s, else 2exp20 RTCCLK seconds */\r
+#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration \r
+ period is 16s, else 2exp19 RTCCLK seconds */\r
+#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration \r
+ period is 8s, else 2exp18 RTCCLK seconds */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \r
+ during a X -second window = Y - CALM[8:0] \r
+ with Y = 512, 256, 128 when X = 32, 16, 8 */\r
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited\r
+ during a 32-second window = CALM[8:0] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions\r
+ * @{\r
+ */ \r
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)\r
+#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions\r
+ * @{\r
+ */ \r
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) \r
+#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the RTC WakeUp Timer peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))\r
+\r
+/**\r
+ * @brief Disable the RTC WakeUp Timer peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))\r
+\r
+/**\r
+ * @brief Enable the RTC WakeUpTimer interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the RTC WakeUpTimer interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Get the selected RTC WakeUpTimer's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_WUTF\r
+ * @arg RTC_FLAG_WUTWF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Clear the RTC Wake Up timer's pending flags.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_WUTF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) \r
+\r
+/**\r
+ * @brief Enable the RTC Tamper1 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))\r
+\r
+/**\r
+ * @brief Disable the RTC Tamper1 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))\r
+\r
+/**\r
+ * @brief Enable the RTC Tamper2 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))\r
+\r
+/**\r
+ * @brief Disable the RTC Tamper2 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))\r
+\r
+/**\r
+ * @brief Enable the RTC Tamper3 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))\r
+\r
+/**\r
+ * @brief Disable the RTC Tamper3 input detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))\r
+\r
+/**\r
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_TAMP: All tampers interrupts\r
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt\r
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt\r
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \\r
+ ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \\r
+ (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))\r
+\r
+/**\r
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_TAMP: All tampers interrupts\r
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt\r
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt\r
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Get the selected RTC Tamper's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag\r
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag\r
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Clear the RTC Tamper's pending flags.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to clear.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag\r
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag\r
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r
+\r
+/**\r
+ * @brief Enable the RTC TimeStamp peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))\r
+\r
+/**\r
+ * @brief Disable the RTC TimeStamp peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))\r
+\r
+/**\r
+ * @brief Enable the RTC TimeStamp interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_TS: TimeStamp interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the RTC TimeStamp interrupt.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. \r
+ * This parameter can be:\r
+ * @arg RTC_IT_TS: TimeStamp interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_TS: TimeStamp interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.\r
+ * This parameter can be:\r
+ * @arg RTC_IT_TS: TimeStamp interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Get the selected RTC TimeStamp's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_TSF\r
+ * @arg RTC_FLAG_TSOVF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Clear the RTC Time Stamp's pending flags.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to clear.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_TSF\r
+ * @arg RTC_FLAG_TSOVF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r
+\r
+/**\r
+ * @brief Enable the RTC internal TimeStamp peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))\r
+\r
+/**\r
+ * @brief Disable the RTC internal TimeStamp peripheral.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))\r
+\r
+/**\r
+ * @brief Get the selected RTC Internal Time Stamp's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_ITSF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Clear the RTC Internal Time Stamp's pending flags.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_ITSF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r
+\r
+/**\r
+ * @brief Enable the RTC calibration output.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))\r
+\r
+/**\r
+ * @brief Disable the calibration output.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))\r
+\r
+/**\r
+ * @brief Enable the clock reference detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))\r
+\r
+/**\r
+ * @brief Disable the clock reference detection.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))\r
+\r
+/**\r
+ * @brief Get the selected RTC shift operation's flag status.\r
+ * @param __HANDLE__: specifies the RTC handle.\r
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.\r
+ * This parameter can be:\r
+ * @arg RTC_FLAG_SHPF\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r
+\r
+/**\r
+ * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r
+\r
+/**\r
+ * @brief Enable event on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Disable event on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r
+\r
+/**\r
+ * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r
+ * This parameter can be:\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.\r
+ * @retval Line Status.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Clear the RTC WakeUp Timer associated Exti line flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r
+\r
+/**\r
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r
+\r
+/**\r
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. \r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r
+\r
+/**\r
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r
+ * This parameter can be:\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.\r
+ * @retval Line Status.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r
+\r
+/**\r
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line\r
+ * @retval None.\r
+ */\r
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* RTC TimeStamp and Tamper functions *****************************************/\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);\r
+\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);\r
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);\r
+\r
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTCEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* RTC Wake-up functions ******************************************************/\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);\r
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);\r
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTCEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Extension Control functions ************************************************/\r
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);\r
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);\r
+\r
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);\r
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);\r
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);\r
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RTCEx_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Extension RTC features functions *******************************************/\r
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); \r
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r
+ * @{\r
+ */\r
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_RTC_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \\r
+ ((__OUTPUT__) == RTC_OUTPUT_ALARMA) || \\r
+ ((__OUTPUT__) == RTC_OUTPUT_ALARMB) || \\r
+ ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))\r
+#define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)\r
+#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \\r
+ ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))\r
+#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & (uint32_t)0xFFFFFFD6) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))\r
+#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)0xFFB6FFFB) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET))\r
+#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_PC13) || \\r
+ ((__PIN__) == RTC_TIMESTAMPPIN_PI8) || \\r
+ ((__PIN__) == RTC_TIMESTAMPPIN_PC1))\r
+#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \\r
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \\r
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \\r
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))\r
+#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \\r
+ ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))\r
+#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \\r
+ ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))\r
+#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \\r
+ ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \\r
+ ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \\r
+ ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))\r
+#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \\r
+ ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))\r
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \\r
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \\r
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \\r
+ ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))\r
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \\r
+ ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))\r
+#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \\r
+ ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))\r
+#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \\r
+ ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \\r
+ ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \\r
+ ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \\r
+ ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \\r
+ ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))\r
+\r
+#define IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFF)\r
+#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \\r
+ ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \\r
+ ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))\r
+#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \\r
+ ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))\r
+#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)\r
+#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \\r
+ ((__SEL__) == RTC_SHIFTADD1S_SET))\r
+#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)\r
+#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \\r
+ ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RTC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SAI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SAI_H\r
+#define __STM32F7xx_HAL_SAI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SAI\r
+ * @{\r
+ */ \r
+ \r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup SAI_Exported_Types SAI Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */\r
+ HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */\r
+ HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */\r
+ HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */ \r
+ HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */ \r
+ HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */\r
+ HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */ \r
+}HAL_SAI_StateTypeDef;\r
+\r
+/** \r
+ * @brief SAI Callback prototype \r
+ */\r
+typedef void (*SAIcallback)(void);\r
+\r
+/** \r
+ * @brief SAI Init Structure definition \r
+ */\r
+typedef struct\r
+{ \r
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. \r
+ This parameter can be a value of @ref SAI_Block_Mode */\r
+\r
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization\r
+ This parameter can be a value of @ref SAI_Block_Synchronization */\r
+ \r
+ uint32_t SynchroExt; /*!< Specifies SAI Block synchronization, this setup is common \r
+ for BLOCKA and BLOCKB\r
+ This parameter can be a value of @ref SAI_Block_SyncExt */\r
+\r
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.\r
+ This parameter can be a value of @ref SAI_Block_Output_Drive\r
+ @note this value has to be set before enabling the audio block \r
+ but after the audio block configuration. */\r
+\r
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.\r
+ This parameter can be a value of @ref SAI_Block_NoDivider\r
+ @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length \r
+ should be aligned to a number equal to a power of 2, from 8 to 256.\r
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can \r
+ take any of the values without constraint since the input clock of \r
+ the audio block should be equal to the bit clock.\r
+ There is no MCLK_x clock which can be output. */\r
+ \r
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.\r
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */\r
+\r
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. \r
+ This parameter can be a value of @ref SAI_Audio_Frequency */\r
+\r
+ uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for \r
+ AudioFrequency the user choice \r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15 */\r
+\r
+ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. \r
+ This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ \r
+ \r
+ uint32_t CompandingMode; /*!< Specifies the companding mode type. \r
+ This parameter can be a value of @ref SAI_Block_Companding_Mode */\r
+ \r
+ uint32_t TriState; /*!< Specifies the companding mode type. \r
+ This parameter can be a value of @ref SAI_TRIState_Management */\r
+ \r
+ /* This part of the structure is automatically filled if your are using the high level initialisation \r
+ function HAL_SAI_InitProtocol */\r
+\r
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.\r
+ This parameter can be a value of @ref SAI_Block_Protocol */\r
+ \r
+ uint32_t DataSize; /*!< Specifies the SAI Block data size.\r
+ This parameter can be a value of @ref SAI_Block_Data_Size */\r
+\r
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */\r
+\r
+ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.\r
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */ \r
+}SAI_InitTypeDef;\r
+\r
+/** \r
+ * @brief SAI Block Frame Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+\r
+ uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.\r
+ This parameter must be a number between Min_Data = 8 and Max_Data = 256.\r
+ @note: If master clock MCLK_x pin is declared as an output, the frame length\r
+ should be aligned to a number equal to power of 2 in order to keep \r
+ in an audio frame, an integer number of MCLK pulses by bit Clock. */ \r
+ \r
+ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.\r
+ This Parameter specifies the length in number of bit clock (SCK + 1) \r
+ of the active level of FS signal in audio frame.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r
+ \r
+ uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.\r
+ This parameter can be a value of @ref SAI_Block_FS_Definition */\r
+ \r
+ uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.\r
+ This parameter can be a value of @ref SAI_Block_FS_Polarity */\r
+\r
+ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.\r
+ This parameter can be a value of @ref SAI_Block_FS_Offset */\r
+\r
+}SAI_FrameInitTypeDef;\r
+\r
+/**\r
+ * @brief SAI Block Slot Init Structure definition\r
+ */ \r
+\r
+typedef struct\r
+{\r
+ uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 24 */\r
+\r
+ uint32_t SlotSize; /*!< Specifies the Slot Size.\r
+ This parameter can be a value of @ref SAI_Block_Slot_Size */\r
+\r
+ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.\r
+ This parameter can be a value of @ref SAI_Block_Slot_Active */\r
+}SAI_SlotInitTypeDef;\r
+\r
+/** \r
+ * @brief SAI handle Structure definition \r
+ */\r
+typedef struct __SAI_HandleTypeDef\r
+{\r
+ SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */\r
+\r
+ SAI_InitTypeDef Init; /*!< SAI communication parameters */\r
+\r
+ SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */\r
+\r
+ SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */\r
+\r
+ uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */\r
+\r
+ uint16_t XferSize; /*!< SAI transfer size */\r
+\r
+ uint16_t XferCount; /*!< SAI transfer counter */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */\r
+\r
+ SAIcallback mutecallback;/*!< SAI mute callback */\r
+ \r
+ void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< SAI locking object */\r
+\r
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< SAI Error code */\r
+}SAI_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Exported_Constants SAI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAI_Error_Code SAI Error Code \r
+ * @{\r
+ */\r
+#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */\r
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */\r
+#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004) /*!< Anticipated Frame synchronisation detection */\r
+#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008) /*!< Late Frame synchronisation detection */\r
+#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010) /*!< codec not ready */\r
+#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020) /*!< Wrong clock configuration */ \r
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040) /*!< Timeout error */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation\r
+ * @{\r
+ */\r
+#define SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000)\r
+#define SAI_SYNCEXT_IN_ENABLE ((uint32_t)0x00000001)\r
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000002)\r
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000004)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Protocol SAI Supported protocol\r
+ * @{\r
+ */\r
+#define SAI_I2S_STANDARD ((uint32_t)0x00000000)\r
+#define SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001)\r
+#define SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002)\r
+#define SAI_PCM_LONG ((uint32_t)0x00000004)\r
+#define SAI_PCM_SHORT ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size\r
+ * @{\r
+ */\r
+#define SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000)\r
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001)\r
+#define SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002)\r
+#define SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Clock_Source SAI Clock Source\r
+ * @{\r
+ */\r
+#define SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000)\r
+#define SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000)\r
+#define SAI_CLKSOURCE_EXT ((uint32_t)0x00200000)\r
+#define SAI_CLKSOURCE_NA ((uint32_t)0x00400000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency\r
+ * @{\r
+ */\r
+#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)\r
+#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)\r
+#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)\r
+#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)\r
+#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)\r
+#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)\r
+#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)\r
+#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)\r
+#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)\r
+#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Mode SAI Block Mode\r
+ * @{\r
+ */\r
+#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)\r
+#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)\r
+#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)\r
+#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Protocol SAI Block Protocol\r
+ * @{\r
+ */\r
+#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)\r
+#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)\r
+#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size\r
+ * @{\r
+ */\r
+#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)\r
+#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r
+#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)\r
+#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))\r
+#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))\r
+#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission \r
+ * @{\r
+ */\r
+#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)\r
+#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing\r
+ * @{\r
+ */\r
+#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)\r
+#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)SAI_xCR1_CKSTR)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization\r
+ * @{\r
+ */\r
+#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)\r
+#define SAI_SYNCHRONOUS ((uint32_t)SAI_xCR1_SYNCEN_0)\r
+#define SAI_SYNCHRONOUS_EXT ((uint32_t)SAI_xCR1_SYNCEN_1) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive \r
+ * @{\r
+ */\r
+#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000)\r
+#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider\r
+ * @{\r
+ */\r
+#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000)\r
+#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition\r
+ * @{\r
+ */\r
+#define SAI_FS_STARTFRAME ((uint32_t)0x00000000)\r
+#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity \r
+ * @{\r
+ */\r
+#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)\r
+#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset \r
+ * @{\r
+ */\r
+#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000)\r
+#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+ /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size\r
+ * @{\r
+ */\r
+#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000) \r
+#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)\r
+#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active\r
+ * @{\r
+ */\r
+#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)\r
+#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000)\r
+#define SAI_SLOTACTIVE_1 ((uint32_t)0x00020000)\r
+#define SAI_SLOTACTIVE_2 ((uint32_t)0x00040000)\r
+#define SAI_SLOTACTIVE_3 ((uint32_t)0x00080000)\r
+#define SAI_SLOTACTIVE_4 ((uint32_t)0x00100000)\r
+#define SAI_SLOTACTIVE_5 ((uint32_t)0x00200000)\r
+#define SAI_SLOTACTIVE_6 ((uint32_t)0x00400000)\r
+#define SAI_SLOTACTIVE_7 ((uint32_t)0x00800000)\r
+#define SAI_SLOTACTIVE_8 ((uint32_t)0x01000000)\r
+#define SAI_SLOTACTIVE_9 ((uint32_t)0x02000000)\r
+#define SAI_SLOTACTIVE_10 ((uint32_t)0x04000000)\r
+#define SAI_SLOTACTIVE_11 ((uint32_t)0x08000000)\r
+#define SAI_SLOTACTIVE_12 ((uint32_t)0x10000000)\r
+#define SAI_SLOTACTIVE_13 ((uint32_t)0x20000000)\r
+#define SAI_SLOTACTIVE_14 ((uint32_t)0x40000000)\r
+#define SAI_SLOTACTIVE_15 ((uint32_t)0x80000000)\r
+#define SAI_SLOTACTIVE_ALL ((uint32_t)0xFFFF0000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode\r
+ * @{\r
+ */\r
+#define SAI_STEREOMODE ((uint32_t)0x00000000)\r
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_TRIState_Management SAI TRIState Management\r
+ * @{\r
+ */\r
+#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)\r
+#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold \r
+ * @{\r
+ */\r
+#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)\r
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0)\r
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1) \r
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))\r
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode\r
+ * @{\r
+ */\r
+#define SAI_NOCOMPANDING ((uint32_t)0x00000000)\r
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1)\r
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))\r
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))\r
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value\r
+ * @{\r
+ */\r
+#define SAI_ZERO_VALUE ((uint32_t)0x00000000)\r
+#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition\r
+ * @{\r
+ */\r
+#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)\r
+#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)\r
+#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)\r
+#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)\r
+#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)\r
+#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)\r
+#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition\r
+ * @{\r
+ */\r
+#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)\r
+#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)\r
+#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)\r
+#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)\r
+#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)\r
+#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)\r
+#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level\r
+ * @{\r
+ */\r
+#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000)\r
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000)\r
+#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000)\r
+#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000) \r
+#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000)\r
+#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Exported_Macros SAI Exported Macros\r
+ * @brief macros to handle interrupts and specific configurations\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset SAI handle state\r
+ * @param __HANDLE__: specifies the SAI Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)\r
+\r
+/** @brief Enable or disable the specified SAI interrupts.\r
+ * @param __HANDLE__: specifies the SAI Handle.\r
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable \r
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable \r
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable \r
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable \r
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable \r
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable \r
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl\r
+ * @retval None\r
+ */\r
+ \r
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))\r
+ \r
+/** @brief Check if the specified SAI interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: specifies the SAI Handle.\r
+ * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.\r
+ * @param __INTERRUPT__: specifies the SAI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SAI_IT_TXE: Tx buffer empty interrupt enable.\r
+ * @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.\r
+ * @arg SAI_IT_ERR: Error interrupt enable.\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified SAI flag is set or not.\r
+ * @param __HANDLE__: specifies the SAI Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.\r
+ * @arg SAI_FLAG_MUTEDET: Mute detection flag.\r
+ * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.\r
+ * @arg SAI_FLAG_FREQ: FIFO request flag.\r
+ * @arg SAI_FLAG_CNRDY: Codec not ready flag.\r
+ * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.\r
+ * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. \r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the specified SAI pending flag.\r
+ * @param __HANDLE__: specifies the SAI Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun \r
+ * @arg SAI_FLAG_MUTEDET: Clear Mute detection \r
+ * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration \r
+ * @arg SAI_FLAG_FREQ: Clear FIFO request \r
+ * @arg SAI_FLAG_CNRDY: Clear Codec not ready\r
+ * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection\r
+ * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection\r
+ * \r
+ * @retval None\r
+ */\r
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) \r
+\r
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)\r
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)\r
+ \r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC SAI Extension module */\r
+#include "stm32f7xx_hal_sai_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup SAI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions **********************************/\r
+/** @addtogroup SAI_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); \r
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);\r
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* I/O operation functions *****************************************************/\r
+/** @addtogroup SAI_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);\r
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);\r
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);\r
+\r
+/* Abort function */\r
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);\r
+\r
+/* Mute management */\r
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);\r
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);\r
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);\r
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);\r
+\r
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);\r
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SAI_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions **************************************************/\r
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);\r
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Types SAI Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Variables SAI Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Constants SAI Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup SAI_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\\r
+ ((STATE) == SAI_SYNCEXT_IN_ENABLE) ||\\r
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\\r
+ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))\r
+\r
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\\r
+ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\\r
+ ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\\r
+ ((PROTOCOL) == SAI_PCM_LONG) ||\\r
+ ((PROTOCOL) == SAI_PCM_SHORT))\r
+\r
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\\r
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\\r
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\\r
+ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))\r
+\r
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\\r
+ ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\\r
+ ((SOURCE) == SAI_CLKSOURCE_EXT))\r
+\r
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \\r
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \\r
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \\r
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \\r
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))\r
+\r
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \\r
+ ((MODE) == SAI_MODEMASTER_RX) || \\r
+ ((MODE) == SAI_MODESLAVE_TX) || \\r
+ ((MODE) == SAI_MODESLAVE_RX))\r
+\r
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \\r
+ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \\r
+ ((PROTOCOL) == SAI_SPDIF_PROTOCOL))\r
+\r
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \\r
+ ((DATASIZE) == SAI_DATASIZE_10) || \\r
+ ((DATASIZE) == SAI_DATASIZE_16) || \\r
+ ((DATASIZE) == SAI_DATASIZE_20) || \\r
+ ((DATASIZE) == SAI_DATASIZE_24) || \\r
+ ((DATASIZE) == SAI_DATASIZE_32))\r
+\r
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \\r
+ ((BIT) == SAI_FIRSTBIT_LSB))\r
+\r
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \\r
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))\r
+\r
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \\r
+ ((SYNCHRO) == SAI_SYNCHRONOUS) || \\r
+ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT))\r
+\r
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \\r
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))\r
+\r
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \\r
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) \r
+ \r
+#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \\r
+ ((STATUS) == SAI_FIFOSTATUS_HALFFULL) || \\r
+ ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL) || \\r
+ ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL) || \\r
+ ((STATUS) == SAI_FIFOSTATUS_FULL) || \\r
+ ((STATUS) == SAI_FIFOSTATUS_EMPTY))\r
+\r
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)\r
+\r
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \\r
+ ((VALUE) == SAI_LAST_SENT_VALUE)) \r
+\r
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \\r
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \\r
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \\r
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \\r
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING)) \r
+\r
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \\r
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \\r
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \\r
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \\r
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) \r
+\r
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\\r
+ ((STATE) == SAI_OUTPUT_RELEASED)) \r
+\r
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\\r
+ ((MODE) == SAI_STEREOMODE)) \r
+\r
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((((ACTIVE) >> 16 ) > 0) && (((ACTIVE) >> 16 ) <= (SAI_SLOTACTIVE_ALL >> 16)))\r
+\r
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) \r
+\r
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \\r
+ ((SIZE) == SAI_SLOTSIZE_16B) || \\r
+ ((SIZE) == SAI_SLOTSIZE_32B))\r
+\r
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) \r
+\r
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \\r
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))\r
+\r
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \\r
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH)) \r
+\r
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \\r
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) \r
+ \r
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) \r
+\r
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) \r
+\r
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Functions SAI Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SAI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SAI Extension HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SAI_EX_H\r
+#define __STM32F7xx_HAL_SAI_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SAIEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SAIEx_Exported_Functions SAI Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SAIEx_Exported_Functions_Group1 SAI Extended Functions Group1\r
+ * @{\r
+ */\r
+\r
+/* Extended features functions ************************************************/\r
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); \r
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SAI_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sd.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SD_H\r
+#define __STM32F7xx_HAL_SD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_sdmmc.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SD SD\r
+ * @brief SD HAL module driver\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup SD_Exported_Types SD Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition \r
+ * @{\r
+ */\r
+#define SD_InitTypeDef SDMMC_InitTypeDef \r
+#define SD_TypeDef SDMMC_TypeDef\r
+\r
+typedef struct\r
+{\r
+ SD_TypeDef *Instance; /*!< SDMMC register base address */\r
+ \r
+ SD_InitTypeDef Init; /*!< SD required parameters */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< SD locking object */\r
+ \r
+ uint32_t CardType; /*!< SD card type */\r
+ \r
+ uint32_t RCA; /*!< SD relative card address */\r
+ \r
+ uint32_t CSD[4]; /*!< SD card specific data table */\r
+ \r
+ uint32_t CID[4]; /*!< SD card identification number table */\r
+ \r
+ __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */\r
+ \r
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */\r
+ \r
+ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */\r
+ \r
+ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */\r
+ \r
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */\r
+ \r
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */\r
+ \r
+}SD_HandleTypeDef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register \r
+ * @{\r
+ */ \r
+typedef struct\r
+{\r
+ __IO uint8_t CSDStruct; /*!< CSD structure */\r
+ __IO uint8_t SysSpecVersion; /*!< System specification version */\r
+ __IO uint8_t Reserved1; /*!< Reserved */\r
+ __IO uint8_t TAAC; /*!< Data read access time 1 */\r
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */\r
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */\r
+ __IO uint16_t CardComdClasses; /*!< Card command classes */\r
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */\r
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */\r
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */\r
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */\r
+ __IO uint8_t DSRImpl; /*!< DSR implemented */\r
+ __IO uint8_t Reserved2; /*!< Reserved */\r
+ __IO uint32_t DeviceSize; /*!< Device Size */\r
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */\r
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */\r
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */\r
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */\r
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */\r
+ __IO uint8_t EraseGrSize; /*!< Erase group size */\r
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */\r
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */\r
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */\r
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */\r
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */\r
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */\r
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */\r
+ __IO uint8_t Reserved3; /*!< Reserved */\r
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */\r
+ __IO uint8_t FileFormatGrouop; /*!< File format group */\r
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */\r
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */\r
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */\r
+ __IO uint8_t FileFormat; /*!< File format */\r
+ __IO uint8_t ECC; /*!< ECC code */\r
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */\r
+ __IO uint8_t Reserved4; /*!< Always 1 */\r
+\r
+}HAL_SD_CSDTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */\r
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */\r
+ __IO uint32_t ProdName1; /*!< Product Name part1 */\r
+ __IO uint8_t ProdName2; /*!< Product Name part2 */\r
+ __IO uint8_t ProdRev; /*!< Product Revision */\r
+ __IO uint32_t ProdSN; /*!< Product Serial Number */\r
+ __IO uint8_t Reserved1; /*!< Reserved1 */\r
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */\r
+ __IO uint8_t CID_CRC; /*!< CID CRC */\r
+ __IO uint8_t Reserved2; /*!< Always 1 */\r
+\r
+}HAL_SD_CIDTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */\r
+ __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */\r
+ __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */\r
+ __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */\r
+ __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */\r
+ __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */\r
+ __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */\r
+ __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */\r
+ __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */\r
+ __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */\r
+\r
+}HAL_SD_CardStatusTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */\r
+ HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */\r
+ uint64_t CardCapacity; /*!< Card capacity */\r
+ uint32_t CardBlockSize; /*!< Card block size */\r
+ uint16_t RCA; /*!< SD relative card address */\r
+ uint8_t CardType; /*!< SD card type */\r
+\r
+}HAL_SD_CardInfoTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+/** \r
+ * @brief SD specific error defines \r
+ */ \r
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */\r
+ SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */\r
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */\r
+ SD_DATA_TIMEOUT = (4), /*!< Data timeout */\r
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */\r
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */\r
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */\r
+ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */\r
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */\r
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */\r
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */\r
+ SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */\r
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */\r
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */\r
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */\r
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */\r
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */\r
+ SD_CC_ERROR = (18), /*!< Internal card controller error */\r
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */\r
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */\r
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */\r
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */\r
+ SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */\r
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */\r
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */\r
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */\r
+ SD_INVALID_VOLTRANGE = (27),\r
+ SD_ADDR_OUT_OF_RANGE = (28),\r
+ SD_SWITCH_ERROR = (29),\r
+ SD_SDMMC_DISABLED = (30),\r
+ SD_SDMMC_FUNCTION_BUSY = (31),\r
+ SD_SDMMC_FUNCTION_FAILED = (32),\r
+ SD_SDMMC_UNKNOWN_FUNCTION = (33),\r
+\r
+/** \r
+ * @brief Standard error defines \r
+ */ \r
+ SD_INTERNAL_ERROR = (34),\r
+ SD_NOT_CONFIGURED = (35),\r
+ SD_REQUEST_PENDING = (36),\r
+ SD_REQUEST_NOT_APPLICABLE = (37),\r
+ SD_INVALID_PARAMETER = (38),\r
+ SD_UNSUPPORTED_FEATURE = (39),\r
+ SD_UNSUPPORTED_HW = (40),\r
+ SD_ERROR = (41),\r
+ SD_OK = (0) \r
+\r
+}HAL_SD_ErrorTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure\r
+ * @{\r
+ */ \r
+typedef enum\r
+{\r
+ SD_TRANSFER_OK = 0, /*!< Transfer success */\r
+ SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */\r
+ SD_TRANSFER_ERROR = 2 /*!< Transfer failed */\r
+\r
+}HAL_SD_TransferStateTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure\r
+ * @{\r
+ */ \r
+typedef enum\r
+{\r
+ SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */\r
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */\r
+ SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */\r
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ \r
+ SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */\r
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */\r
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */\r
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */\r
+ SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */\r
+\r
+}HAL_SD_CardStateTypedef;\r
+/** \r
+ * @}\r
+ */\r
+\r
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure\r
+ * @{\r
+ */ \r
+typedef enum\r
+{\r
+ SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */\r
+ SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */\r
+ SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */\r
+ SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */\r
+\r
+}HAL_SD_OperationTypedef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SD_Exported_Constants SD Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SD Commands Index \r
+ */\r
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */\r
+#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */\r
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */\r
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */\r
+#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */\r
+#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \r
+ operating condition register (OCR) content in the response on the CMD line. */\r
+#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */\r
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */\r
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \r
+ and asks the card whether card supports voltage. */\r
+#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */\r
+#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */\r
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */\r
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */\r
+#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */\r
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) \r
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */\r
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands \r
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective \r
+ for SDHS and SDXC. */\r
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r
+ fixed 512 bytes in case of SDHC and SDXC. */\r
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by \r
+ STOP_TRANSMISSION command. */\r
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */\r
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */\r
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */\r
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r
+ fixed 512 bytes in case of SDHC and SDXC. */\r
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */\r
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */\r
+#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */\r
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */\r
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */\r
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */\r
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */\r
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */\r
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command \r
+ system set by switch function command (CMD6). */\r
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. \r
+ Reserved for each command system set by switch function command (CMD6). */\r
+#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */\r
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */\r
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */\r
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \r
+ the SET_BLOCK_LEN command. */\r
+#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather \r
+ than a standard command. */\r
+#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card \r
+ for general purpose/application specific commands. */\r
+#define SD_CMD_NO_CMD ((uint8_t)64) \r
+\r
+/** \r
+ * @brief Following commands are SD Card Specific commands.\r
+ * SDMMC_APP_CMD should be sent before sending these commands. \r
+ */\r
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \r
+ widths are given in SCR register. */\r
+#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */\r
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \r
+ 32bit+CRC data block. */\r
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \r
+ send its operating condition register (OCR) content in the response on the CMD line. */\r
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */\r
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */\r
+#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */\r
+#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */\r
+\r
+/** \r
+ * @brief Following commands are SD Card Specific security commands.\r
+ * SD_CMD_APP_CMD should be sent before sending these commands. \r
+ */\r
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */\r
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */\r
+\r
+/** \r
+ * @brief Supported SD Memory Cards \r
+ */\r
+#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)\r
+#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)\r
+#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)\r
+#define MULTIMEDIA_CARD ((uint32_t)0x00000003)\r
+#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)\r
+#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)\r
+#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)\r
+#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup SD_Exported_macros SD Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enable the SD device.\r
+ * @retval None\r
+ */ \r
+#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)\r
+\r
+/**\r
+ * @brief Disable the SD device.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)\r
+\r
+/**\r
+ * @brief Enable the SDMMC DMA transfer.\r
+ * @retval None\r
+ */ \r
+#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)\r
+\r
+/**\r
+ * @brief Disable the SDMMC DMA transfer.\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)\r
+ \r
+/**\r
+ * @brief Enable the SD device interrupt.\r
+ * @param __HANDLE__: SD Handle \r
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the SD device interrupt.\r
+ * @param __HANDLE__: SD Handle \r
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt \r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Check whether the specified SD flag is set or not. \r
+ * @param __HANDLE__: SD Handle \r
+ * @param __FLAG__: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDACT: Command transfer in progress\r
+ * @arg SDMMC_FLAG_TXACT: Data transmit in progress\r
+ * @arg SDMMC_FLAG_RXACT: Data receive in progress\r
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full\r
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full\r
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty\r
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty\r
+ * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO\r
+ * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO\r
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @retval The new state of SD FLAG (SET or RESET).\r
+ */\r
+#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear the SD's pending flags.\r
+ * @param __HANDLE__: SD Handle \r
+ * @param __FLAG__: specifies the flag to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))\r
+\r
+/**\r
+ * @brief Check whether the specified SD interrupt has occurred or not.\r
+ * @param __HANDLE__: SD Handle \r
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @retval The new state of SD IT (SET or RESET).\r
+ */\r
+#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clear the SD's interrupt pending bits.\r
+ * @param __HANDLE__ : SD Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SD_Exported_Functions SD Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);\r
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);\r
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);\r
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions\r
+ * @{\r
+ */\r
+/* Blocking mode: Polling */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);\r
+\r
+/* Callback in non blocking modes (DMA) */\r
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);\r
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);\r
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);\r
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);\r
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Peripheral State functions ************************************************/\r
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\r
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);\r
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup SD_Private_Types SD Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SD_Private_Defines SD Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Variables SD Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Constants SD Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup SD_Private_Macros SD Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Functions SD Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_SD_H */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sdram.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SDRAM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SDRAM_H\r
+#define __STM32F7xx_HAL_SDRAM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_fmc.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDRAM\r
+ * @{\r
+ */ \r
+\r
+/* Exported typedef ----------------------------------------------------------*/ \r
+\r
+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL SDRAM State structure definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */\r
+ HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */\r
+ HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */\r
+ HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */\r
+ HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */\r
+ HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */\r
+ \r
+}HAL_SDRAM_StateTypeDef;\r
+\r
+/** \r
+ * @brief SDRAM handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ FMC_SDRAM_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */\r
+ \r
+ __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< SDRAM locking object */ \r
+\r
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */\r
+ \r
+}SDRAM_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SDRAM handle state\r
+ * @param __HANDLE__: specifies the SDRAM handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDRAM_Exported_Functions_Group1 \r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions *********************************/\r
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);\r
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);\r
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);\r
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);\r
+\r
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);\r
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);\r
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SDRAM_Exported_Functions_Group2 \r
+ * @{\r
+ */\r
+/* I/O operation functions ****************************************************/\r
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+\r
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup SDRAM_Exported_Functions_Group3 \r
+ * @{\r
+ */\r
+/* SDRAM Control functions *****************************************************/\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);\r
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);\r
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);\r
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SDRAM_Exported_Functions_Group4 \r
+ * @{\r
+ */\r
+/* SDRAM State functions ********************************************************/\r
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SDRAM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SMARTCARD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SMARTCARD_H\r
+#define __STM32F7xx_HAL_SMARTCARD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SMARTCARD\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SMARTCARD Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.\r
+ The baud rate register is computed using the following formula:\r
+ Baud Rate Register = ((PCLKx) / ((hsc->Init.BaudRate))) */\r
+ \r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits. \r
+ Only 1.5 stop bits are authorized in SmartCard mode. */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref SMARTCARD_Parity\r
+ @note The parity is enabled by default (PCE is forced to 1).\r
+ Since the WordLength is forced to 8 bits + parity, M is\r
+ forced to 1 and the parity bit is the 9th bit. */\r
+ \r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref SMARTCARD_Mode */\r
+\r
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */\r
+\r
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */\r
+\r
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */\r
+ \r
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
+ Selecting the single sample method increases the receiver tolerance to clock\r
+ deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */\r
+\r
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler */\r
+ \r
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time */\r
+ \r
+ uint32_t NACKState; /*!< Specifies whether the SmartCard NACK transmission is enabled\r
+ in case of parity error.\r
+ This parameter can be a value of @ref SmartCard_NACK_State */ \r
+ \r
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. \r
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/\r
+ \r
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: \r
+ it is used to implement the Character Wait Time (CWT) and \r
+ Block Wait Time (BWT). It is coded over 24 bits. */ \r
+ \r
+ uint32_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.\r
+ This parameter can be any value from 0x0 to 0xFF */ \r
+ \r
+ uint32_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in\r
+ receive and transmit mode). When set to 0, retransmission is \r
+ disabled. Otherwise, its maximum value is 7 (before signalling\r
+ an error) */ \r
+\r
+}SMARTCARD_InitTypeDef;\r
+\r
+/** \r
+ * @brief SMARTCARD advanced features initalization structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several\r
+ advanced features may be initialized at the same time. This parameter \r
+ can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */\r
+\r
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.\r
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */\r
+\r
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.\r
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */\r
+\r
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic\r
+ vs negative/inverted logic).\r
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */\r
+\r
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. \r
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */\r
+\r
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. \r
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */\r
+\r
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. \r
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */\r
+\r
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. \r
+ This parameter can be a value of @ref SMARTCARD_MSB_First */\r
+}SMARTCARD_AdvFeatureInitTypeDef;\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */\r
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ \r
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */\r
+}HAL_SMARTCARD_StateTypeDef;\r
+\r
+\r
+/**\r
+ * @brief SMARTCARD clock sources definition\r
+ */\r
+typedef enum\r
+{\r
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */\r
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */\r
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */\r
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */\r
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */\r
+}SMARTCARD_ClockSourceTypeDef;\r
+\r
+/** \r
+ * @brief SMARTCARD handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ USART_TypeDef *Instance; /* USART registers base address */\r
+\r
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */\r
+\r
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /* SmartCard advanced features initialization parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /* SmartCard Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /* SmartCard Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /* Locking object */\r
+\r
+ __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */\r
+\r
+ __IO uint32_t ErrorCode; /* SmartCard Error code */\r
+\r
+}SMARTCARD_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants\r
+ * @{\r
+ */\r
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code\r
+ * @brief SMARTCARD Error Code \r
+ * @{\r
+ */ \r
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */\r
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */\r
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */\r
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */\r
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */\r
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */\r
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length\r
+ * @{\r
+ */\r
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits\r
+ * @{\r
+ */\r
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity\r
+ * @{\r
+ */\r
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Mode SMARTCARD Mode\r
+ * @{\r
+ */\r
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity\r
+ * @{\r
+ */\r
+#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000)\r
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase\r
+ * @{\r
+ */\r
+#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000)\r
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit\r
+ * @{\r
+ */\r
+#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000)\r
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling\r
+ * @{\r
+ */\r
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000)\r
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SmartCard_NACK_State SMARTCARD NACK State\r
+ * @{\r
+ */\r
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)\r
+#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable\r
+ * @{\r
+ */\r
+#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SmartCard_DMA_Requests SMARTCARD DMA requests\r
+ * @{\r
+ */\r
+\r
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)\r
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)\r
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)\r
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)\r
+#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)\r
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)\r
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)\r
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First\r
+ * @{\r
+ */\r
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)\r
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SmartCard_Flags SMARTCARD Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)\r
+#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)\r
+#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)\r
+#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)\r
+#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)\r
+#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)\r
+#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)\r
+#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)\r
+#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)\r
+#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)\r
+#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)\r
+#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+ \r
+#define SMARTCARD_IT_PE ((uint16_t)0x0028)\r
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727)\r
+#define SMARTCARD_IT_TC ((uint16_t)0x0626)\r
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)\r
+\r
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060)\r
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300)\r
+#define SMARTCARD_IT_NE ((uint16_t)0x0200)\r
+#define SMARTCARD_IT_FE ((uint16_t)0x0100)\r
+\r
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)\r
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags\r
+ * @{\r
+ */\r
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ \r
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ \r
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ \r
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ \r
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ \r
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ \r
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters\r
+ * @{\r
+ */ \r
+#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ \r
+#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS\r
+ * @{\r
+ */\r
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS\r
+ * @{\r
+ */\r
+#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS\r
+ * @{\r
+ */\r
+#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask\r
+ * @{\r
+ */ \r
+#define SMARTCARD_IT_MASK ((uint16_t)0x001F) \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SMARTCARD handle state\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)\r
+\r
+/** @brief Flush the Smartcard DR register \r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))\r
+\r
+/** @brief Checks whether the specified Smartcard flag is set or not.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag\r
+ * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag\r
+ * @arg SMARTCARD_FLAG_BUSY: Busy flag\r
+ * @arg SMARTCARD_FLAG_EOBF: End of block flag \r
+ * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag\r
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag\r
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag\r
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg SMARTCARD_FLAG_ORE: OverRun Error flag\r
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag\r
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag\r
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Enables the specified SmartCard interrupt.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt\r
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt\r
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r
+/** @brief Disables the specified SmartCard interrupt.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt\r
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt\r
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r
+\r
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT__: specifies the SMARTCARD interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt \r
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt\r
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg SMARTCARD_IT_ORE: OverRun Error interrupt\r
+ * @arg SMARTCARD_IT_NE: Noise Error interrupt\r
+ * @arg SMARTCARD_IT_FE: Framing Error interrupt\r
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) \r
+\r
+/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r
+ * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt \r
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt\r
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg SMARTCARD_IT_ORE: OverRun Error interrupt\r
+ * @arg SMARTCARD_IT_NE: Noise Error interrupt\r
+ * @arg SMARTCARD_IT_FE: Framing Error interrupt\r
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\r
+ (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))\r
+\r
+\r
+/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag\r
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag\r
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag\r
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r
+ * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag\r
+ * @arg USART_CLEAR_EOBF: End Of Block Clear Flag \r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) \r
+\r
+/** @brief Set a specific SMARTCARD request flag.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __REQ__: specifies the request flag to set\r
+ * This parameter can be one of the following values: \r
+ * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r
+ * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r
+ *\r
+ * @retval None\r
+ */ \r
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) \r
+\r
+/** @brief Enable the USART associated to the SMARTCARD Handle\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable the USART associated to the SMARTCARD Handle\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @retval None\r
+ */\r
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/** @brief Macros to enable or disable the SmartCard DMA request.\r
+ * @param __HANDLE__: specifies the SMARTCARD Handle.\r
+ * The Handle Instance which can be USART1 or USART2.\r
+ * @param __REQUEST__: specifies the SmartCard DMA request.\r
+ * This parameter can be one of the following values:\r
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request\r
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request\r
+ */\r
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))\r
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include SMARTCARD HAL Extension module */\r
+#include "stm32f7xx_hal_smartcard_ex.h"\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SMARTCARD_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup SMARTCARD_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions **********************************/\r
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);\r
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);\r
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);\r
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SMARTCARD_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);\r
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);\r
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);\r
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SMARTCARD_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions **************************************************/\r
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);\r
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) \r
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)\r
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \\r
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))\r
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))\r
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))\r
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))\r
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \\r
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))\r
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \\r
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))\r
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \\r
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))\r
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \\r
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))\r
+#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \\r
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \\r
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \\r
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \\r
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \\r
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\r
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) \r
+#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \\r
+ ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))\r
+#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \\r
+ ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))\r
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \\r
+ ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))\r
+#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \\r
+ ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))\r
+#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \\r
+ ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))\r
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
+ ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))\r
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)\r
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)\r
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)\r
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)\r
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \\r
+ ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))\r
+#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \\r
+ ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST)) \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SMARTCARD_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SMARTCARD HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SMARTCARD_EX_H\r
+#define __STM32F7xx_HAL_SMARTCARD_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SMARTCARDEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+ \r
+/** @brief Reports the SMARTCARD clock source.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @param __CLOCKSOURCE__ : output variable \r
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/* Initialization and de-initialization functions ****************************/\r
+/* IO operation functions *****************************************************/\r
+/* Peripheral Control functions ***********************************************/\r
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);\r
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r
+\r
+/* Peripheral State and Error functions ***************************************/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spdifrx.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SPDIFRX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SPDIFRX_H\r
+#define __STM32F7xx_HAL_SPDIFRX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPDIFRX\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SPDIFRX Init structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t InputSelection; /*!< Specifies the SPDIF input selection.\r
+ This parameter can be a value of @ref SPDIFRX_Input_Selection */\r
+\r
+ uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.\r
+ This parameter can be a value of @ref SPDIFRX_Max_Retries */\r
+\r
+ uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.\r
+ This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */\r
+\r
+ uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.\r
+ This parameter can be a value of @ref SPDIFRX_Channel_Selection */\r
+\r
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).\r
+ This parameter can be a value of @ref SPDIFRX_Data_Format */\r
+ \r
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.\r
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r
+\r
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */\r
+\r
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r
+ \r
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_V_Mask */ \r
+ \r
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */\r
+ \r
+}SPDIFRX_InitTypeDef;\r
+\r
+/** \r
+ * @brief SPDIFRX SetDataFormat structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).\r
+ This parameter can be a value of @ref SPDIFRX_Data_Format */\r
+ \r
+ uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.\r
+ This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r
+\r
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */\r
+\r
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r
+ \r
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_V_Mask */ \r
+ \r
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.\r
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */\r
+ \r
+}SPDIFRX_SetDataFormatTypeDef;\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */\r
+ HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */\r
+ HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */ \r
+ HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */ \r
+ HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */ \r
+ HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */ \r
+}HAL_SPDIFRX_StateTypeDef;\r
+\r
+/** \r
+ * @brief SPDIFRX handle Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */\r
+\r
+ SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */\r
+ \r
+ uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */\r
+ \r
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */\r
+ \r
+ __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */\r
+ \r
+ __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter \r
+ (This field is initialized at the \r
+ same value as transfer size at the \r
+ beginning of the transfer and \r
+ decremented when a sample is received. \r
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */\r
+ \r
+ __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */\r
+ \r
+ __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter \r
+ (This field is initialized at the \r
+ same value as transfer size at the \r
+ beginning of the transfer and \r
+ decremented when a sample is received. \r
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */\r
+ \r
+ DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */\r
+ \r
+ __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */\r
+ \r
+ __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */\r
+\r
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */\r
+\r
+}SPDIFRX_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code\r
+ * @{\r
+ */ \r
+#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ \r
+#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */\r
+#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */\r
+#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */\r
+#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection\r
+ * @{\r
+ */\r
+#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000)\r
+#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000) \r
+#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000)\r
+#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries\r
+ * @{\r
+ */\r
+#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000)\r
+#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000) \r
+#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000)\r
+#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity\r
+ * @{\r
+ */\r
+#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000)\r
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask\r
+* @{\r
+*/\r
+#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000)\r
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask\r
+* @{\r
+*/\r
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */\r
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask\r
+* @{\r
+*/\r
+#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000)\r
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask\r
+* @{\r
+*/\r
+#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000)\r
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection\r
+ * @{\r
+ */\r
+#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000)\r
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format\r
+ * @{\r
+ */\r
+#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000)\r
+#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010)\r
+#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode\r
+ * @{\r
+ */\r
+#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000)\r
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPDIFRX_State SPDIFRX State\r
+ * @{\r
+ */\r
+\r
+#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC)\r
+#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)\r
+#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition\r
+ * @{\r
+ */\r
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)\r
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)\r
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)\r
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)\r
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)\r
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)\r
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition\r
+ * @{\r
+ */\r
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)\r
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)\r
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)\r
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)\r
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)\r
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)\r
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)\r
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)\r
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SPDIFRX handle state\r
+ * @param __HANDLE__: SPDIFRX handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)\r
+\r
+/** @brief Disable the specified SPDIFRX peripheral (IDLE State).\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)\r
+\r
+/** @brief Enable the specified SPDIFRX peripheral (SYNC State).\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)\r
+\r
+\r
+/** @brief Enable the specified SPDIFRX peripheral (RCV State).\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle. \r
+ * @retval None\r
+ */\r
+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)\r
+\r
+\r
+/** @brief Enable or disable the specified SPDIFRX interrupts.\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle.\r
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPDIFRX_IT_RXNE\r
+ * @arg SPDIFRX_IT_CSRNE\r
+ * @arg SPDIFRX_IT_PERRIE\r
+ * @arg SPDIFRX_IT_OVRIE\r
+ * @arg SPDIFRX_IT_SBLKIE\r
+ * @arg SPDIFRX_IT_SYNCDIE\r
+ * @arg SPDIFRX_IT_IFEIE\r
+ * @retval None\r
+ */ \r
+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))\r
+ \r
+/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle.\r
+ * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPDIFRX_IT_RXNE\r
+ * @arg SPDIFRX_IT_CSRNE\r
+ * @arg SPDIFRX_IT_PERRIE\r
+ * @arg SPDIFRX_IT_OVRIE\r
+ * @arg SPDIFRX_IT_SBLKIE\r
+ * @arg SPDIFRX_IT_SYNCDIE\r
+ * @arg SPDIFRX_IT_IFEIE\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Checks whether the specified SPDIFRX flag is set or not.\r
+ * @param __HANDLE__: specifies the SPDIFRX Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPDIFRX_FLAG_RXNE\r
+ * @arg SPDIFRX_FLAG_CSRNE\r
+ * @arg SPDIFRX_FLAG_PERR\r
+ * @arg SPDIFRX_FLAG_OVR\r
+ * @arg SPDIFRX_FLAG_SBD\r
+ * @arg SPDIFRX_FLAG_SYNCD \r
+ * @arg SPDIFRX_FLAG_FERR \r
+ * @arg SPDIFRX_FLAG_SERR \r
+ * @arg SPDIFRX_FLAG_TERR \r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg SPDIFRX_FLAG_PERR\r
+ * @arg SPDIFRX_FLAG_OVR\r
+ * @arg SPDIFRX_SR_SBD\r
+ * @arg SPDIFRX_SR_SYNCD\r
+ * @retval None\r
+ */\r
+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) \r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SPDIFRX_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup SPDIFRX_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions **********************************/\r
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);\r
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);\r
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPDIFRX_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ***************************************************/\r
+ /* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r
+\r
+ /* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);\r
+\r
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r
+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r
+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPDIFRX_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral Control and State functions ************************************/\r
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);\r
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros\r
+ * @{\r
+ */\r
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \\r
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \\r
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \\r
+ ((INPUT) == SPDIFRX_INPUT_IN0))\r
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \\r
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \\r
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \\r
+ ((RET) == SPDIFRX_MAXRETRIES_63))\r
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \\r
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))\r
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \\r
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))\r
+#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \\r
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))\r
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \\r
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))\r
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \\r
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))\r
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \\r
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \\r
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))\r
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \\r
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))\r
+ \r
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \\r
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))\r
+/** \r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_SPDIFRX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spi.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SPI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SPI_H\r
+#define __STM32F7xx_HAL_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Types SPI Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SPI Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_Mode */\r
+\r
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.\r
+ This parameter can be a value of @ref SPI_Direction */\r
+\r
+ uint32_t DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_Data_Size */\r
+\r
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+\r
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .\r
+ This parameter can be a value of @ref SPI_TI_mode */\r
+\r
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.\r
+ This parameter can be a value of @ref SPI_CRC_Calculation */\r
+\r
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */\r
+\r
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.\r
+ CRC Length is only used with Data8 and Data16, not other data size\r
+ This parameter can be a value of @ref SPI_CRC_length */\r
+\r
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .\r
+ This parameter can be a value of @ref SPI_NSSP_Mode\r
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and\r
+ it takes effect only if the SPI interface is configured as Motorola SPI\r
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r
+ CPOL setting is ignored).. */\r
+} SPI_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */\r
+ HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */\r
+ HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */\r
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing*/\r
+ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */\r
+}HAL_SPI_StateTypeDef;\r
+\r
+/**\r
+ * @brief SPI handle Structure definition\r
+ */\r
+typedef struct __SPI_HandleTypeDef\r
+{\r
+ SPI_TypeDef *Instance; /* SPI registers base address */\r
+\r
+ SPI_InitTypeDef Init; /* SPI communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /* SPI Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /* SPI Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */\r
+\r
+ uint32_t CRCSize; /* SPI CRC size used for the transfer */\r
+\r
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */\r
+\r
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /* Locking object */\r
+\r
+ HAL_SPI_StateTypeDef State; /* SPI communication state */\r
+\r
+ uint32_t ErrorCode; /* SPI Error code */\r
+\r
+}SPI_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants SPI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Error_Code SPI Error Code\r
+ * @{\r
+ */\r
+#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */\r
+#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */\r
+#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */\r
+#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */\r
+#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */\r
+#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */\r
+#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */\r
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknow Error error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SPI_Mode SPI Mode\r
+ * @{\r
+ */\r
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)\r
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Direction SPI Direction Mode\r
+ * @{\r
+ */\r
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)\r
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY\r
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Data_Size SPI Data Size\r
+ * @{\r
+ */\r
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300)\r
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400)\r
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500)\r
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600)\r
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700)\r
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800)\r
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900)\r
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)\r
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)\r
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)\r
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)\r
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)\r
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r
+ * @{\r
+ */\r
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000)\r
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase SPI Clock Phase\r
+ * @{\r
+ */\r
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)\r
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management\r
+ * @{\r
+ */\r
+#define SPI_NSS_SOFT SPI_CR1_SSM\r
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)\r
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r
+ * @{\r
+ */\r
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP\r
+#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r
+ * @{\r
+ */\r
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)\r
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)\r
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)\r
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)\r
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)\r
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)\r
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)\r
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission\r
+ * @{\r
+ */\r
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)\r
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_TI_mode SPI TI mode\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)\r
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r
+ * @{\r
+ */\r
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)\r
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_length SPI CRC Length\r
+ * @{\r
+ * This parameter can be one of the following values:\r
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit\r
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit\r
+ */\r
+#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)\r
+#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)\r
+#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r
+ * @{\r
+ * This parameter can be one of the following values:\r
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r
+ * RXNE event is generated if the FIFO\r
+ * level is greater or equal to 1/2(16-bits).\r
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r
+ * level is greater or equal to 1/4(8 bits). */\r
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition\r
+ * @brief SPI Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define SPI_IT_TXE SPI_CR2_TXEIE\r
+#define SPI_IT_RXNE SPI_CR2_RXNEIE\r
+#define SPI_IT_ERR SPI_CR2_ERRIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SPI_Flag_definition SPI Flag definition\r
+ * @brief Flag definition\r
+ * Elements values convention: 0xXXXXYYYY\r
+ * - XXXX : Flag register Index\r
+ * - YYYY : Flag mask\r
+ * @{\r
+ */\r
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */\r
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */\r
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */\r
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */\r
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */\r
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */\r
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */\r
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */\r
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r
+ * @{\r
+ */\r
+#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)\r
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)\r
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)\r
+#define SPI_FTLVL_FULL ((uint32_t)0x1800)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r
+ * @{\r
+ */\r
+#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)\r
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)\r
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)\r
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Macros SPI Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SPI handle state\r
+ * @param __HANDLE__: SPI handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r
+\r
+/** @brief Enables or disables the specified SPI interrupts.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg SPI_IT_ERR: Error interrupt enable\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))\r
+\r
+/** @brief Checks if the specified SPI interrupt source is enabled or disabled.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __INTERRUPT__ : specifies the SPI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg SPI_IT_ERR: Error interrupt enable\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Checks whether the specified SPI flag is set or not.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __FLAG__ : specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
+ * @arg SPI_FLAG_CRCERR: CRC error flag\r
+ * @arg SPI_FLAG_MODF: Mode fault flag\r
+ * @arg SPI_FLAG_OVR: Overrun flag\r
+ * @arg SPI_FLAG_BSY: Busy flag\r
+ * @arg SPI_FLAG_FRE: Frame format error flag\r
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the SPI CRCERR pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r
+\r
+/** @brief Clears the SPI MODF pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Clears the SPI OVR pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->DR; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Clears the SPI FRE pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Enables the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)\r
+\r
+/** @brief Disables the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Macros SPI Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Sets the SPI transmit-only mode.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)\r
+\r
+/** @brief Sets the SPI receive-only mode.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))\r
+\r
+/** @brief Resets the CRC calculation of the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\\r
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)\r
+\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \\r
+ ((MODE) == SPI_MODE_MASTER))\r
+\r
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \\r
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\\r
+ ((MODE) == SPI_DIRECTION_1LINE))\r
+\r
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)\r
+\r
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \\r
+ ((MODE) == SPI_DIRECTION_1LINE))\r
+\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_4BIT))\r
+\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \\r
+ ((CPOL) == SPI_POLARITY_HIGH))\r
+\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \\r
+ ((CPHA) == SPI_PHASE_2EDGE))\r
+\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \\r
+ ((NSS) == SPI_NSS_HARD_INPUT) || \\r
+ ((NSS) == SPI_NSS_HARD_OUTPUT))\r
+\r
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \\r
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))\r
+\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\r
+\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\r
+ ((BIT) == SPI_FIRSTBIT_LSB))\r
+\r
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \\r
+ ((MODE) == SPI_TIMODE_ENABLE))\r
+\r
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \\r
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))\r
+\r
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\\r
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \\r
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SPI_Exported_Functions SPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions \r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r
+\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions \r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sram.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SRAM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SRAM_H\r
+#define __STM32F7xx_HAL_SRAM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_fmc.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @addtogroup SRAM\r
+ * @{\r
+ */ \r
+\r
+/* Exported typedef ----------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Types SRAM Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief HAL SRAM State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */\r
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */\r
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */\r
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */\r
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */\r
+ \r
+}HAL_SRAM_StateTypeDef;\r
+\r
+/** \r
+ * @brief SRAM handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ \r
+ \r
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */\r
+ \r
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */ \r
+ \r
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */\r
+ \r
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */\r
+ \r
+}SRAM_HandleTypeDef; \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SRAM handle state\r
+ * @param __HANDLE__: SRAM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);\r
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);\r
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions\r
+ * @{\r
+ */\r
+\r
+/* I/O operation functions ***************************************************/\r
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+\r
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions\r
+ * @{\r
+ */\r
+\r
+/* SRAM Control functions ****************************************************/\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+\r
+/* SRAM State functions ******************************************************/\r
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SRAM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of TIM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_TIM_H\r
+#define __STM32F7xx_HAL_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Types TIM Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief TIM Time base Configuration Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_ClockDivision */\r
+\r
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. \r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_Base_InitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Output Compare Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+ \r
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.\r
+ This parameter can be a value of @ref TIM_Output_Fast_State\r
+ @note This parameter is valid only in PWM1 and PWM2 mode. */\r
+\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_OC_InitTypeDef; \r
+\r
+/** \r
+ * @brief TIM One Pulse Mode Configuration Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
+} TIM_OnePulse_InitTypeDef; \r
+\r
+\r
+/** \r
+ * @brief TIM Input Capture Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_IC_InitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Encoder Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Encoder_Mode */\r
+ \r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+ \r
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC2Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_Encoder_InitTypeDef;\r
+\r
+/** \r
+ * @brief Clock Configuration Handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t ClockSource; /*!< TIM clock sources. \r
+ This parameter can be a value of @ref TIM_Clock_Source */ \r
+ uint32_t ClockPolarity; /*!< TIM clock polarity. \r
+ This parameter can be a value of @ref TIM_Clock_Polarity */\r
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler. \r
+ This parameter can be a value of @ref TIM_Clock_Prescaler */\r
+ uint32_t ClockFilter; /*!< TIM clock filter. \r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+}TIM_ClockConfigTypeDef;\r
+\r
+/** \r
+ * @brief Clear Input Configuration Handle Structure definition \r
+ */ \r
+typedef struct\r
+{ \r
+ uint32_t ClearInputState; /*!< TIM clear Input state. \r
+ This parameter can be ENABLE or DISABLE */ \r
+ uint32_t ClearInputSource; /*!< TIM clear Input sources. \r
+ This parameter can be a value of @ref TIMEx_ClearInput_Source */ \r
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. \r
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. \r
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */\r
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter. \r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+}TIM_ClearInputConfigTypeDef;\r
+\r
+/** \r
+ * @brief TIM Slave configuration Structure definition \r
+ */ \r
+typedef struct {\r
+ uint32_t SlaveMode; /*!< Slave mode selection \r
+ This parameter can be a value of @ref TIMEx_Slave_Mode */ \r
+ uint32_t InputTrigger; /*!< Input Trigger source \r
+ This parameter can be a value of @ref TIM_Trigger_Selection */\r
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity \r
+ This parameter can be a value of @ref TIM_Trigger_Polarity */\r
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler \r
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
+ uint32_t TriggerFilter; /*!< Input trigger filter \r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
+\r
+}TIM_SlaveConfigTypeDef;\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */\r
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */\r
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */\r
+}HAL_TIM_StateTypeDef;\r
+\r
+/** \r
+ * @brief HAL Active channel structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */\r
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */\r
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */\r
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */\r
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */\r
+}HAL_TIM_ActiveChannel;\r
+\r
+/** \r
+ * @brief TIM Time Base Handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ TIM_TypeDef *Instance; /*!< Register base address */\r
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */\r
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */\r
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array\r
+ This array is accessed by a @ref DMA_Handle_index */\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */\r
+}TIM_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity\r
+ * @{\r
+ */\r
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
+ * @{\r
+ */\r
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */\r
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */\r
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */\r
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */\r
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
+ * @{\r
+ */\r
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)\r
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR\r
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0\r
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1\r
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClockDivision TIM Clock Division\r
+ * @{\r
+ */\r
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)\r
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)\r
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)\r
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State \r
+ * @{\r
+ */\r
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)\r
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)\r
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity \r
+ * @{\r
+ */\r
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)\r
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)\r
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)\r
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)\r
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity \r
+ * @{\r
+ */\r
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING\r
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING\r
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
+ * @{\r
+ */\r
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively */\r
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */\r
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */\r
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */\r
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
+ * @{\r
+ */\r
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)\r
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
+ * @{\r
+ */\r
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)\r
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)\r
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Interrupt_definition TIM Interrupt definition\r
+ * @{\r
+ */ \r
+#define TIM_IT_UPDATE (TIM_DIER_UIE)\r
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)\r
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)\r
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)\r
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)\r
+#define TIM_IT_COM (TIM_DIER_COMIE)\r
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)\r
+#define TIM_IT_BREAK (TIM_DIER_BIE)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Commutation_Source TIM Commutation Source \r
+ * @{\r
+ */ \r
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)\r
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_sources TIM DMA sources\r
+ * @{\r
+ */\r
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)\r
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)\r
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)\r
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)\r
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)\r
+#define TIM_DMA_COM (TIM_DIER_COMDE)\r
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Event_Source TIM Event Source \r
+ * @{\r
+ */\r
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG \r
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G\r
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G\r
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G\r
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G\r
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG\r
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG \r
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG \r
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Flag_definition TIM Flag definition\r
+ * @{\r
+ */\r
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)\r
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)\r
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)\r
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)\r
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)\r
+#define TIM_FLAG_COM (TIM_SR_COMIF)\r
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)\r
+#define TIM_FLAG_BREAK (TIM_SR_BIF)\r
+#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)\r
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)\r
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)\r
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)\r
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Source TIM Clock Source\r
+ * @{\r
+ */\r
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) \r
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) \r
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)\r
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)\r
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)\r
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)\r
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)\r
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)\r
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)\r
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ \r
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ \r
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ \r
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ \r
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ \r
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r
+ * @{\r
+ */ \r
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)\r
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r
+ * @{\r
+ */\r
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)\r
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Lock_level TIM Lock level\r
+ * @{\r
+ */\r
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)\r
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)\r
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)\r
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State\r
+ * @{\r
+ */ \r
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)\r
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Break_Polarity TIM Break Polarity \r
+ * @{\r
+ */\r
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)\r
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State\r
+ * @{\r
+ */\r
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)\r
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
+ * @{\r
+ */ \r
+#define TIM_TRGO_RESET ((uint32_t)0x0000) \r
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) \r
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) \r
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) \r
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) \r
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) \r
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) \r
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode\r
+ * @{\r
+ */\r
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)\r
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
+ * @{\r
+ */\r
+#define TIM_TS_ITR0 ((uint32_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint32_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint32_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint32_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)\r
+#define TIM_TS_ETRF ((uint32_t)0x0070)\r
+#define TIM_TS_NONE ((uint32_t)0xFFFF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ \r
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ \r
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup TIM_TI1_Selection TIM TI1 Selection\r
+ * @{\r
+ */\r
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)\r
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address TIM DMA Base address\r
+ * @{\r
+ */\r
+#define TIM_DMABASE_CR1 (0x00000000)\r
+#define TIM_DMABASE_CR2 (0x00000001)\r
+#define TIM_DMABASE_SMCR (0x00000002)\r
+#define TIM_DMABASE_DIER (0x00000003)\r
+#define TIM_DMABASE_SR (0x00000004)\r
+#define TIM_DMABASE_EGR (0x00000005)\r
+#define TIM_DMABASE_CCMR1 (0x00000006)\r
+#define TIM_DMABASE_CCMR2 (0x00000007)\r
+#define TIM_DMABASE_CCER (0x00000008)\r
+#define TIM_DMABASE_CNT (0x00000009)\r
+#define TIM_DMABASE_PSC (0x0000000A)\r
+#define TIM_DMABASE_ARR (0x0000000B)\r
+#define TIM_DMABASE_RCR (0x0000000C)\r
+#define TIM_DMABASE_CCR1 (0x0000000D)\r
+#define TIM_DMABASE_CCR2 (0x0000000E)\r
+#define TIM_DMABASE_CCR3 (0x0000000F)\r
+#define TIM_DMABASE_CCR4 (0x00000010)\r
+#define TIM_DMABASE_BDTR (0x00000011)\r
+#define TIM_DMABASE_DCR (0x00000012)\r
+#define TIM_DMABASE_OR (0x00000013)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length \r
+ * @{\r
+ */\r
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)\r
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)\r
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)\r
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)\r
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)\r
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)\r
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)\r
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)\r
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)\r
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)\r
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)\r
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)\r
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)\r
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)\r
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)\r
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)\r
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)\r
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Handle_index DMA Handle index\r
+ * @{\r
+ */\r
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */\r
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */\r
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Channel_CC_State Channel CC State\r
+ * @{\r
+ */\r
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)\r
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)\r
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)\r
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
+ * @{\r
+ */\r
+/** @brief Reset TIM handle state\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enable the TIM peripheral.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
+\r
+/**\r
+ * @brief Enable the TIM update source request.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))\r
+\r
+/**\r
+ * @brief Enable the TIM main Output.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
+\r
+\r
+/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
+ channels have been disabled */\r
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
+\r
+/**\r
+ * @brief Disable the TIM peripheral.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\r
+ { \\r
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+ \r
+/**\r
+ * @brief Disable the TIM update source request.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))\r
+\r
+\r
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN\r
+ channels have been disabled */\r
+/**\r
+ * @brief Disable the TIM main Output.\r
+ * @param __HANDLE__: TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\r
+ { \\r
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
+\r
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
+#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
+\r
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))\r
+\r
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
+\r
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\\r
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))\r
+\r
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))\r
+ \r
+/**\r
+ * @brief Sets the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __COUNTER__: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
+\r
+/**\r
+ * @brief Gets the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)\r
+\r
+/**\r
+ * @brief Sets the TIM Autoreload Register value on runtime without calling \r
+ * another time any Init function.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __AUTORELOAD__: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \\r
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \\r
+ } while(0)\r
+/**\r
+ * @brief Gets the TIM Autoreload Register value on runtime\r
+ * @param __HANDLE__: TIM handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)\r
+\r
+/**\r
+ * @brief Sets the TIM Clock Division value on runtime without calling \r
+ * another time any Init function. \r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CKD__: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CLOCKDIVISION_DIV1\r
+ * @arg TIM_CLOCKDIVISION_DIV2\r
+ * @arg TIM_CLOCKDIVISION_DIV4\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \\r
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \\r
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \\r
+ } while(0)\r
+/**\r
+ * @brief Gets the TIM Clock Division value on runtime\r
+ * @param __HANDLE__: TIM handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
+\r
+/**\r
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling \r
+ * another time HAL_TIM_IC_ConfigChannel() function.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CHANNEL__ : TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+ do{ \\r
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Gets the TIM Input Capture prescaler on runtime\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CHANNEL__ : TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)\r
+ \r
+/**\r
+ * @brief Sets the TIM Capture x input polarity on runtime.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CHANNEL__: TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __POLARITY__: Polarity for TIx source \r
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. \r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+ do{ \\r
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
+ }while(0)\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include TIM HAL Extension module */\r
+#include "stm32f7xx_hal_tim_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIM_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Time Base functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Timer Output Compare functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Timer PWM functions *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Timer Input Capture functions ***********************************************/\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group5\r
+ * @{\r
+ */\r
+/* Timer One Pulse functions ***************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group6\r
+ * @{\r
+ */\r
+/* Timer Encoder functions *****************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
+ /* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group7\r
+ * @{\r
+ */\r
+/* Interrupt Handler functions **********************************************/\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group8\r
+ * @{\r
+ */\r
+/* Control functions *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); \r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group9\r
+ * @{\r
+ */\r
+/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group10\r
+ * @{\r
+ */\r
+/* Peripheral State functions **************************************************/\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Macros TIM Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
+\r
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
+\r
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
+ ((__STATE__) == TIM_OCFAST_ENABLE))\r
+\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))\r
+\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \\r
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))\r
+\r
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))\r
+\r
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r
+\r
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
+\r
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
+\r
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
+\r
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI12)) \r
+\r
+#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))\r
+\r
+\r
+#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \\r
+ ((__IT__) == TIM_IT_CC1) || \\r
+ ((__IT__) == TIM_IT_CC2) || \\r
+ ((__IT__) == TIM_IT_CC3) || \\r
+ ((__IT__) == TIM_IT_CC4) || \\r
+ ((__IT__) == TIM_IT_COM) || \\r
+ ((__IT__) == TIM_IT_TRIGGER) || \\r
+ ((__IT__) == TIM_IT_BREAK))\r
+\r
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))\r
+\r
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))\r
+\r
+#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \\r
+ ((__FLAG__) == TIM_FLAG_CC1) || \\r
+ ((__FLAG__) == TIM_FLAG_CC2) || \\r
+ ((__FLAG__) == TIM_FLAG_CC3) || \\r
+ ((__FLAG__) == TIM_FLAG_CC4) || \\r
+ ((__FLAG__) == TIM_FLAG_COM) || \\r
+ ((__FLAG__) == TIM_FLAG_TRIGGER) || \\r
+ ((__FLAG__) == TIM_FLAG_BREAK) || \\r
+ ((__FLAG__) == TIM_FLAG_BREAK2) || \\r
+ ((__FLAG__) == TIM_FLAG_CC1OF) || \\r
+ ((__FLAG__) == TIM_FLAG_CC2OF) || \\r
+ ((__FLAG__) == TIM_FLAG_CC3OF) || \\r
+ ((__FLAG__) == TIM_FLAG_CC4OF))\r
+\r
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
+\r
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) \r
+\r
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) \r
+\r
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
+\r
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) \r
+\r
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSR_DISABLE))\r
+\r
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSI_DISABLE))\r
+\r
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_3)) \r
+\r
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \\r
+ ((__STATE__) == TIM_BREAK_DISABLE))\r
+\r
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r
+\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r
+\r
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC4REF))\r
+\r
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
+ ((__SELECTION__) == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_NONE))\r
+\r
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))\r
+\r
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) \r
+\r
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) \r
+\r
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
+\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CR2) || \\r
+ ((__BASE__) == TIM_DMABASE_SMCR) || \\r
+ ((__BASE__) == TIM_DMABASE_DIER) || \\r
+ ((__BASE__) == TIM_DMABASE_SR) || \\r
+ ((__BASE__) == TIM_DMABASE_EGR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCER) || \\r
+ ((__BASE__) == TIM_DMABASE_CNT) || \\r
+ ((__BASE__) == TIM_DMABASE_PSC) || \\r
+ ((__BASE__) == TIM_DMABASE_ARR) || \\r
+ ((__BASE__) == TIM_DMABASE_RCR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR4) || \\r
+ ((__BASE__) == TIM_DMABASE_BDTR) || \\r
+ ((__BASE__) == TIM_DMABASE_DCR) || \\r
+ ((__BASE__) == TIM_DMABASE_OR))\r
+\r
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
+\r
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);\r
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_TIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of TIM HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_TIM_EX_H\r
+#define __STM32F7xx_HAL_TIM_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup TIMEx_Exported_Types TIM Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief TIM Hall sensor Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ \r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+ \r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+ \r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ \r
+} TIM_HallSensor_InitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Master configuration Structure definition \r
+ */ \r
+typedef struct {\r
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection. \r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */ \r
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection \r
+ This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */\r
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection. \r
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
+}TIM_MasterConfigTypeDef;\r
+\r
+/** \r
+ * @brief TIM Break input(s) and Dead time configuration Structure definition \r
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable \r
+ * filter and polarity.\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.\r
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.\r
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+ uint32_t LockLevel; /*!< TIM Lock level.\r
+ This parameter can be a value of @ref TIM_Lock_level */ \r
+ uint32_t DeadTime; /*!< TIM dead Time.\r
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+ uint32_t BreakState; /*!< TIM Break State.\r
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.\r
+ This parameter can be a value of @ref TIM_Break_Polarity */\r
+ uint32_t BreakFilter; /*!< Specifies the break input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
+ uint32_t Break2State; /*!< TIM Break2 State \r
+ This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */\r
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity \r
+ This parameter can be a value of @ref TIMEx_Break2_Polarity */\r
+ uint32_t Break2Filter; /*!< TIM break2 input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ \r
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ \r
+} TIM_BreakDeadTimeConfigTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Constants TIM Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup TIMEx_Channel TIM Channel\r
+ * @{\r
+ */\r
+\r
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)\r
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)\r
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)\r
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)\r
+#define TIM_CHANNEL_5 ((uint32_t)0x0010)\r
+#define TIM_CHANNEL_6 ((uint32_t)0x0014)\r
+#define TIM_CHANNEL_ALL ((uint32_t)0x003C)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes\r
+ * @{\r
+ */\r
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)\r
+#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)\r
+#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)\r
+#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r
+#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)\r
+#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r
+#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)\r
+#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)\r
+\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)\r
+#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)\r
+#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)\r
+#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)\r
+#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Remap TIM Remap\r
+ * @{\r
+ */\r
+#define TIM_TIM2_TIM8_TRGO (0x00000000)\r
+#define TIM_TIM2_ETH_PTP (0x00000400)\r
+#define TIM_TIM2_USBFS_SOF (0x00000800)\r
+#define TIM_TIM2_USBHS_SOF (0x00000C00)\r
+#define TIM_TIM5_GPIO (0x00000000)\r
+#define TIM_TIM5_LSI (0x00000040)\r
+#define TIM_TIM5_LSE (0x00000080)\r
+#define TIM_TIM5_RTC (0x000000C0)\r
+#define TIM_TIM11_GPIO (0x00000000)\r
+#define TIM_TIM11_SPDIFRX (0x00000001)\r
+#define TIM_TIM11_HSE (0x00000002)\r
+#define TIM_TIM11_MCO1 (0x00000003)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) \r
+#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) \r
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable\r
+ * @{\r
+ */ \r
+#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)\r
+#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)\r
+#define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
+ * @{\r
+ */\r
+#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
+#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)\r
+ * @{\r
+ */ \r
+#define TIM_TRGO2_RESET ((uint32_t)0x00000000) \r
+#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))\r
+#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) \r
+#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) \r
+#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) \r
+#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) \r
+#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) \r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) \r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) \r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode\r
+ * @{\r
+ */\r
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)\r
+#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))\r
+#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))\r
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))\r
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))\r
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Sets the TIM Capture Compare Register value on runtime without\r
+ * calling another time ConfigChannel function.\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CHANNEL__ : TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @param __COMPARE__: specifies the Capture Compare register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
+ ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))\r
+\r
+/**\r
+ * @brief Gets the TIM Capture Compare Register value on runtime\r
+ * @param __HANDLE__: TIM handle.\r
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
+ ((__HANDLE__)->Instance->CCR6))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Timer Hall Sensor functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);\r
+\r
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);\r
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);\r
+\r
+ /* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Timer Complementary Output Compare functions *****************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Timer Complementary PWM functions ****************************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+/* Timer Complementary One Pulse functions **********************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group5\r
+ * @{\r
+ */\r
+/* Extension Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group6\r
+ * @{\r
+ */ \r
+/* Extension Callback *********************************************************/\r
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);\r
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);\r
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group7\r
+ * @{\r
+ */\r
+/* Extension Peripheral State functions **************************************/\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Macros TIM Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM_CHANNEL_4) || \\r
+ ((CHANNEL) == TIM_CHANNEL_5) || \\r
+ ((CHANNEL) == TIM_CHANNEL_6) || \\r
+ ((CHANNEL) == TIM_CHANNEL_ALL))\r
+ \r
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2))\r
+ \r
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2)) \r
+\r
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM_CHANNEL_3))\r
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \\r
+ ((MODE) == TIM_OCMODE_PWM2) || \\r
+ ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \\r
+ ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \\r
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \\r
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
+ \r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \\r
+ ((MODE) == TIM_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM_OCMODE_TOGGLE) || \\r
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \\r
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \\r
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
+#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_LSI)||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_LSE)||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_RTC)||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_HSE)||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_MCO1)) \r
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) \r
+#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)\r
+#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \\r
+ ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \\r
+ ((MODE) == TIM_CLEARINPUTSOURCE_NONE))\r
+#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \\r
+ ((STATE) == TIM_BREAK2_DISABLE))\r
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
+#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))\r
+#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \\r
+ ((SOURCE) == TIM_TRGO2_ENABLE) || \\r
+ ((SOURCE) == TIM_TRGO2_UPDATE) || \\r
+ ((SOURCE) == TIM_TRGO2_OC1) || \\r
+ ((SOURCE) == TIM_TRGO2_OC1REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC2REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC4REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC5REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC6REF) || \\r
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \\r
+ ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \\r
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \\r
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \\r
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \\r
+ ((MODE) == TIM_SLAVEMODE_RESET) || \\r
+ ((MODE) == TIM_SLAVEMODE_GATED) || \\r
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \\r
+ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_TIM_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of UART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_UART_H\r
+#define __STM32F7xx_HAL_UART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Types UART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.\r
+ The baud rate register is computed using the following formula:\r
+ - If oversampling is 16 or in LIN mode,\r
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))\r
+ - If oversampling is 8,\r
+ Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]\r
+ Baud Rate Register[3] = 0\r
+ Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref UARTEx_Word_Length */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref UART_Stop_Bits */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref UART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref UART_Mode */\r
+\r
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */\r
+\r
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r
+ This parameter can be a value of @ref UART_Over_Sampling */\r
+\r
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.\r
+ Selecting the single sample method increases the receiver tolerance to clock\r
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling */\r
+}UART_InitTypeDef;\r
+\r
+/**\r
+ * @brief UART Advanced Features initalization structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several\r
+ Advanced Features may be initialized at the same time .\r
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */\r
+\r
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Tx_Inv */\r
+\r
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.\r
+ This parameter can be a value of @ref UART_Rx_Inv */\r
+\r
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic\r
+ vs negative/inverted logic).\r
+ This parameter can be a value of @ref UART_Data_Inv */\r
+\r
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.\r
+ This parameter can be a value of @ref UART_Rx_Tx_Swap */\r
+\r
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.\r
+ This parameter can be a value of @ref UART_Overrun_Disable */\r
+\r
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.\r
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */\r
+\r
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.\r
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */\r
+\r
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate\r
+ detection is carried out.\r
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */\r
+\r
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.\r
+ This parameter can be a value of @ref UART_MSB_First */\r
+} UART_AdvFeatureInitTypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief HAL UART State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */\r
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */\r
+}HAL_UART_StateTypeDef;\r
+\r
+/**\r
+ * @brief UART clock sources definition\r
+ */\r
+typedef enum\r
+{\r
+ UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */\r
+ UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */\r
+ UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */\r
+ UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */\r
+ UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */\r
+ UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */\r
+}UART_ClockSourceTypeDef;\r
+\r
+/**\r
+ * @brief UART handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ USART_TypeDef *Instance; /*!< UART registers base address */\r
+\r
+ UART_InitTypeDef Init; /*!< UART communication parameters */\r
+\r
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /*!< UART Rx RDR register mask */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< UART Error code */\r
+\r
+}UART_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Constants UART Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup UART_Error_Definition UART Error Definition\r
+ * @{\r
+ */\r
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */\r
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */\r
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */\r
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */\r
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define UART_STOPBITS_1 ((uint32_t)0x0000)\r
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Parity UART Parity\r
+ * @{\r
+ */\r
+#define UART_PARITY_NONE ((uint32_t)0x00000000)\r
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r
+ * @{\r
+ */\r
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)\r
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)\r
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)\r
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mode UART Transfer Mode\r
+ * @{\r
+ */\r
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup UART_State UART State\r
+ * @{\r
+ */\r
+#define UART_STATE_DISABLE ((uint32_t)0x00000000)\r
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Over_Sampling UART Over Sampling\r
+ * @{\r
+ */\r
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)\r
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r
+ * @{\r
+ */\r
+#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r
+ * @{\r
+ */\r
+#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)\r
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN UART Local Interconnection Network mode\r
+ * @{\r
+ */\r
+#define UART_LIN_DISABLE ((uint32_t)0x00000000)\r
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection\r
+ * @{\r
+ */\r
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)\r
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Tx UART DMA Tx\r
+ * @{\r
+ */\r
+#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000)\r
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Rx UART DMA Rx\r
+ * @{\r
+ */\r
+#define UART_DMA_RX_DISABLE ((uint32_t)0x0000)\r
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection\r
+ * @{\r
+ */\r
+#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)\r
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods\r
+ * @{\r
+ */\r
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)\r
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Request_Parameters UART Request Parameters\r
+ * @{\r
+ */\r
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */\r
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */\r
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */\r
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */\r
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)\r
+#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)\r
+#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)\r
+#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)\r
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)\r
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)\r
+#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable\r
+ * @{\r
+ */\r
+#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)\r
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register\r
+ * @{\r
+ */\r
+#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity\r
+ * @{\r
+ */\r
+#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)\r
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r
+ * @{\r
+ */\r
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask\r
+ * @{\r
+ */\r
+#define UART_IT_MASK ((uint32_t)0x001F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value\r
+ * @{\r
+ */\r
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Flags UART Status Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define UART_FLAG_TEACK ((uint32_t)0x00200000)\r
+#define UART_FLAG_SBKF ((uint32_t)0x00040000\r
+#define UART_FLAG_CMF ((uint32_t)0x00020000)\r
+#define UART_FLAG_BUSY ((uint32_t)0x00010000)\r
+#define UART_FLAG_ABRF ((uint32_t)0x00008000)\r
+#define UART_FLAG_ABRE ((uint32_t)0x00004000)\r
+#define UART_FLAG_EOBF ((uint32_t)0x00001000)\r
+#define UART_FLAG_RTOF ((uint32_t)0x00000800)\r
+#define UART_FLAG_CTS ((uint32_t)0x00000400)\r
+#define UART_FLAG_CTSIF ((uint32_t)0x00000200)\r
+#define UART_FLAG_LBDF ((uint32_t)0x00000100)\r
+#define UART_FLAG_TXE ((uint32_t)0x00000080)\r
+#define UART_FLAG_TC ((uint32_t)0x00000040)\r
+#define UART_FLAG_RXNE ((uint32_t)0x00000020)\r
+#define UART_FLAG_IDLE ((uint32_t)0x00000010)\r
+#define UART_FLAG_ORE ((uint32_t)0x00000008)\r
+#define UART_FLAG_NE ((uint32_t)0x00000004)\r
+#define UART_FLAG_FE ((uint32_t)0x00000002)\r
+#define UART_FLAG_PE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+#define UART_IT_PE ((uint32_t)0x0028)\r
+#define UART_IT_TXE ((uint32_t)0x0727)\r
+#define UART_IT_TC ((uint32_t)0x0626)\r
+#define UART_IT_RXNE ((uint32_t)0x0525)\r
+#define UART_IT_IDLE ((uint32_t)0x0424)\r
+#define UART_IT_LBD ((uint32_t)0x0846)\r
+#define UART_IT_CTS ((uint32_t)0x096A)\r
+#define UART_IT_CM ((uint32_t)0x112E)\r
+\r
+/** Elements values convention: 000000000XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ */\r
+#define UART_IT_ERR ((uint32_t)0x0060)\r
+\r
+/** Elements values convention: 0000ZZZZ00000000b\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ */\r
+#define UART_IT_ORE ((uint32_t)0x0300)\r
+#define UART_IT_NE ((uint32_t)0x0200)\r
+#define UART_IT_FE ((uint32_t)0x0100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags\r
+ * @{\r
+ */\r
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */\r
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */\r
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */\r
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */\r
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */\r
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */\r
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */\r
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */\r
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */\r
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */\r
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup UART_Exported_Macros UART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset UART handle state\r
+ * @param __HANDLE__: UART handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)\r
+\r
+/** @brief Flush the UART Data registers\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ */\r
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\r
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\r
+ } while(0)\r
+\r
+/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __FLAG__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_CLEAR_PEF: Parity Error Clear Flag\r
+ * @arg UART_CLEAR_FEF: Framing Error Clear Flag\r
+ * @arg UART_CLEAR_NEF: Noise detected Clear Flag\r
+ * @arg UART_CLEAR_OREF: OverRun Error Clear Flag\r
+ * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag\r
+ * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag\r
+ * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag\r
+ * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag\r
+ * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag\r
+ * @arg UART_CLEAR_EOBF: End Of Block Clear Flag\r
+ * @arg UART_CLEAR_CMF: Character Match Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))\r
+\r
+/** @brief Clear the UART PE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)\r
+\r
+/** @brief Clear the UART FE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)\r
+\r
+/** @brief Clear the UART NE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)\r
+\r
+/** @brief Clear the UART ORE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)\r
+\r
+/** @brief Clear the UART IDLE pending flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)\r
+\r
+/** @brief Checks whether the specified UART flag is set or not.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_FLAG_REACK: Receive enable acknowledge flag\r
+ * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag\r
+ * @arg UART_FLAG_WUF: Wake up from stop mode flag\r
+ * @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)\r
+ * @arg UART_FLAG_SBKF: Send Break flag\r
+ * @arg UART_FLAG_CMF: Character match flag\r
+ * @arg UART_FLAG_BUSY: Busy flag\r
+ * @arg UART_FLAG_ABRF: Auto Baud rate detection flag\r
+ * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag\r
+ * @arg UART_FLAG_EOBF: End of block flag\r
+ * @arg UART_FLAG_RTOF: Receiver timeout flag\r
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
+ * @arg UART_FLAG_LBD: LIN Break detection flag\r
+ * @arg UART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg UART_FLAG_TC: Transmission Complete flag\r
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg UART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg UART_FLAG_ORE: OverRun Error flag\r
+ * @arg UART_FLAG_NE: Noise Error flag\r
+ * @arg UART_FLAG_FE: Framing Error flag\r
+ * @arg UART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Enables the specified UART interrupt.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+\r
+/** @brief Disables the specified UART interrupt.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r
+\r
+/** @brief Checks whether the specified UART interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __IT__: specifies the UART interrupt to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CM: Character match interrupt\r
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_ORE: OverRun Error interrupt\r
+ * @arg UART_IT_NE: Noise Error interrupt\r
+ * @arg UART_IT_FE: Framing Error interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r
+\r
+/** @brief Checks whether the specified UART interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __IT__: specifies the UART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg UART_IT_LBD: LIN Break detection interrupt\r
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg UART_IT_TC: Transmission complete interrupt\r
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg UART_IT_IDLE: Idle line detection interrupt\r
+ * @arg UART_IT_ORE: OverRun Error interrupt\r
+ * @arg UART_IT_NE: Noise Error interrupt\r
+ * @arg UART_IT_FE: Framing Error interrupt\r
+ * @arg UART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))\r
+\r
+/** @brief Set a specific UART request flag.\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @param __REQ__: specifies the request flag to set\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request\r
+ * @arg UART_SENDBREAK_REQUEST: Send Break Request\r
+ * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request\r
+ * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r
+ * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))\r
+\r
+/** @brief Enables the UART one bit sample method\r
+ * @param __HANDLE__: specifies the UART Handle. \r
+ * @retval None\r
+ */ \r
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r
+\r
+/** @brief Disables the UART one bit sample method\r
+ * @param __HANDLE__: specifies the UART Handle. \r
+ * @retval None\r
+ */ \r
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))\r
+\r
+/** @brief Enable UART\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable UART\r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/** @brief Enable CTS flow control \r
+ * This macro allows to enable CTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \\r
+ } while(0)\r
+\r
+/** @brief Disable CTS flow control \r
+ * This macro allows to disable CTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \\r
+ } while(0)\r
+\r
+/** @brief Enable RTS flow control \r
+ * This macro allows to enable RTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \\r
+ do{ \\r
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\r
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \\r
+ } while(0)\r
+\r
+/** @brief Disable RTS flow control \r
+ * This macro allows to disable RTS hardware flow control for a given UART instance, \r
+ * without need to call HAL_UART_Init() function.\r
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )\r
+ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r
+ * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r
+ * @param __HANDLE__: specifies the UART Handle.\r
+ * The Handle Instance can be USART1, USART2 or LPUART.\r
+ * @retval None\r
+ */\r
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \\r
+ do{ \\r
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\r
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \\r
+ } while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup UART_Private_Macros UART Private Macros\r
+ * @{\r
+ */\r
+/** @brief BRR division operation to set BRR register with LPUART\r
+ * @param _PCLK_: LPUART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_)))\r
+\r
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode\r
+ * @param _PCLK_: UART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_)))\r
+\r
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode\r
+ * @param _PCLK_: UART clock\r
+ * @param _BAUD_: Baud rate set by the user\r
+ * @retval Division result\r
+ */\r
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))\r
+\r
+/** @brief Check UART Baud rate\r
+ * @param BAUDRATE: Baudrate specified by the user\r
+ * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 200 MHz)\r
+ * divided by the smallest oversampling used on the USART (i.e. 8)\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)\r
+\r
+/** @brief Check UART assertion time\r
+ * @param TIME: 5-bit value assertion time\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r
+\r
+/** @brief Check UART deassertion time\r
+ * @param TIME: 5-bit value deassertion time\r
+ * @retval Test result (TRUE or FALSE).\r
+ */\r
+#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r
+\r
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\r
+ ((STOPBITS) == UART_STOPBITS_2))\r
+\r
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\r
+ ((PARITY) == UART_PARITY_EVEN) || \\r
+ ((PARITY) == UART_PARITY_ODD))\r
+\r
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == UART_HWCONTROL_NONE) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_CTS) || \\r
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))\r
+\r
+#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))\r
+\r
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\r
+ ((STATE) == UART_STATE_ENABLE))\r
+\r
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\r
+ ((SAMPLING) == UART_OVERSAMPLING_8))\r
+\r
+#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \\r
+ ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \\r
+ ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r
+\r
+#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \\r
+ ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))\r
+\r
+#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \\r
+ ((LIN) == UART_LIN_ENABLE))\r
+\r
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\r
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\r
+\r
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\r
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\r
+\r
+#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \\r
+ ((DMATX) == UART_DMA_TX_ENABLE))\r
+\r
+#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \\r
+ ((DMARX) == UART_DMA_RX_ENABLE))\r
+\r
+#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \\r
+ ((HDSEL) == UART_HALF_DUPLEX_ENABLE))\r
+\r
+#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \\r
+ ((PARAM) == UART_SENDBREAK_REQUEST) || \\r
+ ((PARAM) == UART_MUTE_MODE_REQUEST) || \\r
+ ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \\r
+ ((PARAM) == UART_TXDATA_FLUSH_REQUEST))\r
+\r
+#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \\r
+ UART_ADVFEATURE_TXINVERT_INIT | \\r
+ UART_ADVFEATURE_RXINVERT_INIT | \\r
+ UART_ADVFEATURE_DATAINVERT_INIT | \\r
+ UART_ADVFEATURE_SWAP_INIT | \\r
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\r
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \\r
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \\r
+ UART_ADVFEATURE_MSBFIRST_INIT))\r
+\r
+#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \\r
+ ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \\r
+ ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \\r
+ ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \\r
+ ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))\r
+\r
+#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\r
+ ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))\r
+\r
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\r
+ ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r
+\r
+#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\r
+ ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r
+\r
+#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\r
+ ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r
+\r
+#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\r
+ ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r
+\r
+#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \\r
+ ((POLARITY) == UART_DE_POLARITY_LOW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Include UART HAL Extension module */\r
+#include "stm32f7xx_hal_uart_ex.h"\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup UART_Exported_Functions UART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);\r
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);\r
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Errors functions **************************************************/\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions -----------------------------------------------------------*/\r
+/** @addtogroup UART_Private_Functions UART Private Functions\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_UART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of UART HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_UART_EX_H\r
+#define __STM32F7xx_HAL_UART_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup UARTEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup UARTEx_Word_Length UARTEx Word Length\r
+ * @{\r
+ */\r
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)\r
+#define UART_WORDLENGTH_8B ((uint32_t)0x0000)\r
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)\r
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \\r
+ ((__LENGTH__) == UART_WORDLENGTH_9B))\r
+#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r
+ * @{\r
+ */\r
+#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)\r
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)\r
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\r
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reports the UART clock source.\r
+ * @param __HANDLE__: specifies the UART Handle\r
+ * @param __CLOCKSOURCE__ : output variable \r
+ * @retval UART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == UART4) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \\r
+ { \\r
+ case RCC_UART4CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART4CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART5) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \\r
+ { \\r
+ case RCC_UART5CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART5CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART7) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \\r
+ { \\r
+ case RCC_UART7CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART7CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Instance == UART8) \\r
+ { \\r
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \\r
+ { \\r
+ case RCC_UART8CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_UART8CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/** @brief Reports the UART mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * If PCE = 1, the parity bit is not included in the data extracted\r
+ * by the reception API().\r
+ * This masking operation is not carried out in the case of\r
+ * DMA transfers. \r
+ * @param __HANDLE__: specifies the UART Handle\r
+ * @retval mask to apply to UART RDR register value.\r
+ */\r
+#define UART_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003F ; \\r
+ } \\r
+ } \\r
+} while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_UART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_usart.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of USART HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_USART_H\r
+#define __STM32F7xx_HAL_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Types USART Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USART Init Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */\r
+\r
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USARTEx_Word_Length */\r
+\r
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint32_t Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+\r
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r
+ This parameter can be a value of @ref USART_Over_Sampling */ \r
+\r
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+}USART_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL USART State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */\r
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */\r
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */\r
+}HAL_USART_StateTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USART clock sources definitions\r
+ */\r
+typedef enum\r
+{\r
+ USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */\r
+ USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */\r
+ USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */\r
+ USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */\r
+ USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */\r
+ USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */\r
+}USART_ClockSourceTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USART handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ USART_TypeDef *Instance; /*!< USART registers base address */\r
+\r
+ USART_InitTypeDef Init; /*!< USART communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /*!< USART Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /*!< USART Rx Transfer Counter */\r
+\r
+ uint16_t Mask; /*!< USART Rx RDR register mask */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+\r
+ HAL_USART_StateTypeDef State; /*!< USART communication state */\r
+\r
+ __IO uint32_t ErrorCode; /*!< USART Error code */\r
+\r
+}USART_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Constants USART Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Error_Code USART Error Code\r
+ * @brief USART Error Code \r
+ * @{\r
+ */ \r
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */\r
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */\r
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */\r
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */\r
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits\r
+ * @{\r
+ */\r
+#define USART_STOPBITS_1 ((uint32_t)0x0000)\r
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)\r
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Parity USART Parity\r
+ * @{\r
+ */\r
+#define USART_PARITY_NONE ((uint32_t)0x0000)\r
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)\r
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Mode USART Mode\r
+ * @{\r
+ */\r
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)\r
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)\r
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Over_Sampling USART Over Sampling\r
+ * @{\r
+ */\r
+#define USART_OVERSAMPLING_16 ((uint32_t)0x0000)\r
+#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup USART_Clock USART Clock\r
+ * @{\r
+ */\r
+#define USART_CLOCK_DISABLE ((uint32_t)0x0000)\r
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Clock_Polarity USART Clock Polarity\r
+ * @{\r
+ */\r
+#define USART_POLARITY_LOW ((uint32_t)0x0000)\r
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Clock_Phase USART Clock Phase\r
+ * @{\r
+ */\r
+#define USART_PHASE_1EDGE ((uint32_t)0x0000)\r
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit USART Last Bit\r
+ * @{\r
+ */\r
+#define USART_LASTBIT_DISABLE ((uint32_t)0x0000)\r
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Request_Parameters USART Request Parameters\r
+ * @{\r
+ */\r
+#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ \r
+#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Flags USART Flags\r
+ * Elements values convention: 0xXXXX\r
+ * - 0xXXXX : Flag mask in the ISR register\r
+ * @{\r
+ */\r
+#define USART_FLAG_REACK ((uint32_t)0x00400000)\r
+#define USART_FLAG_TEACK ((uint32_t)0x00200000) \r
+#define USART_FLAG_BUSY ((uint32_t)0x00010000)\r
+#define USART_FLAG_CTS ((uint32_t)0x00000400)\r
+#define USART_FLAG_CTSIF ((uint32_t)0x00000200)\r
+#define USART_FLAG_LBDF ((uint32_t)0x00000100)\r
+#define USART_FLAG_TXE ((uint32_t)0x00000080)\r
+#define USART_FLAG_TC ((uint32_t)0x00000040)\r
+#define USART_FLAG_RXNE ((uint32_t)0x00000020)\r
+#define USART_FLAG_IDLE ((uint32_t)0x00000010)\r
+#define USART_FLAG_ORE ((uint32_t)0x00000008)\r
+#define USART_FLAG_NE ((uint32_t)0x00000004)\r
+#define USART_FLAG_FE ((uint32_t)0x00000002)\r
+#define USART_FLAG_PE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition\r
+ * Elements values convention: 0000ZZZZ0XXYYYYYb\r
+ * - YYYYY : Interrupt source position in the XX register (5bits)\r
+ * - XX : Interrupt source register (2bits)\r
+ * - 01: CR1 register\r
+ * - 10: CR2 register\r
+ * - 11: CR3 register\r
+ * - ZZZZ : Flag position in the ISR register(4bits)\r
+ * @{\r
+ */\r
+\r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+\r
+#define USART_IT_ORE ((uint16_t)0x0300)\r
+#define USART_IT_NE ((uint16_t)0x0200)\r
+#define USART_IT_FE ((uint16_t)0x0100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags\r
+ * @{\r
+ */\r
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */\r
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */\r
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */\r
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */\r
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */\r
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */\r
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup USART_Exported_Macros USART Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset USART handle state\r
+ * @param __HANDLE__: USART handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)\r
+\r
+/** @brief Checks whether the specified USART flag is set or not.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_REACK: Receive enable acknowledge flag\r
+ * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag\r
+ * @arg USART_FLAG_BUSY: Busy flag\r
+ * @arg USART_FLAG_CTS: CTS Change flag\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg USART_FLAG_TC: Transmission Complete flag\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg USART_FLAG_ORE: OverRun Error flag\r
+ * @arg USART_FLAG_NE: Noise Error flag\r
+ * @arg USART_FLAG_FE: Framing Error flag\r
+ * @arg USART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r
+\r
+\r
+/** @brief Enables the specified USART interrupt.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @param __INTERRUPT__: specifies the USART interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r
+\r
+/** @brief Disables the specified USART interrupt.\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @param __INTERRUPT__: specifies the USART interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\r
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r
+\r
+\r
+/** @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @param __IT__: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r
+\r
+/** @brief Checks whether the specified USART interrupt source is enabled.\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @param __IT__: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\r
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\r
+ (((uint16_t)(__IT__)) & USART_IT_MASK)))\r
+\r
+\r
+/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r
+ * to clear the corresponding interrupt\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag\r
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag\r
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag\r
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r
+ * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag\r
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r
+ * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r
+\r
+/** @brief Set a specific USART request flag.\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @param __REQ__: specifies the request flag to set\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r
+ * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r
+\r
+/** @brief Enable USART\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)\r
+\r
+/** @brief Disable USART\r
+ * @param __HANDLE__: specifies the USART Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Include UART HAL Extension module */\r
+#include "stm32f7xx_hal_usart_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup USART_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions **********************************/\r
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);\r
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);\r
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup USART_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);\r
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);\r
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);\r
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup USART_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);\r
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup USART_Private_Constants USART Private Constants\r
+ * @{\r
+ */\r
+/** @brief USART interruptions flag mask\r
+ * \r
+ */ \r
+#define USART_IT_MASK ((uint16_t)0x001F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup USART_Private_Macros USART Private Macros\r
+ * @{\r
+ */\r
+/** @brief Reports the USART clock source.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @param __CLOCKSOURCE__ : output variable\r
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.\r
+ */\r
+#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\\r
+ do { \\r
+ if((__HANDLE__)->Instance == USART1) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \\r
+ { \\r
+ case RCC_USART1CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART1CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART2) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \\r
+ { \\r
+ case RCC_USART2CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART2CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART3) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \\r
+ { \\r
+ case RCC_USART3CLKSOURCE_PCLK1: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART3CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ else if((__HANDLE__)->Instance == USART6) \\r
+ { \\r
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \\r
+ { \\r
+ case RCC_USART6CLKSOURCE_PCLK2: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_HSI: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_SYSCLK: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \\r
+ break; \\r
+ case RCC_USART6CLKSOURCE_LSE: \\r
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \\r
+ break; \\r
+ default: \\r
+ break; \\r
+ } \\r
+ } \\r
+ } while(0)\r
+ \r
+\r
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \\r
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \\r
+ ((__STOPBITS__) == USART_STOPBITS_2))\r
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \\r
+ ((__PARITY__) == USART_PARITY_EVEN) || \\r
+ ((__PARITY__) == USART_PARITY_ODD))\r
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))\r
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \\r
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))\r
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__)== USART_CLOCK_DISABLE) || \\r
+ ((__CLOCK__)== USART_CLOCK_ENABLE))\r
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))\r
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))\r
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \\r
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))\r
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \\r
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) \r
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup USART_Private_Functions USART Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_USART_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_usart_ex.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of USART HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_USART_EX_H\r
+#define __STM32F7xx_HAL_USART_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USARTEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USARTEx_Word_Length USARTEx Word Length\r
+ * @{\r
+ */\r
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)\r
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)\r
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Computes the USART mask to apply to retrieve the received data\r
+ * according to the word length and to the parity bits activation.\r
+ * If PCE = 1, the parity bit is not included in the data extracted\r
+ * by the reception API().\r
+ * This masking operation is not carried out in the case of\r
+ * DMA transfers.\r
+ * @param __HANDLE__: specifies the USART Handle\r
+ * @retval none\r
+ */\r
+#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \\r
+ do { \\r
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x01FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x00FF ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ } \\r
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \\r
+ { \\r
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x007F ; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Mask = 0x003F ; \\r
+ } \\r
+ } \\r
+} while(0)\r
+\r
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \\r
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \\r
+ ((__LENGTH__) == USART_WORDLENGTH_9B)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/* Initialization/de-initialization methods **********************************/\r
+/* IO operation methods *******************************************************/\r
+/* Peripheral Control methods ************************************************/\r
+/* Peripheral State methods **************************************************/\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_USART_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of WWDG HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_WWDG_H\r
+#define __STM32F7xx_HAL_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup WWDG_Exported_Types WWDG Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief WWDG HAL State Structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */\r
+ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */\r
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */\r
+ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */\r
+ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */\r
+}HAL_WWDG_StateTypeDef;\r
+\r
+/** \r
+ * @brief WWDG Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.\r
+ This parameter can be a value of @ref WWDG_Prescaler */\r
+ \r
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.\r
+ This parameter must be a number lower than Max_Data = 0x80 */ \r
+ \r
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.\r
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */\r
+\r
+}WWDG_InitTypeDef;\r
+\r
+/** \r
+ * @brief WWDG handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ WWDG_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< WWDG locking object */\r
+ \r
+ __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */\r
+ \r
+}WWDG_HandleTypeDef;\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition\r
+ * @{\r
+ */ \r
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Flag_definition WWDG Flag definition\r
+ * @brief WWDG Flag definition\r
+ * @{\r
+ */ \r
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Prescaler WWDG Prescaler\r
+ * @{\r
+ */ \r
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */\r
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */\r
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */\r
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset WWDG handle state\r
+ * @param __HANDLE__: WWDG handle\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)\r
+\r
+/**\r
+ * @brief Enables the WWDG peripheral.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)\r
+\r
+/**\r
+ * @brief Disables the WWDG peripheral.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @note WARNING: This is a dummy macro for HAL code alignment.\r
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */\r
+\r
+/**\r
+ * @brief Gets the selected WWDG's it status.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __INTERRUPT__: specifies the it to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT\r
+ * @retval The new state of WWDG_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))\r
+\r
+/** @brief Clear the WWDG's interrupt pending bits\r
+ * bits to clear the selected interrupt pending bits.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r
+ */\r
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the WWDG early wakeup interrupt.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __INTERRUPT__: specifies the interrupt to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_IT_EWI: Early wakeup interrupt\r
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))\r
+ \r
+/**\r
+ * @brief Disables the WWDG early wakeup interrupt.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __INTERRUPT__: specifies the interrupt to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_IT_EWI: Early wakeup interrupt\r
+ * @note WARNING: This is a dummy macro for HAL code alignment. \r
+ * Once enabled this interrupt cannot be disabled except by a system reset.\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */\r
+ \r
+/**\r
+ * @brief Gets the selected WWDG's flag status.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r
+ * @retval The new state of WWDG_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clears the WWDG's pending flags.\r
+ * @param __HANDLE__: WWDG handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r
+ * @retval None\r
+ */\r
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))\r
+\r
+/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.\r
+ * @param __HANDLE__: WWDG Handle.\r
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt\r
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup WWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization/de-initialization functions **********************************/\r
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);\r
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);\r
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);\r
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);\r
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup WWDG_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* I/O operation functions ******************************************************/\r
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);\r
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);\r
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);\r
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup WWDG_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions **************************************************/\r
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup WWDG_Private_Constants WWDG Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup WWDG_Private_Macros WWDG Private Macros\r
+ * @{\r
+ */\r
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \\r
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \\r
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \\r
+ ((__PRESCALER__) == WWDG_PRESCALER_8))\r
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)\r
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup WWDG_Private_Functions WWDG Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_WWDG_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_fmc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of FMC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_LL_FMC_H\r
+#define __STM32F7xx_LL_FMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FMC_LL\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+ \r
+\r
+/** @addtogroup FMC_LL_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \\r
+ ((BANK) == FMC_NORSRAM_BANK2) || \\r
+ ((BANK) == FMC_NORSRAM_BANK3) || \\r
+ ((BANK) == FMC_NORSRAM_BANK4))\r
+\r
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \\r
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))\r
+\r
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \\r
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \\r
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))\r
+\r
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \\r
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \\r
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))\r
+\r
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \\r
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \\r
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \\r
+ ((__MODE__) == FMC_ACCESS_MODE_D))\r
+\r
+#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)\r
+\r
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \\r
+ ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))\r
+\r
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \\r
+ ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))\r
+\r
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \\r
+ ((STATE) == FMC_NAND_ECC_ENABLE))\r
+\r
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \\r
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \\r
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \\r
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \\r
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \\r
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))\r
+ \r
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \\r
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \\r
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))\r
+\r
+#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \\r
+ ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) \r
+\r
+#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \\r
+ ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \\r
+ ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))\r
+ \r
+#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \\r
+ ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))\r
+ \r
+#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \\r
+ ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \\r
+ ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))\r
+\r
+#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \\r
+ ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))\r
+\r
+#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \\r
+ ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \\r
+ ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) \r
+ \r
+/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time\r
+ * @{\r
+ */\r
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time \r
+ * @{\r
+ */\r
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Setup_Time FMC Setup Time \r
+ * @{\r
+ */\r
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time \r
+ * @{\r
+ */\r
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time \r
+ * @{\r
+ */\r
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time \r
+ * @{\r
+ */\r
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \\r
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))\r
+\r
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \\r
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))\r
+\r
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \\r
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) \r
+\r
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \\r
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))\r
+\r
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \\r
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))\r
+\r
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \\r
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))\r
+\r
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \\r
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))\r
+\r
+/** @defgroup FMC_Data_Latency FMC Data Latency \r
+ * @{\r
+ */\r
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \\r
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))\r
+\r
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \\r
+ ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))\r
+\r
+\r
+/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time\r
+ * @{\r
+ */\r
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time\r
+ * @{\r
+ */\r
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time\r
+ * @{\r
+ */\r
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration\r
+ * @{\r
+ */\r
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_CLK_Division FMC CLK Division \r
+ * @{\r
+ */\r
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay\r
+ * @{\r
+ */\r
+#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay\r
+ * @{\r
+ */\r
+#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time\r
+ * @{\r
+ */ \r
+#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay\r
+ * @{\r
+ */ \r
+#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time\r
+ * @{\r
+ */ \r
+#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay\r
+ * @{\r
+ */ \r
+#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay\r
+ * @{\r
+ */ \r
+#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number\r
+ * @{\r
+ */ \r
+#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition\r
+ * @{\r
+ */\r
+#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate\r
+ * @{\r
+ */\r
+#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance\r
+ * @{\r
+ */\r
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance\r
+ * @{\r
+ */\r
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance\r
+ * @{\r
+ */\r
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance\r
+ * @{\r
+ */\r
+#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \\r
+ ((BANK) == FMC_SDRAM_BANK2))\r
+\r
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \\r
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \\r
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \\r
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))\r
+\r
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \\r
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \\r
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))\r
+\r
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \\r
+ ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))\r
+\r
+\r
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \\r
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \\r
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))\r
+\r
+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \\r
+ ((__SIZE__) == FMC_PAGE_SIZE_128) || \\r
+ ((__SIZE__) == FMC_PAGE_SIZE_256) || \\r
+ ((__SIZE__) == FMC_PAGE_SIZE_1024))\r
+\r
+#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \\r
+ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported typedef ----------------------------------------------------------*/\r
+/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types\r
+ * @{\r
+ */\r
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef\r
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef\r
+#define FMC_NAND_TypeDef FMC_Bank3_TypeDef\r
+#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef\r
+\r
+#define FMC_NORSRAM_DEVICE FMC_Bank1\r
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E\r
+#define FMC_NAND_DEVICE FMC_Bank3\r
+#define FMC_SDRAM_DEVICE FMC_Bank5_6\r
+\r
+/** \r
+ * @brief FMC NORSRAM Configuration Structure definition\r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.\r
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */\r
+\r
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are\r
+ multiplexed on the data bus or not. \r
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */\r
+\r
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to\r
+ the corresponding memory device.\r
+ This parameter can be a value of @ref FMC_Memory_Type */\r
+\r
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */\r
+\r
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
+ valid only with synchronous burst Flash memories.\r
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */\r
+\r
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
+ the Flash memory in burst mode.\r
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */\r
+\r
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
+ clock cycle before the wait state or during the wait state,\r
+ valid only when accessing memories in burst mode. \r
+ This parameter can be a value of @ref FMC_Wait_Timing */\r
+\r
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. \r
+ This parameter can be a value of @ref FMC_Write_Operation */\r
+\r
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait\r
+ signal, valid for Flash memory access in burst mode. \r
+ This parameter can be a value of @ref FMC_Wait_Signal */\r
+\r
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.\r
+ This parameter can be a value of @ref FMC_Extended_Mode */\r
+\r
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
+ valid only with asynchronous Flash memories.\r
+ This parameter can be a value of @ref FMC_AsynchronousWait */\r
+\r
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.\r
+ This parameter can be a value of @ref FMC_Write_Burst */\r
+\r
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.\r
+ This parameter is only enabled through the FMC_BCR1 register, and don't care \r
+ through FMC_BCR2..4 registers.\r
+ This parameter can be a value of @ref FMC_CONTINUOUS_Clock */\r
+\r
+ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.\r
+ This parameter is only enabled through the FMC_BCR1 register, and don't care \r
+ through FMC_BCR2..4 registers.\r
+ This parameter can be a value of @ref FMC_Write_FIFO */\r
+\r
+ uint32_t PageSize; /*!< Specifies the memory page size.\r
+ This parameter can be a value of @ref FMC_Page_Size */\r
+\r
+}FMC_NORSRAM_InitTypeDef;\r
+\r
+/** \r
+ * @brief FMC NORSRAM Timing parameters structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address setup time. \r
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r
+ @note This parameter is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address hold time.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15. \r
+ @note This parameter is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the data setup time.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.\r
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed \r
+ NOR Flash memories. */\r
+\r
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the bus turnaround.\r
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r
+ @note This parameter is only used for multiplexed NOR Flash memories. */\r
+\r
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of \r
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.\r
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM \r
+ accesses. */\r
+\r
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue\r
+ to the memory before getting the first data.\r
+ The parameter value depends on the memory type as shown below:\r
+ - It must be set to 0 in case of a CRAM\r
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses\r
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories\r
+ with synchronous burst mode enable */\r
+\r
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. \r
+ This parameter can be a value of @ref FMC_Access_Mode */\r
+}FMC_NORSRAM_TimingTypeDef;\r
+\r
+/** \r
+ * @brief FMC NAND Configuration Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.\r
+ This parameter can be a value of @ref FMC_NAND_Bank */\r
+\r
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.\r
+ This parameter can be any value of @ref FMC_Wait_feature */\r
+\r
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be any value of @ref FMC_NAND_Data_Width */\r
+\r
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.\r
+ This parameter can be any value of @ref FMC_ECC */\r
+\r
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.\r
+ This parameter can be any value of @ref FMC_ECC_Page_Size */\r
+\r
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */\r
+\r
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r
+}FMC_NAND_InitTypeDef;\r
+\r
+/** \r
+ * @brief FMC NAND Timing parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
+ the command assertion for NAND-Flash read or write access\r
+ to common/Attribute or I/O memory space (depending on\r
+ the memory space timing to be configured).\r
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */\r
+\r
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
+ command for NAND-Flash read or write access to\r
+ common/Attribute or I/O memory space (depending on the\r
+ memory space timing to be configured). \r
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r
+\r
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
+ (and data for write access) after the command de-assertion\r
+ for NAND-Flash read or write access to common/Attribute\r
+ or I/O memory space (depending on the memory space timing\r
+ to be configured).\r
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r
+\r
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
+ data bus is kept in HiZ after the start of a NAND-Flash\r
+ write access to common/Attribute or I/O memory space (depending\r
+ on the memory space timing to be configured).\r
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r
+}FMC_NAND_PCC_TimingTypeDef;\r
+\r
+/** \r
+ * @brief FMC SDRAM Configuration Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.\r
+ This parameter can be a value of @ref FMC_SDRAM_Bank */\r
+\r
+ uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.\r
+ This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */\r
+\r
+ uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.\r
+ This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */\r
+\r
+ uint32_t MemoryDataWidth; /*!< Defines the memory device width.\r
+ This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */\r
+\r
+ uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.\r
+ This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */\r
+\r
+ uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.\r
+ This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */\r
+\r
+ uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.\r
+ This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */\r
+\r
+ uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow \r
+ to disable the clock before changing frequency.\r
+ This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */\r
+\r
+ uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read \r
+ commands during the CAS latency and stores data in the Read FIFO.\r
+ This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */\r
+\r
+ uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.\r
+ This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */\r
+}FMC_SDRAM_InitTypeDef;\r
+\r
+/** \r
+ * @brief FMC SDRAM Timing parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and \r
+ an active or Refresh command in number of memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to \r
+ issuing the Activate command in number of memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock \r
+ cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command\r
+ and the delay between two consecutive Refresh commands in number of \r
+ memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command \r
+ in number of memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+\r
+ uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write \r
+ command in number of memory clock cycles.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ \r
+}FMC_SDRAM_TimingTypeDef;\r
+\r
+/** \r
+ * @brief SDRAM command parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.\r
+ This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */\r
+\r
+ uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.\r
+ This parameter can be a value of @ref FMC_SDRAM_Command_Target. */\r
+\r
+ uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued\r
+ in auto refresh mode.\r
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */\r
+ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */\r
+}FMC_SDRAM_CommandTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank\r
+ * @{\r
+ */\r
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)\r
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)\r
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)\r
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing\r
+ * @{\r
+ */\r
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Memory_Type FMC Memory Type\r
+ * @{\r
+ */\r
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)\r
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)\r
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width\r
+ * @{\r
+ */\r
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)\r
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)\r
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access\r
+ * @{\r
+ */\r
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)\r
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode\r
+ * @{\r
+ */\r
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) \r
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity\r
+ * @{\r
+ */\r
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)\r
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Wait_Timing FMC Wait Timing\r
+ * @{\r
+ */\r
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)\r
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Write_Operation FMC Write Operation\r
+ * @{\r
+ */\r
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Wait_Signal FMC Wait Signal\r
+ * @{\r
+ */\r
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Extended_Mode FMC Extended Mode\r
+ * @{\r
+ */\r
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait\r
+ * @{\r
+ */\r
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_Page_Size FMC Page Size\r
+ * @{\r
+ */\r
+#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)\r
+#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)\r
+#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)\r
+#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_Write_Burst FMC Write Burst\r
+ * @{\r
+ */\r
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_Continous_Clock FMC Continous Clock\r
+ * @{\r
+ */\r
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)\r
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_Write_FIFO FMC Write FIFO \r
+ * @{\r
+ */\r
+#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_Access_Mode FMC Access Mode \r
+ * @{\r
+ */\r
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)\r
+#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) \r
+#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)\r
+#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller \r
+ * @{\r
+ */\r
+/** @defgroup FMC_NAND_Bank FMC NAND Bank \r
+ * @{\r
+ */\r
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_Wait_feature FMC Wait feature\r
+ * @{\r
+ */\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type \r
+ * @{\r
+ */\r
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width \r
+ * @{\r
+ */\r
+#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)\r
+#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_ECC FMC ECC \r
+ * @{\r
+ */\r
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size \r
+ * @{\r
+ */\r
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)\r
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)\r
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)\r
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)\r
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)\r
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller \r
+ * @{\r
+ */\r
+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number \r
+ * @{\r
+ */\r
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)\r
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)\r
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)\r
+#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)\r
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)\r
+#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)\r
+#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)\r
+#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)\r
+#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)\r
+#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)\r
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)\r
+#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)\r
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)\r
+#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target\r
+ * @{\r
+ */\r
+#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2\r
+#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1\r
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status \r
+ * @{\r
+ */\r
+#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)\r
+#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0\r
+#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition \r
+ * @{\r
+ */ \r
+#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)\r
+#define FMC_IT_LEVEL ((uint32_t)0x00000010)\r
+#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)\r
+#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition \r
+ * @{\r
+ */ \r
+#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)\r
+#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)\r
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)\r
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
+#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE\r
+#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY\r
+#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros\r
+ * @brief macros to handle NOR device enable/disable and read/write operations\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enable the NORSRAM device access.\r
+ * @param __INSTANCE__: FMC_NORSRAM Instance\r
+ * @param __BANK__: FMC_NORSRAM Bank \r
+ * @retval None\r
+ */ \r
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)\r
+\r
+/**\r
+ * @brief Disable the NORSRAM device access.\r
+ * @param __INSTANCE__: FMC_NORSRAM Instance\r
+ * @param __BANK__: FMC_NORSRAM Bank \r
+ * @retval None\r
+ */ \r
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros\r
+ * @brief macros to handle NAND device enable/disable\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enable the NAND device access.\r
+ * @param __INSTANCE__: FMC_NAND Instance \r
+ * @retval None\r
+ */ \r
+#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)\r
+\r
+/**\r
+ * @brief Disable the NAND device access.\r
+ * @param __INSTANCE__: FMC_NAND Instance \r
+ * @retval None\r
+ */\r
+#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FMC_Interrupt FMC Interrupt\r
+ * @brief macros to handle FMC interrupts\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enable the NAND device interrupt.\r
+ * @param __INSTANCE__: FMC_NAND instance \r
+ * @param __INTERRUPT__: FMC_NAND interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r
+ * @arg FMC_IT_LEVEL: Interrupt level.\r
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. \r
+ * @retval None\r
+ */ \r
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the NAND device interrupt.\r
+ * @param __INSTANCE__: FMC_NAND Instance\r
+ * @param __INTERRUPT__: FMC_NAND interrupt\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r
+ * @arg FMC_IT_LEVEL: Interrupt level.\r
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. \r
+ * @retval None\r
+ */\r
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))\r
+ \r
+/**\r
+ * @brief Get flag status of the NAND device.\r
+ * @param __INSTANCE__: FMC_NAND Instance\r
+ * @param __BANK__: FMC_NAND Bank \r
+ * @param __FLAG__: FMC_NAND flag\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag. \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear flag status of the NAND device.\r
+ * @param __INSTANCE__: FMC_NAND Instance \r
+ * @param __FLAG__: FMC_NAND flag\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag. \r
+ * @retval None\r
+ */\r
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) \r
+\r
+/**\r
+ * @brief Enable the SDRAM device interrupt.\r
+ * @param __INSTANCE__: FMC_SDRAM instance \r
+ * @param __INTERRUPT__: FMC_SDRAM interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error \r
+ * @retval None\r
+ */\r
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the SDRAM device interrupt.\r
+ * @param __INSTANCE__: FMC_SDRAM instance \r
+ * @param __INTERRUPT__: FMC_SDRAM interrupt \r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error \r
+ * @retval None\r
+ */\r
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Get flag status of the SDRAM device.\r
+ * @param __INSTANCE__: FMC_SDRAM instance \r
+ * @param __FLAG__: FMC_SDRAM flag\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.\r
+ * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.\r
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.\r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Clear flag status of the SDRAM device.\r
+ * @param __INSTANCE__: FMC_SDRAM instance \r
+ * @param __FLAG__: FMC_SDRAM flag\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR\r
+ * @retval None\r
+ */\r
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NORSRAM NOR SRAM\r
+ * @{\r
+ */\r
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);\r
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);\r
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_NAND NAND\r
+ * @{\r
+ */\r
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);\r
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_SDRAM SDRAM\r
+ * @{\r
+ */\r
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);\r
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);\r
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);\r
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F756xx || STM32F746xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_LL_FMC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_sdmmc.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of SDMMC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_LL_SDMMC_H\r
+#define __STM32F7xx_LL_SDMMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDMMC_LL\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief SDMMC Configuration Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SDMMC_LL_Clock_Edge */\r
+\r
+ uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is\r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */\r
+\r
+ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or\r
+ disabled when the bus is idle.\r
+ This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */\r
+\r
+ uint32_t BusWide; /*!< Specifies the SDMMC bus width.\r
+ This parameter can be a value of @ref SDMMC_LL_Bus_Wide */\r
+\r
+ uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.\r
+ This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */\r
+\r
+ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.\r
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ \r
+ \r
+}SDMMC_InitTypeDef;\r
+ \r
+\r
+/** \r
+ * @brief SDMMC Command Control structure \r
+ */\r
+typedef struct \r
+{\r
+ uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent\r
+ to a card as part of a command message. If a command\r
+ contains an argument, it must be loaded into this register\r
+ before writing the command to the command register. */\r
+\r
+ uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and \r
+ Max_Data = 64 */\r
+\r
+ uint32_t Response; /*!< Specifies the SDMMC response type.\r
+ This parameter can be a value of @ref SDMMC_LL_Response_Type */\r
+\r
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is \r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */\r
+\r
+ uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDMMC_LL_CPSM_State */\r
+}SDMMC_CmdInitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief SDMMC Data Control structure \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
+\r
+ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
+ \r
+ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.\r
+ This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */\r
+ \r
+ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
+ is a read or write.\r
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */\r
+ \r
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
+ This parameter can be a value of @ref SDMMC_LL_Transfer_Type */\r
+ \r
+ uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDMMC_LL_DPSM_State */\r
+}SDMMC_DataInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge\r
+ * @{\r
+ */\r
+#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)\r
+#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE\r
+\r
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \\r
+ ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass\r
+ * @{\r
+ */\r
+#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)\r
+#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS \r
+\r
+#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \\r
+ ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving\r
+ * @{\r
+ */\r
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)\r
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV\r
+\r
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \\r
+ ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width\r
+ * @{\r
+ */\r
+#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)\r
+#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0\r
+#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1\r
+\r
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \\r
+ ((WIDE) == SDMMC_BUS_WIDE_4B) || \\r
+ ((WIDE) == SDMMC_BUS_WIDE_8B))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control\r
+ * @{\r
+ */\r
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)\r
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN\r
+\r
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \\r
+ ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDMMC_LL_Clock_Division Clock Division\r
+ * @{\r
+ */\r
+#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup SDMMC_LL_Command_Index Command Index\r
+ * @{\r
+ */\r
+#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Response_Type Response Type\r
+ * @{\r
+ */\r
+#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)\r
+#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0\r
+#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP\r
+\r
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \\r
+ ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \\r
+ ((RESPONSE) == SDMMC_RESPONSE_LONG))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt\r
+ * @{\r
+ */\r
+#define SDMMC_WAIT_NO ((uint32_t)0x00000000)\r
+#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT \r
+#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND\r
+\r
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \\r
+ ((WAIT) == SDMMC_WAIT_IT) || \\r
+ ((WAIT) == SDMMC_WAIT_PEND))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_CPSM_State CPSM State\r
+ * @{\r
+ */\r
+#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)\r
+#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN\r
+\r
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \\r
+ ((CPSM) == SDMMC_CPSM_ENABLE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDMMC_LL_Response_Registers Response Register\r
+ * @{\r
+ */\r
+#define SDMMC_RESP1 ((uint32_t)0x00000000)\r
+#define SDMMC_RESP2 ((uint32_t)0x00000004)\r
+#define SDMMC_RESP3 ((uint32_t)0x00000008)\r
+#define SDMMC_RESP4 ((uint32_t)0x0000000C)\r
+\r
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \\r
+ ((RESP) == SDMMC_RESP2) || \\r
+ ((RESP) == SDMMC_RESP3) || \\r
+ ((RESP) == SDMMC_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Data_Length Data Lenght\r
+ * @{\r
+ */\r
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size\r
+ * @{\r
+ */\r
+#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)\r
+#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0\r
+#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1\r
+#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)\r
+#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2\r
+#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)\r
+#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r
+#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r
+#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3\r
+#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)\r
+#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)\r
+#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) \r
+#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
+#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
+#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r
+\r
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \\r
+ ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction\r
+ * @{\r
+ */\r
+#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)\r
+#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR\r
+\r
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \\r
+ ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type\r
+ * @{\r
+ */\r
+#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)\r
+#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE\r
+\r
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \\r
+ ((MODE) == SDMMC_TRANSFER_MODE_STREAM))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_DPSM_State DPSM State\r
+ * @{\r
+ */\r
+#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)\r
+#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN\r
+\r
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\\r
+ ((DPSM) == SDMMC_DPSM_ENABLE))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode\r
+ * @{\r
+ */\r
+#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)\r
+#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)\r
+\r
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \\r
+ ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources\r
+ * @{\r
+ */\r
+#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL\r
+#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL\r
+#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT\r
+#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT\r
+#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR\r
+#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR\r
+#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND\r
+#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT\r
+#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND\r
+#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND\r
+#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT\r
+#define SDMMC_IT_TXACT SDMMC_STA_TXACT\r
+#define SDMMC_IT_RXACT SDMMC_STA_RXACT\r
+#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE\r
+#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF\r
+#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF\r
+#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF\r
+#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE\r
+#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE\r
+#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL\r
+#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL\r
+#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDMMC_LL_Flags Flags\r
+ * @{\r
+ */\r
+#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL\r
+#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL\r
+#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT\r
+#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT\r
+#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR\r
+#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR\r
+#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND\r
+#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT\r
+#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND\r
+#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND\r
+#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT\r
+#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT\r
+#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT\r
+#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE\r
+#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF\r
+#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF\r
+#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF\r
+#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE\r
+#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE\r
+#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL\r
+#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL\r
+#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions\r
+ * @brief SDMMC_LL registers bit address in the alias region\r
+ * @{\r
+ */\r
+/* ---------------------- SDMMC registers bit mask --------------------------- */\r
+/* --- CLKCR Register ---*/\r
+/* CLKCR register clear mask */ \r
+#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\\r
+ SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\\r
+ SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))\r
+\r
+/* --- DCTRL Register ---*/\r
+/* SDMMC DCTRL Clear Mask */\r
+#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\\r
+ SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))\r
+\r
+/* --- CMD Register ---*/\r
+/* CMD Register clear mask */\r
+#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\\r
+ SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\\r
+ SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))\r
+\r
+/* SDMMC Initialization Frequency (400KHz max) */\r
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)\r
+\r
+/* SDMMC Data Transfer Frequency (25MHz max) */\r
+#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enable the SDMMC device.\r
+ * @param __INSTANCE__: SDMMC Instance \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)\r
+\r
+/**\r
+ * @brief Disable the SDMMC device.\r
+ * @param __INSTANCE__: SDMMC Instance \r
+ * @retval None\r
+ */\r
+#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)\r
+\r
+/**\r
+ * @brief Enable the SDMMC DMA transfer.\r
+ * @param __INSTANCE__: SDMMC Instance \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)\r
+/**\r
+ * @brief Disable the SDMMC DMA transfer.\r
+ * @param __INSTANCE__: SDMMC Instance \r
+ * @retval None\r
+ */\r
+#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)\r
+ \r
+/**\r
+ * @brief Enable the SDMMC device interrupt.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt \r
+ * @retval None\r
+ */\r
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the SDMMC device interrupt.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt \r
+ * @retval None\r
+ */\r
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified SDMMC flag is set or not. \r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __FLAG__: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDACT: Command transfer in progress\r
+ * @arg SDMMC_FLAG_TXACT: Data transmit in progress\r
+ * @arg SDMMC_FLAG_RXACT: Data receive in progress\r
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full\r
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full\r
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty\r
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty\r
+ * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO\r
+ * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO\r
+ * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received\r
+ * @retval The new state of SDMMC_FLAG (SET or RESET).\r
+ */\r
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)\r
+\r
+\r
+/**\r
+ * @brief Clears the SDMMC pending flags.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __FLAG__: specifies the flag to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received\r
+ * @retval None\r
+ */\r
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified SDMMC interrupt has occurred or not.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @retval The new state of SDMMC_IT (SET or RESET).\r
+ */\r
+#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the SDMMC's interrupt pending bits.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @retval None\r
+ */\r
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enable Start the SD I/O Read Wait operation.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)\r
+\r
+/**\r
+ * @brief Disable Start the SD I/O Read Wait operations.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)\r
+\r
+/**\r
+ * @brief Enable Start the SD I/O Read Wait operation.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)\r
+\r
+/**\r
+ * @brief Disable Stop the SD I/O Read Wait operations.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)\r
+\r
+/**\r
+ * @brief Enable the SD I/O Mode Operation.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) \r
+\r
+/**\r
+ * @brief Disable the SD I/O Mode Operation.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) \r
+\r
+/**\r
+ * @brief Enable the SD I/O Suspend command sending.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) \r
+\r
+/**\r
+ * @brief Disable the SD I/O Suspend command sending.\r
+ * @param __INSTANCE__ : Pointer to SDMMC register base \r
+ * @retval None\r
+ */ \r
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SDMMC_LL_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/* Initialization/de-initialization functions **********************************/\r
+/** @addtogroup HAL_SDMMC_LL_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* I/O operation functions *****************************************************/\r
+/** @addtogroup HAL_SDMMC_LL_Group2\r
+ * @{\r
+ */\r
+/* Blocking mode: Polling */\r
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);\r
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Peripheral Control functions ************************************************/\r
+/** @addtogroup HAL_SDMMC_LL_Group3\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);\r
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);\r
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);\r
+\r
+/* Command path state machine (CPSM) management functions */\r
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);\r
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);\r
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);\r
+\r
+/* Data path state machine (DPSM) management functions */\r
+HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);\r
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);\r
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);\r
+\r
+/* SDMMC Cards mode management functions */\r
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_LL_SDMMC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_usb.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of USB Core HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_LL_USB_H\r
+#define __STM32F7xx_LL_USB_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USB_Core\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** \r
+ * @brief USB Mode definition \r
+ */ \r
+typedef enum \r
+{\r
+ USB_OTG_DEVICE_MODE = 0,\r
+ USB_OTG_HOST_MODE = 1,\r
+ USB_OTG_DRD_MODE = 2\r
+ \r
+}USB_OTG_ModeTypeDef;\r
+\r
+/** \r
+ * @brief URB States definition \r
+ */ \r
+typedef enum {\r
+ URB_IDLE = 0,\r
+ URB_DONE,\r
+ URB_NOTREADY,\r
+ URB_NYET,\r
+ URB_ERROR,\r
+ URB_STALL\r
+ \r
+}USB_OTG_URBStateTypeDef;\r
+\r
+/** \r
+ * @brief Host channel States definition \r
+ */ \r
+typedef enum {\r
+ HC_IDLE = 0,\r
+ HC_XFRC,\r
+ HC_HALTED,\r
+ HC_NAK,\r
+ HC_NYET,\r
+ HC_STALL,\r
+ HC_XACTERR, \r
+ HC_BBLERR, \r
+ HC_DATATGLERR\r
+ \r
+}USB_OTG_HCStateTypeDef;\r
+\r
+/** \r
+ * @brief PCD Initialization Structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t dev_endpoints; /*!< Device Endpoints number.\r
+ This parameter depends on the used USB core. \r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ \r
+ \r
+ uint32_t Host_channels; /*!< Host Channels number.\r
+ This parameter Depends on the used USB core. \r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ \r
+\r
+ uint32_t speed; /*!< USB Core speed.\r
+ This parameter can be any value of @ref USB_Core_Speed_ */ \r
+ \r
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ \r
+\r
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. \r
+ This parameter can be any value of @ref USB_EP0_MPS_ */ \r
+ \r
+ uint32_t phy_itface; /*!< Select the used PHY interface.\r
+ This parameter can be any value of @ref USB_Core_PHY_ */ \r
+ \r
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ \r
+ \r
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */\r
+ \r
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */\r
+ \r
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ \r
+\r
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ \r
+ \r
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ \r
+ \r
+}USB_OTG_CfgTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint8_t num; /*!< Endpoint number\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ \r
+ \r
+ uint8_t is_in; /*!< Endpoint direction\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ \r
+ \r
+ uint8_t is_stall; /*!< Endpoint stall condition\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ \r
+ \r
+ uint8_t type; /*!< Endpoint type\r
+ This parameter can be any value of @ref USB_EP_Type_ */ \r
+ \r
+ uint8_t data_pid_start; /*!< Initial data PID\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */\r
+ \r
+ uint8_t even_odd_frame; /*!< IFrame parity\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */\r
+ \r
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r
+ \r
+ uint32_t maxpacket; /*!< Endpoint Max packet size\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r
+\r
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */\r
+ \r
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */\r
+ \r
+ uint32_t xfer_len; /*!< Current transfer length */\r
+ \r
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */\r
+\r
+}USB_OTG_EPTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint8_t dev_addr ; /*!< USB device address.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ \r
+\r
+ uint8_t ch_num; /*!< Host channel number.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ \r
+ \r
+ uint8_t ep_num; /*!< Endpoint number.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ \r
+ \r
+ uint8_t ep_is_in; /*!< Endpoint direction\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ \r
+ \r
+ uint8_t speed; /*!< USB Host speed.\r
+ This parameter can be any value of @ref USB_Core_Speed_ */\r
+ \r
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */\r
+ \r
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */\r
+\r
+ uint8_t ep_type; /*!< Endpoint Type.\r
+ This parameter can be any value of @ref USB_EP_Type_ */\r
+ \r
+ uint16_t max_packet; /*!< Endpoint Max packet size.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r
+ \r
+ uint8_t data_pid; /*!< Initial data PID.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */\r
+ \r
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */\r
+ \r
+ uint32_t xfer_len; /*!< Current transfer length. */\r
+ \r
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */\r
+ \r
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */\r
+ \r
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */\r
+ \r
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */\r
+ \r
+ uint32_t ErrCnt; /*!< Host channel error count.*/\r
+ \r
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state. \r
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ \r
+ \r
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state. \r
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ \r
+ \r
+}USB_OTG_HCTypeDef;\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PCD_Exported_Constants PCD Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USB_Core_Mode_ USB Core Mode\r
+ * @{\r
+ */\r
+#define USB_OTG_MODE_DEVICE 0\r
+#define USB_OTG_MODE_HOST 1\r
+#define USB_OTG_MODE_DRD 2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_Core_Speed_ USB Core Speed\r
+ * @{\r
+ */ \r
+#define USB_OTG_SPEED_HIGH 0\r
+#define USB_OTG_SPEED_HIGH_IN_FULL 1\r
+#define USB_OTG_SPEED_LOW 2 \r
+#define USB_OTG_SPEED_FULL 3\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USB_Core_PHY_ USB Core PHY\r
+ * @{\r
+ */ \r
+#define USB_OTG_ULPI_PHY 1\r
+#define USB_OTG_EMBEDDED_PHY 2\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USB_Core_MPS_ USB Core MPS\r
+ * @{\r
+ */\r
+#define USB_OTG_HS_MAX_PACKET_SIZE 512\r
+#define USB_OTG_FS_MAX_PACKET_SIZE 64\r
+#define USB_OTG_MAX_EP0_SIZE 64\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency\r
+ * @{\r
+ */\r
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)\r
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)\r
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)\r
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval\r
+ * @{\r
+ */ \r
+#define DCFG_FRAME_INTERVAL_80 0\r
+#define DCFG_FRAME_INTERVAL_85 1\r
+#define DCFG_FRAME_INTERVAL_90 2\r
+#define DCFG_FRAME_INTERVAL_95 3\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_EP0_MPS_ USB EP0 MPS\r
+ * @{\r
+ */\r
+#define DEP0CTL_MPS_64 0\r
+#define DEP0CTL_MPS_32 1\r
+#define DEP0CTL_MPS_16 2\r
+#define DEP0CTL_MPS_8 3\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_EP_Speed_ USB EP Speed\r
+ * @{\r
+ */\r
+#define EP_SPEED_LOW 0\r
+#define EP_SPEED_FULL 1\r
+#define EP_SPEED_HIGH 2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_EP_Type_ USB EP Type\r
+ * @{\r
+ */\r
+#define EP_TYPE_CTRL 0\r
+#define EP_TYPE_ISOC 1\r
+#define EP_TYPE_BULK 2\r
+#define EP_TYPE_INTR 3\r
+#define EP_TYPE_MSK 3\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USB_STS_Defines_ USB STS Defines\r
+ * @{\r
+ */\r
+#define STS_GOUT_NAK 1\r
+#define STS_DATA_UPDT 2\r
+#define STS_XFER_COMP 3\r
+#define STS_SETUP_COMP 4\r
+#define STS_SETUP_UPDT 6\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines\r
+ * @{\r
+ */ \r
+#define HCFG_30_60_MHZ 0\r
+#define HCFG_48_MHZ 1\r
+#define HCFG_6_MHZ 2\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines\r
+ * @{\r
+ */ \r
+#define HPRT0_PRTSPD_HIGH_SPEED 0\r
+#define HPRT0_PRTSPD_FULL_SPEED 1\r
+#define HPRT0_PRTSPD_LOW_SPEED 2\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#define HCCHAR_CTRL 0\r
+#define HCCHAR_ISOC 1\r
+#define HCCHAR_BULK 2\r
+#define HCCHAR_INTR 3\r
+ \r
+#define HC_PID_DATA0 0\r
+#define HC_PID_DATA2 1\r
+#define HC_PID_DATA1 2\r
+#define HC_PID_SETUP 3\r
+\r
+#define GRXSTS_PKTSTS_IN 2\r
+#define GRXSTS_PKTSTS_IN_XFER_COMP 3\r
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5\r
+#define GRXSTS_PKTSTS_CH_HALTED 7\r
+ \r
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)\r
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)\r
+\r
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) \r
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) \r
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) \r
+#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)\r
+\r
+#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) \r
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))\r
+/**\r
+ * @}\r
+ */\r
+/* Exported macro ------------------------------------------------------------*/\r
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\r
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\r
+ \r
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\r
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);\r
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);\r
+void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);\r
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\r
+\r
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);\r
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);\r
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps);\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);\r
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_LL_USB_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HAL module driver.\r
+ * This is the common part of the HAL initialization\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The common HAL driver contains a set of generic and common APIs that can be\r
+ used by the PPP peripheral drivers and the user to start using the HAL. \r
+ [..]\r
+ The HAL contains two APIs' categories: \r
+ (+) Common HAL APIs\r
+ (+) Services HAL APIs\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL HAL\r
+ * @brief HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/**\r
+ * @brief STM32F7xx HAL Driver version number V0.1.0\r
+ */\r
+#define __STM32F7xx_HAL_VERSION_MAIN (0x00) /*!< [31:24] main version */\r
+#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */\r
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7xx_HAL_VERSION_RC))\r
+ \r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static __IO uint32_t uwTick;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Private_Functions HAL Private Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initializes the Flash interface the NVIC allocation and initial clock \r
+ configuration. It initializes the systick also when timeout is needed \r
+ and the backup domain when enabled.\r
+ (+) de-Initializes common part of the HAL\r
+ (+) Configure The time base source to have 1ms time base with a dedicated \r
+ Tick interrupt priority. \r
+ (++) Systick timer is used by default as source of time base, but user \r
+ can eventually implement his proper time base source (a general purpose \r
+ timer for example or other time source), keeping in mind that Time base \r
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \r
+ handled in milliseconds basis.\r
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically \r
+ at the beginning of the program after reset by HAL_Init() or at any time \r
+ when clock is configured, by HAL_RCC_ClockConfig(). \r
+ (++) Source of time base is configured to generate interrupts at regular \r
+ time intervals. Care must be taken if HAL_Delay() is called from a \r
+ peripheral ISR process, the Tick interrupt line must have higher priority \r
+ (numerically lower) than the peripheral interrupt. Otherwise the caller \r
+ ISR process will be blocked. \r
+ (++) functions affecting time base configurations are declared as __weak \r
+ to make override possible in case of other implementations in user file.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is used to initialize the HAL Library; it must be the first \r
+ * instruction to be executed in the main program (before to call any other\r
+ * HAL function), it performs the following:\r
+ * Configure the Flash prefetch, and instruction cache through ART accelerator.\r
+ * Configures the SysTick to generate an interrupt each 1 millisecond,\r
+ * which is clocked by the HSI (at this stage, the clock is not yet\r
+ * configured and thus the system is running from the internal HSI at 16 MHz).\r
+ * Set NVIC Group Priority to 4.\r
+ * Calls the HAL_MspInit() callback function defined in user file \r
+ * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization \r
+ * \r
+ * @note SysTick is used as time base for the HAL_Delay() function, the application\r
+ * need to ensure that the SysTick time base is always set to 1 millisecond\r
+ * to have correct HAL operation.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+ /* Configure Flash prefetch and Instruction cache through ART accelerator */ \r
+#if (ART_ACCLERATOR_ENABLE != 0)\r
+ __HAL_FLASH_ART_ENABLE();\r
+#endif /* ART_ACCLERATOR_ENABLE */\r
+\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r
+ HAL_InitTick(TICK_INT_PRIORITY);\r
+ \r
+ /* Init the low level hardware */\r
+ HAL_MspInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function de-Initializes common part of the HAL and stops the systick.\r
+ * This function is optional. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+ /* Reset of all peripherals */\r
+ __HAL_RCC_APB1_FORCE_RESET();\r
+ __HAL_RCC_APB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB2_FORCE_RESET();\r
+ __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB1_FORCE_RESET();\r
+ __HAL_RCC_AHB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB2_FORCE_RESET();\r
+ __HAL_RCC_AHB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB3_FORCE_RESET();\r
+ __HAL_RCC_AHB3_RELEASE_RESET();\r
+\r
+ /* De-Init the low level hardware */\r
+ HAL_MspDeInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MSP. \r
+ * @retval None\r
+ */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief This function configures the source of the time base.\r
+ * The time source is configured to have 1ms time base with a dedicated \r
+ * Tick interrupt priority.\r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
+ * @note In the default implementation, SysTick timer is the source of time base. \r
+ * It is used to generate interrupts at regular time intervals. \r
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process, \r
+ * The the SysTick interrupt must have higher priority (numerically lower) \r
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+ * The function is declared as __weak to be overwritten in case of other\r
+ * implementation in user file.\r
+ * @param TickPriority: Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ /*Configure the SysTick to have interrupt in 1ms time basis*/\r
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);\r
+\r
+ /*Configure the SysTick IRQ priority */\r
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Group2 HAL Control functions \r
+ * @brief HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### HAL Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Provide a tick value in millisecond\r
+ (+) Provide a blocking delay in millisecond\r
+ (+) Suspend the time base source interrupt\r
+ (+) Resume the time base source interrupt\r
+ (+) Get the HAL API driver version\r
+ (+) Get the device identifier\r
+ (+) Get the device revision identifier\r
+ (+) Enable/Disable Debug module during SLEEP mode\r
+ (+) Enable/Disable Debug module during STOP mode\r
+ (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is called to increment a global variable "uwTick"\r
+ * used as application time base.\r
+ * @note In the default implementation, this variable is incremented each 1ms\r
+ * in Systick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IncTick(void)\r
+{\r
+ uwTick++;\r
+}\r
+\r
+/**\r
+ * @brief Provides a tick value in millisecond.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval tick value\r
+ */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+ return uwTick;\r
+}\r
+\r
+/**\r
+ * @brief This function provides accurate delay (in milliseconds) based \r
+ * on variable incremented.\r
+ * @note In the default implementation , SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals where uwTick\r
+ * is incremented.\r
+ * @note ThiS function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @param Delay: specifies the delay time length, in milliseconds.\r
+ * @retval None\r
+ */\r
+__weak void HAL_Delay(__IO uint32_t Delay)\r
+{\r
+ uint32_t tickstart = 0;\r
+ tickstart = HAL_GetTick();\r
+ while((HAL_GetTick() - tickstart) < Delay)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+ * is called, the the SysTick interrupt will be disabled and so Tick increment \r
+ * is suspended.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+ /* Disable SysTick Interrupt */\r
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+ * is called, the the SysTick interrupt will be enabled and so Tick increment \r
+ * is resumed.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+ /* Enable SysTick Interrupt */\r
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HAL revision\r
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+ return __STM32F7xx_HAL_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_EnableDBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DisableDBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Enables the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_EnableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;\r
+}\r
+\r
+/**\r
+ * @brief Power-down the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_DisableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);\r
+}\r
+\r
+/**\r
+ * @brief Enables the FMC Memory Mapping Swapping.\r
+ * \r
+ * @note SDRAM is accessible at 0x60000000 \r
+ * and NOR/RAM is accessible at 0xC0000000 \r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_EnableFMCMemorySwapping(void)\r
+{\r
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;\r
+}\r
+\r
+/**\r
+ * @brief Disables the FMC Memory Mapping Swapping\r
+ * \r
+ * @note SDRAM is accessible at 0xC0000000 (default mapping) \r
+ * and NOR/RAM is accessible at 0x60000000 (default mapping) \r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_DisableFMCMemorySwapping(void)\r
+{\r
+\r
+ SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + State and errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### ADC Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.\r
+ (#) Interrupt generation at the end of conversion, end of injected conversion, \r
+ and in case of analog watchdog or overrun events\r
+ (#) Single and continuous conversion modes.\r
+ (#) Scan mode for automatic conversion of channel 0 to channel x.\r
+ (#) Data alignment with in-built data coherency.\r
+ (#) Channel-wise programmable sampling time.\r
+ (#) External trigger option with configurable polarity for both regular and \r
+ injected conversion.\r
+ (#) Dual/Triple mode (on devices with 2 ADCs or more).\r
+ (#) Configurable DMA data storage in Dual/Triple ADC mode. \r
+ (#) Configurable delay between conversions in Dual/Triple interleaved mode.\r
+ (#) ADC conversion type (refer to the datasheets).\r
+ (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at \r
+ slower speed.\r
+ (#) ADC input range: VREF(minus) = VIN = VREF(plus).\r
+ (#) DMA request generation during regular channel conversion.\r
+\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r
+ (##) ADC pins configuration\r
+ (+++) Enable the clock for the ADC GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream.\r
+ \r
+ *** Configuration of ADC, groups regular/injected, channels parameters ***\r
+ ==============================================================================\r
+ [..]\r
+ (#) Configure the ADC parameters (resolution, data alignment, ...)\r
+ and regular group parameters (conversion trigger, sequencer, ...)\r
+ using function HAL_ADC_Init().\r
+\r
+ (#) Configure the channels for regular group parameters (channel number, \r
+ channel rank into sequencer, ..., into regular group)\r
+ using function HAL_ADC_ConfigChannel().\r
+\r
+ (#) Optionally, configure the injected group parameters (conversion trigger, \r
+ sequencer, ..., of injected group)\r
+ and the channels for injected group parameters (channel number, \r
+ channel rank into sequencer, ..., into injected group)\r
+ using function HAL_ADCEx_InjectedConfigChannel().\r
+\r
+ (#) Optionally, configure the analog watchdog parameters (channels\r
+ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().\r
+\r
+ (#) Optionally, for devices with several ADC instances: configure the \r
+ multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().\r
+\r
+ *** Execution of ADC conversions ***\r
+ ==============================================================================\r
+ [..] \r
+ (#) ADC driver can be used among three modes: polling, interruption,\r
+ transfer by DMA. \r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start() \r
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r
+ user can specify the value of timeout according to his end application \r
+ (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start_IT() \r
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r
+ (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r
+ (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() \r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r
+ (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADC_ErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()\r
+ \r
+ *** ADC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in ADC HAL driver.\r
+ \r
+ (+) __HAL_ADC_ENABLE : Enable the ADC peripheral\r
+ (+) __HAL_ADC_DISABLE : Disable the ADC peripheral\r
+ (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt\r
+ (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt\r
+ (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled\r
+ (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags\r
+ (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status\r
+ (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register \r
+ \r
+ [..] \r
+ (@) You can refer to the ADC HAL driver header file for more useful macros \r
+\r
+ *** Deinitialization of ADC ***\r
+ ==============================================================================\r
+ [..]\r
+ (#) Disable the ADC interface\r
+ (++) ADC clock can be hard reset and disabled at RCC top level.\r
+ (++) Hard reset of ADC peripherals\r
+ using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().\r
+ (++) ADC clock disable using the equivalent macro/functions as configuration step.\r
+ (+++) Example:\r
+ Into HAL_ADC_MspDeInit() (recommended code location) or with\r
+ other device clock parameters configuration:\r
+ (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);\r
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)\r
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);\r
+\r
+ (#) ADC pins configuration\r
+ (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()\r
+\r
+ (#) Optionally, in case of usage of ADC with interruptions:\r
+ (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)\r
+\r
+ (#) Optionally, in case of usage of DMA:\r
+ (++) Deinitialize the DMA using function HAL_DMA_DeInit().\r
+ (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) \r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC ADC\r
+ * @brief ADC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void ADC_Init(ADC_HandleTypeDef* hadc);\r
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\r
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);\r
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup ADC_Exported_Functions ADC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the ADC. \r
+ (+) De-initialize the ADC. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters \r
+ * in the ADC_InitStruct and initializes the ADC MSP.\r
+ * \r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,\r
+ * the rest of the configuration parameters are specific to the regular\r
+ * channels group (scan mode activation, continuous mode activation,\r
+ * External trigger source and edge, DMA continuous request after the \r
+ * last transfer and End of conversion selection).\r
+ * \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Check ADC handle */\r
+ if(hadc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));\r
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));\r
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));\r
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));\r
+\r
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r
+ {\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ }\r
+\r
+ if(hadc->State == HAL_ADC_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_ADC_MspInit(hadc);\r
+ }\r
+\r
+ /* Initialize the ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY;\r
+ \r
+ /* Set ADC parameters */\r
+ ADC_Init(hadc);\r
+ \r
+ /* Set ADC error code to none */\r
+ hadc->ErrorCode = HAL_ADC_ERROR_NONE;\r
+ \r
+ /* Initialize the ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hadc);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values. \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Check ADC handle */\r
+ if(hadc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_ADC_MspDeInit(hadc);\r
+ \r
+ /* Set ADC error code to none */\r
+ hadc->ErrorCode = HAL_ADC_ERROR_NONE;\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_RESET;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADC MSP.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the ADC MSP.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion of regular channel.\r
+ (+) Stop conversion of regular channel.\r
+ (+) Start conversion of regular channel and enable interrupt.\r
+ (+) Stop conversion of regular channel and disable interrupt.\r
+ (+) Start conversion of regular channel and enable DMA transfer.\r
+ (+) Stop conversion of regular channel and disable DMA transfer.\r
+ (+) Handle ADC interrupt request. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables ADC and starts conversion of the regular channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Check if an injected conversion is ongoing */\r
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_REG;\r
+ } \r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+\r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC and stop conversion of regular channels.\r
+ * \r
+ * @note Caution: This function will stop also injected channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ *\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Disable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Poll for regular conversion complete\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Verification that ADC configuration is compliant with polling for */\r
+ /* each conversion: */\r
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */\r
+ /* several ranks and polling for end of each conversion. */\r
+ /* For code simplicity sake, this particular case is generalized to */\r
+ /* ADC configured in DMA mode and polling for end of each conversion. */\r
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&\r
+ HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )\r
+ {\r
+ /* Update ADC state machine to error */\r
+ hadc->State = HAL_ADC_STATE_ERROR;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check End of conversion flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hadc->State= HAL_ADC_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check if an injected conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_REG;\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Poll for conversion event\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param EventType: the ADC event type.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.\r
+ * @arg ADC_OVR_EVENT: ADC Overrun event.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_EVENT_TYPE(EventType));\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check selected event flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hadc->State= HAL_ADC_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check analog watchdog flag */\r
+ if(EventType == ADC_AWD_EVENT)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_AWD;\r
+ \r
+ /* Clear the ADCx's analog watchdog flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_ERROR;\r
+ \r
+ /* Clear the ADCx's Overrun flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables the interrupt and starts ADC conversion of regular channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Check if an injected conversion is ongoing */\r
+ if(hadc->State == HAL_ADC_STATE_BUSY_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_REG;\r
+ } \r
+ \r
+ /* Set ADC error code to none */\r
+ hadc->ErrorCode = HAL_ADC_ERROR_NONE;\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Enable the ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Enable the ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the interrupt and stop ADC conversion of regular channels.\r
+ * \r
+ * @note Caution: This function will stop also injected channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Disable the ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Disable the ADC end of conversion interrupt for injected group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles ADC interrupt request \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r
+ assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);\r
+ /* Check End of conversion flag for regular channels */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Check if an injected conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_REG;\r
+ }\r
+\r
+ if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r
+ {\r
+ if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)\r
+ { \r
+ /* DISABLE the ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* DISABLE the ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ }\r
+ else\r
+ {\r
+ if (hadc->NbrOfCurrentConversionRank == 0)\r
+ {\r
+ hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;\r
+ }\r
+ \r
+ /* Decrement the number of conversion when an interrupt occurs */\r
+ hadc->NbrOfCurrentConversionRank--;\r
+ \r
+ /* Check if all conversions are finished */\r
+ if(hadc->NbrOfCurrentConversionRank == 0)\r
+ {\r
+ /* DISABLE the ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* DISABLE the ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Conversion complete callback */ \r
+ HAL_ADC_ConvCpltCallback(hadc);\r
+ \r
+ /* Clear the ADCx flag for regular end of conversion */\r
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); \r
+ /* Check End of conversion flag for injected channels */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Check if a regular conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_REG)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ;\r
+ }\r
+ \r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)\r
+ {\r
+ /* DISABLE the ADC end of conversion interrupt for injected group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r
+ }\r
+ \r
+ /* Conversion complete callback */ \r
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);\r
+ \r
+ /* Clear the ADCx flag for injected end of conversion */\r
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); \r
+ /* Check Analog watchdog flag */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_AWD;\r
+ \r
+ /* Clear the ADCx's Analog watchdog flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);\r
+ \r
+ /* Level out of window callback */ \r
+ HAL_ADC_LevelOutOfWindowCallback(hadc);\r
+ }\r
+ \r
+ tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);\r
+ tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);\r
+ /* Check Overrun flag */\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Change ADC state to overrun state */\r
+ hadc->State = HAL_ADC_STATE_ERROR;\r
+ \r
+ /* Set ADC error code to overrun */\r
+ hadc->ErrorCode |= HAL_ADC_ERROR_OVR;\r
+ \r
+ /* Clear the Overrun flag */\r
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);\r
+ \r
+ /* Error callback */ \r
+ HAL_ADC_ErrorCallback(hadc);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Enable ADC DMA mode */\r
+ hadc->Instance->CR2 |= ADC_CR2_DMA;\r
+ \r
+ /* Set the DMA transfer complete callback */\r
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;\r
+ \r
+ /* Set the DMA half transfer complete callback */\r
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_REG;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+\r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for ADC stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= ADC_CR2_SWSTART;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Disable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Disable ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Disable the selected ADC DMA mode */\r
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;\r
+ \r
+ /* Disable the ADC DMA Stream */\r
+ HAL_DMA_Abort(hadc->DMA_Handle);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets the converted value from data register of regular channel.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval Converted value\r
+ */\r
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)\r
+{ \r
+ /* Return the selected ADC converted value */ \r
+ return hadc->Instance->DR;\r
+}\r
+\r
+/**\r
+ * @brief Regular conversion complete callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Regular conversion half DMA transfer callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Analog watchdog callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error ADC callback.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure regular channels. \r
+ (+) Configure injected channels.\r
+ (+) Configure multimode.\r
+ (+) Configure the analog watch dog.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param sConfig: ADC configuration structure. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)\r
+{\r
+ __IO uint32_t counter = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r
+ if (sConfig->Channel > ADC_CHANNEL_9)\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);\r
+ }\r
+ \r
+ /* For Rank 1 to 6 */\r
+ if (sConfig->Rank < 7)\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (sConfig->Rank < 13)\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ /* For Rank 13 to 16 */\r
+ else\r
+ {\r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);\r
+ }\r
+ \r
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */\r
+ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))\r
+ {\r
+ /* Enable the VBAT channel*/\r
+ ADC->CCR |= ADC_CCR_VBATE;\r
+ }\r
+ \r
+ /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r
+ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))\r
+ {\r
+ /* Enable the TSVREFE channel*/\r
+ ADC->CCR |= ADC_CCR_TSVREFE;\r
+\r
+ if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))\r
+ {\r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure \r
+ * that contains the configuration information of ADC analog watchdog.\r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)\r
+{\r
+#ifdef USE_FULL_ASSERT \r
+ uint32_t tmp = 0;\r
+#endif /* USE_FULL_ASSERT */ \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));\r
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));\r
+\r
+#ifdef USE_FULL_ASSERT \r
+ tmp = ADC_GET_RESOLUTION(hadc);\r
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));\r
+ assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));\r
+#endif /* USE_FULL_ASSERT */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ if(AnalogWDGConfig->ITMode == ENABLE)\r
+ {\r
+ /* Enable the ADC Analog watchdog interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Analog watchdog interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);\r
+ }\r
+ \r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);\r
+ \r
+ /* Set the analog watchdog enable mode */\r
+ hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;\r
+ \r
+ /* Set the high threshold */\r
+ hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;\r
+ \r
+ /* Set the low threshold */\r
+ hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;\r
+ \r
+ /* Clear the Analog watchdog channel select bits */\r
+ hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;\r
+ \r
+ /* Set the Analog watchdog channel */\r
+ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions\r
+ * @brief ADC Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the ADC state\r
+ (+) Check the ADC Error\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the ADC state\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL state\r
+ */\r
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Return ADC state */\r
+ return hadc->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the ADC error code\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval ADC Error Code\r
+ */\r
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)\r
+{\r
+ return hadc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters \r
+ * in the ADC_InitStruct without initializing the ADC MSP. \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @retval None\r
+ */\r
+static void ADC_Init(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Set ADC parameters */\r
+ /* Set the ADC clock prescaler */\r
+ ADC->CCR &= ~(ADC_CCR_ADCPRE);\r
+ ADC->CCR |= hadc->Init.ClockPrescaler;\r
+ \r
+ /* Set ADC scan mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);\r
+ hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);\r
+ \r
+ /* Set ADC resolution */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_RES);\r
+ hadc->Instance->CR1 |= hadc->Init.Resolution;\r
+ \r
+ /* Set ADC data alignment */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);\r
+ hadc->Instance->CR2 |= hadc->Init.DataAlign;\r
+ \r
+ /* Enable external trigger if trigger selection is different of software */\r
+ /* start. */\r
+ /* Note: This configuration keeps the hardware feature of parameter */\r
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */\r
+ /* software start. */\r
+ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r
+ {\r
+ /* Select external trigger to start conversion */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;\r
+ \r
+ /* Select external trigger polarity */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r
+ hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the external trigger */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r
+ }\r
+ \r
+ /* Enable or disable ADC continuous conversion mode */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_CONT);\r
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);\r
+ \r
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)\r
+ {\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));\r
+ \r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ \r
+ /* Set the number of channels to be converted in discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);\r
+ hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);\r
+ }\r
+ \r
+ /* Set ADC number of conversion */\r
+ hadc->Instance->SQR1 &= ~(ADC_SQR1_L);\r
+ hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);\r
+ \r
+ /* Enable or disable ADC DMA continuous request */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_DDS);\r
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);\r
+ \r
+ /* Enable or disable ADC end of conversion selection */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);\r
+ hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);\r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Check if an injected conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_REG;\r
+ }\r
+ \r
+ HAL_ADC_ConvCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvHalfCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hadc->State= HAL_ADC_STATE_ERROR;\r
+ /* Set ADC error code to DMA error */\r
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r
+ HAL_ADC_ErrorCallback(hadc); \r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_adc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the ADC extension peripheral:\r
+ * + Extended features functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r
+ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r
+ (##) ADC pins configuration\r
+ (+++) Enable the clock for the ADC GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r
+ (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r
+ (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the ADC DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream. \r
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment \r
+ using the HAL_ADC_Init() function. \r
+ \r
+ (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()\r
+ and HAL_ADC_ConfigChannel() functions.\r
+ \r
+ (#) Three operation modes are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() \r
+ (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r
+ user can specify the value of timeout according to his end application \r
+ (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() \r
+ (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r
+ (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r
+ (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()\r
+ \r
+ \r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r
+ (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r
+ (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()\r
+ \r
+ *** Multi mode ADCs Regular channels configuration ***\r
+ ======================================================\r
+ [..] \r
+ (+) Select the Multi mode ADC regular channels features (dual or triple mode) \r
+ and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. \r
+ (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.\r
+ \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADCEx ADCEx\r
+ * @brief ADC Extended driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup ADCEx_Private_Functions\r
+ * @{\r
+ */\r
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);\r
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);\r
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup ADCEx_Exported_Functions ADC Exported Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion of injected channel.\r
+ (+) Stop conversion of injected channel.\r
+ (+) Start multimode and enable DMA transfer.\r
+ (+) Stop multimode and disable DMA transfer.\r
+ (+) Get result of injected channel conversion.\r
+ (+) Get result of multimode conversion.\r
+ (+) Configure injected channels.\r
+ (+) Configure multimode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Check if a regular conversion is ongoing */\r
+ if(hadc->State == HAL_ADC_STATE_BUSY_REG)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ;\r
+ } \r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if((hadc->Instance == ADC1) && tmp1 && tmp2) \r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the interrupt and starts ADC conversion of injected channels.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ *\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ uint32_t tmp1 = 0, tmp2 =0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Check if a regular conversion is ongoing */\r
+ if(hadc->State == HAL_ADC_STATE_BUSY_REG)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_INJ;\r
+ }\r
+ \r
+ /* Set ADC error code to none */\r
+ hadc->ErrorCode = HAL_ADC_ERROR_NONE;\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* Enable the ADC end of conversion interrupt for injected group */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);\r
+ \r
+ /* Enable the ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Check if Multimode enabled */\r
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if(tmp1 && tmp2)\r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r
+ if((hadc->Instance == ADC1) && tmp1 && tmp2) \r
+ {\r
+ /* Enable the selected ADC software conversion for injected group */\r
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r
+ }\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC and stop conversion of injected channels.\r
+ *\r
+ * @note Caution: This function will stop also regular channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Disable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Poll for injected conversion complete\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param Timeout: Timeout value in millisecond. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check End of conversion flag */\r
+ while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hadc->State= HAL_ADC_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check if a regular conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_REG)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ;\r
+ }\r
+ \r
+ /* Return ADC state */\r
+ return HAL_OK;\r
+} \r
+ \r
+/**\r
+ * @brief Disables the interrupt and stop ADC conversion of injected channels.\r
+ * \r
+ * @note Caution: This function will stop also regular channels. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Disable the ADC end of conversion interrupt for regular group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r
+ \r
+ /* Disable the ADC end of conversion interrupt for injected group */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets the converted value from data register of injected channel.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param InjectedRank: the ADC injected rank.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected\r
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected\r
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected\r
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected\r
+ * @retval None\r
+ */\r
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));\r
+ \r
+ /* Clear the ADCx's flag for injected end of conversion */\r
+ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);\r
+ \r
+ /* Return the selected ADC converted value */ \r
+ switch(InjectedRank)\r
+ { \r
+ case ADC_INJECTED_RANK_4:\r
+ {\r
+ tmp = hadc->Instance->JDR4;\r
+ } \r
+ break;\r
+ case ADC_INJECTED_RANK_3: \r
+ { \r
+ tmp = hadc->Instance->JDR3;\r
+ } \r
+ break;\r
+ case ADC_INJECTED_RANK_2: \r
+ { \r
+ tmp = hadc->Instance->JDR2;\r
+ }\r
+ break;\r
+ case ADC_INJECTED_RANK_1:\r
+ {\r
+ tmp = hadc->Instance->JDR1;\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral\r
+ * \r
+ * @note Caution: This function must be used only with the ADC master. \r
+ *\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. \r
+ * @param Length: The length of data to be transferred from ADC peripheral to memory. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r
+{\r
+ __IO uint32_t counter = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable ADC overrun interrupt */\r
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ if (hadc->Init.DMAContinuousRequests != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADC->CCR |= ADC_CCR_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADC->CCR &= ~ADC_CCR_DDS;\r
+ }\r
+ \r
+ /* Set the DMA transfer complete callback */\r
+ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;\r
+ \r
+ /* Set the DMA half transfer complete callback */\r
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_BUSY_REG;\r
+ \r
+ /* Check if ADC peripheral is disabled in order to enable it and wait during \r
+ Tstab time the ADC's stabilization */\r
+ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r
+ { \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_ENABLE(hadc);\r
+ \r
+ /* Delay for temperature sensor stabilization time */\r
+ /* Compute number of CPU cycles to wait for */\r
+ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r
+ while(counter != 0)\r
+ {\r
+ counter--;\r
+ }\r
+ }\r
+ \r
+ /* if no external trigger present enable software conversion of regular channels */\r
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r
+ {\r
+ /* Enable the selected ADC software conversion for regular group */\r
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_ADC_DISABLE(hadc);\r
+ \r
+ /* Disable ADC overrun interrupt */\r
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r
+ \r
+ /* Disable the selected ADC DMA request after last transfer */\r
+ ADC->CCR &= ~ADC_CCR_DDS;\r
+ \r
+ /* Disable the ADC DMA Stream */\r
+ HAL_DMA_Abort(hadc->DMA_Handle);\r
+ \r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results \r
+ * data in the selected multi mode.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval The converted data value.\r
+ */\r
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* Return the multi mode conversion value */\r
+ return ADC->CDR;\r
+}\r
+\r
+/**\r
+ * @brief Injected conversion complete callback in non blocking mode \r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param hadc: pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC.\r
+ * @param sConfigInjected: ADC configuration structure for injected channel. \r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)\r
+{\r
+\r
+#ifdef USE_FULL_ASSERT \r
+ uint32_t tmp = 0;\r
+#endif /* USE_FULL_ASSERT */\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));\r
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));\r
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));\r
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));\r
+\r
+#ifdef USE_FULL_ASSERT\r
+ tmp = ADC_GET_RESOLUTION(hadc);\r
+ assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r
+ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Clear the old sample time */\r
+ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);\r
+ \r
+ /* Set the new sample time */\r
+ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r
+ }\r
+ \r
+ /*---------------------------- ADCx JSQR Configuration -----------------*/\r
+ hadc->Instance->JSQR &= ~(ADC_JSQR_JL);\r
+ hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);\r
+ \r
+ /* Rank configuration */\r
+ \r
+ /* Clear the old SQx bits for the selected rank */\r
+ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r
+ \r
+ /* Set the SQx bits for the selected rank */\r
+ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r
+\r
+ /* Select external trigger to start conversion */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;\r
+ \r
+ /* Select external trigger polarity */\r
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);\r
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;\r
+ \r
+ if (sConfigInjected->AutoInjectedConv != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ hadc->Instance->CR1 |= ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);\r
+ }\r
+ \r
+ if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ hadc->Instance->CR1 |= ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);\r
+ }\r
+ \r
+ switch(sConfigInjected->InjectedRank)\r
+ {\r
+ case 1:\r
+ /* Set injected channel 1 offset */\r
+ hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);\r
+ hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ case 2:\r
+ /* Set injected channel 2 offset */\r
+ hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);\r
+ hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ case 3:\r
+ /* Set injected channel 3 offset */\r
+ hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);\r
+ hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ default:\r
+ /* Set injected channel 4 offset */\r
+ hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);\r
+ hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;\r
+ break;\r
+ }\r
+ \r
+ /* if ADC1 Channel_18 is selected enable VBAT Channel */\r
+ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))\r
+ {\r
+ /* Enable the VBAT channel*/\r
+ ADC->CCR |= ADC_CCR_VBATE;\r
+ }\r
+ \r
+ /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r
+ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))\r
+ {\r
+ /* Enable the TSVREFE channel*/\r
+ ADC->CCR |= ADC_CCR_TSVREFE;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADC multi-mode \r
+ * @param hadc : pointer to a ADC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified ADC. \r
+ * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains \r
+ * the configuration information for multimode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_MODE(multimode->Mode));\r
+ assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));\r
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hadc);\r
+ \r
+ /* Set ADC mode */\r
+ ADC->CCR &= ~(ADC_CCR_MULTI);\r
+ ADC->CCR |= multimode->Mode;\r
+ \r
+ /* Set the ADC DMA access mode */\r
+ ADC->CCR &= ~(ADC_CCR_DMA);\r
+ ADC->CCR |= multimode->DMAAccessMode;\r
+ \r
+ /* Set delay between two sampling phases */\r
+ ADC->CCR &= ~(ADC_CCR_DELAY);\r
+ ADC->CCR |= multimode->TwoSamplingDelay;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hadc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @brief DMA transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Check if an injected conversion is ready */\r
+ if(hadc->State == HAL_ADC_STATE_EOC_INJ)\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; \r
+ }\r
+ else\r
+ {\r
+ /* Change ADC state */\r
+ hadc->State = HAL_ADC_STATE_EOC_REG;\r
+ }\r
+ \r
+ HAL_ADC_ConvCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_ADC_ConvHalfCpltCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hadc->State= HAL_ADC_STATE_ERROR;\r
+ /* Set ADC error code to DMA error */\r
+ hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r
+ HAL_ADC_ErrorCallback(hadc); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_can.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CAN HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Controller Area Network (CAN) peripheral:\r
+ * + Initialization and de-initialization functions \r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Error functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) Enable the CAN controller interface clock using \r
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN1_CLK_ENABLE() for CAN2\r
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.\r
+ \r
+ (#) CAN pins configuration\r
+ (++) Enable the clock for the CAN GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (++) Connect and configure the involved CAN pins to AF9 using the \r
+ following function HAL_GPIO_Init() \r
+ \r
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function. \r
+ \r
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.\r
+ \r
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission and wait the end of this operation \r
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout\r
+ according to his end application\r
+ (+) Start the CAN peripheral reception and wait the end of this operation \r
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout\r
+ according to his end application \r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()\r
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() \r
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine\r
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback \r
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback\r
+ \r
+ *** CAN HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in CAN HAL driver.\r
+ \r
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts\r
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts\r
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled\r
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags\r
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status\r
+ \r
+ [..] \r
+ (@) You can refer to the CAN HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN CAN\r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+ \r
+#ifdef HAL_CAN_MODULE_ENABLED \r
+\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CAN_Private_Constants\r
+ * @{\r
+ */\r
+#define CAN_TIMEOUT_VALUE 10\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Functions CAN Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the CAN. \r
+ (+) De-initialize the CAN. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t InitStatus = 3;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));\r
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));\r
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));\r
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));\r
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));\r
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\r
+ \r
+\r
+ if(hcan->State == HAL_CAN_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware */\r
+ HAL_CAN_MspInit(hcan);\r
+ }\r
+ \r
+ /* Initialize the CAN state*/\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* Exit from sleep mode */\r
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
+\r
+ /* Request initialisation */\r
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledge */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_INITSTATUS_FAILED;\r
+ }\r
+ else \r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (hcan->Init.TTCM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (hcan->Init.ABOM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (hcan->Init.AWUM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (hcan->Init.NART == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (hcan->Init.RFLM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (hcan->Init.TXFP == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \\r
+ ((uint32_t)hcan->Init.SJW) | \\r
+ ((uint32_t)hcan->Init.BS1) | \\r
+ ((uint32_t)hcan->Init.BS2) | \\r
+ ((uint32_t)hcan->Init.Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledged */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_INITSTATUS_FAILED;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CAN_INITSTATUS_SUCCESS;\r
+ }\r
+ }\r
+ \r
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)\r
+ {\r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR;\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the CAN reception filter according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that\r
+ * contains the filter configuration information.\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)\r
+{\r
+ uint32_t filternbrbitpos = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));\r
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));\r
+ \r
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;\r
+ \r
+ /* Select the start slave bank */\r
+ CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);\r
+ CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);\r
+ \r
+ /* Filter Deactivation */\r
+ CAN1->FA1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* Filter Scale */\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN1->FS1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);\r
+ }\r
+\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN1->FS1R |= filternbrbitpos;\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN1->FM1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN1->FM1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN1->FFA1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (sFilterConfig->FilterActivation == ENABLE)\r
+ {\r
+ CAN1->FA1R |= filternbrbitpos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the CANx peripheral registers to their default reset values. \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_CAN_MspDeInit(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a CAN frame message.\r
+ (+) Receive a CAN frame message.\r
+ (+) Enter CAN peripheral in sleep mode. \r
+ (+) Wake up the CAN peripheral from sleep mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)\r
+{\r
+ uint32_t transmitmailbox = 5;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = 0;\r
+ }\r
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = 1;\r
+ }\r
+ else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmitmailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ }\r
+\r
+ if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)\r
+ {\r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check End of transmission flag */\r
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t transmitmailbox = 5;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+ \r
+ tmp = hcan->State;\r
+ if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = 0;\r
+ }\r
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = 1;\r
+ }\r
+ else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmitmailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ }\r
+\r
+ if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)\r
+ {\r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Enable Error warning Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Enable Error passive Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Enable Bus-off Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Enable Last error code Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Enable Error Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);\r
+ \r
+ /* Enable Transmit mailbox empty Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);\r
+ \r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: FIFO Number value\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check pending message */\r
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ \r
+ /* Release the FIFO */\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Release FIFO0 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ }\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ /* Release FIFO1 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ tmp = hcan->State;\r
+ if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))\r
+ {\r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Enable Error warning Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Enable Error passive Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Enable Bus-off Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Enable Last error code Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Enable Error Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Enable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ else\r
+ {\r
+ /* Enable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters the Sleep (low power) mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Request Sleep mode */\r
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral\r
+ * is in the normal mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Wake up request */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Sleep mode status */\r
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles CAN interrupt request \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;\r
+ \r
+ /* Check End of transmission flag */\r
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))\r
+ {\r
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);\r
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);\r
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);\r
+ if(tmp1 || tmp2 || tmp3) \r
+ {\r
+ /* Call transmit function */\r
+ CAN_Transmit_IT(hcan);\r
+ }\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);\r
+ /* Check End of reception flag for FIFO0 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO0);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);\r
+ /* Check End of reception flag for FIFO1 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Error Warning Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EWG error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;\r
+ /* Clear Error Warning Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Error Passive Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EPV error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;\r
+ /* Clear Error Passive Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Bus-Off Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to BOF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;\r
+ /* Clear Bus-Off Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);\r
+ }\r
+ \r
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Last error code Flag */\r
+ if((!tmp1) && tmp2 && tmp3)\r
+ {\r
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;\r
+ switch(tmp1)\r
+ {\r
+ case(CAN_ESR_LEC_0):\r
+ /* Set CAN error code to STF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;\r
+ break;\r
+ case(CAN_ESR_LEC_1):\r
+ /* Set CAN error code to FOR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;\r
+ break;\r
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to ACK error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;\r
+ break;\r
+ case(CAN_ESR_LEC_2):\r
+ /* Set CAN error code to BR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to BD error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\r
+ /* Set CAN error code to CRC error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Clear Last error code Flag */ \r
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);\r
+ }\r
+\r
+ /* Call the Error call Back in case of Errors */\r
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)\r
+ {\r
+ /* Set the CAN state ready to be able to start again the process */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ /* Call Error callback function */\r
+ HAL_CAN_ErrorCallback(hcan);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error CAN callback.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions\r
+ * @brief CAN Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Check the CAN state.\r
+ (+) Check CAN Errors detected during interrupt process\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the CAN state\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL state\r
+ */\r
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Return CAN state */\r
+ return hcan->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the CAN error code\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval CAN Error Code\r
+ */\r
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\r
+{\r
+ return hcan->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Disable Transmit mailbox empty Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)\r
+ { \r
+ /* Disable Error warning Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Disable Error passive Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Disable Bus-off Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Disable Last error code Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Disable Error Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+ \r
+ /* Transmission complete callback */ \r
+ HAL_CAN_TxCpltCallback(hcan);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ \r
+ /* Disable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ \r
+ /* Disable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)\r
+ { \r
+ /* Disable Error warning Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Disable Error passive Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Disable Bus-off Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Disable Last error code Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Disable Error Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Disable CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+\r
+ /* Receive complete callback */ \r
+ HAL_CAN_RxCpltCallback(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cec.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CEC HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the High Definition Multimedia Interface \r
+ * Consumer Electronics Control Peripheral (CEC).\r
+ * + Initialization and de-initialization function\r
+ * + IO operation function\r
+ * + Peripheral Control function\r
+ *\r
+ * \r
+ @verbatim \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The CEC HAL driver can be used as follow:\r
+ \r
+ (#) Declare a CEC_HandleTypeDef handle structure.\r
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:\r
+ (##) Enable the CEC interface clock.\r
+ (##) CEC pins configuration:\r
+ (+) Enable the clock for the CEC GPIOs.\r
+ (+) Configure these CEC pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()\r
+ and HAL_CEC_Receive_IT() APIs):\r
+ (+) Configure the CEC interrupt priority.\r
+ (+) Enable the NVIC CEC IRQ handle.\r
+ (@) The specific CEC interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit \r
+ and receive process.\r
+\r
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in\r
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical\r
+ address and Listen mode in the hcec Init structure.\r
+\r
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.\r
+ \r
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customed HAL_CEC_MspInit() API.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC CEC \r
+ * @brief HAL CEC module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup CEC_Private_Constants CEC Private Constants\r
+ * @{\r
+ */\r
+#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \\r
+ | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \\r
+ | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup CEC_Private_Functions CEC Private Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);\r
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CEC_Exported_Functions CEC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the CEC\r
+ (+) The following parameters need to be configured: \r
+ (++) SignalFreeTime\r
+ (++) Tolerance \r
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)\r
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)\r
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)\r
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)\r
+ (++) SignalFreeTimeOption (SFT Timer start definition)\r
+ (++) OwnAddress (CEC device address)\r
+ (++) ListenMode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CEC mode according to the specified\r
+ * parameters in the CEC_InitTypeDef and creates the associated handle .\r
+ * @param hcec: CEC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)\r
+{\r
+ uint32_t tmpreg = 0x0;\r
+ \r
+ /* Check the CEC handle allocation */\r
+ if(hcec == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));\r
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); \r
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));\r
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));\r
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));\r
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));\r
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); \r
+ assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); \r
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));\r
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); \r
+\r
+ \r
+ if(hcec->State == HAL_CEC_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_CEC_MspInit(hcec);\r
+ }\r
+ \r
+ hcec->State = HAL_CEC_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ tmpreg = hcec->Init.SignalFreeTime;\r
+ tmpreg |= hcec->Init.Tolerance;\r
+ tmpreg |= hcec->Init.BRERxStop;\r
+ tmpreg |= hcec->Init.BREErrorBitGen;\r
+ tmpreg |= hcec->Init.LBPEErrorBitGen;\r
+ tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;\r
+ tmpreg |= hcec->Init.SignalFreeTimeOption;\r
+ tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);\r
+ tmpreg |= hcec->Init.ListenMode;\r
+ \r
+ /* Write to CEC Control Register */\r
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ hcec->State = HAL_CEC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CEC peripheral \r
+ * @param hcec: CEC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* Check the CEC handle allocation */\r
+ if(hcec == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r
+\r
+ hcec->State = HAL_CEC_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_CEC_MspDeInit(hcec);\r
+ /* Disable the Peripheral */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ hcec->State = HAL_CEC_STATE_RESET;\r
+ \r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief CEC MSP Init\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief CEC MSP DeInit\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions \r
+ * @brief CEC Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### I/O operation functions ##### \r
+ =============================================================================== \r
+ This subsection provides a set of functions allowing to manage the CEC data transfers.\r
+ \r
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)\r
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)\r
+ \r
+ (#) There are two mode of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode. \r
+ The HAL status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (+) No-Blocking mode: The communication is performed using Interrupts. \r
+ These API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated CEC IRQ when using Interrupt mode.\r
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks \r
+ will be executed respectivelly at the end of the transmit or Receive process\r
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication \r
+ error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_CEC_Transmit()\r
+ (+) HAL_CEC_Receive() \r
+ \r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_CEC_Transmit_IT()\r
+ (+) HAL_CEC_Receive_IT()\r
+ (+) HAL_CEC_IRQHandler()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (+) HAL_CEC_TxCpltCallback()\r
+ (+) HAL_CEC_RxCpltCallback()\r
+ (+) HAL_CEC_ErrorCallback()\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send data in blocking mode \r
+ * @param hcec: CEC handle\r
+ * @param DestinationAddress: destination logical address \r
+ * @param pData: pointer to input byte data buffer\r
+ * @param Size: amount of data to be sent in bytes (without counting the header).\r
+ * 0 means only the header is sent (ping operation).\r
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). \r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)\r
+{\r
+ uint8_t temp = 0; \r
+ uint32_t tempisr = 0; \r
+ uint32_t tickstart = 0;\r
+\r
+ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) \r
+ {\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ if((pData == NULL ) && (Size > 0)) \r
+ {\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ assert_param(IS_CEC_ADDRESS(DestinationAddress)); \r
+ assert_param(IS_CEC_MSGSIZE(Size));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ \r
+ hcec->State = HAL_CEC_STATE_BUSY_TX;\r
+\r
+ hcec->TxXferCount = Size;\r
+ \r
+ /* case no data to be sent, sender is only pinging the system */\r
+ if (Size == 0)\r
+ {\r
+ /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ \r
+ /* send header block */\r
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;\r
+ hcec->Instance->TXDR = temp;\r
+ /* Set TX Start of Message (TXSOM) bit */\r
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);\r
+ \r
+ while (hcec->TxXferCount > 0)\r
+ {\r
+ hcec->TxXferCount--;\r
+\r
+ tickstart = HAL_GetTick();\r
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > Timeout)\r
+ {\r
+ hcec->State = HAL_CEC_STATE_TIMEOUT; \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec); \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+\r
+ /* check whether error occured while waiting for TXBR to be set:\r
+ * has Tx underrun occurred ?\r
+ * has Tx error occurred ?\r
+ * has Tx Missing Acknowledge error occurred ? \r
+ * has Arbitration Loss error occurred ? */\r
+ tempisr = hcec->Instance->ISR;\r
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)\r
+ {\r
+ /* copy ISR for error handling purposes */\r
+ hcec->ErrorCode = tempisr;\r
+ /* clear all error flags by default */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ __HAL_UNLOCK(hcec);\r
+ return HAL_ERROR; \r
+ }\r
+ } \r
+ /* TXBR to clear BEFORE writing TXDR register */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);\r
+ if (hcec->TxXferCount == 0)\r
+ {\r
+ /* if last byte transmission, set TX End of Message (TXEOM) bit */\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ hcec->Instance->TXDR = *pData++;\r
+ \r
+ /* error check after TX byte write up */\r
+ tempisr = hcec->Instance->ISR;\r
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)\r
+ {\r
+ /* copy ISR for error handling purposes */\r
+ hcec->ErrorCode = tempisr;\r
+ /* clear all error flags by default */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ __HAL_UNLOCK(hcec);\r
+ return HAL_ERROR; \r
+ }\r
+ } /* end while (while (hcec->TxXferCount > 0)) */\r
+ \r
+ \r
+ /* if no error up to this point, check that transmission is \r
+ * complete, that is wait until TXEOM is reset */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > Timeout)\r
+ {\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ __HAL_UNLOCK(hcec); \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+\r
+ /* Final error check once all bytes have been transmitted */\r
+ tempisr = hcec->Instance->ISR;\r
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)\r
+ {\r
+ /* copy ISR for error handling purposes */\r
+ hcec->ErrorCode = tempisr;\r
+ /* clear all error flags by default */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ __HAL_UNLOCK(hcec);\r
+ return HAL_ERROR; \r
+ } \r
+\r
+ hcec->State = HAL_CEC_STATE_READY;\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. \r
+ * @param hcec: CEC handle\r
+ * @param pData: pointer to received data buffer.\r
+ * @param Timeout: Timeout duration.\r
+ * Note that the received data size is not known beforehand, the latter is known\r
+ * when the reception is complete and is stored in hcec->RxXferSize. \r
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).\r
+ * If only a header is received, hcec->RxXferSize = 0 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)\r
+{ \r
+ uint32_t temp;\r
+ uint32_t tickstart = 0; \r
+\r
+ if (hcec->State == HAL_CEC_STATE_READY)\r
+ { \r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ if (pData == NULL ) \r
+ {\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ hcec->RxXferSize = 0;\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ \r
+ \r
+ /* Rx loop until CEC_ISR_RXEND is set */\r
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))\r
+ {\r
+ tickstart = HAL_GetTick();\r
+ /* Wait for next byte to be received */\r
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > Timeout)\r
+ {\r
+ hcec->State = HAL_CEC_STATE_TIMEOUT;\r
+ __HAL_UNLOCK(hcec); \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* any error so far ? \r
+ * has Rx Missing Acknowledge occurred ?\r
+ * has Rx Long Bit Period error occurred ?\r
+ * has Rx Short Bit Period error occurred ? \r
+ * has Rx Bit Rising error occurred ? \r
+ * has Rx Overrun error occurred ? */\r
+ temp = (uint32_t) (hcec->Instance->ISR);\r
+ if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)\r
+ {\r
+ /* copy ISR for error handling purposes */\r
+ hcec->ErrorCode = temp;\r
+ /* clear all error flags by default */\r
+ __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ __HAL_UNLOCK(hcec);\r
+ return HAL_ERROR; \r
+ }\r
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */\r
+ \r
+\r
+ /* read received data */\r
+ *pData++ = hcec->Instance->RXDR;\r
+ temp = (uint32_t) (hcec->Instance->ISR);\r
+ /* end of message ? */\r
+ if ((temp & CEC_ISR_RXEND) != 0) \r
+ {\r
+ assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));\r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);\r
+ hcec->State = HAL_CEC_STATE_READY; \r
+ __HAL_UNLOCK(hcec); \r
+ return HAL_OK; \r
+ }\r
+ \r
+ /* clear Rx-Byte Received flag */\r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); \r
+ /* increment payload byte counter */\r
+ hcec->RxXferSize++;\r
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ \r
+ \r
+ /* if the instructions below are executed, it means RXEND was set when RXBR was \r
+ * set for the first time:\r
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"\r
+ * loop has not been executed and this means a single byte has been sent */\r
+ *pData++ = hcec->Instance->RXDR;\r
+ /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ \r
+ hcec->RxXferSize = 0;\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);\r
+ \r
+ hcec->State = HAL_CEC_STATE_READY; \r
+ __HAL_UNLOCK(hcec); \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send data in interrupt mode \r
+ * @param hcec: CEC handle \r
+ * @param DestinationAddress: destination logical address \r
+ * @param pData: pointer to input byte data buffer\r
+ * @param Size: amount of data to be sent in bytes (without counting the header).\r
+ * 0 means only the header is sent (ping operation).\r
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)\r
+{\r
+ uint8_t temp = 0; \r
+ /* if the IP isn't already busy and if there is no previous transmission\r
+ already pending due to arbitration lost */\r
+ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) \r
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) \r
+ { \r
+ if((pData == NULL ) && (Size > 0)) \r
+ {\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ assert_param(IS_CEC_ADDRESS(DestinationAddress)); \r
+ assert_param(IS_CEC_MSGSIZE(Size));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ hcec->pTxBuffPtr = pData;\r
+ hcec->State = HAL_CEC_STATE_BUSY_TX;\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ \r
+ /* Disable Peripheral to write CEC_IER register */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Enable the following two CEC Transmission interrupts as\r
+ * well as the following CEC Transmission Errors interrupts: \r
+ * Tx Byte Request IT \r
+ * End of Transmission IT\r
+ * Tx Missing Acknowledge IT\r
+ * Tx-Error IT\r
+ * Tx-Buffer Underrun IT \r
+ * Tx arbitration lost */\r
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ /* initialize the number of bytes to send,\r
+ * 0 means only one header is sent (ping operation) */\r
+ hcec->TxXferCount = Size;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec); \r
+ \r
+ /* in case of no payload (Size = 0), sender is only pinging the system;\r
+ * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */\r
+ if (Size == 0)\r
+ {\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ \r
+ /* send header block */\r
+ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;\r
+ hcec->Instance->TXDR = temp;\r
+ /* Set TX Start of Message (TXSOM) bit */\r
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ /* if the IP is already busy or if there is a previous transmission\r
+ already pending due to arbitration loss */\r
+ else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)\r
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))\r
+ {\r
+ __HAL_LOCK(hcec);\r
+ /* set state to BUSY TX, in case it wasn't set already (case\r
+ * of transmission new attempt after arbitration loss) */\r
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)\r
+ {\r
+ hcec->State = HAL_CEC_STATE_BUSY_TX;\r
+ }\r
+\r
+ /* if all data have been sent */\r
+ if(hcec->TxXferCount == 0)\r
+ {\r
+ /* Disable Peripheral to write CEC_IER register */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Disable the CEC Transmission Interrupts */\r
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);\r
+ /* Disable the CEC Transmission Error Interrupts */\r
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);\r
+ \r
+ hcec->State = HAL_CEC_STATE_READY;\r
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to\r
+ start again the Transmission under the Tx call back API */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ HAL_CEC_TxCpltCallback(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if (hcec->TxXferCount == 1)\r
+ {\r
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ /* clear Tx-Byte request flag */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); \r
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r
+ hcec->TxXferCount--;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive data in interrupt mode. \r
+ * @param hcec: CEC handle\r
+ * @param pData: pointer to received data buffer.\r
+ * Note that the received data size is not known beforehand, the latter is known\r
+ * when the reception is complete and is stored in hcec->RxXferSize. \r
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).\r
+ * If only a header is received, hcec->RxXferSize = 0 \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)\r
+{ \r
+ if(hcec->State == HAL_CEC_STATE_READY)\r
+ {\r
+ if(pData == NULL ) \r
+ {\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ hcec->RxXferSize = 0;\r
+ hcec->pRxBuffPtr = pData;\r
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r
+ /* the IP is moving to a ready to receive state */\r
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;\r
+\r
+ /* Disable Peripheral to write CEC_IER register */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Enable the following CEC Reception Error Interrupts: \r
+ * Rx overrun\r
+ * Rx bit rising error\r
+ * Rx short bit period error\r
+ * Rx long bit period error\r
+ * Rx missing acknowledge */\r
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ /* Enable the following two CEC Reception interrupts: \r
+ * Rx Byte Received IT \r
+ * End of Reception IT */\r
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);\r
+ \r
+ __HAL_CEC_ENABLE(hcec);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get size of the received frame.\r
+ * @param hcec: CEC handle\r
+ * @retval Frame size\r
+ */\r
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)\r
+{\r
+ return hcec->RxXferSize;\r
+}\r
+ \r
+/**\r
+ * @brief This function handles CEC interrupt requests.\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* save interrupts register for further error or interrupts handling purposes */\r
+ hcec->ErrorCode = hcec->Instance->ISR;\r
+ /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ }\r
+ \r
+ /* CEC transmit error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ }\r
+ \r
+ /* CEC TX underrun error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ }\r
+ \r
+ /* CEC TX arbitration error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ }\r
+ \r
+ /* CEC RX overrun error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ } \r
+ \r
+ /* CEC RX bit rising error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ } \r
+ \r
+ /* CEC RX short bit period error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ } \r
+ \r
+ /* CEC RX long bit period error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ } \r
+ \r
+ /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))\r
+ { \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);\r
+ hcec->State = HAL_CEC_STATE_ERROR;\r
+ } \r
+\r
+ if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)\r
+ {\r
+ HAL_CEC_ErrorCallback(hcec);\r
+ }\r
+\r
+ /* CEC RX byte received interrupt ---------------------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))\r
+ { \r
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */\r
+ CEC_Receive_IT(hcec);\r
+ }\r
+ \r
+ /* CEC RX end received interrupt ---------------------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))\r
+ { \r
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */\r
+ CEC_Receive_IT(hcec);\r
+ }\r
+ \r
+ \r
+ /* CEC TX byte request interrupt ------------------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))\r
+ {\r
+ /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */\r
+ CEC_Transmit_IT(hcec);\r
+ } \r
+ \r
+ /* CEC TX end interrupt ------------------------------------------------*/\r
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))\r
+ {\r
+ /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */\r
+ CEC_Transmit_IT(hcec);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callback\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_TxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief CEC error callbacks\r
+ * @param hcec: CEC handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CEC_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function \r
+ * @brief CEC control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control function #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CEC.\r
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief return the CEC state\r
+ * @param hcec: CEC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)\r
+{\r
+ return hcec->State;\r
+}\r
+\r
+/**\r
+* @brief Return the CEC error code\r
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CEC.\r
+* @retval CEC Error Code\r
+*/\r
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)\r
+{\r
+ return hcec->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @brief Send data in interrupt mode \r
+ * @param hcec: CEC handle. \r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_CEC_Transmit_IT() \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)\r
+{\r
+ /* if the IP is already busy or if there is a previous transmission\r
+ already pending due to arbitration loss */\r
+ if ((hcec->State == HAL_CEC_STATE_BUSY_TX)\r
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))\r
+ {\r
+ __HAL_LOCK(hcec);\r
+ /* set state to BUSY TX, in case it wasn't set already (case\r
+ * of transmission new attempt after arbitration loss) */\r
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)\r
+ {\r
+ hcec->State = HAL_CEC_STATE_BUSY_TX;\r
+ }\r
+\r
+ /* if all data have been sent */\r
+ if(hcec->TxXferCount == 0)\r
+ {\r
+ /* Disable Peripheral to write CEC_IER register */\r
+ __HAL_CEC_DISABLE(hcec);\r
+ \r
+ /* Disable the CEC Transmission Interrupts */\r
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);\r
+ /* Disable the CEC Transmission Error Interrupts */\r
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_CEC_ENABLE(hcec);\r
+ \r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);\r
+ \r
+ hcec->State = HAL_CEC_STATE_READY;\r
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to\r
+ start again the Transmission under the Tx call back API */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ HAL_CEC_TxCpltCallback(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if (hcec->TxXferCount == 1)\r
+ {\r
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */\r
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r
+ }\r
+ /* clear Tx-Byte request flag */\r
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); \r
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r
+ hcec->TxXferCount--;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive data in interrupt mode. \r
+ * @param hcec: CEC handle.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_CEC_Receive_IT() \r
+ * @retval HAL status\r
+ */ \r
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)\r
+{\r
+ uint32_t tempisr;\r
+ \r
+ /* Three different conditions are tested to carry out the RX IT processing:\r
+ * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and \r
+ * the reception of the first byte is starting\r
+ * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)\r
+ * and a new byte is being received\r
+ * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)\r
+ * but has been interrupted by a new message reception or discarded due to \r
+ * arbitration loss: the reception of the first or higher priority message \r
+ * (the arbitration winner) is starting */\r
+ if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) \r
+ || (hcec->State == HAL_CEC_STATE_BUSY_RX)\r
+ || (hcec->State == HAL_CEC_STATE_BUSY_TX)) \r
+ {\r
+ /* reception is starting */ \r
+ hcec->State = HAL_CEC_STATE_BUSY_RX;\r
+ tempisr = (uint32_t) (hcec->Instance->ISR);\r
+ if ((tempisr & CEC_FLAG_RXBR) != 0)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcec);\r
+ /* read received byte */\r
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;\r
+ /* if last byte has been received */ \r
+ if ((tempisr & CEC_FLAG_RXEND) != 0)\r
+ {\r
+ /* clear IT */\r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR|CEC_FLAG_RXEND);\r
+ /* RX interrupts are not disabled at this point.\r
+ * Indeed, to disable the IT, the IP must be disabled first\r
+ * which resets the TXSOM flag. In case of arbitration loss,\r
+ * this leads to a transmission abort.\r
+ * Therefore, RX interruptions disabling if so required,\r
+ * is done in HAL_CEC_RxCpltCallback */\r
+ \r
+ /* IP state is moved to READY.\r
+ * If the IP must remain in standby mode to listen\r
+ * any new message, it is up to HAL_CEC_RxCpltCallback\r
+ * to move it again to HAL_CEC_STATE_STANDBY_RX */ \r
+ hcec->State = HAL_CEC_STATE_READY; \r
+ \r
+ /* Call the Process Unlocked before calling the Rx call back API */\r
+ __HAL_UNLOCK(hcec);\r
+ HAL_CEC_RxCpltCallback(hcec);\r
+ \r
+ return HAL_OK;\r
+ } \r
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); \r
+\r
+ hcec->RxXferSize++;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcec);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CORTEX HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the CORTEX:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..] \r
+ *** How to configure Interrupts using CORTEX HAL driver ***\r
+ ===========================================================\r
+ [..] \r
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M4 exceptions are managed by CMSIS functions.\r
+ \r
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r
+ function according to the following table.\r
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
+ (#) please refer to programing manual for details in how to configure priority. \r
+ \r
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r
+ The pending IRQ priority will be managed only by the sub priority.\r
+ \r
+ -@- IRQ priority order (sorted by highest to lowest priority):\r
+ (+@) Lowest preemption priority\r
+ (+@) Lowest sub priority\r
+ (+@) Lowest hardware priority (IRQ number)\r
+ \r
+ [..] \r
+ *** How to configure Systick using CORTEX HAL driver ***\r
+ ========================================================\r
+ [..]\r
+ Setup SysTick Timer for time base.\r
+ \r
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
+ is a CMSIS function that:\r
+ (++) Configures the SysTick Reload register with value passed as function parameter.\r
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+ (++) Resets the SysTick Counter register.\r
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+ (++) Enables the SysTick Interrupt.\r
+ (++) Starts the SysTick Counter.\r
+ \r
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
+ inside the stm32f7xx_hal_cortex.h file.\r
+\r
+ (+) You can change the SysTick IRQ priority by calling the\r
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+ (+) To adjust the SysTick time base, use the following formula:\r
+ \r
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+ (++) Reload Value should not exceed 0xFFFFFF\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+ * @brief CORTEX HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
+ Systick functionalities \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Sets the priority grouping field (preemption priority and subpriority)\r
+ * using the required unlock sequence.\r
+ * @param PriorityGroup: The priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+ NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+ * @brief Sets the priority of an interrupt.\r
+ * @param IRQn: External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PreemptPriority: The preemption priority for the IRQn channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority \r
+ * @param SubPriority: the subpriority level for the IRQ channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{ \r
+ uint32_t prioritygroup = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+ \r
+ prioritygroup = NVIC_GetPriorityGrouping();\r
+ \r
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Enable interrupt */\r
+ NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Disable interrupt */\r
+ NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initiates a system reset request to reset the MCU.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+ /* System Reset */\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ * Counter is in free running mode to generate periodic interrupts.\r
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r
+ * @retval status: - 0 Function succeeded.\r
+ * - 1 Function failed.\r
+ */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+ return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Cortex control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CORTEX\r
+ (NVIC, SYSTICK, MPU) functionalities. \r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Initializes and configures the Region and the memory to be protected.\r
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r
+ * the initialization and configuration information.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+ /* Set the Region number */\r
+ MPU->RNR = MPU_Init->Number;\r
+\r
+ if ((MPU_Init->Enable) != RESET)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+ \r
+ MPU->RBAR = MPU_Init->BaseAddress;\r
+ MPU->RASR = (MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
+ (MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
+ (MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
+ (MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
+ (MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
+ (MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
+ (MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
+ (MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
+ (MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
+ }\r
+ else\r
+ {\r
+ MPU->RBAR = 0x00;\r
+ MPU->RASR = 0x00;\r
+ }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+ */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+ /* Get the PRIGROUP[10:8] field value */\r
+ return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+ * @brief Gets the priority of an interrupt.\r
+ * @param IRQn: External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PriorityGroup: the priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+ * @brief Sets Pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Set interrupt pending */\r
+ NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC \r
+ * and returns the pending bit for the specified interrupt).\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if pending else 0 */\r
+ return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Clear pending interrupt */\r
+ NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if active else 0 */\r
+ return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+ {\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SYSTICK interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+ HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+ * @brief SYSTICK callback.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SYSTICK_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CRC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### CRC How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+\r
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();\r
+\r
+ (#) Initialize CRC calculator\r
+ (++) specify generating polynomial (IP default or non-default one)\r
+ (++) specify initialization value (IP default or non-default one)\r
+ (++) specify input data format\r
+ (++) specify input or output data inversion mode if any\r
+\r
+ (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the \r
+ input data buffer starting with the previously computed CRC as \r
+ initialization value\r
+\r
+ (#) Use HAL_CRC_Calculate() function to compute the CRC value of the \r
+ input data buffer starting with the defined initialization value \r
+ (default or non-default) to initiate CRC calculation\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC CRC\r
+ * @brief CRC HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);\r
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the CRC according to the specified parameters \r
+ in the CRC_InitTypeDef and create the associated handle\r
+ (+) DeInitialize the CRC peripheral\r
+ (+) Initialize the CRC MSP\r
+ (+) DeInitialize CRC MSP \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRC according to the specified\r
+ * parameters in the CRC_InitTypeDef and creates the associated handle.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Check the CRC handle allocation */\r
+ if(hcrc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r
+\r
+ if(hcrc->State == HAL_CRC_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_CRC_MspInit(hcrc);\r
+ }\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* check whether or not non-default generating polynomial has been \r
+ * picked up by user */\r
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); \r
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)\r
+ {\r
+ /* initialize IP with default generating polynomial */\r
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);\r
+ }\r
+ else\r
+ {\r
+ /* initialize CRC IP with generating polynomial defined by user */\r
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* check whether or not non-default CRC initial value has been \r
+ * picked up by user */\r
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));\r
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)\r
+ {\r
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); \r
+ }\r
+ else\r
+ {\r
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);\r
+ }\r
+ \r
+\r
+ /* set input data inversion mode */\r
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); \r
+ \r
+ /* set output data inversion mode */\r
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); \r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); \r
+ \r
+ /* makes sure the input data format (bytes, halfwords or words stream)\r
+ * is properly specified by user */\r
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CRC peripheral.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* Check the CRC handle allocation */\r
+ if(hcrc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r
+ \r
+ /* Check the CRC peripheral state */\r
+ if(hcrc->State == HAL_CRC_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* Reset CRC calculation unit */\r
+ __HAL_CRC_DR_RESET(hcrc);\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_CRC_MspDeInit(hcrc);\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_RESET;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRC MSP.\r
+ * @param hcrc: CRC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CRC_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CRC MSP.\r
+ * @param hcrc: CRC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_CRC_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group2 Peripheral Control functions \r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ using combination of the previous CRC value and the new one.\r
+ \r
+ or\r
+ \r
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ independently of the previous CRC value.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ * starting with the previously computed CRC as initialization value.\r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer, exact input data format is\r
+ * provided by hcrc->InputDataFormat. \r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */\r
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0; /* CRC input data buffer index */\r
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcrc); \r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ switch (hcrc->InputDataFormat)\r
+ {\r
+ case CRC_INPUTDATA_FORMAT_WORDS: \r
+ /* Enter Data to the CRC calculator */\r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ hcrc->Instance->DR = pBuffer[index];\r
+ }\r
+ temp = hcrc->Instance->DR;\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_BYTES: \r
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_HALFWORDS: \r
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+ \r
+ /* Return the CRC computed value */ \r
+ return temp;\r
+}\r
+\r
+\r
+/** \r
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r
+ * starting with hcrc->Instance->INIT as initialization value.\r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer, exact input data format is\r
+ * provided by hcrc->InputDataFormat. \r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */ \r
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0; /* CRC input data buffer index */\r
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcrc); \r
+ \r
+ /* Change CRC peripheral state */ \r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+ \r
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is \r
+ * written in hcrc->Instance->DR) */\r
+ __HAL_CRC_DR_RESET(hcrc);\r
+ \r
+ switch (hcrc->InputDataFormat)\r
+ {\r
+ case CRC_INPUTDATA_FORMAT_WORDS: \r
+ /* Enter 32-bit input data to the CRC calculator */\r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ hcrc->Instance->DR = pBuffer[index];\r
+ }\r
+ temp = hcrc->Instance->DR;\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_BYTES: \r
+ /* Specific 8-bit input data handling */\r
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r
+ break;\r
+ \r
+ case CRC_INPUTDATA_FORMAT_HALFWORDS: \r
+ /* Specific 16-bit input data handling */\r
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcrc);\r
+ \r
+ /* Return the CRC computed value */ \r
+ return temp;\r
+}\r
+\r
+\r
+\r
+/** \r
+ * @brief Enter 8-bit input data to the CRC calculator.\r
+ * Specific data handling to optimize processing time. \r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer\r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */\r
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t i = 0; /* input data buffer index */\r
+ \r
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,\r
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type\r
+ * handling by the IP */\r
+ for(i = 0; i < (BufferLength/4); i++)\r
+ {\r
+ hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));\r
+ }\r
+ /* last bytes specific handling */\r
+ if ((BufferLength%4) != 0)\r
+ {\r
+ if (BufferLength%4 == 1)\r
+ {\r
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];\r
+ }\r
+ if (BufferLength%4 == 2)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
+ }\r
+ if (BufferLength%4 == 3)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));\r
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; \r
+ }\r
+ }\r
+ \r
+ /* Return the CRC computed value */ \r
+ return hcrc->Instance->DR;\r
+}\r
+\r
+\r
+\r
+/** \r
+ * @brief Enter 16-bit input data to the CRC calculator.\r
+ * Specific data handling to optimize processing time. \r
+ * @param hcrc: CRC handle\r
+ * @param pBuffer: pointer to the input data buffer\r
+ * @param BufferLength: input data buffer length\r
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r
+ */ \r
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t i = 0; /* input data buffer index */\r
+ \r
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,\r
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure \r
+ * a correct type handling by the IP */\r
+ for(i = 0; i < (BufferLength/2); i++)\r
+ {\r
+ hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));\r
+ }\r
+ if ((BufferLength%2) != 0)\r
+ {\r
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r
+ }\r
+ \r
+ /* Return the CRC computed value */ \r
+ return hcrc->Instance->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Group3 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the CRC state.\r
+ * @param hcrc: CRC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)\r
+{\r
+ return hcrc->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_crc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extended CRC HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the CRC peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### CRC specific features #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) Polynomial configuration.\r
+ (#) Input data reverse mode.\r
+ (#) Output data reverse mode.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRCEx\r
+ * @brief CRC Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup CRCEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRCEx_Exported_Functions_Group1\r
+ * @brief Extended CRC features functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### CRC Extended features functions #####\r
+ =============================================================================== \r
+ [..]\r
+This subsection provides function allowing to:\r
+ (+) Set CRC polynomial if different from default one.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRC polynomial if different from default one.\r
+ * @param hcrc: CRC handle\r
+ * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)\r
+ * This parameter is written in normal representation, e.g.\r
+ * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 \r
+ * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 \r
+ * @param PolyLength: CRC polynomial length \r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)\r
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)\r
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)\r
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32) \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)\r
+{\r
+ uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));\r
+ \r
+ /* check polynomial definition vs polynomial size:\r
+ * polynomial length must be aligned with polynomial\r
+ * definition. HAL_ERROR is reported if Pol degree is \r
+ * larger than that indicated by PolyLength.\r
+ * Look for MSB position: msb will contain the degree of\r
+ * the second to the largest polynomial member. E.g., for\r
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */\r
+ while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))\r
+ {\r
+ }\r
+\r
+ switch (PolyLength)\r
+ {\r
+ case CRC_POLYLENGTH_7B:\r
+ if (msb >= HAL_CRC_LENGTH_7B)\r
+ { \r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_8B:\r
+ if (msb >= HAL_CRC_LENGTH_8B)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_16B:\r
+ if (msb >= HAL_CRC_LENGTH_16B)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ case CRC_POLYLENGTH_32B:\r
+ /* no polynomial definition vs. polynomial length issue possible */\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* set generating polynomial */\r
+ WRITE_REG(hcrc->Instance->POL, Pol);\r
+ \r
+ /* set generating polynomial size */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the Reverse Input data mode.\r
+ * @param hcrc: CRC handle\r
+ * @param InputReverseMode: Input Data inversion mode\r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)\r
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal\r
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal\r
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+\r
+ /* set input data inversion mode */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the Reverse Output data mode.\r
+ * @param hcrc: CRC handle\r
+ * @param OutputReverseMode: Output Data inversion mode\r
+ * This parameter can be one of the following values:\r
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)\r
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));\r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_BUSY;\r
+\r
+ /* set output data inversion mode */\r
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); \r
+ \r
+ /* Change CRC peripheral state */\r
+ hcrc->State = HAL_CRC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CRYP HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Cryptography (CRYP) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + AES processing functions\r
+ * + DES processing functions\r
+ * + TDES processing functions\r
+ * + DMA callback functions\r
+ * + CRYP IRQ handler management\r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The CRYP HAL driver can be used as follows:\r
+\r
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r
+ (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()\r
+ (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())\r
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams one for managing data transfer from\r
+ memory to peripheral (input stream) and another stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ \r
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r
+ (##) The encryption/decryption key. It's size depends on the algorithm\r
+ used for encryption/decryption\r
+ (##) The initialization vector (counter). It is not used ECB mode.\r
+ \r
+ (#)Three processing (encryption/decryption) functions are available:\r
+ (##) Polling mode: encryption and decryption APIs are blocking functions\r
+ i.e. they process the data and wait till the processing is finished,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt_IT()\r
+ (##) DMA mode: encryption and decryption APIs are not blocking functions\r
+ i.e. the data transfer is ensured by DMA,\r
+ e.g. HAL_CRYP_AESCBC_Encrypt_DMA()\r
+ \r
+ (#)When the processing function is called at first time after HAL_CRYP_Init()\r
+ the CRYP peripheral is initialized and processes the buffer in input.\r
+ At second call, the processing function performs an append of the already\r
+ processed buffer.\r
+ When a new data block is to be processed, call HAL_CRYP_Init() then the\r
+ processing function.\r
+ \r
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYP CRYP\r
+ * @brief CRYP HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CRYP_Private_define\r
+ * @{\r
+ */\r
+#define CRYP_TIMEOUT_VALUE 1\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup CRYP_Private_Functions_prototypes\r
+ * @{\r
+ */ \r
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);\r
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);\r
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r
+/**\r
+ * @}\r
+ */ \r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup CRYP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA CRYP Input Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit\r
+ in the DMACR register */\r
+ CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r
+ \r
+ /* Call input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP Output Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit\r
+ in the DMACR register */\r
+ CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r
+ \r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Change the CRYP state to ready */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Call output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ hcryp->State= HAL_CRYP_STATE_READY;\r
+ HAL_CRYP_ErrorCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief Writes the Key in Key registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Key: Pointer to Key buffer\r
+ * @param KeySize: Size of Key\r
+ * @retval None\r
+ */\r
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r
+{\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ \r
+ switch(KeySize)\r
+ {\r
+ case CRYP_KEYSIZE_256B:\r
+ /* Key Initialisation */\r
+ CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_192B:\r
+ CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_128B: \r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes the InitVector/InitCounter in IV registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param InitVector: Pointer to InitVector/InitCounter buffer\r
+ * @param IVSize: Size of the InitVector/InitCounter\r
+ * @retval None\r
+ */\r
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)\r
+{\r
+ uint32_t ivaddr = (uint32_t)InitVector;\r
+ \r
+ switch(IVSize)\r
+ {\r
+ case CRYP_KEYSIZE_128B:\r
+ CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */\r
+ case CRYP_KEYSIZE_192B:\r
+ CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_256B:\r
+ CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Writes Input data in polling mode and read the output data\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16.\r
+ * @param Output: Pointer to the returned buffer\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=16)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))\r
+ { \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Write Input data in polling mode. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 8\r
+ * @param Output: Pointer to the returned buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=8)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the DMA configuration and start the DMA transfer\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param inputaddr: address of the Input buffer\r
+ * @param Size: Size of the Input buffer, must be a multiple of 16.\r
+ * @param outputaddr: address of the Output buffer\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r
+{\r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;\r
+ \r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);\r
+ \r
+ /* Enable In DMA request */\r
+ CRYP->DMACR = (CRYP_DMACR_DIEN);\r
+ \r
+ /* Enable the DMA Out DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);\r
+ \r
+ /* Enable Out DMA request */\r
+ CRYP->DMACR |= CRYP_DMACR_DOEN;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in DES ECB mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r
+ CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in DES CBC mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r
+ CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in TDES ECB mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the CRYP peripheral in TDES CBC mode\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Direction: Encryption or decryption\r
+ * @retval None\r
+ */\r
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r
+{\r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the CRYP peripheral in AES CBC mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CRYP_Exported_Functions\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the CRYP according to the specified parameters \r
+ in the CRYP_InitTypeDef and creates the associated handle\r
+ (+) DeInitialize the CRYP peripheral\r
+ (+) Initialize the CRYP MSP\r
+ (+) DeInitialize CRYP MSP \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP according to the specified\r
+ * parameters in the CRYP_InitTypeDef and creates the associated handle.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)\r
+{ \r
+ /* Check the CRYP handle allocation */\r
+ if(hcryp == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));\r
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_CRYP_MspInit(hcryp);\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the key size and data type*/\r
+ CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);\r
+ \r
+ /* Reset CrypInCount and CrypOutCount */\r
+ hcryp->CrypInCount = 0;\r
+ hcryp->CrypOutCount = 0;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Set the default CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CRYP peripheral. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* Check the CRYP handle allocation */\r
+ if(hcryp == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the default CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_READY;\r
+ \r
+ /* Reset CrypInCount and CrypOutCount */\r
+ hcryp->CrypInCount = 0;\r
+ hcryp->CrypOutCount = 0;\r
+ \r
+ /* Disable the CRYP Peripheral Clock */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+ HAL_CRYP_MspDeInit(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hcryp);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP MSP.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes CRYP MSP.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### AES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using AES-128/192/256 using chaining modes\r
+ (+) Decrypt cyphertext using AES-128/192/256 using chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ { \r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES ECB decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES Key mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Reset the ALGOMODE bits*/\r
+ CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r
+ \r
+ /* Set the CRYP peripheral in AES CBC decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{ \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CTR mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### DES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using DES using ECB or CBC chaining modes\r
+ (+) Decrypt cyphertext using ECB or CBC chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ \r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ \r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ \r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ \r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB encryption mode */\r
+ CRYP_SetDESECBMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC encryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES ECB decryption mode */\r
+ CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in DES CBC decryption mode */\r
+ CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions \r
+ * @brief processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### TDES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes\r
+ (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes\r
+ [..] Three processing functions are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Cypher Data and Get Plain Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode\r
+ * then encrypt pPlainData. The cypher data are available in pCypherData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write Cypher Data and Get Plain Data */\r
+ if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ /* Disable IT */\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call the Output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ \r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable CRYP */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+\r
+ hcryp->pCrypInBuffPtr += 8;\r
+ hcryp->CrypInCount -= 8;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+\r
+ hcryp->pCrypOutBuffPtr += 8;\r
+ hcryp->CrypOutCount -= 8;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Disable CRYP */\r
+ __HAL_CRYP_DISABLE();\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB encryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC encryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, 0);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES ECB decryption mode */\r
+ CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 8\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Set CRYP peripheral in TDES CBC decryption mode */\r
+ CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions \r
+ * @brief DMA callback functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### DMA callback functions #####\r
+ ============================================================================== \r
+ [..] This section provides DMA callback functions:\r
+ (+) DMA Input data transfer complete\r
+ (+) DMA Output data transfer complete\r
+ (+) DMA error\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Input FIFO transfer completed callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_InCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Output FIFO transfer completed callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief CRYP error callbacks.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CRYP_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management \r
+ * @brief CRYP IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### CRYP IRQ handler management #####\r
+ ============================================================================== \r
+[..] This section provides CRYP IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles CRYP interrupt request.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r
+ {\r
+ case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:\r
+ HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:\r
+ HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:\r
+ HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:\r
+ HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:\r
+ HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:\r
+ HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:\r
+ HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:\r
+ HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:\r
+ HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:\r
+ HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:\r
+ HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:\r
+ HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:\r
+ HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL); \r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:\r
+ HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL); \r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the CRYP state.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval HAL state\r
+ */\r
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ return hcryp->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F756xx */\r
+\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cryp_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extended CRYP HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of CRYP extension peripheral:\r
+ * + Extended AES processing functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The CRYP Extension HAL driver can be used as follows:\r
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r
+ (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()\r
+ (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())\r
+ (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable two DMA streams one for managing data transfer from\r
+ memory to peripheral (input stream) and another stream for managing data\r
+ transfer from peripheral to memory (output stream)\r
+ (+++) Associate the initialized DMA handle to the CRYP DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the two DMA Streams. The output stream should have higher\r
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r
+ (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r
+ (##) The encryption/decryption key. Its size depends on the algorithm\r
+ used for encryption/decryption\r
+ (##) The initialization vector (counter). It is not used ECB mode.\r
+ (#)Three processing (encryption/decryption) functions are available:\r
+ (##) Polling mode: encryption and decryption APIs are blocking functions\r
+ i.e. they process the data and wait till the processing is finished\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()\r
+ (##) DMA mode: encryption and decryption APIs are not blocking functions\r
+ i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()\r
+ (#)When the processing function is called at first time after HAL_CRYP_Init()\r
+ the CRYP peripheral is initialized and processes the buffer in input.\r
+ At second call, the processing function performs an append of the already\r
+ processed buffer.\r
+ When a new data block is to be processed, call HAL_CRYP_Init() then the\r
+ processing function.\r
+ (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms\r
+ which provide authentication messages.\r
+ HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those\r
+ authentication messages.\r
+ Call those functions after the processing ones (polling, interrupt or DMA).\r
+ e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data\r
+ then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message\r
+ @note: For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.\r
+ @note: The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length \r
+ (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).\r
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYPEx CRYPEx\r
+ * @brief CRYP Extension HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Private_define\r
+ * @{\r
+ */\r
+#define CRYPEx_TIMEOUT_VALUE 1\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes\r
+ * @{\r
+ */\r
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);\r
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);\r
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);\r
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA CRYP Input Data process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit\r
+ in the DMACR register */\r
+ CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r
+ \r
+ /* Call input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP Output Data process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit\r
+ in the DMACR register */\r
+ CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Call output data transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief DMA CRYP communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hcryp->State= HAL_CRYP_STATE_READY;\r
+ HAL_CRYP_ErrorCallback(hcryp);\r
+}\r
+\r
+/**\r
+ * @brief Writes the Key in Key registers. \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Key: Pointer to Key buffer\r
+ * @param KeySize: Size of Key\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r
+{\r
+ uint32_t keyaddr = (uint32_t)Key;\r
+ \r
+ switch(KeySize)\r
+ {\r
+ case CRYP_KEYSIZE_256B:\r
+ /* Key Initialisation */\r
+ CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_192B:\r
+ CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ case CRYP_KEYSIZE_128B: \r
+ CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));\r
+ keyaddr+=4;\r
+ CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes the InitVector/InitCounter in IV registers.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param InitVector: Pointer to InitVector/InitCounter buffer\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)\r
+{\r
+ uint32_t ivaddr = (uint32_t)InitVector;\r
+ \r
+ CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));\r
+ ivaddr+=4;\r
+ CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));\r
+}\r
+\r
+/**\r
+ * @brief Process Data: Writes Input data in polling mode and read the Output data.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer.\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16\r
+ * @param Output: Pointer to the returned buffer\r
+ * @param Timeout: Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t i = 0;\r
+ uint32_t inputaddr = (uint32_t)Input;\r
+ uint32_t outputaddr = (uint32_t)Output;\r
+ \r
+ for(i=0; (i < Ilength); i+=16)\r
+ {\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the Output block from the OUT FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the header phase\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Input: Pointer to the Input buffer.\r
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16\r
+ * @param Timeout: Timeout value \r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t loopcounter = 0;\r
+ uint32_t headeraddr = (uint32_t)Input;\r
+ \r
+ /***************************** Header phase *********************************/\r
+ if(hcryp->Init.HeaderSize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Wait until the complete message has been processed */\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the DMA configuration and start the DMA transfer.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param inputaddr: Address of the Input buffer\r
+ * @param Size: Size of the Input buffer, must be a multiple of 16\r
+ * @param outputaddr: Address of the Output buffer\r
+ * @retval None\r
+ */\r
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r
+{\r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r
+ \r
+ /* Set the CRYP DMA transfer complete callback */\r
+ hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;\r
+ /* Set the DMA error callback */\r
+ hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);\r
+ \r
+ /* Enable In DMA request */\r
+ CRYP->DMACR = CRYP_DMACR_DIEN;\r
+ \r
+ /* Enable the DMA Out DMA Stream */\r
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);\r
+ \r
+ /* Enable Out DMA request */\r
+ CRYP->DMACR |= CRYP_DMACR_DOEN;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions---------------------------------------------------------*/\r
+/** @addtogroup CRYPEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions \r
+ * @brief Extended processing functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extended AES processing functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes\r
+ (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes\r
+ (+) Finish the processing. This function is available only for GCM and CCM\r
+ [..] Three processing methods are available:\r
+ (+) Polling mode\r
+ (+) Interrupt mode\r
+ (+) DMA mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode then \r
+ * encrypt pPlainData. The cypher data are available in pCypherData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *********************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 **************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter *****************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks\r
+ are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /***************************** Header phase *******************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode then \r
+ * encrypt pPlainData. The cypher data are available in pCypherData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode then\r
+ * decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Computes the authentication TAG.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param Size: Total length of the plain/cyphertext buffer\r
+ * @param AuthTag: Pointer to the authentication buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r
+ uint64_t inputlength = Size * 8; /* input length in bits */\r
+ uint32_t tagaddr = (uint32_t)AuthTag;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r
+ {\r
+ /* Change the CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r
+ \r
+ /* Disable CRYP to start the final phase */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select final phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write the number of bits in header (64 bits) followed by the number of bits\r
+ in the payload */\r
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r
+ {\r
+ CRYP->DR = __RBIT(headerlength >> 32);\r
+ CRYP->DR = __RBIT(headerlength);\r
+ CRYP->DR = __RBIT(inputlength >> 32);\r
+ CRYP->DR = __RBIT(inputlength);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r
+ {\r
+ CRYP->DR = __REV(headerlength >> 32);\r
+ CRYP->DR = __REV(headerlength);\r
+ CRYP->DR = __REV(inputlength >> 32);\r
+ CRYP->DR = __REV(inputlength);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r
+ {\r
+ CRYP->DR = __ROR((uint32_t)(headerlength >> 32), 16);\r
+ CRYP->DR = __ROR((uint32_t)headerlength, 16);\r
+ CRYP->DR = __ROR((uint32_t)(inputlength >> 32), 16);\r
+ CRYP->DR = __ROR((uint32_t)inputlength, 16);\r
+ }\r
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r
+ {\r
+ CRYP->DR = (uint32_t)(headerlength >> 32);\r
+ CRYP->DR = (uint32_t)(headerlength);\r
+ CRYP->DR = (uint32_t)(inputlength >> 32);\r
+ CRYP->DR = (uint32_t)(inputlength);\r
+ }\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the Auth TAG in the IN FIFO */\r
+ *(uint32_t*)(tagaddr) = CRYP->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = CRYP->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = CRYP->DOUT;\r
+ tagaddr+=4;\r
+ *(uint32_t*)(tagaddr) = CRYP->DOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Computes the authentication TAG for AES CCM mode.\r
+ * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() \r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param AuthTag: Pointer to the authentication buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t tagaddr = (uint32_t)AuthTag;\r
+ uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;\r
+ uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */\r
+ uint32_t loopcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r
+ {\r
+ /* Change the CRYP phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r
+ \r
+ /* Disable CRYP to start the final phase */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select final phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Write the counter block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ CRYP->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ CRYP->DR = *(uint32_t*)ctraddr;\r
+ ctraddr+=4;\r
+ CRYP->DR = *(uint32_t*)ctraddr;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the Auth TAG in the IN FIFO */\r
+ temptag[0] = CRYP->DOUT;\r
+ temptag[1] = CRYP->DOUT;\r
+ temptag[2] = CRYP->DOUT;\r
+ temptag[3] = CRYP->DOUT;\r
+ }\r
+ \r
+ /* Copy temporary authentication TAG in user TAG buffer */\r
+ for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)\r
+ {\r
+ /* Set the authentication TAG buffer */\r
+ *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode then\r
+ * decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *********************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 **************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter *****************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /***************************** Header phase *******************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Write Plain Data and Get Cypher Data */\r
+ if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ \r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ \r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ { \r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ }\r
+ else\r
+ {\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ /* Get the buffer addresses and sizes */ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ if(Size != 0)\r
+ {\r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP state and phase */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer \r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t tickstart = 0;\r
+ uint32_t headersize = hcryp->Init.HeaderSize;\r
+ uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if(hcryp->State == HAL_CRYP_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Enable Interrupts */\r
+ __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))\r
+ {\r
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r
+ /* Write the Input block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ inputaddr+=4;\r
+ CRYP->DR = *(uint32_t*)(inputaddr);\r
+ hcryp->pCrypInBuffPtr += 16;\r
+ hcryp->CrypInCount -= 16;\r
+ if(hcryp->CrypInCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);\r
+ /* Call the Input data transfer complete callback */\r
+ HAL_CRYP_InCpltCallback(hcryp);\r
+ }\r
+ }\r
+ else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))\r
+ {\r
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = CRYP->DOUT;\r
+ hcryp->pCrypOutBuffPtr += 16;\r
+ hcryp->CrypOutCount -= 16;\r
+ if(hcryp->CrypOutCount == 0)\r
+ {\r
+ __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_READY;\r
+ /* Call Input transfer complete callback */\r
+ HAL_CRYP_OutCpltCallback(hcryp);\r
+ }\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pCypherData: Pointer to the cyphertext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t headersize;\r
+ uint32_t headeraddr;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pPlainData;\r
+ outputaddr = (uint32_t)pCypherData;\r
+ \r
+ headersize = hcryp->Init.HeaderSize;\r
+ headeraddr = (uint32_t)hcryp->Init.Header;\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pPlainData;\r
+ hcryp->pCrypOutBuffPtr = pCypherData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer.\r
+ * @param Size: Length of the cyphertext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES GCM decryption mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r
+ \r
+ /* Enable CRYP to start the init phase */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the header phase */\r
+ if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Disable the CRYP peripheral */\r
+ __HAL_CRYP_DISABLE();\r
+ \r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ \r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA\r
+ * then decrypted pCypherData. The cypher data are available in pPlainData.\r
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @param pCypherData: Pointer to the cyphertext buffer \r
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16\r
+ * @param pPlainData: Pointer to the plaintext buffer \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r
+{\r
+ uint32_t tickstart = 0; \r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t headersize;\r
+ uint32_t headeraddr;\r
+ uint32_t loopcounter = 0;\r
+ uint32_t bufferidx = 0;\r
+ uint8_t blockb0[16] = {0};/* Block B0 */\r
+ uint8_t ctr[16] = {0}; /* Counter */\r
+ uint32_t b0addr = (uint32_t)blockb0;\r
+ \r
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcryp);\r
+ \r
+ inputaddr = (uint32_t)pCypherData;\r
+ outputaddr = (uint32_t)pPlainData;\r
+ \r
+ headersize = hcryp->Init.HeaderSize;\r
+ headeraddr = (uint32_t)hcryp->Init.Header;\r
+ \r
+ hcryp->CrypInCount = Size;\r
+ hcryp->pCrypInBuffPtr = pCypherData;\r
+ hcryp->pCrypOutBuffPtr = pPlainData;\r
+ hcryp->CrypOutCount = Size;\r
+ \r
+ /* Change the CRYP peripheral state */\r
+ hcryp->State = HAL_CRYP_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r
+ {\r
+ /************************ Formatting the header block *******************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r
+ if(headersize < 65280)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r
+ hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r
+ headersize += 2;\r
+ }\r
+ else\r
+ {\r
+ /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFF;\r
+ hcryp->Init.pScratch[bufferidx++] = 0xFE;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;\r
+ hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;\r
+ headersize += 6;\r
+ }\r
+ /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */\r
+ for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r
+ }\r
+ /* Check if the header size is modulo 16 */\r
+ if ((headersize % 16) != 0)\r
+ {\r
+ /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r
+ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = 0;\r
+ }\r
+ /* Set the header size to modulo 16 */\r
+ headersize = ((headersize/16) + 1) * 16;\r
+ }\r
+ /* Set the pointer headeraddr to hcryp->Init.pScratch */\r
+ headeraddr = (uint32_t)hcryp->Init.pScratch;\r
+ }\r
+ /*********************** Formatting the block B0 ************************/\r
+ if(headersize != 0)\r
+ {\r
+ blockb0[0] = 0x40;\r
+ }\r
+ /* Flags byte */\r
+ /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r
+ blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r
+ \r
+ for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r
+ }\r
+ for ( ; loopcounter < 13; loopcounter++)\r
+ {\r
+ blockb0[loopcounter+1] = 0;\r
+ }\r
+ \r
+ blockb0[14] = (Size >> 8);\r
+ blockb0[15] = (Size & 0xFF);\r
+ \r
+ /************************* Formatting the initial counter ***************/\r
+ /* Byte 0:\r
+ Bits 7 and 6 are reserved and shall be set to 0\r
+ Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r
+ blocks are distinct from B0\r
+ Bits 0, 1, and 2 contain the same encoding of q as in B0\r
+ */\r
+ ctr[0] = blockb0[0] & 0x07;\r
+ /* byte 1 to NonceSize is the IV (Nonce) */\r
+ for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r
+ {\r
+ ctr[loopcounter] = blockb0[loopcounter];\r
+ }\r
+ /* Set the LSB to 1 */\r
+ ctr[15] |= 0x01;\r
+ \r
+ /* Set the key */\r
+ CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r
+ \r
+ /* Set the CRYP peripheral in AES CCM mode */\r
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r
+ \r
+ /* Set the Initialization Vector */\r
+ CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r
+ \r
+ /* Select init phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);\r
+ \r
+ b0addr = (uint32_t)blockb0;\r
+ /* Write the blockb0 block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ b0addr+=4;\r
+ CRYP->DR = *(uint32_t*)(b0addr);\r
+ \r
+ /* Enable the CRYP peripheral */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r
+ {\r
+ /* Check for the Timeout */\r
+ \r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ \r
+ }\r
+ }\r
+ /***************************** Header phase *****************************/\r
+ if(headersize != 0)\r
+ {\r
+ /* Select header phase */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);\r
+ \r
+ /* Enable Crypto processor */\r
+ __HAL_CRYP_ENABLE();\r
+ \r
+ for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write the header block in the IN FIFO */\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ CRYP->DR = *(uint32_t*)(headeraddr);\r
+ headeraddr+=4;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r
+ {\r
+ /* Change state */\r
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Save formatted counter into the scratch buffer pScratch */\r
+ for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r
+ {\r
+ hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r
+ }\r
+ /* Reset bit 0 */\r
+ hcryp->Init.pScratch[15] &= 0xfe;\r
+ /* Select payload phase once the header phase is performed */\r
+ __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);\r
+ \r
+ /* Flush FIFO */\r
+ __HAL_CRYP_FIFO_FLUSH();\r
+ \r
+ /* Set the phase */\r
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r
+ }\r
+ /* Set the input and output addresses and start DMA transfer */ \r
+ CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r
+ \r
+ /* Unlock process */\r
+ __HAL_UNLOCK(hcryp);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management \r
+ * @brief CRYPEx IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### CRYPEx IRQ handler management #####\r
+ ============================================================================== \r
+[..] This section provides CRYPEx IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles CRYPEx interrupt request.\r
+ * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains\r
+ * the configuration information for CRYP module\r
+ * @retval None\r
+ */\r
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)\r
+{\r
+ switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r
+ { \r
+ case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:\r
+ HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:\r
+ HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:\r
+ HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:\r
+ HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx */\r
+\r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DAC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions \r
+ * \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### DAC Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ *** DAC Channels ***\r
+ ==================== \r
+ [..] \r
+ The device integrates two 12-bit Digital Analog Converters that can \r
+ be used independently or simultaneously (dual mode):\r
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output\r
+ (#) DAC channel2 with DAC_OUT2 (PA5) as output\r
+ \r
+ *** DAC Triggers ***\r
+ ====================\r
+ [..]\r
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE\r
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. \r
+ [..] \r
+ Digital to Analog conversion can be triggered by:\r
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.\r
+ The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ \r
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 \r
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)\r
+ \r
+ (#) Software using DAC_TRIGGER_SOFTWARE\r
+ \r
+ *** DAC Buffer mode feature ***\r
+ =============================== \r
+ [..] \r
+ Each DAC channel integrates an output buffer that can be used to \r
+ reduce the output impedance, and to drive external loads directly\r
+ without having to add an external operational amplifier.\r
+ To enable, the output buffer use \r
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;\r
+ [..] \r
+ (@) Refer to the device datasheet for more details about output \r
+ impedance value with and without output buffer.\r
+ \r
+ *** DAC wave generation feature ***\r
+ =================================== \r
+ [..] \r
+ Both DAC channels can be used to generate\r
+ (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() \r
+ (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()\r
+ \r
+ *** DAC data format ***\r
+ =======================\r
+ [..] \r
+ The DAC data format can be:\r
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R\r
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L\r
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R\r
+ \r
+ *** DAC data value to voltage correspondence *** \r
+ ================================================ \r
+ [..] \r
+ The analog output voltage on each DAC channel pin is determined\r
+ by the following equation: \r
+ DAC_OUTx = VREF+ * DOR / 4095\r
+ with DOR is the Data Output Register\r
+ VEF+ is the input voltage reference (refer to the device datasheet)\r
+ e.g. To set DAC_OUT1 to 0.7V, use\r
+ Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
+ \r
+ *** DMA requests ***\r
+ =====================\r
+ [..] \r
+ A DMA1 request can be generated when an external trigger (but not\r
+ a software trigger) occurs if DMA1 requests are enabled using\r
+ HAL_DAC_Start_DMA()\r
+ [..]\r
+ DMA1 requests are mapped as following:\r
+ (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be \r
+ already configured\r
+ (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be \r
+ already configured\r
+ \r
+ -@- For Dual mode and specific signal (Triangle and noise) generation please \r
+ refer to Extension Features Driver description \r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) DAC APB clock must be enabled to get write access to DAC\r
+ registers using HAL_DAC_Init()\r
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.\r
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the DAC peripheral using HAL_DAC_Start() \r
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.\r
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()\r
+\r
+ \r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length \r
+ of data to be transferred at each end of conversion \r
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() \r
+ function is executed and user can add his own code by customization of function pointer \r
+ HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2\r
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can \r
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1\r
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()\r
+\r
+ \r
+ *** DAC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DAC HAL driver.\r
+ \r
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral\r
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral\r
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags\r
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status\r
+ \r
+ [..]\r
+ (@) You can refer to the DAC HAL driver header file for more useful macros \r
+ \r
+ @endverbatim \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC DAC\r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);\r
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);\r
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DAC_Exported_Functions DAC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DAC. \r
+ (+) De-initialize the DAC. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified parameters\r
+ * in the DAC_InitStruct.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)\r
+{ \r
+ /* Check DAC handle */\r
+ if(hdac == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r
+ \r
+ if(hdac->State == HAL_DAC_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware */\r
+ HAL_DAC_MspInit(hdac);\r
+ }\r
+ \r
+ /* Initialize the DAC state*/\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Set DAC error code to none */\r
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r
+ \r
+ /* Initialize the DAC state*/\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Check DAC handle */\r
+ if(hdac == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r
+\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_DAC_MspDeInit(hdac);\r
+\r
+ /* Set DAC error code to none */\r
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r
+\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdac);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC MSP.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DAC MSP.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion.\r
+ (+) Stop conversion.\r
+ (+) Start conversion and enable DMA transfer.\r
+ (+) Stop conversion and disable DMA transfer.\r
+ (+) Get result of conversion.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables DAC and starts conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DAC_ENABLE(hdac, Channel);\r
+ \r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN1;\r
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;\r
+ /* Check if software trigger enabled */\r
+ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))\r
+ {\r
+ /* Enable the selected DAC software conversion */\r
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp1 = hdac->Instance->CR & DAC_CR_TEN2;\r
+ tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; \r
+ /* Check if software trigger enabled */\r
+ if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))\r
+ {\r
+ /* Enable the selected DAC software conversion*/\r
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;\r
+ }\r
+ }\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables DAC and stop conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_DAC_DISABLE(hdac, Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables DAC and starts conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param pData: The destination peripheral Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to DAC peripheral\r
+ * @param Alignment: Specifies the data alignment for DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ /* Set the DMA transfer complete callback for channel1 */\r
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;\r
+\r
+ /* Set the DMA half transfer complete callback for channel1 */\r
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;\r
+\r
+ /* Set the DMA error callback for channel1 */\r
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;\r
+\r
+ /* Enable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR |= DAC_CR_DMAEN1;\r
+ \r
+ /* Case of use of channel 1 */\r
+ switch(Alignment)\r
+ {\r
+ case DAC_ALIGN_12B_R:\r
+ /* Get DHR12R1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;\r
+ break;\r
+ case DAC_ALIGN_12B_L:\r
+ /* Get DHR12L1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;\r
+ break;\r
+ case DAC_ALIGN_8B_R:\r
+ /* Get DHR8R1 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the DMA transfer complete callback for channel2 */\r
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;\r
+\r
+ /* Set the DMA half transfer complete callback for channel2 */\r
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;\r
+\r
+ /* Set the DMA error callback for channel2 */\r
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;\r
+\r
+ /* Enable the selected DAC channel2 DMA request */\r
+ hdac->Instance->CR |= DAC_CR_DMAEN2;\r
+\r
+ /* Case of use of channel 2 */\r
+ switch(Alignment)\r
+ {\r
+ case DAC_ALIGN_12B_R:\r
+ /* Get DHR12R2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;\r
+ break;\r
+ case DAC_ALIGN_12B_L:\r
+ /* Get DHR12L2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;\r
+ break;\r
+ case DAC_ALIGN_8B_R:\r
+ /* Get DHR8R2 address */\r
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Enable the DMA Stream */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ /* Enable the DAC DMA underrun interrupt */\r
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);\r
+ } \r
+ else\r
+ {\r
+ /* Enable the DAC DMA underrun interrupt */\r
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DAC_ENABLE(hdac, Channel);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables DAC and stop conversion of channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Disable the selected DAC channel DMA request */\r
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_DAC_DISABLE(hdac, Channel);\r
+ \r
+ /* Disable the DMA Channel */\r
+ /* Channel1 is used */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ { \r
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);\r
+ }\r
+ else /* Channel2 is used for */\r
+ { \r
+ status = HAL_DMA_Abort(hdac->DMA_Handle2); \r
+ }\r
+\r
+ /* Check if DMA Channel effectively disabled */\r
+ if(status != HAL_OK)\r
+ {\r
+ /* Update DAC state machine to error */\r
+ hdac->State = HAL_DAC_STATE_ERROR; \r
+ }\r
+ else\r
+ {\r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ return hdac->Instance->DOR1;\r
+ }\r
+ else\r
+ {\r
+ return hdac->Instance->DOR2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handles DAC interrupt request \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Check underrun channel 1 flag */\r
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))\r
+ {\r
+ /* Change DAC state to error state */\r
+ hdac->State = HAL_DAC_STATE_ERROR;\r
+ \r
+ /* Set DAC error code to channel1 DMA underrun error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;\r
+ \r
+ /* Clear the underrun flag */\r
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);\r
+ \r
+ /* Disable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;\r
+ \r
+ /* Error callback */ \r
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);\r
+ }\r
+ /* Check underrun channel 2 flag */\r
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))\r
+ {\r
+ /* Change DAC state to error state */\r
+ hdac->State = HAL_DAC_STATE_ERROR;\r
+ \r
+ /* Set DAC error code to channel2 DMA underrun error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;\r
+ \r
+ /* Clear the underrun flag */\r
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);\r
+ \r
+ /* Disable the selected DAC channel1 DMA request */\r
+ hdac->Instance->CR &= ~DAC_CR_DMAEN2;\r
+ \r
+ /* Error callback */ \r
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Conversion complete callback in non blocking mode for Channel1 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error DAC callback for Channel1.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA underrun DAC callback for channel1.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure channels. \r
+ (+) Set the specified data holding register value for DAC channel.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param sConfig: DAC configuration structure.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Get the DAC CR value */\r
+ tmpreg1 = hdac->Instance->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << Channel;\r
+ /* Write to DAC CR */\r
+ hdac->Instance->CR = tmpreg1;\r
+ /* Disable wave generation */\r
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected\r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected \r
+ * @param Alignment: Specifies the data alignment.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @param Data: Data to be loaded in the selected data holding register.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)hdac->Instance; \r
+ if(Channel == DAC_CHANNEL_1)\r
+ {\r
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);\r
+ }\r
+ else\r
+ {\r
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);\r
+ }\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DAC state.\r
+ (+) Check the DAC Errors.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the DAC state\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval HAL state\r
+ */\r
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* Return DAC state */\r
+ return hdac->State;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the DAC error code\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval DAC Error Code\r
+ */\r
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)\r
+{\r
+ return hdac->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ HAL_DAC_ConvCpltCallbackCh1(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Set DAC error code to DMA error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r
+ \r
+ HAL_DAC_ErrorCallbackCh1(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dac_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extended DAC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of DAC extension peripheral:\r
+ * + Extended features functions\r
+ * \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :\r
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use\r
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. \r
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.\r
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.\r
+ \r
+ @endverbatim \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DACEx DACEx\r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extended features functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start conversion.\r
+ (+) Stop conversion.\r
+ (+) Start conversion and enable DMA transfer.\r
+ (+) Stop conversion and disable DMA transfer.\r
+ (+) Get result of conversion.\r
+ (+) Get result of dual mode conversion.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ tmp |= hdac->Instance->DOR1;\r
+ \r
+ tmp |= hdac->Instance->DOR2 << 16;\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected \r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param Amplitude: Select max triangle amplitude. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1\r
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3\r
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7\r
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15\r
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31\r
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63\r
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127\r
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255\r
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511\r
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023\r
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047\r
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ MODIFY_REG(hdac->Instance->CR, \\r
+ ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << Channel, \\r
+ (DAC_WAVE_TRIANGLE | Amplitude) << Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC. \r
+ * @param Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected \r
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected\r
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. \r
+ * This parameter can be one of the following values: \r
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation\r
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation\r
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation \r
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(Channel));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdac);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_BUSY;\r
+ \r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ MODIFY_REG(hdac->Instance->CR, \\r
+ ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << Channel, \\r
+ (DAC_WAVE_NOISE | Amplitude) << Channel);\r
+ \r
+ /* Change DAC state */\r
+ hdac->State = HAL_DAC_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdac);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual DAC channel.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @param Alignment: Specifies the data alignment for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * DAC_ALIGN_8B_R: 8bit right data alignment selected\r
+ * DAC_ALIGN_12B_L: 12bit left data alignment selected\r
+ * DAC_ALIGN_12B_R: 12bit right data alignment selected\r
+ * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.\r
+ * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.\r
+ * @note In dual mode, a unique register access is required to write in both\r
+ * DAC channels at the same time.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)\r
+{ \r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(Alignment));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (Alignment == DAC_ALIGN_8B_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)hdac->Instance;\r
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Conversion complete callback in non blocking mode for Channel2 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 \r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error DAC callback for Channel2.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA underrun DAC callback for channel2.\r
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DAC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ HAL_DACEx_ConvCpltCallbackCh2(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief DMA half transfer complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* Conversion complete callback */\r
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); \r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) \r
+{\r
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Set DAC error code to DMA error */\r
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r
+ \r
+ HAL_DACEx_ErrorCallbackCh2(hdac); \r
+ \r
+ hdac->State= HAL_DAC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F756xx || STM32F746xx */\r
+\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DCMI HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Digital Camera Interface (DCMI) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Error functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The sequence below describes how to use this driver to capture image\r
+ from a camera module connected to the DCMI Interface.\r
+ This sequence does not take into account the configuration of the\r
+ camera module, which should be made before to configure and enable\r
+ the DCMI to capture images.\r
+\r
+ (#) Program the required configuration through following parameters:\r
+ horizontal and vertical polarity, pixel clock polarity, Capture Rate,\r
+ Synchronization Mode, code of the frame delimiter and data width \r
+ using HAL_DCMI_Init() function.\r
+\r
+ (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR\r
+ register to the destination memory buffer.\r
+\r
+ (#) Program the required configuration through following parameters:\r
+ DCMI mode, destination memory Buffer address and the data length \r
+ and enable capture using HAL_DCMI_Start_DMA() function.\r
+\r
+ (#) Optionally, configure and Enable the CROP feature to select a rectangular\r
+ window from the received image using HAL_DCMI_ConfigCrop() \r
+ and HAL_DCMI_EnableCROP() functions\r
+\r
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.\r
+\r
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().\r
+\r
+ *** DCMI HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DCMI HAL driver.\r
+ \r
+ (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.\r
+ (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.\r
+ (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.\r
+ (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.\r
+ (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.\r
+ (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.\r
+ (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.\r
+ \r
+ [..] \r
+ (@) You can refer to the DCMI HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup DCMI DCMI\r
+ * @brief DCMI HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);\r
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DCMI\r
+ (+) De-initialize the DCMI \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DCMI according to the specified\r
+ * parameters in the DCMI_InitTypeDef and create the associated handle.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)\r
+{ \r
+ /* Check the DCMI peripheral state */\r
+ if(hdcmi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));\r
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); \r
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));\r
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));\r
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));\r
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));\r
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));\r
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));\r
+\r
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_DCMI_MspInit(hdcmi);\r
+ } \r
+ \r
+ /* Change the DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY; \r
+\r
+ /* Set DCMI parameters */\r
+ /* Configures the HS, VS, DE and PC polarity */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\r
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\r
+ DCMI_CR_ESS);\r
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \\r
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \\r
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \\r
+ hdcmi->Init.JPEGMode);\r
+\r
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)\r
+ {\r
+ DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |\r
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));\r
+ }\r
+\r
+ /* Enable the Line interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);\r
+\r
+ /* Enable the VSYNC interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);\r
+\r
+ /* Enable the Frame capture complete interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);\r
+\r
+ /* Enable the Synchronization error interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);\r
+\r
+ /* Enable the Overflow interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);\r
+\r
+ /* Enable DCMI by setting DCMIEN bit */\r
+ __HAL_DCMI_ENABLE(hdcmi);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r
+ \r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DCMI peripheral registers to their default reset\r
+ * values.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* DeInit the low level hardware */\r
+ HAL_DCMI_MspDeInit(hdcmi);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r
+\r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DCMI MSP.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DCMI MSP.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure destination address and data length and \r
+ Enables DCMI DMA request and enables DCMI capture\r
+ (+) Stop the DCMI capture.\r
+ (+) Handles DCMI interrupt request.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables DCMI DMA request and enables DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.\r
+ * @param pData: The destination memory Buffer address (LCD Frame buffer).\r
+ * @param Length: The length of capture to be transferred.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)\r
+{ \r
+ /* Initialize the second memory address */\r
+ uint32_t SecondMemAddress = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));\r
+\r
+ /* Configure the DCMI Mode */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_CM);\r
+ hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);\r
+\r
+ /* Set the DMA memory0 conversion complete callback */\r
+ hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;\r
+\r
+ if(Length <= 0xFFFF)\r
+ {\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);\r
+ }\r
+ else /* DCMI_DOUBLE_BUFFER Mode */\r
+ {\r
+ /* Set the DMA memory1 conversion complete callback */\r
+ hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt; \r
+\r
+ /* Initialize transfer parameters */\r
+ hdcmi->XferCount = 1;\r
+ hdcmi->XferSize = Length;\r
+ hdcmi->pBuffPtr = pData;\r
+ \r
+ /* Get the number of buffer */\r
+ while(hdcmi->XferSize > 0xFFFF)\r
+ {\r
+ hdcmi->XferSize = (hdcmi->XferSize/2);\r
+ hdcmi->XferCount = hdcmi->XferCount*2;\r
+ }\r
+\r
+ /* Update DCMI counter and transfer number*/\r
+ hdcmi->XferCount = (hdcmi->XferCount - 2);\r
+ hdcmi->XferTransferNumber = hdcmi->XferCount;\r
+\r
+ /* Update second memory address */\r
+ SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));\r
+\r
+ /* Start DMA multi buffer transfer */\r
+ HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);\r
+ }\r
+\r
+ /* Enable Capture */\r
+ DCMI->CR |= DCMI_CR_CAPTURE;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable DCMI DMA request and Disable DCMI capture \r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI. \r
+ * @retval HAL status \r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ __HAL_DCMI_DISABLE(hdcmi);\r
+\r
+ /* Disable Capture */\r
+ DCMI->CR &= ~(DCMI_CR_CAPTURE);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DCMI capture effectively disabled */\r
+ while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+ \r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;\r
+ \r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Disable the DMA */\r
+ HAL_DMA_Abort(hdcmi->DMA_Handle);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;\r
+\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles DCMI interrupt request.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for the DCMI.\r
+ * @retval None\r
+ */\r
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)\r
+{ \r
+ /* Synchronization error interrupt management *******************************/\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)\r
+ {\r
+ if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)\r
+ {\r
+ /* Disable the Synchronization error interrupt */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR); \r
+\r
+ /* Clear the Synchronization error flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;\r
+\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Abort the DMA Transfer */\r
+ HAL_DMA_Abort(hdcmi->DMA_Handle);\r
+ \r
+ /* Synchronization error Callback */\r
+ HAL_DCMI_ErrorCallback(hdcmi);\r
+ }\r
+ }\r
+ /* Overflow interrupt management ********************************************/\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET) \r
+ {\r
+ if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)\r
+ {\r
+ /* Disable the Overflow interrupt */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);\r
+\r
+ /* Clear the Overflow flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;\r
+\r
+ /* Change DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Abort the DMA Transfer */\r
+ HAL_DMA_Abort(hdcmi->DMA_Handle);\r
+\r
+ /* Overflow Callback */\r
+ HAL_DCMI_ErrorCallback(hdcmi);\r
+ }\r
+ }\r
+ /* Line Interrupt management ************************************************/\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)\r
+ {\r
+ if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)\r
+ {\r
+ /* Clear the Line interrupt flag */ \r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* Line interrupt Callback */\r
+ HAL_DCMI_LineEventCallback(hdcmi);\r
+ }\r
+ }\r
+ /* VSYNC interrupt management ***********************************************/\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)\r
+ {\r
+ if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)\r
+ {\r
+ /* Disable the VSYNC interrupt */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC); \r
+\r
+ /* Clear the VSYNC flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* VSYNC Callback */\r
+ HAL_DCMI_VsyncEventCallback(hdcmi);\r
+ }\r
+ }\r
+ /* End of Frame interrupt management ****************************************/\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)\r
+ {\r
+ if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)\r
+ {\r
+ /* Disable the End of Frame interrupt */\r
+ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);\r
+\r
+ /* Clear the End of Frame flag */\r
+ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* End of Frame Callback */\r
+ HAL_DCMI_FrameEventCallback(hdcmi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Error DCMI callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Line Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_LineEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief VSYNC Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_VsyncEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Frame Event callback.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DCMI_FrameEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+[..] This section provides functions allowing to:\r
+ (+) Configure the CROP feature.\r
+ (+) Enable/Disable the CROP feature.\r
+ (+) Enable/Disable the JPEG feature.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the DCMI CROP coordinate.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @param YSize: DCMI Line number\r
+ * @param XSize: DCMI Pixel per line\r
+ * @param X0: DCMI window X offset\r
+ * @param Y0: DCMI window Y offset\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(X0));\r
+ assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));\r
+ assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));\r
+ \r
+ /* Configure CROP */\r
+ DCMI->CWSIZER = (XSize | (YSize << 16));\r
+ DCMI->CWSTRTR = (X0 | (Y0 << 16));\r
+\r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the Crop feature.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Disable DCMI Crop feature */\r
+ DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; \r
+\r
+ /* Change the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Enable the Crop feature.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdcmi);\r
+\r
+ /* Lock the DCMI peripheral state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY;\r
+\r
+ /* Enable DCMI Crop feature */\r
+ DCMI->CR |= (uint32_t)DCMI_CR_CROP;\r
+\r
+ /* Change the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DCMI state.\r
+ (+) Get the specific DCMI error flag. \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the DCMI state\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL state\r
+ */\r
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) \r
+{\r
+ return hdcmi->State;\r
+}\r
+\r
+/**\r
+* @brief Return the DCMI error code\r
+* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+* @retval DCMI Error Code\r
+*/\r
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)\r
+{\r
+ return hdcmi->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DCMI_Private_Functions DCMI Private Functions\r
+ * @{\r
+ */\r
+ /**\r
+ * @brief DMA conversion complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hdcmi->State= HAL_DCMI_STATE_READY;\r
+\r
+ if(hdcmi->XferCount != 0)\r
+ {\r
+ /* Update memory 0 address location */\r
+ tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);\r
+ if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))\r
+ {\r
+ tmp = hdcmi->DMA_Handle->Instance->M0AR;\r
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);\r
+ hdcmi->XferCount--;\r
+ }\r
+ /* Update memory 1 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ tmp = hdcmi->DMA_Handle->Instance->M1AR;\r
+ HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);\r
+ hdcmi->XferCount--;\r
+ }\r
+ }\r
+ /* Update memory 0 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;\r
+ }\r
+ /* Update memory 1 address location */\r
+ else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ tmp = hdcmi->pBuffPtr;\r
+ hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));\r
+ hdcmi->XferCount = hdcmi->XferTransferNumber;\r
+ }\r
+\r
+ if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdcmi);\r
+\r
+ /* FRAME Callback */\r
+ HAL_DCMI_FrameEventCallback(hdcmi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; \r
+ hdcmi->State= HAL_DCMI_STATE_READY;\r
+ HAL_DCMI_ErrorCallback(hdcmi);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dcmi_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DCMI Extension HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of DCMI extension peripheral:\r
+ * + Extension features functions \r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### DCMI peripheral extension features #####\r
+ ==============================================================================\r
+ \r
+ [..] Support of Black and White cameras \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to manage the Black and White feature\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup DCMI DCMI\r
+ * @brief DCMI HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+\r
+#if defined(STM32F746xx) || defined(STM32F756xx)\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DCMI\r
+ (+) De-initialize the DCMI \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DCMI according to the specified\r
+ * parameters in the DCMI_InitTypeDef and create the associated handle.\r
+ * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r
+ * the configuration information for DCMI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)\r
+{ \r
+ /* Check the DCMI peripheral state */\r
+ if(hdcmi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check function parameters */\r
+ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));\r
+ assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));\r
+ assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));\r
+ assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));\r
+ assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));\r
+ assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));\r
+ assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));\r
+ assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));\r
+\r
+ assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));\r
+ assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));\r
+ assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));\r
+ assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));\r
+ \r
+ if(hdcmi->State == HAL_DCMI_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_DCMI_MspInit(hdcmi);\r
+ } \r
+ \r
+ /* Change the DCMI state */\r
+ hdcmi->State = HAL_DCMI_STATE_BUSY; \r
+ /* Configures the HS, VS, DE and PC polarity */\r
+ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\\r
+ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\\r
+ DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\\r
+ DCMI_CR_LSM | DCMI_CR_OELS);\r
+\r
+ hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\\r
+ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\\r
+ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\\r
+ hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\\r
+ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\\r
+ hdcmi->Init.LineSelectStart);\r
+ \r
+ if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)\r
+ {\r
+ DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|\r
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |\r
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));\r
+\r
+ }\r
+\r
+ /* Enable the Line interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);\r
+\r
+ /* Enable the VSYNC interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);\r
+\r
+ /* Enable the Frame capture complete interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);\r
+\r
+ /* Enable the Synchronization error interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);\r
+\r
+ /* Enable the Overflow interrupt */\r
+ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);\r
+\r
+ /* Enable DCMI by setting DCMIEN bit */\r
+ __HAL_DCMI_ENABLE(hdcmi);\r
+\r
+ /* Update error code */\r
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r
+ \r
+ /* Initialize the DCMI state*/\r
+ hdcmi->State = HAL_DCMI_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F746xx || STM32F756xx */\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DMA HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access (DMA) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and errors functions\r
+ @verbatim \r
+ ============================================================================== \r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable and configure the peripheral to be connected to the DMA Stream\r
+ (except for internal SRAM/FLASH memories: no initialization is \r
+ necessary) please refer to Reference manual for connection between peripherals\r
+ and DMA requests . \r
+ \r
+ (#) For a given Stream, program the required configuration through the following parameters: \r
+ Transfer Direction, Source and Destination data formats, \r
+ Circular, Normal or peripheral flow control mode, Stream Priority level, \r
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \r
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r
+ \r
+ *** Polling mode IO operation ***\r
+ ================================= \r
+ [..] \r
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \r
+ address and destination address and the Length of data to be transferred\r
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this \r
+ case a fixed Timeout can be configured by User depending from his application.\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ =================================== \r
+ [..] \r
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() \r
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of \r
+ Source address and destination address and the Length of data to be transferred. In this \r
+ case the DMA interrupt is configured \r
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \r
+ add his own function by customization of function pointer XferCpltCallback and \r
+ XferErrorCallback (i.e a member of DMA handle structure). \r
+ [..] \r
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r
+ detection.\r
+ \r
+ (#) Use HAL_DMA_Abort() function to abort the current transfer\r
+ \r
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+ \r
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r
+ Half-Word data size for the peripheral to access its data register and set Word data size\r
+ for the Memory to gain in access time. Each two half words will be packed and written in\r
+ a single access to a Word in the Memory).\r
+ \r
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r
+ and Destination. In this case the Peripheral Data Size will be applied to both Source\r
+ and Destination. \r
+ \r
+ *** DMA HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DMA HAL driver.\r
+ \r
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r
+ (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.\r
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.\r
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.\r
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.\r
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \r
+ \r
+ [..] \r
+ (@) You can refer to the DMA HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA DMA\r
+ * @brief DMA HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Constants\r
+ * @{\r
+ */\r
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+/**\r
+ * @brief Sets the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Clear DBM bit */\r
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\r
+ \r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This section provides functions allowing to initialize the DMA Stream source\r
+ and destination addresses, incrementation and data sizes, transfer direction, \r
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r
+ [..]\r
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DMA according to the specified\r
+ * parameters in the DMA_InitTypeDef and create the associated handle.\r
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{ \r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\r
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r
+ when FIFO mode is enabled */\r
+ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r
+ {\r
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r
+ }\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Get the CR register value */\r
+ tmp = hdma->Instance->CR;\r
+\r
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r
+ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\r
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \\r
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \\r
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));\r
+\r
+ /* Prepare the DMA Stream configuration */\r
+ tmp |= hdma->Init.Channel | hdma->Init.Direction |\r
+ hdma->Init.PeriphInc | hdma->Init.MemInc |\r
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+ hdma->Init.Mode | hdma->Init.Priority;\r
+\r
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get memory burst and peripheral burst */\r
+ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r
+ }\r
+ \r
+ /* Write to DMA Stream CR register */\r
+ hdma->Instance->CR = tmp; \r
+\r
+ /* Get the FCR register value */\r
+ tmp = hdma->Instance->FCR;\r
+\r
+ /* Clear Direct mode and FIFO threshold bits */\r
+ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r
+\r
+ /* Prepare the DMA Stream FIFO configuration */\r
+ tmp |= hdma->Init.FIFOMode;\r
+\r
+ /* the FIFO threshold is not used when the FIFO mode is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get the FIFO threshold */\r
+ tmp |= hdma->Init.FIFOThreshold;\r
+ }\r
+ \r
+ /* Write to DMA Stream FCR */\r
+ hdma->Instance->FCR = tmp;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA peripheral \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the DMA peripheral state */\r
+ if(hdma->State == HAL_DMA_STATE_BUSY)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the selected DMA Streamx */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Reset DMA Streamx control register */\r
+ hdma->Instance->CR = 0;\r
+\r
+ /* Reset DMA Streamx number of data to transfer register */\r
+ hdma->Instance->NDTR = 0;\r
+\r
+ /* Reset DMA Streamx peripheral address register */\r
+ hdma->Instance->PAR = 0;\r
+\r
+ /* Reset DMA Streamx memory 0 address register */\r
+ hdma->Instance->M0AR = 0;\r
+\r
+ /* Reset DMA Streamx memory 1 address register */\r
+ hdma->Instance->M1AR = 0;\r
+\r
+ /* Reset DMA Streamx FIFO control register */\r
+ hdma->Instance->FCR = (uint32_t)0x00000021;\r
+\r
+ /* Clear all flags */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and Start DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start DMA transfer with interrupt\r
+ (+) Abort DMA transfer\r
+ (+) Poll for transfer complete\r
+ (+) Handle DMA interrupt request \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Start the DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the transfer complete interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);\r
+\r
+ /* Enable the Half transfer complete interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); \r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);\r
+\r
+ /* Enable the FIFO Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);\r
+\r
+ /* Enable the direct mode Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * \r
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is \r
+ * effectively disabled is added. If a Stream is disabled \r
+ * while a data transfer is ongoing, the current data will be transferred\r
+ * and the Stream will be effectively disabled only after the transfer of\r
+ * this single data is finished. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != 0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state*/\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CompleteLevel: Specifies the DMA level complete. \r
+ * @param Timeout: Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)\r
+{\r
+ uint32_t temp, tmp, tmp1, tmp2;\r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Transfer Complete flag */\r
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);\r
+ }\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)\r
+ {\r
+ tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+ tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+ tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+ if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))\r
+ {\r
+ if(tmp != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+\r
+ /* Clear the transfer error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+ }\r
+ if(tmp1 != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ \r
+ /* Clear the FIFO error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+ }\r
+ if(tmp2 != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+\r
+ /* Clear the Direct Mode error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+ }\r
+ /* Change the DMA state */\r
+ hdma->State= HAL_DMA_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_ERROR;\r
+ } \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Multi_Buffering mode enabled */\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+ /* Clear the transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_MEM0;\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_MEM1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+ /* Clear the transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); \r
+\r
+ /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers\r
+ are complete) */\r
+ hdma->State = HAL_DMA_STATE_READY_MEM0;\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ }\r
+ else\r
+ { \r
+ /* Multi_Buffering mode enabled */\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles DMA interrupt request.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval None\r
+ */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer error interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);\r
+\r
+ /* Clear the transfer error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* FIFO Error Interrupt management ******************************************/\r
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\r
+ {\r
+ /* Disable the FIFO Error interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);\r
+\r
+ /* Clear the FIFO error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Direct Mode Error Interrupt management ***********************************/\r
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\r
+ {\r
+ /* Disable the direct mode Error interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);\r
+\r
+ /* Clear the direct mode error flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\r
+ { \r
+ /* Multi_Buffering mode enabled */\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);\r
+ }\r
+ /* Clear the half transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;\r
+ }\r
+\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\r
+ {\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+\r
+ /* Current memory buffer used is Memory 1 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ if(hdma->XferM1CpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory1 */\r
+ hdma->XferM1CpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 0 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) \r
+ {\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory0 */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+ else\r
+ {\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable the transfer complete interrupt */\r
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);\r
+ }\r
+ /* Clear the transfer complete flag */\r
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_NONE;\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY_MEM0;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DMA state\r
+ (+) Get error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the DMA state.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL state\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA error code\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval DMA Error Code\r
+ */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma2d.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DMA2D HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DMA2D peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Program the required configuration through following parameters: \r
+ the Transfer Mode, the output color mode and the output offset using \r
+ HAL_DMA2D_Init() function.\r
+\r
+ (#) Program the required configuration through following parameters: \r
+ the input color mode, the input color, input alpha value, alpha mode \r
+ and the input offset using HAL_DMA2D_ConfigLayer() function for foreground\r
+ or/and background layer.\r
+ \r
+ *** Polling mode IO operation ***\r
+ ================================= \r
+ [..] \r
+ (+) Configure the pdata, Destination and data length and Enable \r
+ the transfer using HAL_DMA2D_Start() \r
+ (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage\r
+ user can specify the value of timeout according to his end application.\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (#) Configure the pdata, Destination and data length and Enable \r
+ the transfer using HAL_DMA2D_Start_IT() \r
+ (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine\r
+ (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can \r
+ add his own function by customization of function pointer XferCpltCallback and \r
+ XferErrorCallback (i.e a member of DMA2D handle structure). \r
+\r
+ -@- In Register-to-Memory transfer mode, the pdata parameter is the register\r
+ color, in Memory-to-memory or memory-to-memory with pixel format\r
+ conversion the pdata is the source address.\r
+\r
+ -@- Configure the foreground source address, the background source address, \r
+ the Destination and data length and Enable the transfer using \r
+ HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()\r
+ in interrupt mode.\r
+ \r
+ -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions\r
+ are used if the memory to memory with blending transfer mode is selected.\r
+ \r
+ (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()\r
+ HAL_DMA2D_EnableCLUT() functions.\r
+\r
+ (#) Optionally, configure and enable LineInterrupt using the following function:\r
+ HAL_DMA2D_ProgramLineEvent().\r
+ \r
+ (#) The transfer can be suspended, continued and aborted using the following\r
+ functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().\r
+ \r
+ (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState() \r
+\r
+ *** DMA2D HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in DMA2D HAL driver :\r
+ \r
+ (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.\r
+ (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.\r
+ (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.\r
+ (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.\r
+ (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.\r
+ (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.\r
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.\r
+ \r
+ [..] \r
+ (@) You can refer to the DMA2D HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @addtogroup DMA2D\r
+ * @brief DMA2D HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup DMA2D_Private_Defines\r
+ * @{\r
+ */\r
+#define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */\r
+#define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup DMA2D_Private_Functions_Prototypes\r
+ * @{\r
+ */\r
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DMA2D_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA2D_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the DMA2D\r
+ (+) De-initialize the DMA2D \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the DMA2D according to the specified\r
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)\r
+{ \r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the DMA2D peripheral state */\r
+ if(hdma2d == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));\r
+ assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));\r
+ assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));\r
+ assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));\r
+\r
+ if(hdma2d->State == HAL_DMA2D_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_DMA2D_MspInit(hdma2d);\r
+ }\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+\r
+/* DMA2D CR register configuration -------------------------------------------*/\r
+ /* Get the CR register value */\r
+ tmp = hdma2d->Instance->CR;\r
+\r
+ /* Clear Mode bits */\r
+ tmp &= (uint32_t)~DMA2D_CR_MODE;\r
+\r
+ /* Prepare the value to be wrote to the CR register */\r
+ tmp |= hdma2d->Init.Mode;\r
+\r
+ /* Write to DMA2D CR register */\r
+ hdma2d->Instance->CR = tmp;\r
+\r
+/* DMA2D OPFCCR register configuration ---------------------------------------*/\r
+ /* Get the OPFCCR register value */\r
+ tmp = hdma2d->Instance->OPFCCR;\r
+\r
+ /* Clear Color Mode bits */\r
+ tmp &= (uint32_t)~DMA2D_OPFCCR_CM;\r
+\r
+ /* Prepare the value to be wrote to the OPFCCR register */\r
+ tmp |= hdma2d->Init.ColorMode;\r
+\r
+ /* Write to DMA2D OPFCCR register */\r
+ hdma2d->Instance->OPFCCR = tmp;\r
+\r
+/* DMA2D OOR register configuration ------------------------------------------*/ \r
+ /* Get the OOR register value */\r
+ tmp = hdma2d->Instance->OOR;\r
+\r
+ /* Clear Offset bits */\r
+ tmp &= (uint32_t)~DMA2D_OOR_LO;\r
+\r
+ /* Prepare the value to be wrote to the OOR register */\r
+ tmp |= hdma2d->Init.OutputOffset;\r
+\r
+ /* Write to DMA2D OOR register */\r
+ hdma2d->Instance->OOR = tmp;\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r
+\r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the DMA2D peripheral registers to their default reset\r
+ * values.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Check the DMA2D peripheral state */\r
+ if(hdma2d == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_DMA2D_MspDeInit(hdma2d);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r
+\r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA2D MSP.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DMA2D_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA2D MSP.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval None\r
+ */\r
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_DMA2D_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the pdata, destination address and data size and \r
+ Start DMA2D transfer.\r
+ (+) Configure the source for foreground and background, destination address \r
+ and data size and Start MultiBuffer DMA2D transfer.\r
+ (+) Configure the pdata, destination address and data size and \r
+ Start DMA2D transfer with interrupt.\r
+ (+) Configure the source for foreground and background, destination address \r
+ and data size and Start MultiBuffer DMA2D transfer with interrupt.\r
+ (+) Abort DMA2D transfer.\r
+ (+) Suspend DMA2D transfer.\r
+ (+) Continue DMA2D transfer. \r
+ (+) Poll for transfer complete.\r
+ (+) handle DMA2D interrupt request.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start the DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param pdata: Configure the source memory Buffer address if \r
+ * the memory to memory or memory to memory with pixel format \r
+ * conversion DMA2D mode is selected, and configure \r
+ * the color value if register to memory DMA2D mode is selected.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_DMA2D_DISABLE(hdma2d);\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the DMA2D Transfer with interrupt enabled.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param pdata: Configure the source memory Buffer address if \r
+ * the memory to memory or memory to memory with pixel format \r
+ * conversion DMA2D mode is selected, and configure \r
+ * the color value if register to memory DMA2D mode is selected.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_DMA2D_DISABLE(hdma2d);\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r
+\r
+ /* Enable the transfer complete interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);\r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ /* Enable the configuration error interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the multi-source DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param SrcAddress1: The source memory Buffer address of the foreground layer.\r
+ * @param SrcAddress2: The source memory Buffer address of the background layer.\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_DMA2D_DISABLE(hdma2d);\r
+\r
+ /* Configure DMA2D Stream source2 address */\r
+ hdma2d->Instance->BGMAR = SrcAddress2;\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Start the multi-source DMA2D Transfer with interrupt enabled.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param SrcAddress1: The source memory Buffer address of the foreground layer.\r
+ * @param SrcAddress2: The source memory Buffer address of the background layer.\r
+ * @param DstAddress: The destination memory Buffer address.\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+\r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LINE(Height));\r
+ assert_param(IS_DMA2D_PIXEL(Width));\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_DMA2D_DISABLE(hdma2d);\r
+ \r
+ /* Configure DMA2D Stream source2 address */\r
+ hdma2d->Instance->BGMAR = SrcAddress2;\r
+\r
+ /* Configure the source, destination address and the data size */\r
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r
+\r
+ /* Enable the configuration error interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);\r
+\r
+ /* Enable the transfer complete interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);\r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA2D_ENABLE(hdma2d);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort the DMA2D Transfer.\r
+ * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Disable the DMA2D */\r
+ __HAL_DMA2D_DISABLE(hdma2d);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DMA2D is effectively disabled */\r
+ while((hdma2d->Instance->CR & DMA2D_CR_START) != 0)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+\r
+ /* Change the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Suspend the DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Suspend the DMA2D transfer */\r
+ hdma2d->Instance->CR |= DMA2D_CR_SUSP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check if the DMA2D is effectively suspended */\r
+ while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Change the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resume the DMA2D Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ /* Resume the DMA2D transfer */\r
+ hdma2d->Instance->CR &= ~DMA2D_CR_SUSP;\r
+\r
+ /* Change the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete or CLUT loading.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)\r
+{\r
+ uint32_t tmp, tmp1;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Polling for DMA2D transfer */\r
+ if((hdma2d->Instance->CR & DMA2D_CR_START) != 0)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)\r
+ {\r
+ tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE);\r
+ tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE);\r
+\r
+ if((tmp != RESET) || (tmp1 != RESET))\r
+ {\r
+ /* Clear the transfer and configuration error flags */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);\r
+\r
+ /* Change DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+\r
+ /* Change the DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ }\r
+ /* Polling for CLUT loading */\r
+ if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)\r
+ {\r
+ if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))\r
+ { \r
+ /* Clear the transfer and configuration error flags */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);\r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_ERROR;\r
+ \r
+ return HAL_ERROR; \r
+ } \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA2D state */\r
+ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ }\r
+ /* Clear the transfer complete flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);\r
+ \r
+ /* Clear the CLUT loading flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d);\r
+ \r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Handles DMA2D interrupt request.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL status\r
+ */\r
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)\r
+{ \r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)\r
+ {\r
+ if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer Error interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); \r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;\r
+ \r
+ /* Clear the transfer error flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);\r
+\r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error Callback */\r
+ hdma2d->XferErrorCallback(hdma2d);\r
+ }\r
+ }\r
+ }\r
+ /* Configuration Error Interrupt management **********************************/\r
+ if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)\r
+ {\r
+ if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)\r
+ {\r
+ /* Disable the Configuration Error interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);\r
+ \r
+ /* Clear the Configuration error flag */\r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error Callback */\r
+ hdma2d->XferErrorCallback(hdma2d);\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Complete Interrupt management ************************************/\r
+ if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)\r
+ {\r
+ if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)\r
+ { \r
+ /* Disable the transfer complete interrupt */\r
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);\r
+ \r
+ /* Clear the transfer complete flag */ \r
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);\r
+\r
+ /* Update error code */\r
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; \r
+ \r
+ /* Change DMA2D state */\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ if(hdma2d->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback */\r
+ hdma2d->XferCpltCallback(hdma2d);\r
+ } \r
+ }\r
+ }\r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the DMA2D foreground or/and background parameters.\r
+ (+) Configure the DMA2D CLUT transfer.\r
+ (+) Enable DMA2D CLUT.\r
+ (+) Disable DMA2D CLUT.\r
+ (+) Configure the line watermark\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configure the DMA2D Layer according to the specified\r
+ * parameters in the DMA2D_InitTypeDef and create the associated handle.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{ \r
+ DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];\r
+ \r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); \r
+ if(hdma2d->Init.Mode != DMA2D_R2M)\r
+ { \r
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));\r
+ if(hdma2d->Init.Mode != DMA2D_M2M)\r
+ {\r
+ assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));\r
+ }\r
+ }\r
+ \r
+ /* Configure the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* DMA2D BGPFCR register configuration -----------------------------------*/\r
+ /* Get the BGPFCCR register value */\r
+ tmp = hdma2d->Instance->BGPFCCR;\r
+ \r
+ /* Clear Input color mode, alpha value and alpha mode bits */\r
+ tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); \r
+ \r
+ if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
+ {\r
+ /* Prepare the value to be wrote to the BGPFCCR register */\r
+ tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));\r
+ }\r
+ else\r
+ {\r
+ /* Prepare the value to be wrote to the BGPFCCR register */\r
+ tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));\r
+ }\r
+ \r
+ /* Write to DMA2D BGPFCCR register */\r
+ hdma2d->Instance->BGPFCCR = tmp; \r
+ \r
+ /* DMA2D BGOR register configuration -------------------------------------*/ \r
+ /* Get the BGOR register value */\r
+ tmp = hdma2d->Instance->BGOR;\r
+ \r
+ /* Clear colors bits */\r
+ tmp &= (uint32_t)~DMA2D_BGOR_LO; \r
+ \r
+ /* Prepare the value to be wrote to the BGOR register */\r
+ tmp |= pLayerCfg->InputOffset;\r
+ \r
+ /* Write to DMA2D BGOR register */\r
+ hdma2d->Instance->BGOR = tmp;\r
+ \r
+ if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
+ {\r
+ /* Prepare the value to be wrote to the BGCOLR register */\r
+ tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
+ \r
+ /* Write to DMA2D BGCOLR register */\r
+ hdma2d->Instance->BGCOLR = tmp;\r
+ } \r
+ }\r
+ /* Configure the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* DMA2D FGPFCR register configuration -----------------------------------*/\r
+ /* Get the FGPFCCR register value */\r
+ tmp = hdma2d->Instance->FGPFCCR;\r
+ \r
+ /* Clear Input color mode, alpha value and alpha mode bits */\r
+ tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); \r
+ \r
+ if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
+ {\r
+ /* Prepare the value to be wrote to the FGPFCCR register */\r
+ tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));\r
+ }\r
+ else\r
+ {\r
+ /* Prepare the value to be wrote to the FGPFCCR register */\r
+ tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));\r
+ }\r
+ \r
+ /* Write to DMA2D FGPFCCR register */\r
+ hdma2d->Instance->FGPFCCR = tmp; \r
+ \r
+ /* DMA2D FGOR register configuration -------------------------------------*/ \r
+ /* Get the FGOR register value */\r
+ tmp = hdma2d->Instance->FGOR;\r
+ \r
+ /* Clear colors bits */\r
+ tmp &= (uint32_t)~DMA2D_FGOR_LO; \r
+ \r
+ /* Prepare the value to be wrote to the FGOR register */\r
+ tmp |= pLayerCfg->InputOffset;\r
+ \r
+ /* Write to DMA2D FGOR register */\r
+ hdma2d->Instance->FGOR = tmp;\r
+ \r
+ if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))\r
+ {\r
+ /* Prepare the value to be wrote to the FGCOLR register */\r
+ tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);\r
+ \r
+ /* Write to DMA2D FGCOLR register */\r
+ hdma2d->Instance->FGCOLR = tmp;\r
+ } \r
+ } \r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA2D CLUT Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r
+ * the configuration information for the color look up table.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx)); \r
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r
+ \r
+ /* Configure the CLUT of the background DMA2D layer */\r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Get the BGCMAR register value */\r
+ tmp = hdma2d->Instance->BGCMAR;\r
+\r
+ /* Clear CLUT address bits */\r
+ tmp &= (uint32_t)~DMA2D_BGCMAR_MA; \r
+ \r
+ /* Prepare the value to be wrote to the BGCMAR register */\r
+ tmp |= (uint32_t)CLUTCfg.pCLUT;\r
+ \r
+ /* Write to DMA2D BGCMAR register */\r
+ hdma2d->Instance->BGCMAR = tmp;\r
+ \r
+ /* Get the BGPFCCR register value */\r
+ tmp = hdma2d->Instance->BGPFCCR;\r
+\r
+ /* Clear CLUT size and CLUT address bits */\r
+ tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM); \r
+\r
+ /* Get the CLUT size */\r
+ tmp1 = CLUTCfg.Size << 16;\r
+ \r
+ /* Prepare the value to be wrote to the BGPFCCR register */\r
+ tmp |= (CLUTCfg.CLUTColorMode | tmp1);\r
+ \r
+ /* Write to DMA2D BGPFCCR register */\r
+ hdma2d->Instance->BGPFCCR = tmp; \r
+ }\r
+ /* Configure the CLUT of the foreground DMA2D layer */\r
+ else\r
+ {\r
+ /* Get the FGCMAR register value */\r
+ tmp = hdma2d->Instance->FGCMAR;\r
+\r
+ /* Clear CLUT address bits */\r
+ tmp &= (uint32_t)~DMA2D_FGCMAR_MA; \r
+ \r
+ /* Prepare the value to be wrote to the FGCMAR register */\r
+ tmp |= (uint32_t)CLUTCfg.pCLUT;\r
+ \r
+ /* Write to DMA2D FGCMAR register */\r
+ hdma2d->Instance->FGCMAR = tmp;\r
+ \r
+ /* Get the FGPFCCR register value */\r
+ tmp = hdma2d->Instance->FGPFCCR;\r
+\r
+ /* Clear CLUT size and CLUT address bits */\r
+ tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM); \r
+\r
+ /* Get the CLUT size */\r
+ tmp1 = CLUTCfg.Size << 8;\r
+ \r
+ /* Prepare the value to be wrote to the FGPFCCR register */\r
+ tmp |= (CLUTCfg.CLUTColorMode | tmp1);\r
+ \r
+ /* Write to DMA2D FGPFCCR register */\r
+ hdma2d->Instance->FGPFCCR = tmp; \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the DMA2D CLUT Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx));\r
+ \r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Enable the CLUT loading for the background */\r
+ hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;\r
+ }\r
+ else\r
+ {\r
+ /* Enable the CLUT loading for the foreground */\r
+ hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the DMA2D CLUT Transfer.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param LayerIdx: DMA2D Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0(background) / 1(foreground)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LAYER(LayerIdx));\r
+ \r
+ if(LayerIdx == 0)\r
+ {\r
+ /* Disable the CLUT loading for the background */\r
+ hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the CLUT loading for the foreground */\r
+ hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Define the configuration of the line watermark .\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D.\r
+ * @param Line: Line Watermark configuration.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma2d);\r
+ \r
+ /* Change DMA2D peripheral state */\r
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA2D_LineWatermark(Line));\r
+\r
+ /* Sets the Line watermark configuration */\r
+ DMA2D->LWR = (uint32_t)Line;\r
+ \r
+ /* Initialize the DMA2D state*/\r
+ hdma2d->State = HAL_DMA2D_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma2d); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA2D_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Check the DMA2D state\r
+ (+) Get error code \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the DMA2D state\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the DMA2D. \r
+ * @retval HAL state\r
+ */\r
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)\r
+{ \r
+ return hdma2d->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA2D error code\r
+ * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for DMA2D.\r
+ * @retval DMA2D Error Code\r
+ */\r
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)\r
+{\r
+ return hdma2d->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Set the DMA2D Transfer parameter.\r
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA2D. \r
+ * @param pdata: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param Width: The width of data to be transferred from source to destination.\r
+ * @param Height: The height of data to be transferred from source to destination.\r
+ * @retval HAL status\r
+ */\r
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r
+{ \r
+ uint32_t tmp = 0;\r
+ uint32_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+ uint32_t tmp3 = 0;\r
+ uint32_t tmp4 = 0;\r
+ \r
+ tmp = Width << 16;\r
+ \r
+ /* Configure DMA2D data size */\r
+ hdma2d->Instance->NLR = (Height | tmp);\r
+ \r
+ /* Configure DMA2D destination address */\r
+ hdma2d->Instance->OMAR = DstAddress;\r
+ \r
+ /* Register to memory DMA2D mode selected */\r
+ if (hdma2d->Init.Mode == DMA2D_R2M)\r
+ { \r
+ tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;\r
+ tmp2 = pdata & DMA2D_OCOLR_RED_1;\r
+ tmp3 = pdata & DMA2D_OCOLR_GREEN_1;\r
+ tmp4 = pdata & DMA2D_OCOLR_BLUE_1;\r
+ \r
+ /* Prepare the value to be wrote to the OCOLR register according to the color mode */\r
+ if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)\r
+ {\r
+ tmp = (tmp3 | tmp2 | tmp1| tmp4);\r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_RGB888)\r
+ {\r
+ tmp = (tmp3 | tmp2 | tmp4); \r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_RGB565)\r
+ {\r
+ tmp2 = (tmp2 >> 19);\r
+ tmp3 = (tmp3 >> 10);\r
+ tmp4 = (tmp4 >> 3 );\r
+ tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); \r
+ }\r
+ else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)\r
+ { \r
+ tmp1 = (tmp1 >> 31);\r
+ tmp2 = (tmp2 >> 19);\r
+ tmp3 = (tmp3 >> 11);\r
+ tmp4 = (tmp4 >> 3 ); \r
+ tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); \r
+ } \r
+ else /* DMA2D_CMode = DMA2D_ARGB4444 */\r
+ {\r
+ tmp1 = (tmp1 >> 28);\r
+ tmp2 = (tmp2 >> 20);\r
+ tmp3 = (tmp3 >> 12);\r
+ tmp4 = (tmp4 >> 4 );\r
+ tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);\r
+ } \r
+ /* Write to DMA2D OCOLR register */\r
+ hdma2d->Instance->OCOLR = tmp;\r
+ } \r
+ else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */\r
+ {\r
+ /* Configure DMA2D source address */\r
+ hdma2d->Instance->FGMAR = pdata;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief DMA Extension HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DMA Extension peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The DMA Extension HAL driver can be used as follows:\r
+ (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r
+ \r
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+ -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.\r
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for \r
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+ * @brief DMA Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+\r
+/**\r
+ * @brief Set the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{ \r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+ \r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ { \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+ \r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup DMAEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer with interrupt\r
+ (+) Change on the fly the memory0 or memory1 address.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_BUSY_MEM0;\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_BUSY_MEM1;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma); \r
+\r
+ /* Enable the double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == 0)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_BUSY_MEM0;\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_BUSY_MEM1;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma); \r
+\r
+ /* Enable the Double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \r
+\r
+ /* Enable the transfer complete interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);\r
+\r
+ /* Enable the Half transfer interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);\r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);\r
+\r
+ /* Enable the fifo Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); \r
+\r
+ /* Enable the direct mode Error interrupt */\r
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); \r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Change the memory0 or memory1 address on the fly.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param Address: The new address\r
+ * @param memory: the memory to be changed, This parameter can be one of \r
+ * the following values:\r
+ * MEMORY0 /\r
+ * MEMORY1\r
+ * @note The MEMORY0 address can be changed only when the current transfer use\r
+ * MEMORY1 and the MEMORY1 address can be changed only when the current \r
+ * transfer use MEMORY0.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r
+{\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ hdma->Instance->M0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ hdma->Instance->M1AR = Address;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+ \r
+ (#)Fill parameters of Init structure in heth handle\r
+ \r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) \r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using \r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode) \r
+ \r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer \r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received \r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY \r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+ \r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH \r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */\r
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tempreg = 0, phyreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t tickstart = 0;\r
+ uint32_t err = ETH_SUCCESS;\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); \r
+ \r
+ if(heth->State == HAL_ETH_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit(heth);\r
+ }\r
+ \r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+ \r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+ \r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ (heth->Instance)->DMABMR |= ETH_DMABMR_SR;\r
+ \r
+ /* Wait for software reset */\r
+ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ }\r
+ \r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tempreg = (heth->Instance)->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tempreg &= ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Get hclk frequency value */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+ \r
+ /* Set CR bits depending on hclk value */\r
+ if((hclk >= 20000000)&&(hclk < 35000000))\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if((hclk >= 35000000)&&(hclk < 60000000))\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;\r
+ } \r
+ else if((hclk >= 60000000)&&(hclk < 100000000))\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ } \r
+ else if((hclk >= 100000000)&&(hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-200 MHz */ \r
+ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; \r
+ }\r
+ \r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ (heth->Instance)->MACMIIAR = (uint32_t)tempreg;\r
+ \r
+ /*-------------------- PHY initialization and configuration ----------------*/\r
+ /* Put the PHY in reset mode */\r
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Delay to assure PHY reset */\r
+ HAL_Delay(PHY_RESET_DELAY);\r
+ \r
+ if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* We wait for linked status */\r
+ do\r
+ {\r
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r
+ \r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));\r
+\r
+ \r
+ /* Enable Auto-Negotiation */\r
+ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until the auto-negotiation will be completed */\r
+ do\r
+ {\r
+ HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r
+ \r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));\r
+ \r
+ /* Read the result of the auto-negotiation */\r
+ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */\r
+ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */\r
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; \r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */\r
+ (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; \r
+ }\r
+ /* Configure the MAC with the speed fixed by the auto-negotiation process */\r
+ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)\r
+ { \r
+ /* Set Ethernet speed to 10M following the auto-negotiation */\r
+ (heth->Init).Speed = ETH_SPEED_10M; \r
+ }\r
+ else\r
+ { \r
+ /* Set Ethernet speed to 100M following the auto-negotiation */ \r
+ (heth->Init).Speed = ETH_SPEED_100M;\r
+ }\r
+ }\r
+ else /* AutoNegotiation Disable */\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+ \r
+ /* Set MAC Speed and Duplex Mode */\r
+ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |\r
+ (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)\r
+ {\r
+ /* In case of write timeout */\r
+ err = ETH_ERROR;\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set the ETH peripheral state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return HAL_ERROR */\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ /* Delay to assure PHY configuration */\r
+ HAL_Delay(PHY_CONFIG_DELAY);\r
+ }\r
+ \r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit(heth);\r
+ \r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(heth);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param DMATxDescTab: Pointer to the first Tx desc list \r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *dmatxdesc;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ heth->TxDesc = DMATxDescTab;\r
+ \r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ dmatxdesc = DMATxDescTab + i;\r
+ \r
+ /* Set Second Address Chained bit */\r
+ dmatxdesc->Status = ETH_DMATXDESC_TCH; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);\r
+ \r
+ if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion */\r
+ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+ \r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Descriptor List Address Register */\r
+ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param DMARxDescTab: Pointer to the first Rx desc list \r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *DMARxDesc;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */\r
+ heth->RxDesc = DMARxDescTab; \r
+ \r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ \r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARXDESC_OWN;\r
+ \r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);\r
+ \r
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+ \r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ }\r
+ \r
+ /* Set Receive Descriptor List Address Register */\r
+ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+ \r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ if (FrameLength == 0) \r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)\r
+ { \r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get the number of needed Tx buffers for the current frame */\r
+ if (FrameLength > ETH_TX_BUF_SIZE)\r
+ {\r
+ bufcount = FrameLength/ETH_TX_BUF_SIZE;\r
+ if (FrameLength % ETH_TX_BUF_SIZE) \r
+ {\r
+ bufcount++;\r
+ }\r
+ }\r
+ else \r
+ { \r
+ bufcount = 1;\r
+ }\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r
+ }\r
+ else\r
+ {\r
+ for (i=0; i< bufcount; i++)\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);\r
+ \r
+ if (i == 0) \r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_FS; \r
+ }\r
+ \r
+ /* Program size */\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ \r
+ if (i == (bufcount-1))\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+ \r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r
+ }\r
+ }\r
+ \r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ (heth->Instance)->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ (heth->Instance)->DMATPDR = 0;\r
+ }\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t framelength = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Check if segment is not owned by DMA */\r
+ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */\r
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))\r
+ {\r
+ /* Check if last segment */\r
+ if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) \r
+ {\r
+ /* increment segment count */\r
+ (heth->RxFrameInfos).SegCount++;\r
+ \r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if ((heth->RxFrameInfos).SegCount == 1)\r
+ {\r
+ (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;\r
+ }\r
+ \r
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r
+ \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r
+ heth->RxFrameInfos.length = framelength;\r
+ \r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r
+ /* point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ /* Check if first segment */\r
+ else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)\r
+ {\r
+ (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;\r
+ (heth->RxFrameInfos).LSRxDesc = NULL;\r
+ (heth->RxFrameInfos).SegCount = 1;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Check if intermediate segment */ \r
+ else\r
+ {\r
+ (heth->RxFrameInfos).SegCount++;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ } \r
+ }\r
+ \r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Gets the Received frame in interrupt mode. \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t descriptorscancounter = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set ETH HAL State to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Scan descriptors owned by CPU */\r
+ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))\r
+ {\r
+ /* Just for security */\r
+ descriptorscancounter++;\r
+ \r
+ /* Check if first segment in frame */\r
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ \r
+ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)\r
+ { \r
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r
+ heth->RxFrameInfos.SegCount = 1; \r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Check if intermediate segment */\r
+ /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */\r
+ else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)\r
+ {\r
+ /* Increment segment count */\r
+ (heth->RxFrameInfos.SegCount)++;\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);\r
+ }\r
+ /* Should be last segment */\r
+ else\r
+ { \r
+ /* Last segment */\r
+ heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r
+ \r
+ /* Increment segment count */\r
+ (heth->RxFrameInfos.SegCount)++;\r
+ \r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if ((heth->RxFrameInfos.SegCount) == 1)\r
+ {\r
+ heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r
+ }\r
+ \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r
+ \r
+ /* Get the address of the buffer start address */ \r
+ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r
+ \r
+ /* Point to next descriptor */ \r
+ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ }\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief This function handles ETH interrupt request.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Frame received */\r
+ if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) \r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback(heth);\r
+ \r
+ /* Clear the Eth DMA Rx IT pending bits */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+\r
+ }\r
+ /* Frame transmitted */\r
+ else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) \r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback(heth);\r
+ \r
+ /* Clear the Eth DMA Tx IT pending bits */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);\r
+\r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ }\r
+ \r
+ /* Clear the interrupt flags */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);\r
+ \r
+ /* ETH DMA Error */\r
+ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback(heth);\r
+\r
+ /* Clear the interrupt flags */\r
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);\r
+ \r
+ /* Set HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * PHY_BCR: Transceiver Basic Control Register, \r
+ * PHY_BSR: Transceiver Basic Status Register. \r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+ uint32_t tmpreg = 0; \r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth->State == HAL_ETH_STATE_BUSY_RD)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ \r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Prepare the MII address register value */\r
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ \r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check for the Busy flag */\r
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > PHY_READ_TO)\r
+ {\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ }\r
+ \r
+ /* Get MACMIIDR value */\r
+ *RegValue = (uint16_t)(heth->Instance->MACMIIDR);\r
+ \r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * PHY_BCR: Transceiver Control Register. \r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+ \r
+ /* Check the ETH peripheral state */\r
+ if(heth->State == HAL_ETH_STATE_BUSY_WR)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ \r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+ \r
+ /* Prepare the MII register address value */\r
+ tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ \r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = (uint16_t)RegValue;\r
+ \r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check for the Busy flag */\r
+ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)\r
+ {\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ }\r
+ \r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception. \r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable(heth);\r
+ \r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable(heth);\r
+ \r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO(heth);\r
+ \r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable(heth);\r
+ \r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable(heth);\r
+ \r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission \r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+ \r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable(heth);\r
+ \r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable(heth);\r
+ \r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable(heth);\r
+ \r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO(heth);\r
+ \r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable(heth);\r
+ \r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+ \r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); \r
+ \r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+ \r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ \r
+ tmpreg |= (uint32_t)(macconf->Watchdog | \r
+ macconf->Jabber | \r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ (heth->Init).Speed | \r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ (heth->Init).DuplexMode | \r
+ macconf->ChecksumOffload | \r
+ macconf->RetryTransmission | \r
+ macconf->AutomaticPadCRCStrip | \r
+ macconf->BackOffLimit | \r
+ macconf->DeferralCheck);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg; \r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Write to ETHERNET MACFFR */ \r
+ (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | \r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception | \r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFFR = tmpreg;\r
+ \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+ \r
+ /* Write to ETHERNET MACHTLR */\r
+ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+ \r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+ \r
+ tmpreg |= (uint32_t)((macconf->PauseTime << 16) | \r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect | \r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl); \r
+ \r
+ /* Write to ETHERNET MACFCR */\r
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFCR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | \r
+ macconf->VLANTagIdentifier);\r
+ \r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ \r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+ \r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+ }\r
+ \r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(heth);\r
+ \r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+ \r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | \r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward | \r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | \r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration | \r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(heth);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+ \r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;\r
+ \r
+ /* Set Ethernet speed to 100M */\r
+ (heth->Init).Speed = ETH_SPEED_100M;\r
+ }\r
+ \r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+ \r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */ \r
+ /* Set the DO bit according to ETH ReceiveOwn value */ \r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */ \r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog | \r
+ macinit.Jabber | \r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ (heth->Init).Speed | \r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ (heth->Init).DuplexMode | \r
+ macinit.ChecksumOffload | \r
+ macinit.RetryTransmission | \r
+ macinit.AutomaticPadCRCStrip | \r
+ macinit.BackOffLimit | \r
+ macinit.DeferralCheck);\r
+ \r
+ /* Write to ETHERNET MACCR */\r
+ (heth->Instance)->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg; \r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */ \r
+ (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | \r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception | \r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFFR = tmpreg;\r
+ \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+ \r
+ /* Write to ETHERNET MACHTLR */\r
+ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+ \r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+ \r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */ \r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) | \r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect | \r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl); \r
+ \r
+ /* Write to ETHERNET MACFCR */\r
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACFCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACFCR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */ \r
+ (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | \r
+ macinit.VLANTagIdentifier);\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACVLANTR = tmpreg;\r
+ \r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; \r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+ \r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+ \r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | \r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward | \r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+ \r
+ /* Write to ETHERNET DMAOMR */\r
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+ \r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | \r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMABMR = tmpreg;\r
+\r
+ if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */ \r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0 \r
+ * @arg ETH_MAC_Address1: MAC Address1 \r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];\r
+ /* Load the selected MAC address high register */\r
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];\r
+ \r
+ /* Load the selected MAC address low register */\r
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Enable the MAC transmission */\r
+ (heth->Instance)->MACCR |= ETH_MACCR_TE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Disable the MAC transmission */\r
+ (heth->Instance)->MACCR &= ~ETH_MACCR_TE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Enable the MAC reception */\r
+ (heth->Instance)->MACCR |= ETH_MACCR_RE;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Disable the MAC reception */\r
+ (heth->Instance)->MACCR &= ~ETH_MACCR_RE; \r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->MACCR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->MACCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; \r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Disable the DMA transmission */\r
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Enable the DMA reception */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; \r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module \r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{ \r
+ /* Disable the DMA reception */\r
+ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+ \r
+ /* Set the Flush Transmit FIFO bit */\r
+ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;\r
+ \r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = (heth->Instance)->DMAOMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ (heth->Instance)->DMAOMR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the internal FLASH memory:\r
+ * + Program operations functions\r
+ * + Memory Control functions \r
+ * + Peripheral Errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FLASH peripheral features #####\r
+ ==============================================================================\r
+ \r
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r
+ to the Flash memory. It implements the erase and program Flash memory operations \r
+ and the read and write protection mechanisms.\r
+ \r
+ [..] The Flash memory interface accelerates code execution with a system of instruction\r
+ prefetch and cache lines. \r
+\r
+ [..] The FLASH main features are:\r
+ (+) Flash memory read operations\r
+ (+) Flash memory program/erase operations\r
+ (+) Read / write protections\r
+ (+) Prefetch on I-Code\r
+ (+) 64 cache lines of 128 bits on I-Code\r
+ (+) 8 cache lines of 128 bits on D-Code\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver provides functions and macros to configure and program the FLASH \r
+ memory of all STM32F7xx devices.\r
+ \r
+ (#) FLASH Memory IO Programming functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Program functions: byte, half word, word and double word\r
+ (++) There Two modes of programming :\r
+ (+++) Polling mode using HAL_FLASH_Program() function\r
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r
+ \r
+ (#) Interrupts and flags management functions : \r
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r
+ (++) Wait for last FLASH operation according to its status\r
+ (++) Get error flag status by calling HAL_SetErrorCode() \r
+ [..] \r
+ In addition to these functions, this driver includes a set of macros allowing\r
+ to handle the following operations:\r
+ (+) Set the latency\r
+ (+) Enable/Disable the prefetch buffer\r
+ (+) Enable/Disable the Instruction cache and the Data cache\r
+ (+) Reset the Instruction cache and the Data cache\r
+ (+) Enable/Disable the FLASH interrupts\r
+ (+) Monitor the FLASH flags status\r
+ [..] \r
+ (@) For any Flash memory program operation (erase or program), the CPU clock frequency\r
+ (HCLK) must be at least 1MHz. \r
+ (@) The contents of the Flash memory are not guaranteed if a device reset occurs during \r
+ a Flash memory operation.\r
+ (@) Any attempt to read the Flash memory while it is being written or erased, causes the \r
+ bus to stall. Read operations are processed correctly once the program operation has \r
+ completed. This means that code or data fetches cannot be performed while a write/erase \r
+ operation is ongoing.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH FLASH\r
+ * @brief FLASH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Constants\r
+ * @{\r
+ */\r
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07)\r
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+/* Variable used for Erase sectors under interruption */\r
+FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+/* Program operations */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);\r
+static void FLASH_SetErrorCode(void);\r
+\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r
+ * @brief Programming operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the FLASH \r
+ program operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address\r
+ * @param TypeProgram: Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.\r
+ * @param TypeProgram: Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
+ pFlash.Address = Address;\r
+ \r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function handles FLASH interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_FLASH_IRQHandler(void)\r
+{\r
+ uint32_t temp = 0;\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+\r
+ /* If the erase operation is completed, disable the SER Bit */\r
+ FLASH->CR &= (~FLASH_CR_SER);\r
+ FLASH->CR &= SECTOR_MASK; \r
+\r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+\r
+ /* Check FLASH End of Operation flag */\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r
+ {\r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* Nb of sector to erased can be decreased */\r
+ pFlash.NbSectorsToErase--;\r
+\r
+ /* Check if there are still sectors to erase */\r
+ if(pFlash.NbSectorsToErase != 0)\r
+ {\r
+ temp = pFlash.Sector;\r
+ /* Indicate user which sector has been erased */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+\r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); \r
+\r
+ /* Increment sector number */\r
+ temp = ++pFlash.Sector;\r
+ FLASH_Erase_Sector(temp, pFlash.VoltageForErase);\r
+ }\r
+ else\r
+ {\r
+ /* No more sectors to Erase, user callback can be called.*/\r
+ /* Reset Sector and stop Erase sectors procedure */\r
+ pFlash.Sector = temp = 0xFFFFFFFF;\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+ /* Sector Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ }\r
+ break;\r
+ }\r
+ \r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* MassErase ended. Return the selected bank : in this product we don't have Banks */\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(0);\r
+ /* MAss Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ break;\r
+ }\r
+\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*Program ended. Return the selected address*/\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
+ /* Programming procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Check FLASH operation error flags */\r
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r
+ {\r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* return the faulty sector */\r
+ temp = pFlash.Sector;\r
+ pFlash.Sector = 0xFFFFFFFF;\r
+ break;\r
+ }\r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* No return in case of Mass Erase */\r
+ temp = 0;\r
+ break;\r
+ }\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*return the faulty address*/\r
+ temp = pFlash.Address;\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /*Save the Error code*/\r
+ FLASH_SetErrorCode();\r
+\r
+ /* FLASH error interrupt user callback */\r
+ HAL_FLASH_OperationErrorCallback(temp);\r
+ /* Clear FLASH error pending bits */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );\r
+\r
+ /*Stop the procedure ongoing */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+ \r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
+ {\r
+ /* Disable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\r
+\r
+ /* Disable Error source interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief FLASH end of operation interrupt callback\r
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FLASH operation error interrupt callback\r
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the FLASH \r
+ memory operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlock the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
+{\r
+ if((FLASH->CR & FLASH_CR_LOCK) != RESET)\r
+ {\r
+ /* Authorize the FLASH Registers access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
+{\r
+ /* Set the LOCK Bit to lock the FLASH Registers access */\r
+ FLASH->CR |= FLASH_CR_LOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Unlock the FLASH Option Control Registers access.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r
+ {\r
+ /* Authorizes the Option Byte register programming */\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY1;\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Lock the FLASH Option Control Registers access.\r
+ * @retval HAL Status \r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OPTSTRT bit in OPTCR register */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;\r
+\r
+ /* Wait for last operation to be completed */\r
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time Errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get the specific FLASH error flag.\r
+ * @param None\r
+ * @retval FLASH_ErrorCode: The returned value can be:\r
+ * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r
+ * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag \r
+ * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r
+ * @arg FLASH_ERROR_WRP: FLASH Write protected error flag\r
+ * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag \r
+ */\r
+uint32_t HAL_FLASH_GetError(void)\r
+{ \r
+ return pFlash.ErrorCode;\r
+} \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @brief Wait for a FLASH operation to complete.\r
+ * @param Timeout: maximum flash operationtimeout\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Clear Error Code */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+ \r
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+ flag will be set */\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \r
+ { \r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\r
+ FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r
+ {\r
+ /*Save the error code*/\r
+ FLASH_SetErrorCode();\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* If there is an error flag set */\r
+ return HAL_OK;\r
+ \r
+} \r
+\r
+/**\r
+ * @brief Program a double word (64-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V and an External Vpp is present.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+ \r
+ *(__IO uint64_t*)Address = Data;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Program word (32-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint32_t*)Address = Data;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Program a half-word (16-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint16_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Program byte (8-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_BYTE;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint8_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Set the specific FLASH error flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void FLASH_SetErrorCode(void)\r
+{ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extended FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH extension peripheral:\r
+ * + Extended programming operations functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Flash Extension features #####\r
+ ==============================================================================\r
+ \r
+ [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and \r
+ devices contains the following additional features \r
+ \r
+ (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r
+ capability (RWW)\r
+ (+) Dual bank memory organization \r
+ (+) PCROP protection for all banks\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the FLASH memory \r
+ of all STM32F7xx devices. It includes\r
+ (#) FLASH Memory Erase functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Erase function: Erase sector, erase all sectors\r
+ (++) There are two modes of erase :\r
+ (+++) Polling Mode using HAL_FLASHEx_Erase()\r
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r
+ \r
+ (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\r
+ (++) Set/Reset the write protection\r
+ (++) Set the Read protection Level\r
+ (++) Set the BOR level\r
+ (++) Program the user Option Bytes\r
+ (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : \r
+ (++) Extended space (bank 2) erase function\r
+ (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)\r
+ (++) Dual Boot activation\r
+ (++) Write protection configuration for bank 2\r
+ (++) PCROP protection configuration and control for both banks\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx FLASHEx\r
+ * @brief FLASH HAL Extension module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Constants\r
+ * @{\r
+ */ \r
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07)\r
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Variables\r
+ * @{\r
+ */ \r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Functions\r
+ * @{\r
+ */\r
+/* Option bytes control */\r
+static void FLASH_MassErase(uint8_t VoltageRange);\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);\r
+static uint32_t FLASH_OB_GetUser(void);\r
+static uint32_t FLASH_OB_GetWRP(void);\r
+static FlagStatus FLASH_OB_GetRDP(void);\r
+static uint32_t FLASH_OB_GetBOR(void);\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);\r
+\r
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r
+ * @brief Extended IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the Extension FLASH \r
+ programming operations Operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors \r
+ * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @param[out] SectorError: pointer to variable that\r
+ * contains the configuration information on faulty sector in case of error \r
+ * (0xFFFFFFFF means that all the sectors have been correctly erased)\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t index = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Initialization of SectorError variable*/\r
+ *SectorError = 0xFFFFFFFF;\r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ /* Erase by sector by sector to be done*/\r
+ for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\r
+ {\r
+ FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the erase operation is completed, disable the SER Bit */\r
+ FLASH->CR &= (~FLASH_CR_SER);\r
+ FLASH->CR &= SECTOR_MASK; \r
+\r
+ if(status != HAL_OK) \r
+ {\r
+ /* In case of error, stop erase procedure and return the faulty sector*/\r
+ *SectorError = index;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled\r
+ * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);\r
+ }\r
+ else\r
+ {\r
+ /* Erase by sector to be done*/\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\r
+ pFlash.NbSectorsToErase = pEraseInit->NbSectors;\r
+ pFlash.Sector = pEraseInit->Sector;\r
+ pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\r
+\r
+ /*Erase 1st sector and wait for IT*/\r
+ FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program option bytes\r
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
+\r
+ /* Write protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r
+ {\r
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));\r
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r
+ {\r
+ /*Enable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_EnableWRP(pOBInit->WRPSector);\r
+ }\r
+ else\r
+ {\r
+ /*Disable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_DisableWRP(pOBInit->WRPSector);\r
+ }\r
+ }\r
+\r
+ /* Read protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r
+ {\r
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r
+ }\r
+\r
+ /* USER configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r
+ {\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r
+ pOBInit->USERConfig & OB_IWDG_SW,\r
+ pOBInit->USERConfig & OB_STOP_NO_RST,\r
+ pOBInit->USERConfig & OB_STDBY_NO_RST, \r
+ pOBInit->USERConfig & OB_IWDG_STOP_FREEZE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_FREEZE);\r
+ }\r
+ \r
+ /* BOR Level configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r
+ {\r
+ status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\r
+ }\r
+ \r
+ /* Boot 0 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);\r
+ }\r
+ \r
+ /* Boot 1 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Get the Option byte configuration\r
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;\r
+\r
+ /*Get WRP*/\r
+ pOBInit->WRPSector = FLASH_OB_GetWRP();\r
+\r
+ /*Get RDP Level*/\r
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
+\r
+ /*Get USER*/\r
+ pOBInit->USERConfig = FLASH_OB_GetUser();\r
+\r
+ /*Get BOR Level*/\r
+ pOBInit->BORLevel = FLASH_OB_GetBOR();\r
+ \r
+ /*Get Boot Address when Boot pin = 0 */\r
+ pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);\r
+ \r
+ /*Get Boot Address when Boot pin = 1 */\r
+ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Full erase of FLASH memory sectors \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ *\r
+ * @retval HAL Status\r
+ */\r
+static void FLASH_MassErase(uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+\r
+ /* if the previous operation is completed, proceed to erase all sectors */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ FLASH->CR |= FLASH_CR_MER;\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Erase the specified FLASH memory sector\r
+ * @param Sector: FLASH sector to erase\r
+ * The value of this parameter depend on device used within the same series \r
+ * @param VoltageRange: The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * \r
+ * @retval None\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_SECTOR(Sector));\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ \r
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_BYTE;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_HALF_WORD;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_WORD;\r
+ }\r
+ else\r
+ {\r
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r
+ }\r
+\r
+ /* If the previous operation is completed, proceed to erase the sector */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ FLASH->CR &= SECTOR_MASK;\r
+ FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Enable the write protection of the desired bank1 or bank 2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM4 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). \r
+ * \r
+ * @param WRPSector: specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 \r
+ * @arg OB_WRP_SECTOR_All\r
+ *\r
+ * @retval HAL FLASH State \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Write protection enabled on sectors */\r
+ FLASH->OPTCR &= (~WRPSector); \r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Disable the write protection of the desired bank1 or bank 2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM4 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * \r
+ * @param WRPSector: specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 \r
+ * @arg OB_WRP_Sector_All\r
+ *\r
+ *\r
+ * @retval HAL Status \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Write protection disabled on sectors */\r
+ FLASH->OPTCR |= (WRPSector); \r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief Set the read protection level.\r
+ * @param Level: specifies the read protection level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_RDP_LEVEL_0: No protection\r
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+ * @arg OB_RDP_LEVEL_2: Full chip protection\r
+ * \r
+ * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP_LEVEL(Level));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r
+ * @param Wwdg: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_WWDG_SW: Software WWDG selected\r
+ * @arg OB_WWDG_HW: Hardware WWDG selected\r
+ * @param Iwdg: Selects the WWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param Stop: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param Stdby: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r
+ * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )\r
+{\r
+ uint32_t useroptionmask = 0x00;\r
+ uint32_t useroptionvalue = 0x00;\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r
+ assert_param(IS_OB_STOP_SOURCE(Stop));\r
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));\r
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\r
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);\r
+ \r
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);\r
+ \r
+ /* Update User Option Byte */ \r
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r
+ }\r
+ \r
+ return status; \r
+\r
+}\r
+\r
+/**\r
+ * @brief Set the BOR Level. \r
+ * @param Level: specifies the Option Bytes BOR Reset Level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(Level));\r
+\r
+ /* Set the BOR Level */\r
+ MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);\r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * Address: specifies Boot base address\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);\r
+ }\r
+ else\r
+ {\r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));\r
+ }\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH User Option Byte value.\r
+ * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)\r
+ * and RST_STDBY(Bit2).\r
+ */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH Write Protection Option Bytes value.\r
+ * @retval uint32_t FLASH Write Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Read Protection level.\r
+ * @retval FlagStatus FLASH ReadOut Protection Status:\r
+ * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set\r
+ * - RESET, when OB_RDP_Level_0 is set\r
+ */\r
+static FlagStatus FLASH_OB_GetRDP(void)\r
+{\r
+ FlagStatus readstatus = RESET;\r
+\r
+ if (((uint16_t)(FLASH->OPTCR & 0xFF00)) != (uint16_t)OB_RDP_LEVEL_0)\r
+ {\r
+ readstatus = SET;\r
+ }\r
+ \r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @retval uint32_t The FLASH BOR level:\r
+ * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V \r
+ */\r
+static uint32_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the FLASH BOR level */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x0C));\r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * \r
+ * @retval uint32_t Boot Base Address:\r
+ * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ */\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)\r
+{ \r
+ uint32_t Address = 0;\r
+ \r
+ /* Return the Boot base Address */\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;\r
+ }\r
+ else\r
+ {\r
+ Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);\r
+ }\r
+\r
+ return Address;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief GPIO HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### GPIO Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r
+ in several modes:\r
+ (+) Input mode \r
+ (+) Analog mode\r
+ (+) Output mode\r
+ (+) Alternate function mode\r
+ (+) External interrupt/event lines\r
+\r
+ [..] \r
+ During and just after reset, the alternate functions and external interrupt \r
+ lines are not active and the I/O ports are configured in input floating mode.\r
+ \r
+ [..] \r
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r
+ activated or not.\r
+\r
+ [..]\r
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+ type and the IO speed can be selected depending on the VDD value.\r
+\r
+ [..] \r
+ All ports have external interrupt/event capability. To use external interrupt \r
+ lines, the port must be configured in input mode. All available GPIO pins are \r
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+ \r
+ [..]\r
+ The external interrupt/event controller consists of up to 23 edge detectors \r
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each \r
+ input line can be independently configured to select the type (interrupt or event) \r
+ and the corresponding trigger event (rising or falling or both). Each line can \r
+ also be masked independently. \r
+\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \r
+\r
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef \r
+ structure.\r
+ (++) In case of Output or alternate function mode selection: the speed is \r
+ configured through "Speed" member from GPIO_InitTypeDef structure.\r
+ (++) In alternate mode is selection, the alternate function connected to the IO\r
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
+ (++) Analog mode is required when a pin is to be used as ADC channel \r
+ or DAC output.\r
+ (++) In case of external interrupt/event selection the "Mode" member from \r
+ GPIO_InitTypeDef structure select the type (interrupt or event) and \r
+ the corresponding trigger event (rising or falling or both).\r
+\r
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+ HAL_NVIC_EnableIRQ().\r
+ \r
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+ \r
+ (#) To set/reset the level of a pin configured in output mode use \r
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+ \r
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+\r
+ \r
+ (#) During and just after reset, the alternate functions are not \r
+ active and the GPIO pins are configured in input floating mode (except JTAG\r
+ pins).\r
+ \r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r
+ priority over the GPIO function.\r
+ \r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r
+ The HSE has priority over the GPIO function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+#define GPIO_MODE ((uint32_t)0x00000003)\r
+#define EXTI_MODE ((uint32_t)0x10000000)\r
+#define GPIO_MODE_IT ((uint32_t)0x00010000)\r
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)\r
+#define RISING_EDGE ((uint32_t)0x00100000)\r
+#define FALLING_EDGE ((uint32_t)0x00200000)\r
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)\r
+\r
+#define GPIO_NUMBER ((uint32_t)16)\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize and de-initialize the GPIOs\r
+ to be ready for use.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{\r
+ uint32_t position = 0x00;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t temp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
+\r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*--------------------- GPIO Mode Configuration ------------------------*/\r
+ /* In case of Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Alternate function parameter */\r
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+ \r
+ /* Configure Alternate function mapped with the current IO */\r
+ temp = GPIOx->AFR[position >> 3];\r
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));\r
+ GPIOx->AFR[position >> 3] = temp;\r
+ }\r
+\r
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+ temp = GPIOx->MODER;\r
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r
+ GPIOx->MODER = temp;\r
+\r
+ /* In case of Output or Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Speed parameter */\r
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+ /* Configure the IO Speed */\r
+ temp = GPIOx->OSPEEDR; \r
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+ temp |= (GPIO_Init->Speed << (position * 2));\r
+ GPIOx->OSPEEDR = temp;\r
+\r
+ /* Configure the IO Output Type */\r
+ temp = GPIOx->OTYPER;\r
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r
+ GPIOx->OTYPER = temp;\r
+ }\r
+\r
+ /* Activate the Pull-up or Pull down resistor for the current IO */\r
+ temp = GPIOx->PUPDR;\r
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ temp |= ((GPIO_Init->Pull) << (position * 2));\r
+ GPIOx->PUPDR = temp;\r
+\r
+ /*--------------------- EXTI Mode Configuration ------------------------*/\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
+ {\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ temp = SYSCFG->EXTICR[position >> 2];\r
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r
+ SYSCFG->EXTICR[position >> 2] = temp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ temp = EXTI->IMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->IMR = temp;\r
+\r
+ temp = EXTI->EMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->EMR = temp;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ temp = EXTI->RTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->RTSR = temp;\r
+\r
+ temp = EXTI->FTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->FTSR = temp;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+ uint32_t position;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ \r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (GPIO_Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*------------------------- GPIO Mode Configuration --------------------*/\r
+ /* Configure IO Direction in Input Floating Mode */\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+\r
+ /* Configure the default Alternate Function in current IO */\r
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+\r
+ /* Configure the default value for IO Speed */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+\r
+ /* Configure the default value IO Output Type */\r
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+\r
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+\r
+ /*------------------------- EXTI Mode Configuration --------------------*/\r
+ tmp = SYSCFG->EXTICR[position >> 2];\r
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ if(tmp == ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))))\r
+ {\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));\r
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~((uint32_t)iocurrent);\r
+ EXTI->EMR &= ~((uint32_t)iocurrent);\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~((uint32_t)iocurrent);\r
+ EXTI->FTSR &= ~((uint32_t)iocurrent);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_PIN_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ GPIO_PinState bitstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r
+ {\r
+ bitstatus = GPIO_PIN_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = GPIO_PIN_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ *\r
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify\r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ *\r
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @param PinState: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the GPIO_PinState enum values:\r
+ * @arg GPIO_PIN_RESET: to clear the port pin\r
+ * @arg GPIO_PIN_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+ if(PinState != GPIO_PIN_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins.\r
+ * @param GPIOx: Where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->ODR ^= GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family\r
+ * @param GPIO_Pin: specifies the port bit to be locked.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Apply lock key write sequence */\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+\r
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI interrupt request.\r
+ * @param GPIO_Pin: Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+ /* EXTI line interrupt detected */\r
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r
+ {\r
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief EXTI line detection callbacks.\r
+ * @param GPIO_Pin: Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the HASH peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + HASH/HMAC Processing functions by algorithm using polling mode\r
+ * + HASH/HMAC functions by algorithm using interrupt mode\r
+ * + HASH/HMAC functions by algorithm using DMA mode\r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The HASH HAL driver can be used as follows:\r
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())\r
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable one DMA stream one for managing data transfer from\r
+ memory to peripheral (input stream). Managing data transfer from\r
+ peripheral to memory can be performed only using CPU\r
+ (+++) Associate the initialized DMA handle to the HASH DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r
+ (##) For HMAC, the encryption key.\r
+ (##) For HMAC, the key size used for encryption.\r
+ (#)Three processing functions are available:\r
+ (##) Polling mode: processing APIs are blocking functions\r
+ i.e. they process the data and wait till the digest computation is finished\r
+ e.g. HAL_HASH_SHA1_Start()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_HASH_SHA1_Start_IT()\r
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is\r
+ not used for data transfer i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_HASH_SHA1_Start_DMA()\r
+ (#)When the processing function is called at first time after HAL_HASH_Init()\r
+ the HASH peripheral is initialized and processes the buffer in input.\r
+ After that, the digest computation is started.\r
+ When processing multi-buffer use the accumulate function to write the\r
+ data in the peripheral without starting the digest computation. In last \r
+ buffer use the start function to input the last buffer ans start the digest\r
+ computation.\r
+ (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r
+ (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation\r
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().\r
+ After that, call the finish function in order to get the digest value\r
+ e.g. HAL_HASH_SHA1_Finish()\r
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASH HASH\r
+ * @brief HASH HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup HASH_Private_Functions HASH Private Functions\r
+ * @{\r
+ */\r
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);\r
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);\r
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup HASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DMA HASH Input Data complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ uint32_t inputaddr = 0;\r
+ uint32_t buffersize = 0;\r
+ \r
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ else\r
+ {\r
+ /* Increment Interrupt counter */\r
+ hhash->HashInCount++;\r
+ /* Disable the DMA transfer before starting the next transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ if(hhash->HashInCount <= 2)\r
+ {\r
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r
+ if(hhash->HashInCount == 1)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ buffersize = hhash->HashBuffSize;\r
+ }\r
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r
+ else if(hhash->HashInCount == 2)\r
+ {\r
+ inputaddr = (uint32_t)hhash->Init.pKey;\r
+ buffersize = hhash->Init.KeySize;\r
+ }\r
+ /* Configure the number of valid bits in last word of the message */\r
+ HASH->STR |= 8 * (buffersize % 4);\r
+ \r
+ /* Set the HASH DMA transfer complete */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Reset the InCount */\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hhash->State= HAL_HASH_STATE_READY;\r
+ HAL_HASH_ErrorCallback(hhash);\r
+}\r
+\r
+/**\r
+ * @brief Writes the input buffer in data register.\r
+ * @param pInBuffer: Pointer to input buffer\r
+ * @param Size: The size of input buffer\r
+ * @retval None\r
+ */\r
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t buffercounter;\r
+ uint32_t inputaddr = (uint32_t) pInBuffer;\r
+ \r
+ for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Provides the message digest result.\r
+ * @param pMsgDigest: Pointer to the message digest\r
+ * @param Size: The size of the message digest in bytes\r
+ * @retval None\r
+ */\r
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r
+{\r
+ uint32_t msgdigest = (uint32_t)pMsgDigest;\r
+ \r
+ switch(Size)\r
+ {\r
+ case 16:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ break;\r
+ case 20:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ break;\r
+ case 28:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ break;\r
+ case 32:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HASH_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the HASH according to the specified parameters \r
+ in the HASH_InitTypeDef and creates the associated handle.\r
+ (+) DeInitialize the HASH peripheral.\r
+ (+) Initialize the HASH MSP.\r
+ (+) DeInitialize HASH MSP. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH according to the specified parameters in the\r
+ HASH_HandleTypeDef and creates the associated handle.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* Check the hash handle allocation */\r
+ if(hhash == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));\r
+ \r
+ if(hhash->State == HAL_HASH_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_HASH_MspInit(hhash);\r
+ }\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Reset HashInCount, HashBuffSize and HashITCounter */\r
+ hhash->HashInCount = 0;\r
+ hhash->HashBuffSize = 0;\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* Set the data type */\r
+ HASH->CR |= (uint32_t) (hhash->Init.DataType);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Set the default HASH phase */\r
+ hhash->Phase = HAL_HASH_PHASE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the HASH peripheral.\r
+ * @note This API must be called before starting a new processing. \r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)\r
+{ \r
+ /* Check the HASH handle allocation */\r
+ if(hhash == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Set the default HASH phase */\r
+ hhash->Phase = HAL_HASH_PHASE_READY;\r
+ \r
+ /* Reset HashInCount, HashBuffSize and HashITCounter */\r
+ hhash->HashInCount = 0;\r
+ hhash->HashBuffSize = 0;\r
+ hhash->HashITCounter = 0;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_HASH_MspDeInit(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hhash);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH MSP.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes HASH MSP.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input data transfer complete callback.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_InCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Data transfer Error callback.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Digest computation complete callback. It is used only with interrupt.\r
+ * @note This callback is not relevant with DMA.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_HASH_DgstCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode \r
+ * @brief processing functions using polling mode \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using polling mode functions#####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware\r
+ * and appending the input buffer is no more possible.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @param Timeout: Timeout value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is multiple of 64 bytes, appending the input buffer is possible.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware\r
+ * and appending the input buffer is no more possible.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode\r
+ * @brief processing functions using interrupt mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using interrupt mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in interrupt mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashITCounter = 0;\r
+ }\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r
+ \r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount > 64)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount -= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ }\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t outputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashITCounter = 0;\r
+ }\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r
+ /* Read the Output block from the Output FIFO */\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r
+ outputaddr+=4;\r
+ *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount > 64)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ \r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount -= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ }\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles HASH interrupt request.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)\r
+{\r
+ switch(HASH->CR & HASH_CR_ALGO)\r
+ {\r
+ case HASH_ALGOSELECTION_MD5:\r
+ HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case HASH_ALGOSELECTION_SHA1:\r
+ HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode\r
+ * @brief processing functions using DMA mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using DMA mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the hash value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in MD5 mode\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA1;\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA1 mode.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. \r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process UnLock */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode \r
+ * @brief HMAC processing functions using polling mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 16);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */ \r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASH_GetDigest(pOutBuffer, 20);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode \r
+ * @brief HMAC processing functions using DMA mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using DMA mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) MD5\r
+ (+) SHA1\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC MD5 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC MD5 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA1 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA1 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the HASH state\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval HAL state\r
+ */\r
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)\r
+{\r
+ return hhash->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F756xx */\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hash_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HASH HAL Extension module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of HASH peripheral:\r
+ * + Extended HASH processing functions based on SHA224 Algorithm\r
+ * + Extended HASH processing functions based on SHA256 Algorithm\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The HASH HAL driver can be used as follows:\r
+ (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r
+ (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r
+ (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())\r
+ (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r
+ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r
+ (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())\r
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r
+ (+++) Configure and enable one DMA stream one for managing data transfer from\r
+ memory to peripheral (input stream). Managing data transfer from\r
+ peripheral to memory can be performed only using CPU\r
+ (+++) Associate the initialized DMA handle to the HASH DMA handle\r
+ using __HAL_LINKDMA()\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete\r
+ interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r
+ (##) For HMAC, the encryption key.\r
+ (##) For HMAC, the key size used for encryption.\r
+ (#)Three processing functions are available:\r
+ (##) Polling mode: processing APIs are blocking functions\r
+ i.e. they process the data and wait till the digest computation is finished\r
+ e.g. HAL_HASHEx_SHA224_Start()\r
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r
+ i.e. they process the data under interrupt\r
+ e.g. HAL_HASHEx_SHA224_Start_IT()\r
+ (##) DMA mode: processing APIs are not blocking functions and the CPU is\r
+ not used for data transfer i.e. the data transfer is ensured by DMA\r
+ e.g. HAL_HASHEx_SHA224_Start_DMA()\r
+ (#)When the processing function is called at first time after HAL_HASH_Init()\r
+ the HASH peripheral is initialized and processes the buffer in input.\r
+ After that, the digest computation is started.\r
+ When processing multi-buffer use the accumulate function to write the\r
+ data in the peripheral without starting the digest computation. In last \r
+ buffer use the start function to input the last buffer ans start the digest\r
+ computation.\r
+ (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r
+ (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r
+ (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation\r
+ (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r
+ (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().\r
+ After that, call the finish function in order to get the digest value\r
+ e.g. HAL_HASHEx_SHA224_Finish()\r
+ (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HASHEx HASHEx\r
+ * @brief HASH Extension HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup HASHEx_Private_Functions\r
+ * @{\r
+ */\r
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);\r
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);\r
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup HASHEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes the input buffer in data register.\r
+ * @param pInBuffer: Pointer to input buffer\r
+ * @param Size: The size of input buffer\r
+ * @retval None\r
+ */\r
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t buffercounter;\r
+ uint32_t inputaddr = (uint32_t) pInBuffer;\r
+ \r
+ for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Provides the message digest result.\r
+ * @param pMsgDigest: Pointer to the message digest\r
+ * @param Size: The size of the message digest in bytes\r
+ * @retval None\r
+ */\r
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r
+{\r
+ uint32_t msgdigest = (uint32_t)pMsgDigest;\r
+ \r
+ switch(Size)\r
+ {\r
+ case 16:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ break;\r
+ case 20:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ break;\r
+ case 28:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ break;\r
+ case 32:\r
+ /* Read the message digest */\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r
+ msgdigest+=4;\r
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH Input Data complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ uint32_t inputaddr = 0;\r
+ uint32_t buffersize = 0;\r
+ \r
+ if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ else\r
+ {\r
+ /* Increment Interrupt counter */\r
+ hhash->HashInCount++;\r
+ /* Disable the DMA transfer before starting the next transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ if(hhash->HashInCount <= 2)\r
+ {\r
+ /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r
+ if(hhash->HashInCount == 1)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ buffersize = hhash->HashBuffSize;\r
+ }\r
+ /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r
+ else if(hhash->HashInCount == 2)\r
+ {\r
+ inputaddr = (uint32_t)hhash->Init.pKey;\r
+ buffersize = hhash->Init.KeySize;\r
+ }\r
+ /* Configure the number of valid bits in last word of the message */\r
+ HASH->STR |= 8 * (buffersize % 4);\r
+ \r
+ /* Set the HASH DMA transfer complete */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer */\r
+ HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r
+ \r
+ /* Reset the InCount */\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA HASH communication error callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hhash->State= HAL_HASH_STATE_READY;\r
+ HAL_HASH_ErrorCallback(hhash);\r
+}\r
+\r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup HASHEx_Group1 HASH processing functions \r
+ * @brief processing functions using polling mode \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode \r
+ * @brief HMAC processing functions using polling mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using polling mode functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in polling mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode\r
+ * then processes pInBuffer. The digest is available in pOutBuffer\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). \r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r
+ }\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /************************** STEP 1 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 2 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(pInBuffer, Size);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /************************** STEP 3 ******************************************/\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Write input buffer in data register */\r
+ HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r
+ \r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > Timeout)\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode\r
+ * @brief processing functions using interrupt mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using interrupt functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in interrupt mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashITCounter = 0;\r
+ }\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount > 64)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount -= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ }\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r
+ * The digest is available in pOutBuffer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r
+{\r
+ uint32_t inputaddr;\r
+ uint32_t buffercounter;\r
+ uint32_t inputcounter;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ hhash->HashITCounter = 1;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashITCounter = 0;\r
+ }\r
+ if(hhash->State == HAL_HASH_STATE_READY)\r
+ {\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ hhash->HashInCount = Size;\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->pHashOutBuffPtr = pOutBuffer;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256;\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Enable Interrupts */\r
+ HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r
+ {\r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);\r
+ if(hhash->HashInCount == 0)\r
+ {\r
+ /* Disable Interrupts */\r
+ HASH->IMR = 0;\r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ /* Call digest computation complete callback */\r
+ HAL_HASH_DgstCpltCallback(hhash);\r
+ }\r
+ }\r
+ if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r
+ {\r
+ if(hhash->HashInCount > 64)\r
+ {\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ if(hhash->HashITCounter == 0)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ \r
+ if(hhash->HashInCount >= 68)\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 68;\r
+ hhash->pHashInBuffPtr+= 68;\r
+ }\r
+ else\r
+ {\r
+ hhash->HashInCount -= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Decrement buffer counter */\r
+ hhash->HashInCount -= 64;\r
+ hhash->pHashInBuffPtr+= 64;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the buffer address */\r
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r
+ /* Get the buffer counter */\r
+ inputcounter = hhash->HashInCount;\r
+ /* Disable Interrupts */\r
+ HASH->IMR &= ~(HASH_IT_DINI);\r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r
+ \r
+ if((inputcounter > 4) && (inputcounter%4))\r
+ {\r
+ inputcounter = (inputcounter+4-inputcounter%4);\r
+ }\r
+ \r
+ /* Write the Input block in the Data IN register */\r
+ for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r
+ {\r
+ HASH->DIN = *(uint32_t*)inputaddr;\r
+ inputaddr+=4;\r
+ }\r
+ /* Start the digest calculation */\r
+ __HAL_HASH_START_DIGEST();\r
+ /* Reset buffer counter */\r
+ hhash->HashInCount = 0;\r
+ }\r
+ /* Call Input data transfer complete callback */\r
+ HAL_HASH_InCpltCallback(hhash);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles HASH interrupt request.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @retval None\r
+ */\r
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)\r
+{\r
+ switch(HASH->CR & HASH_CR_ALGO)\r
+ {\r
+ \r
+ case HASH_ALGOSELECTION_SHA224:\r
+ HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ case HASH_ALGOSELECTION_SHA256:\r
+ HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode\r
+ * @brief processing functions using DMA mode. \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HASH processing using DMA functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the hash value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA224\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 28);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to\r
+ control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr = (uint32_t)pInBuffer;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(Size);\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r
+ \r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process UnLock */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the computed digest in SHA256.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r
+ * @param Timeout: Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Change state */\r
+ hhash->State = HAL_HASH_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Read the message digest */\r
+ HASHEx_GetDigest(pOutBuffer, 32);\r
+ \r
+ /* Change HASH peripheral state */\r
+ hhash->State = HAL_HASH_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode \r
+ * @brief HMAC processing functions using DMA mode . \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### HMAC processing using DMA functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to calculate in DMA mode\r
+ the HMAC value using one of the following algorithms:\r
+ (+) SHA224\r
+ (+) SHA256\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA224 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA224 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r
+ }\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HASH peripheral in HMAC SHA256 mode\r
+ * then enables DMA to control data transfer.\r
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains\r
+ * the configuration information for HASH module\r
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).\r
+ * @param Size: Length of the input buffer in bytes.\r
+ * If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r
+{\r
+ uint32_t inputaddr;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hhash);\r
+ \r
+ /* Change the HASH state */\r
+ hhash->State = HAL_HASH_STATE_BUSY;\r
+ \r
+ /* Save buffer pointer and size in handle */\r
+ hhash->pHashInBuffPtr = pInBuffer;\r
+ hhash->HashBuffSize = Size;\r
+ hhash->HashInCount = 0;\r
+ \r
+ /* Check if initialization phase has already been performed */\r
+ if(hhash->Phase == HAL_HASH_PHASE_READY)\r
+ {\r
+ /* Check if key size is greater than 64 bytes */\r
+ if(hhash->Init.KeySize > 64)\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r
+ }\r
+ else\r
+ {\r
+ /* Select the HMAC SHA256 mode */\r
+ HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r
+ }\r
+ /* Reset the HASH processor core, so that the HASH will be ready to compute \r
+ the message digest of a new message */\r
+ HASH->CR |= HASH_CR_INIT;\r
+ }\r
+ \r
+ /* Set the phase */\r
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;\r
+ \r
+ /* Configure the number of valid bits in last word of the message */\r
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r
+ \r
+ /* Get the key address */\r
+ inputaddr = (uint32_t)(hhash->Init.pKey);\r
+ \r
+ /* Set the HASH DMA transfer complete callback */\r
+ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r
+ /* Set the DMA error callback */\r
+ hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r
+ \r
+ /* Enable the DMA In DMA Stream */\r
+ HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r
+ /* Enable DMA requests */\r
+ HASH->CR |= (HASH_CR_DMAE);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hhash);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx */\r
+\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_hcd.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a HCD_HandleTypeDef handle structure, for example:\r
+ HCD_HandleTypeDef hhcd;\r
+ \r
+ (#)Fill parameters of Init structure in HCD handle\r
+ \r
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) \r
+\r
+ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:\r
+ (##) Enable the HCD/USB Low Level interface clock using the following macros\r
+ (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()\r
+ (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure HCD pin-out\r
+ (##) Configure HCD NVIC interrupt\r
+ \r
+ (#)Associate the Upper USB Host stack to the HAL HCD Driver:\r
+ (##) hhcd.pData = phost;\r
+\r
+ (#)Enable HCD transmission and reception:\r
+ (##) HAL_HCD_Start();\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HCD\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function ----------------------------------------------------------*/\r
+/** @addtogroup HCD_Private_Functions\r
+ * @{\r
+ */\r
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); \r
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);\r
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HCD_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HCD_Exported_Functions_Group1\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the host driver\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ /* Check the HCD handle allocation */\r
+ if(hhcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));\r
+\r
+ hhcd->State = HAL_HCD_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_HCD_MspInit(hhcd);\r
+\r
+ /* Disable the Interrupts */\r
+ __HAL_HCD_DISABLE(hhcd);\r
+ \r
+ /*Init the Core (common init.) */\r
+ USB_CoreInit(hhcd->Instance, hhcd->Init);\r
+ \r
+ /* Force Host Mode*/\r
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);\r
+ \r
+ /* Init Host */\r
+ USB_HostInit(hhcd->Instance, hhcd->Init);\r
+ \r
+ hhcd->State= HAL_HCD_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel\r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum: Endpoint number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address : Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed: Current device speed.\r
+ * This parameter can be one of these values:\r
+ * HCD_SPEED_HIGH: High speed mode,\r
+ * HCD_SPEED_FULL: Full speed mode,\r
+ * HCD_SPEED_LOW: Low speed mode\r
+ * @param ep_type: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * EP_TYPE_CTRL: Control type,\r
+ * EP_TYPE_ISOC: Isochronous type,\r
+ * EP_TYPE_BULK: Bulk type,\r
+ * EP_TYPE_INTR: Interrupt type\r
+ * @param mps: Max Packet Size.\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ __HAL_LOCK(hhcd); \r
+ \r
+ hhcd->hc[ch_num].dev_addr = dev_address;\r
+ hhcd->hc[ch_num].max_packet = mps;\r
+ hhcd->hc[ch_num].ch_num = ch_num;\r
+ hhcd->hc[ch_num].ep_type = ep_type;\r
+ hhcd->hc[ch_num].ep_num = epnum & 0x7F;\r
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);\r
+ hhcd->hc[ch_num].speed = speed;\r
+\r
+ status = USB_HC_Init(hhcd->Instance, \r
+ ch_num,\r
+ epnum,\r
+ dev_address,\r
+ speed,\r
+ ep_type,\r
+ mps);\r
+ __HAL_UNLOCK(hhcd); \r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel\r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ __HAL_LOCK(hhcd); \r
+ USB_HC_Halt(hhcd->Instance, ch_num); \r
+ __HAL_UNLOCK(hhcd);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the host driver\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* Check the HCD handle allocation */\r
+ if(hhcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ hhcd->State = HAL_HCD_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_HCD_MspDeInit(hhcd);\r
+ \r
+ __HAL_HCD_DISABLE(hhcd);\r
+ \r
+ hhcd->State = HAL_HCD_STATE_RESET; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the HCD MSP.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes HCD MSP.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HCD_Exported_Functions_Group2\r
+ * @brief HCD IO operation functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the USB Host Data \r
+ Transfer\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief Submit a new URB for processing \r
+ * @param hhcd: HCD handle\r
+ * @param ch_num: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param direction: Channel number.\r
+ * This parameter can be one of these values:\r
+ * 0 : Output / 1 : Input\r
+ * @param ep_type: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * EP_TYPE_CTRL: Control type/\r
+ * EP_TYPE_ISOC: Isochronous type/\r
+ * EP_TYPE_BULK: Bulk type/\r
+ * EP_TYPE_INTR: Interrupt type/\r
+ * @param token: Endpoint Type.\r
+ * This parameter can be one of these values:\r
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1\r
+ * @param pbuff: pointer to URB data\r
+ * @param length: Length of URB data\r
+ * @param do_ping: activate do ping protocol (for high speed only).\r
+ * This parameter can be one of these values:\r
+ * 0 : do ping inactive / 1 : do ping active \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r
+ uint8_t ch_num, \r
+ uint8_t direction ,\r
+ uint8_t ep_type, \r
+ uint8_t token, \r
+ uint8_t* pbuff, \r
+ uint16_t length,\r
+ uint8_t do_ping) \r
+{\r
+ hhcd->hc[ch_num].ep_is_in = direction;\r
+ hhcd->hc[ch_num].ep_type = ep_type; \r
+ \r
+ if(token == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_SETUP;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ \r
+ /* Manage Data Toggle */\r
+ switch(ep_type)\r
+ {\r
+ case EP_TYPE_CTRL:\r
+ if((token == 1) && (direction == 0)) /*send data */\r
+ {\r
+ if ( length == 0 )\r
+ { /* For Status OUT stage, Length==0, Status Out PID = 1 */\r
+ hhcd->hc[ch_num].toggle_out = 1;\r
+ }\r
+ \r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)\r
+ {\r
+ hhcd->hc[ch_num].do_ping = do_ping;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case EP_TYPE_BULK:\r
+ if(direction == 0)\r
+ {\r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)\r
+ {\r
+ hhcd->hc[ch_num].do_ping = do_ping;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( hhcd->hc[ch_num].toggle_in == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ }\r
+ \r
+ break;\r
+ case EP_TYPE_INTR:\r
+ if(direction == 0)\r
+ {\r
+ /* Set the Data Toggle bit as per the Flag */\r
+ if ( hhcd->hc[ch_num].toggle_out == 0)\r
+ { /* Put the PID 0 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; \r
+ }\r
+ else\r
+ { /* Put the PID 1 */\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( hhcd->hc[ch_num].toggle_in == 0)\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case EP_TYPE_ISOC: \r
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r
+ break; \r
+ }\r
+ \r
+ hhcd->hc[ch_num].xfer_buff = pbuff;\r
+ hhcd->hc[ch_num].xfer_len = length;\r
+ hhcd->hc[ch_num].urb_state = URB_IDLE; \r
+ hhcd->hc[ch_num].xfer_count = 0 ;\r
+ hhcd->hc[ch_num].ch_num = ch_num;\r
+ hhcd->hc[ch_num].state = HC_IDLE;\r
+ \r
+ return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);\r
+}\r
+\r
+/**\r
+ * @brief This function handles HCD interrupt request.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ uint32_t i = 0 , interrupt = 0;\r
+ \r
+ /* ensure that we are in device mode */\r
+ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)\r
+ {\r
+ /* avoid spurious interrupt */\r
+ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) \r
+ {\r
+ return;\r
+ }\r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
+ }\r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);\r
+ }\r
+\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);\r
+ } \r
+ \r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);\r
+ } \r
+ \r
+ /* Handle Host Disconnect Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))\r
+ {\r
+ \r
+ /* Cleanup HPRT */\r
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ HAL_HCD_Disconnect_Callback(hhcd);\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);\r
+ }\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))\r
+ {\r
+ HCD_Port_IRQHandler (hhcd);\r
+ }\r
+ \r
+ /* Handle Host SOF Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))\r
+ {\r
+ HAL_HCD_SOF_Callback(hhcd);\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);\r
+ }\r
+ \r
+ /* Handle Host channel Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))\r
+ {\r
+ interrupt = USB_HC_ReadInterrupt(hhcd->Instance);\r
+ for (i = 0; i < hhcd->Init.Host_channels ; i++)\r
+ {\r
+ if (interrupt & (1 << i))\r
+ {\r
+ if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)\r
+ {\r
+ HCD_HC_IN_IRQHandler (hhcd, i);\r
+ }\r
+ else\r
+ {\r
+ HCD_HC_OUT_IRQHandler (hhcd, i);\r
+ }\r
+ }\r
+ }\r
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);\r
+ } \r
+ \r
+ /* Handle Rx Queue Level Interrupts */\r
+ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))\r
+ {\r
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ \r
+ HCD_RXQLVL_IRQHandler (hhcd);\r
+ \r
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief SOF callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_SOF_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Connexion Event callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_Connect_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Disconnexion Event callback.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file\r
+ */\r
+} \r
+\r
+/**\r
+ * @brief Notify URB state change callback.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @param urb_state:\r
+ * This parameter can be one of these values:\r
+ * URB_IDLE/\r
+ * URB_DONE/\r
+ * URB_NOTREADY/\r
+ * URB_NYET/ \r
+ * URB_ERROR/ \r
+ * URB_STALL/ \r
+ * @retval None\r
+ */\r
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HCD_Exported_Functions_Group3\r
+ * @brief Peripheral management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the HCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Start the host driver\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ __HAL_LOCK(hhcd); \r
+ __HAL_HCD_ENABLE(hhcd);\r
+ USB_DriveVbus(hhcd->Instance, 1); \r
+ __HAL_UNLOCK(hhcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the host driver\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)\r
+{ \r
+ __HAL_LOCK(hhcd); \r
+ USB_StopHost(hhcd->Instance);\r
+ __HAL_UNLOCK(hhcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reset the host port\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_ResetPort(hhcd->Instance));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HCD_Exported_Functions_Group4\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the HCD state\r
+ * @param hhcd: HCD handle\r
+ * @retval HAL state\r
+ */\r
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return hhcd->State;\r
+}\r
+\r
+/**\r
+ * @brief Return URB state for a channel\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval URB state.\r
+ * This parameter can be one of these values:\r
+ * URB_IDLE/\r
+ * URB_DONE/\r
+ * URB_NOTREADY/\r
+ * URB_NYET/ \r
+ * URB_ERROR/ \r
+ * URB_STALL/\r
+ */\r
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].urb_state;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the last host transfer size\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval last transfer size in byte\r
+ */\r
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].xfer_count; \r
+}\r
+ \r
+/**\r
+ * @brief Return the Host Channel state\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval Host channel state\r
+ * This parameter can be one of the these values:\r
+ * HC_IDLE/\r
+ * HC_XFRC/\r
+ * HC_HALTED/\r
+ * HC_NYET/ \r
+ * HC_NAK/ \r
+ * HC_STALL/ \r
+ * HC_XACTERR/ \r
+ * HC_BBLERR/ \r
+ * HC_DATATGLERR/ \r
+ */\r
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ return hhcd->hc[chnum].state;\r
+}\r
+\r
+/**\r
+ * @brief Return the current Host frame number\r
+ * @param hhcd: HCD handle\r
+ * @retval Current Host frame number\r
+ */\r
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_GetCurrentFrame(hhcd->Instance));\r
+}\r
+\r
+/**\r
+ * @brief Return the Host enumeration speed\r
+ * @param hhcd: HCD handle\r
+ * @retval Enumeration speed\r
+ */\r
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)\r
+{\r
+ return (USB_GetHostSpeed(hhcd->Instance));\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HCD_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles Host Channel IN interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval none\r
+ */\r
+static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ } \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) \r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ hhcd->hc[chnum].state = HC_STALL;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); \r
+ hhcd->hc[chnum].state = HC_DATATGLERR;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);\r
+ } \r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)\r
+ {\r
+ \r
+ if (hhcd->Init.dma_enable)\r
+ {\r
+ hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \\r
+ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);\r
+ }\r
+ \r
+ hhcd->hc[chnum].state = HC_XFRC;\r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r
+ \r
+ \r
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ \r
+ }\r
+ else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;\r
+ hhcd->hc[chnum].urb_state = URB_DONE; \r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r
+ }\r
+ hhcd->hc[chnum].toggle_in ^= 1;\r
+ \r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)\r
+ {\r
+ __HAL_HCD_MASK_HALT_HC_INT(chnum); \r
+ \r
+ if(hhcd->hc[chnum].state == HC_XFRC)\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_DONE; \r
+ }\r
+ \r
+ else if (hhcd->hc[chnum].state == HC_STALL) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_STALL;\r
+ } \r
+ \r
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r
+ (hhcd->hc[chnum].state == HC_DATATGLERR))\r
+ {\r
+ if(hhcd->hc[chnum].ErrCnt++ > 3)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ hhcd->hc[chnum].urb_state = URB_ERROR;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ \r
+ /* re-activate the channel */\r
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; \r
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r
+ } \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ hhcd->hc[chnum].ErrCnt++;\r
+ hhcd->hc[chnum].state = HC_XACTERR;\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r
+ }\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)\r
+ { \r
+ if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ }\r
+ else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r
+ {\r
+ /* re-activate the channel */\r
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; \r
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ \r
+ }\r
+ hhcd->hc[chnum].state = HC_NAK;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Host Channel OUT interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @param chnum: Channel number.\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval none\r
+ */\r
+static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r
+ \r
+ if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ } \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)\r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r
+ \r
+ if( hhcd->hc[chnum].do_ping == 1)\r
+ {\r
+ hhcd->hc[chnum].state = HC_NYET; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)\r
+ {\r
+ hhcd->hc[chnum].state = HC_NYET;\r
+ hhcd->hc[chnum].ErrCnt= 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);\r
+ \r
+ } \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)\r
+ {\r
+ hhcd->hc[chnum].ErrCnt = 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r
+ hhcd->hc[chnum].state = HC_XFRC;\r
+\r
+ } \r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) \r
+ {\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_STALL; \r
+ }\r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0; \r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_NAK;\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ }\r
+\r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ hhcd->hc[chnum].state = HC_XACTERR; \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r
+ }\r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)\r
+ {\r
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r
+ USB_HC_Halt(hhcd->Instance, chnum); \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); \r
+ hhcd->hc[chnum].state = HC_DATATGLERR;\r
+ }\r
+ \r
+ \r
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)\r
+ {\r
+ __HAL_HCD_MASK_HALT_HC_INT(chnum); \r
+ \r
+ if(hhcd->hc[chnum].state == HC_XFRC)\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_DONE;\r
+ if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)\r
+ {\r
+ hhcd->hc[chnum].toggle_out ^= 1; \r
+ } \r
+ }\r
+ else if (hhcd->hc[chnum].state == HC_NAK) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ } \r
+ \r
+ else if (hhcd->hc[chnum].state == HC_NYET) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ hhcd->hc[chnum].do_ping = 0;\r
+ } \r
+ \r
+ else if (hhcd->hc[chnum].state == HC_STALL) \r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_STALL;\r
+ } \r
+ \r
+ else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r
+ (hhcd->hc[chnum].state == HC_DATATGLERR))\r
+ {\r
+ if(hhcd->hc[chnum].ErrCnt++ > 3)\r
+ { \r
+ hhcd->hc[chnum].ErrCnt = 0;\r
+ hhcd->hc[chnum].urb_state = URB_ERROR;\r
+ }\r
+ else\r
+ {\r
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;\r
+ }\r
+ \r
+ /* re-activate the channel */\r
+ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; \r
+ USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ \r
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); \r
+ }\r
+} \r
+\r
+/**\r
+ * @brief This function handles Rx Queue Level interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @retval none\r
+ */\r
+static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; \r
+ uint8_t channelnum =0; \r
+ uint32_t pktsts;\r
+ uint32_t pktcnt; \r
+ uint32_t temp = 0;\r
+ \r
+ temp = hhcd->Instance->GRXSTSP ;\r
+ channelnum = temp & USB_OTG_GRXSTSP_EPNUM; \r
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;\r
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ \r
+ switch (pktsts)\r
+ {\r
+ case GRXSTS_PKTSTS_IN:\r
+ /* Read the data into the host buffer. */\r
+ if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))\r
+ { \r
+ \r
+ USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);\r
+ \r
+ /*manage multiple Xfer */\r
+ hhcd->hc[channelnum].xfer_buff += pktcnt; \r
+ hhcd->hc[channelnum].xfer_count += pktcnt;\r
+ \r
+ if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)\r
+ {\r
+ /* re-activate the channel when more packets are expected */\r
+ USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; \r
+ USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ hhcd->hc[channelnum].toggle_in ^= 1;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:\r
+ break;\r
+ case GRXSTS_PKTSTS_IN_XFER_COMP:\r
+ case GRXSTS_PKTSTS_CH_HALTED:\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Host Port interrupt requests.\r
+ * @param hhcd: HCD handle\r
+ * @retval None\r
+ */\r
+static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; \r
+ __IO uint32_t hprt0, hprt0_dup;\r
+ \r
+ /* Handle Host Port Interrupts */\r
+ hprt0 = USBx_HPRT0;\r
+ hprt0_dup = USBx_HPRT0;\r
+ \r
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ /* Check whether Port Connect detected */\r
+ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)\r
+ { \r
+ if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)\r
+ {\r
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);\r
+ HAL_HCD_Connect_Callback(hhcd);\r
+ }\r
+ hprt0_dup |= USB_OTG_HPRT_PCDET;\r
+ \r
+ }\r
+ \r
+ /* Check whether Port Enable Changed */\r
+ if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)\r
+ {\r
+ hprt0_dup |= USB_OTG_HPRT_PENCHNG;\r
+ \r
+ if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)\r
+ { \r
+ if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)\r
+ {\r
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))\r
+ {\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );\r
+ }\r
+ else\r
+ {\r
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(hhcd->Init.speed == HCD_SPEED_FULL)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)60000;\r
+ }\r
+ }\r
+ HAL_HCD_Connect_Callback(hhcd);\r
+ \r
+ if(hhcd->Init.speed == HCD_SPEED_HIGH)\r
+ {\r
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Cleanup HPRT */\r
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); \r
+ } \r
+ }\r
+ \r
+ /* Check For an overcurrent */\r
+ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)\r
+ {\r
+ hprt0_dup |= USB_OTG_HPRT_POCCHNG;\r
+ }\r
+\r
+ /* Clear Port Interrupts */\r
+ USBx_HPRT0 = hprt0_dup;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief I2C HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The I2C HAL driver can be used as follows:\r
+ \r
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:\r
+ I2C_HandleTypeDef hi2c; \r
+\r
+ (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:\r
+ (##) Enable the I2Cx interface clock\r
+ (##) I2C pins configuration\r
+ (+++) Enable the clock for the I2C GPIOs\r
+ (+++) Configure I2C pins as alternate function open-drain\r
+ (##) NVIC configuration if you need to use interrupt process\r
+ (+++) Configure the I2Cx interrupt priority\r
+ (+++) Enable the NVIC I2C IRQ Channel\r
+ (##) DMA Configuration if you need to use DMA process\r
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\r
+ (+++) Enable the DMAx interface clock using\r
+ (+++) Configure the DMA handle parameters\r
+ (+++) Configure the DMA Tx or Rx Stream\r
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream\r
+\r
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode,\r
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r
+\r
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware \r
+ (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.\r
+\r
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()\r
+\r
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()\r
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()\r
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()\r
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()\r
+\r
+ *** Polling mode IO MEM operation ***\r
+ =====================================\r
+ [..]\r
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()\r
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()\r
+\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback\r
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()\r
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback\r
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()\r
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback\r
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()\r
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback\r
+\r
+ *** Interrupt mode IO MEM operation ***\r
+ =======================================\r
+ [..]\r
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using\r
+ HAL_I2C_Mem_Write_IT()\r
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback\r
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using\r
+ HAL_I2C_Mem_Read_IT()\r
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback\r
+\r
+ *** DMA mode IO operation ***\r
+ ==============================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using\r
+ HAL_I2C_Master_Transmit_DMA()\r
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback\r
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using\r
+ HAL_I2C_Master_Receive_DMA()\r
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback\r
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using\r
+ HAL_I2C_Slave_Transmit_DMA()\r
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback\r
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using\r
+ HAL_I2C_Slave_Receive_DMA()\r
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback\r
+\r
+ *** DMA mode IO MEM operation ***\r
+ =================================\r
+ [..]\r
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using\r
+ HAL_I2C_Mem_Write_DMA()\r
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback\r
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using\r
+ HAL_I2C_Mem_Read_DMA()\r
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback\r
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback\r
+\r
+\r
+ *** I2C HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in I2C HAL driver.\r
+\r
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral\r
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral\r
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not\r
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag\r
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r
+\r
+ [..]\r
+ (@) You can refer to the I2C HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C I2C\r
+ * @brief I2C HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */\r
+#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */\r
+#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */\r
+#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);\r
+\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);\r
+\r
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);\r
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);\r
+\r
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);\r
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);\r
+\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Functions I2C Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the I2Cx peripheral:\r
+\r
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_I2C_Init() to configure the selected device with \r
+ the selected configuration:\r
+ (++) Clock Timing\r
+ (++) Own Address 1\r
+ (++) Addressing mode (Master, Slave)\r
+ (++) Dual Addressing mode\r
+ (++) Own Address 2\r
+ (++) Own Address 2 Mask\r
+ (++) General call mode\r
+ (++) Nostretch mode\r
+\r
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration \r
+ of the selected I2Cx peripheral. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the I2C according to the specified parameters \r
+ * in the I2C_InitTypeDef and create the associated handle.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r
+{ \r
+ /* Check the I2C handle allocation */\r
+ if(hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r
+\r
+ if(hi2c->State == HAL_I2C_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2C_MspInit(hi2c);\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r
+ /* Configure I2Cx: Frequency range */\r
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r
+ \r
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */\r
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r
+ if(hi2c->Init.OwnAddress1 != 0)\r
+ {\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r
+ }\r
+ else /* I2C_ADDRESSINGMODE_10BIT */\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r
+ }\r
+ }\r
+ \r
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r
+ /* Configure I2Cx: Addressing Master mode */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r
+ }\r
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r
+ \r
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r
+ /* Configure I2Cx: Dual mode and Own Address2 */\r
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r
+\r
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r
+ /* Configure I2Cx: Generalcall and NoStretch mode */\r
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r
+ \r
+ /* Enable the selected I2C peripheral */\r
+ __HAL_I2C_ENABLE(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the I2C peripheral. \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Check the I2C handle allocation */\r
+ if(hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the I2C Peripheral Clock */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_I2C_MspDeInit(hi2c);\r
+ \r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ hi2c->State = HAL_I2C_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief I2C MSP Init.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief I2C MSP DeInit\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the I2C data \r
+ transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the \r
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_I2C_Master_Transmit()\r
+ (++) HAL_I2C_Master_Receive()\r
+ (++) HAL_I2C_Slave_Transmit()\r
+ (++) HAL_I2C_Slave_Receive()\r
+ (++) HAL_I2C_Mem_Write()\r
+ (++) HAL_I2C_Mem_Read()\r
+ (++) HAL_I2C_IsDeviceReady()\r
+ \r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_I2C_Master_Transmit_IT()\r
+ (++) HAL_I2C_Master_Receive_IT()\r
+ (++) HAL_I2C_Slave_Transmit_IT()\r
+ (++) HAL_I2C_Slave_Receive_IT()\r
+ (++) HAL_I2C_Mem_Write_IT()\r
+ (++) HAL_I2C_Mem_Read_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_I2C_Master_Transmit_DMA()\r
+ (++) HAL_I2C_Master_Receive_DMA()\r
+ (++) HAL_I2C_Slave_Transmit_DMA()\r
+ (++) HAL_I2C_Slave_Receive_DMA()\r
+ (++) HAL_I2C_Mem_Write_DMA()\r
+ (++) HAL_I2C_Mem_Read_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_I2C_MemTxCpltCallback()\r
+ (++) HAL_I2C_MemRxCpltCallback()\r
+ (++) HAL_I2C_MasterTxCpltCallback()\r
+ (++) HAL_I2C_MasterRxCpltCallback()\r
+ (++) HAL_I2C_SlaveTxCpltCallback()\r
+ (++) HAL_I2C_SlaveRxCpltCallback()\r
+ (++) HAL_I2C_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits in master mode an amount of data in blocking mode.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t sizetmp = 0;\r
+\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+ sizetmp = Size;\r
+ }\r
+ \r
+ do\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*pData++);\r
+ sizetmp--;\r
+ Size--;\r
+\r
+ if((sizetmp == 0)&&(Size!=0))\r
+ {\r
+ /* Wait until TXE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ sizetmp = Size;\r
+ }\r
+ }\r
+\r
+ }while(Size > 0);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives in master mode an amount of data in blocking mode. \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t sizetmp = 0;\r
+\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ sizetmp = Size;\r
+ }\r
+ \r
+ do\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Write data to RXDR */\r
+ (*pData++) =hi2c->Instance->RXDR;\r
+ sizetmp--;\r
+ Size--;\r
+\r
+ if((sizetmp == 0)&&(Size!=0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ sizetmp = Size;\r
+ }\r
+ }\r
+\r
+ }while(Size > 0);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits in slave mode an amount of data in blocking mode. \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+\r
+ /* If 10bit addressing mode is selected */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Wait until DIR flag is set Transmitter mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ do\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Read data from TXDR */\r
+ hi2c->Instance->TXDR = (*pData++);\r
+ Size--;\r
+ }while(Size > 0);\r
+ \r
+ /* Wait until STOP flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Normal use case for Transmitter mode */\r
+ /* A NACK is generated to confirm the end of transfer */\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in blocking mode \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* Wait until DIR flag is reset Receiver mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ while(Size > 0)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Read data from RXDR */\r
+ (*pData++) = hi2c->Instance->RXDR;\r
+ Size--;\r
+ }\r
+ \r
+ /* Wait until STOP flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI );\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferSize = Size;\r
+ hi2c->XferCount = Size;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI );\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferSize = Size;\r
+ hi2c->XferCount = Size;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in no-blocking mode with DMA\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+ } \r
+\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in no-blocking mode with DMA \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c); \r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = Size;\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* If 10bits addressing mode is selected */\r
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ }\r
+ \r
+ /* Wait until DIR flag is set Transmitter mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in no-blocking mode with DMA \r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferSize = Size;\r
+ hi2c->XferCount = Size;\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);\r
+ \r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r
+ \r
+ /* Wait until DIR flag is set Receiver mode */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK) \r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in blocking mode to a specific memory address\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t Sizetmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = Size;\r
+ }\r
+ \r
+ do\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Write data to DR */\r
+ hi2c->Instance->TXDR = (*pData++);\r
+ Sizetmp--;\r
+ Size--;\r
+\r
+ if((Sizetmp == 0)&&(Size!=0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ \r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = Size;\r
+ }\r
+ }\r
+ \r
+ }while(Size > 0);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in blocking mode from a specific memory address\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t Sizetmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ { \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ Sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ Sizetmp = Size;\r
+ }\r
+ \r
+ do\r
+ { \r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Read data from RXDR */\r
+ (*pData++) = hi2c->Instance->RXDR;\r
+\r
+ /* Decrement the Size counter */\r
+ Sizetmp--;\r
+ Size--; \r
+\r
+ if((Sizetmp == 0)&&(Size!=0))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ if(Size > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ Sizetmp = Size;\r
+ }\r
+ }\r
+\r
+ }while(Size > 0);\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ } \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ /* Size > 255, need to set RELOAD bit */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process \r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+/**\r
+ * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+ \r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be read\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;\r
+ \r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ if(Size > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = Size;\r
+ }\r
+\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address and Memory Address */\r
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks if target device is ready for communication. \r
+ * @note This function is used with Memory devices\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param Trials: Number of trials\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0;\r
+ \r
+ __IO uint32_t I2C_Trials = 0;\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ \r
+ do\r
+ {\r
+ /* Generate Start */\r
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);\r
+ \r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set or a NACK flag is set*/\r
+ tickstart = HAL_GetTick();\r
+ while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Device is ready */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Check if the NACKF flag has not been set */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r
+ {\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Device is ready */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Clear STOP Flag, auto generated with autoend*/\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ }\r
+ \r
+ /* Check if the maximum allowed number of trials has been reached */\r
+ if (I2C_Trials++ == Trials)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ \r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ } \r
+ }while(I2C_Trials < Trials);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief This function handles I2C event interrupt request.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* I2C in mode Transmitter ---------------------------------------------------*/\r
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET))\r
+ { \r
+ /* Slave mode selected */\r
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)\r
+ {\r
+ I2C_SlaveTransmit_ISR(hi2c);\r
+ }\r
+ }\r
+ \r
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))\r
+ { \r
+ /* Master mode selected */\r
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))\r
+ {\r
+ I2C_MasterTransmit_ISR(hi2c);\r
+ }\r
+ }\r
+\r
+ /* I2C in mode Receiver ----------------------------------------------------*/\r
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))\r
+ {\r
+ /* Slave mode selected */\r
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)\r
+ {\r
+ I2C_SlaveReceive_ISR(hi2c);\r
+ }\r
+ } \r
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET))\r
+ {\r
+ /* Master mode selected */\r
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))\r
+ {\r
+ I2C_MasterReceive_ISR(hi2c);\r
+ }\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C error interrupt request.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* I2C Bus error interrupt occurred ------------------------------------*/\r
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))\r
+ { \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r
+ \r
+ /* Clear BERR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r
+ }\r
+ \r
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))\r
+ { \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r
+\r
+ /* Clear OVR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r
+ }\r
+\r
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))\r
+ { \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r
+\r
+ /* Clear ARLO flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r
+ }\r
+\r
+ /* Call the Error Callback in case of Error detected */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Master Tx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Master Rx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/** @brief Slave Tx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Slave Rx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Memory Tx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Memory Rx Transfer completed callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2C error callbacks.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2C_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permit to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the I2C state.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL state\r
+ */\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the I2C error code\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+* @retval I2C Error Code\r
+*/\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Handle Interrupt Flags Master Transmit Mode\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) \r
+{\r
+ uint16_t DevAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c); \r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--; \r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)\r
+ {\r
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))\r
+ {\r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ if(hi2c->XferCount > 255)\r
+ { \r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Wrong size Status regarding TCR flag event */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)\r
+ {\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Wrong size Status regarding TCR flag event */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)\r
+ {\r
+ HAL_I2C_MemTxCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Handle Interrupt Flags Master Receive Mode\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) \r
+{\r
+ uint16_t DevAddress;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
+ { \r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)\r
+ {\r
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))\r
+ { \r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ if(hi2c->XferCount > 255)\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ hi2c->XferSize = 255;\r
+ } \r
+ else\r
+ { \r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ } \r
+ } \r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Wrong size Status regarding TCR flag event */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)\r
+ {\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Wrong size Status regarding TCR flag event */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)\r
+ {\r
+ HAL_I2C_MemRxCpltCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c); \r
+ \r
+ return HAL_OK; \r
+\r
+} \r
+\r
+/**\r
+ * @brief Handle Interrupt Flags Slave Transmit Mode\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) \r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)\r
+ {\r
+ /* Check that I2C transfer finished */\r
+ /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */\r
+ /* Mean XferCount == 0*/\r
+ /* So clear Flag NACKF only */\r
+ if(hi2c->XferCount == 0)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ /* Call the Error callback to prevent upper layer */\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)\r
+ {\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+ /* Check first if STOPF is set */\r
+ /* to prevent a Write Data in TX buffer */\r
+ /* which is stuck in TXDR until next */\r
+ /* communication with Master */\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)\r
+ {\r
+ /* Write data to TXDR only if XferCount not reach "0" */\r
+ /* A TXIS flag can be set, during STOP treatment */\r
+ if(hi2c->XferCount > 0)\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r
+ hi2c->XferCount--;\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Handle Interrupt Flags Slave Receive Mode\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) \r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+ \r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)\r
+ {\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
+ {\r
+ /* Read data from RXDR */\r
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );\r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ \r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for write request.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) \r
+{\r
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* If Memory address size is 8Bit */\r
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); \r
+ } \r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); \r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); \r
+ }\r
+ \r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for read request.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress: Target device address\r
+ * @param MemAddress: Internal memory address\r
+ * @param MemAddSize: Size of internal memory address\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)\r
+{\r
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* If Memory address size is 8Bit */\r
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); \r
+ } \r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); \r
+ \r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); \r
+ }\r
+ \r
+ /* Wait until TC flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master transmit process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ uint16_t DevAddress;\r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Check if last DMA request was done with RELOAD */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; \r
+ \r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ if(hi2c->XferCount > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ } \r
+\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; \r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave transmit process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Wait until STOP flag is set */\r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Normal Use case, a AF is generated by master */\r
+ /* to inform slave the end of transfer */\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; \r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master receive process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ uint16_t DevAddress;\r
+ \r
+ /* Check if last DMA request was done with RELOAD */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; \r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ if(hi2c->XferCount > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ } \r
+\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ \r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; \r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave receive process complete callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{ \r
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOPF flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Wait until BUSY flag is reset */ \r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; \r
+ \r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C Memory Write process complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ uint16_t DevAddress;\r
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Check if last DMA request was done with RELOAD */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; \r
+ \r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ if(hi2c->XferCount > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ } \r
+\r
+ /* Wait until TXIS flag is set */\r
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; \r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MemTxCpltCallback(hi2c);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C Memory Read process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{ \r
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; \r
+ uint16_t DevAddress;\r
+ \r
+ /* Check if last DMA request was done with RELOAD */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; \r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+ if(hi2c->XferCount > 255)\r
+ {\r
+ hi2c->XferSize = 255;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+ \r
+ /* Enable the DMA channel */\r
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\r
+ \r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if size > 255 */\r
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ } \r
+\r
+ /* Wait until RXNE flag is set */\r
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) \r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ \r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */ \r
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)\r
+ {\r
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ else\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ \r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+ \r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; \r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Check if Errors has been detected during transfer */\r
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+ }\r
+ else\r
+ {\r
+ HAL_I2C_MemRxCpltCallback(hi2c);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C communication error callback. \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ \r
+ hi2c->XferCount = 0;\r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+ \r
+ HAL_I2C_ErrorCallback(hi2c);\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Flag: specifies the I2C flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) \r
+{ \r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ { \r
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) \r
+{ \r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0x00;\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0x00;\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r
+ {\r
+ /* Check if a STOPF is detected */\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check for the Timeout */\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.\r
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0x00;\r
+ tickstart = HAL_GetTick();\r
+\r
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+ {\r
+ /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */\r
+ if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)\r
+ || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))\r
+ {\r
+ /* No need to generate the STOP condition if AUTOEND mode is enabled */\r
+ /* Generate the STOP condition only in case of SOFTEND mode is enabled */\r
+ if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ }\r
+ \r
+ /* Wait until STOP Flag is reset */\r
+ /* AutoEnd should be initiate after AF */\r
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Clear NACKF Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;\r
+ hi2c->State= HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r
+ * @param hi2c: I2C handle.\r
+ * @param DevAddress: specifies the slave address to be programmed.\r
+ * @param Size: specifies the number of bytes to be programmed.\r
+ * This parameter must be a value between 0 and 255.\r
+ * @param Mode: new state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_RELOAD_MODE: Enable Reload mode .\r
+ * @arg I2C_AUTOEND_MODE: Enable Automatic end mode.\r
+ * @arg I2C_SOFTEND_MODE: Enable Software end mode.\r
+ * @param Request: new state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.\r
+ * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).\r
+ * @arg I2C_GENERATE_START_READ: Generate Restart for read request.\r
+ * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.\r
+ * @retval None\r
+ */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_TRANSFER_MODE(Mode));\r
+ assert_param(IS_TRANSFER_REQUEST(Request));\r
+ \r
+ /* Get the CR2 register value */\r
+ tmpreg = hi2c->Instance->CR2;\r
+ \r
+ /* clear tmpreg specific bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));\r
+ \r
+ /* update tmpreg */\r
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \\r
+ (uint32_t)Mode | (uint32_t)Request);\r
+ \r
+ /* update CR2 register */\r
+ hi2c->Instance->CR2 = tmpreg; \r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief I2C Extended HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of I2C Extended peripheral:\r
+ * + Extended features functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### I2C peripheral Extended features #####\r
+ ==============================================================================\r
+ \r
+ [..] Comparing to other previous devices, the I2C interface for STM32L4XX\r
+ devices contains the following additional features\r
+ \r
+ (+) Possibility to disable or enable Analog Noise Filter\r
+ (+) Use of a configured Digital Noise Filter\r
+ (+) Disable or enable wakeup from Stop mode\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to:\r
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx I2C Extended HAL module driver\r
+ * @brief I2C Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure Noise Filters \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Configures I2C Analog noise filter. \r
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param AnalogFilter : new state of the Analog filter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r
+ \r
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)\r
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c); \r
+ \r
+ /* Reset I2Cx ANOFF bit */\r
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); \r
+ \r
+ /* Set analog filter bit*/\r
+ hi2c->Instance->CR1 |= AnalogFilter;\r
+ \r
+ __HAL_I2C_ENABLE(hi2c); \r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configures I2C Digital noise filter. \r
+ * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r
+ \r
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)\r
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ \r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c); \r
+ \r
+ /* Get the old register value */\r
+ tmpreg = hi2c->Instance->CR1;\r
+ \r
+ /* Reset I2Cx DNF bits [11:8] */\r
+ tmpreg &= ~(I2C_CR1_DFN);\r
+ \r
+ /* Set I2Cx DNF coefficient */\r
+ tmpreg |= DigitalFilter << 8;\r
+ \r
+ /* Store the new register value */\r
+ hi2c->Instance->CR1 = tmpreg;\r
+ \r
+ __HAL_I2C_ENABLE(hi2c); \r
+ \r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2s.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief I2S HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The I2S HAL driver can be used as follows:\r
+ \r
+ (#) Declare a I2S_HandleTypeDef handle structure.\r
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:\r
+ (##) Enable the SPIx interface clock. \r
+ (##) I2S pins configuration:\r
+ (+++) Enable the clock for the I2S GPIOs.\r
+ (+++) Configure these I2S pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()\r
+ and HAL_I2S_Receive_IT() APIs).\r
+ (+++) Configure the I2Sx interrupt priority.\r
+ (+++) Enable the NVIC I2S IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()\r
+ and HAL_I2S_Receive_DMA() APIs:\r
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Channel.\r
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r
+ DMA Tx/Rx Channel.\r
+ \r
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity\r
+ using HAL_I2S_Init() function.\r
+\r
+ -@- The specific I2S interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.\r
+ -@- Make sure that either:\r
+ (+@) I2S clock is configured based on SYSCLK or \r
+ (+@) External clock source is configured after setting correctly \r
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file. \r
+\r
+ (#) Three mode of operations are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() \r
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() \r
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() \r
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback\r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() \r
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() \r
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() \r
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume() \r
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop() \r
+ \r
+ *** I2S HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in I2S HAL driver.\r
+ \r
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) \r
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) \r
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts\r
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts\r
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not\r
+ \r
+ [..] \r
+ (@) You can refer to the I2S HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F3xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2S I2S HAL module driver\r
+ * @brief I2S HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);\r
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);\r
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);\r
+static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);\r
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2S_Exported_Functions I2S Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the I2Sx peripheral in simplex mode:\r
+\r
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_I2S_Init() to configure the selected device with \r
+ the selected configuration:\r
+ (++) Mode\r
+ (++) Standard \r
+ (++) Data Format\r
+ (++) MCLK Output\r
+ (++) Audio frequency\r
+ (++) Polarity\r
+ (++) Full duplex mode\r
+\r
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration \r
+ of the selected I2Sx peripheral. \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the I2S according to the specified parameters \r
+ * in the I2S_InitTypeDef and create the associated handle.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0, i2sclk = 0;\r
+ \r
+ /* Check the I2S handle allocation */\r
+ if(hi2s == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));\r
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));\r
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); \r
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));\r
+ \r
+ hi2s->State = HAL_I2S_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2S_MspInit(hi2s);\r
+ \r
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \\r
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \\r
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); \r
+ hi2s->Instance->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = hi2s->Instance->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) *******************/\r
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+ \r
+ /* Get I2S source Clock frequency ****************************************/\r
+\r
+ /* If an external I2S clock has to be used, the specific define should be set \r
+ in the project configuration or in the stm32f3xx_conf.h file */\r
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)\r
+ { \r
+ /* Set the I2S clock to the external clock value */\r
+ i2sclk = EXTERNAL_CLOCK_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* Get the I2S source clock value */\r
+ i2sclk = I2S_GetClockFreq(hi2s);\r
+ }\r
+ \r
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */\r
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flatting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+ \r
+ /* Write to SPIx I2SPR register the computed value */\r
+ hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));\r
+ \r
+ /* Configure the I2S with the I2S_InitStruct values */\r
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \\r
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \\r
+ (uint16_t)hi2s->Init.CPOL))));\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ hi2s->Instance->I2SCFGR = tmpreg;\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief DeInitializes the I2S peripheral \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Check the I2S handle allocation */\r
+ if(hi2s == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r
+\r
+ hi2s->State = HAL_I2S_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_I2S_MspDeInit(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief I2S MSP Init\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief I2S MSP DeInit\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the I2S data \r
+ transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the \r
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_I2S_Transmit()\r
+ (++) HAL_I2S_Receive()\r
+ \r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_I2S_Transmit_IT()\r
+ (++) HAL_I2S_Receive_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_I2S_Transmit_DMA()\r
+ (++) HAL_I2S_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_I2S_TxCpltCallback()\r
+ (++) HAL_I2S_RxCpltCallback()\r
+ (++) HAL_I2S_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @param Timeout: Timeout duration\r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ }\r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ while(hi2s->TxXferCount > 0)\r
+ {\r
+ hi2s->Instance->DR = (*pData++);\r
+ hi2s->TxXferCount--; \r
+ /* Wait until TXE flag is set */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)\r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ /* Check if an underrun occurs */\r
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) \r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ } \r
+ \r
+ /* Wait until Busy flag is reset */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) \r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @param Timeout: Timeout duration\r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate\r
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ }\r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Check if Master Receiver mode is selected */\r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r
+ {\r
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read\r
+ access to the SPI_SR register. */ \r
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s); \r
+ }\r
+ \r
+ /* Receive data */\r
+ while(hi2s->RxXferCount > 0)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) \r
+ {\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Check if an overrun occurs */\r
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) \r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ (*pData++) = hi2s->Instance->DR;\r
+ hi2s->RxXferCount--;\r
+ } \r
+\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ hi2s->pTxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation \r
+ * between Master and Slave otherwise the I2S interrupt should be optimized. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ hi2s->pRxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+\r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with DMA\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Transmit data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ hi2s->pTxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->TxXferSize = (Size << 1);\r
+ hi2s->TxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->TxXferSize = Size;\r
+ hi2s->TxXferCount = Size;\r
+ } \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;\r
+\r
+ /* Set the I2S Tx DMA Half transfer complete callback */\r
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;\r
+\r
+ /* Set the I2S TxDMA transfer complete callback */\r
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;\r
+ \r
+ /* Enable the Tx DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Enable Tx DMA Request */ \r
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with DMA \r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param pData: a 16-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be sent:\r
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r
+ * configuration phase, the Size parameter means the number of 16-bit data length \r
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r
+ * the Size parameter means the number of 16-bit data length. \r
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r
+ * between Master and Slave(example: audio streaming).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_READY)\r
+ { \r
+ hi2s->pRxBuffPtr = pData;\r
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\r
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r
+ {\r
+ hi2s->RxXferSize = (Size << 1);\r
+ hi2s->RxXferCount = (Size << 1);\r
+ } \r
+ else\r
+ {\r
+ hi2s->RxXferSize = Size;\r
+ hi2s->RxXferCount = Size;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;\r
+ \r
+ /* Set the I2S Rx DMA Half transfer complete callback */\r
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;\r
+\r
+ /* Set the I2S Rx DMA transfer complete callback */\r
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;\r
+ \r
+ /* Check if Master Receiver mode is selected */\r
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r
+ {\r
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read\r
+ access to the SPI_SR register. */ \r
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s); \r
+ }\r
+ \r
+ /* Enable the Rx DMA Channel */\r
+ tmp = (uint32_t*)&pData; \r
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);\r
+ \r
+ /* Check if the I2S is already enabled */ \r
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Enable Rx DMA Request */ \r
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the I2S DMA Tx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ {\r
+ /* Disable the I2S DMA Rx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))\r
+ {\r
+ /* Disable the I2S DMA Tx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the I2S DMA Rx request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resumes the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the I2S DMA Tx request */\r
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ {\r
+ /* Enable the I2S DMA Rx request */\r
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r
+ }\r
+ \r
+ /* If the I2S peripheral is still not enabled, enable it */\r
+ if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))\r
+ {\r
+ /* Enable I2S peripheral */ \r
+ __HAL_I2S_ENABLE(hi2s);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the audio stream playing from the Media.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2s);\r
+ \r
+ /* Disable the I2S Tx/Rx DMA requests */\r
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r
+ \r
+ /* Abort the I2S DMA Channel tx */\r
+ if(hi2s->hdmatx != NULL)\r
+ {\r
+ /* Disable the I2S DMA channel */\r
+ __HAL_DMA_DISABLE(hi2s->hdmatx);\r
+ HAL_DMA_Abort(hi2s->hdmatx);\r
+ }\r
+ /* Abort the I2S DMA Channel rx */\r
+ if(hi2s->hdmarx != NULL)\r
+ {\r
+ /* Disable the I2S DMA channel */\r
+ __HAL_DMA_DISABLE(hi2s->hdmarx);\r
+ HAL_DMA_Abort(hi2s->hdmarx);\r
+ }\r
+\r
+ /* Disable I2S peripheral */\r
+ __HAL_I2S_DISABLE(hi2s);\r
+ \r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2S interrupt request.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL status\r
+ */\r
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)\r
+{ \r
+ __IO uint32_t i2ssr = hi2s->Instance->SR;\r
+\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r
+ { \r
+ /* I2S in mode Receiver ----------------------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))\r
+ {\r
+ I2S_Receive_IT(hi2s);\r
+ }\r
+\r
+ /* I2S Overrun error interrupt occurred -------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r
+ {\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ } \r
+ }\r
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r
+ { \r
+ /* I2S in mode Transmitter ---------------------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))\r
+ { \r
+ I2S_Transmit_IT(hi2s);\r
+ } \r
+ \r
+ /* I2S Underrun error interrupt occurred ------------------------------------*/\r
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r
+ {\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+\r
+ /* Set the I2S State ready */\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles I2S Communication Timeout.\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @param Flag: Flag checked\r
+ * @param State: Value of the flag expected\r
+ * @param Timeout: Duration of the timeout\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, \r
+ uint32_t State, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is set */\r
+ if(State == RESET)\r
+ {\r
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Set the I2S State ready */\r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2s);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions \r
+ * @{\r
+ */\r
+/**\r
+ * @brief Tx Transfer Half completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer half completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2S error callbacks\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_I2S_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the I2S state\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval HAL state\r
+ */\r
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)\r
+{\r
+ return hi2s->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the I2S error code\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval I2S Error Code\r
+ */\r
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)\r
+{\r
+ return hi2s->ErrorCode;\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @brief Get I2S Input Clock based on I2S source clock selection\r
+ * @param hsai: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module. \r
+ * @retval I2S Clock Input \r
+ */\r
+static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* This variable used to store the VCO Input (value in Hz) */\r
+ uint32_t vcoinput = 0;\r
+ /* This variable used to store the I2S_CK_x (value in Hz) */\r
+ uint32_t i2sclocksource = 0;\r
+\r
+ /* Configure I2S Clock based on I2S source clock selection */ \r
+ \r
+ /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */\r
+ switch(hi2s->Init.ClockSource)\r
+ {\r
+ case I2S_CLOCK_SYSCLK :\r
+ {\r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;\r
+ i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+ \r
+ break;\r
+ }\r
+ case I2S_CLOCK_EXTERNAL :\r
+ {\r
+ i2sclocksource = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* the return result is the value of I2S clock */\r
+ return i2sclocksource; \r
+}\r
+\r
+/** @addtogroup I2S_Private_Functions I2S Private Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief DMA I2S transmit process complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hi2s->TxXferCount = 0;\r
+\r
+ /* Disable Tx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+ \r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if(hi2s->RxXferCount == 0)\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ }\r
+ }\r
+ HAL_I2S_TxCpltCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief DMA I2S transmit process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_I2S_TxHalfCpltCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief DMA I2S receive process complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Rx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+\r
+ hi2s->RxXferCount = 0;\r
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r
+ {\r
+ if(hi2s->TxXferCount == 0)\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ }\r
+ }\r
+ HAL_I2S_RxCpltCallback(hi2s); \r
+}\r
+ \r
+/**\r
+ * @brief DMA I2S receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_I2S_RxHalfCpltCallback(hi2s); \r
+}\r
+\r
+/**\r
+ * @brief DMA I2S communication error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void I2S_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx and Tx DMA Request */\r
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));\r
+ hi2s->TxXferCount = 0;\r
+ hi2s->RxXferCount = 0;\r
+ \r
+ hi2s->State= HAL_I2S_STATE_READY;\r
+\r
+ /* Set the error code and execute error callback*/\r
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;\r
+ HAL_I2S_ErrorCallback(hi2s);\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains\r
+ * the configuration information for I2S module\r
+ * @retval None\r
+ */\r
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Transmit data */\r
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);\r
+ hi2s->TxXferCount--; \r
+\r
+ if(hi2s->TxXferCount == 0)\r
+ {\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r
+\r
+ hi2s->State = HAL_I2S_STATE_READY;\r
+ HAL_I2S_TxCpltCallback(hi2s);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2s: I2S handle\r
+ * @retval None\r
+ */\r
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)\r
+{\r
+ /* Receive data */ \r
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;\r
+ hi2s->RxXferCount--;\r
+\r
+ if(hi2s->RxXferCount == 0)\r
+ { \r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r
+\r
+ hi2s->State = HAL_I2S_STATE_READY; \r
+ HAL_I2S_RxCpltCallback(hi2s); \r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_irda.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief IRDA HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the IrDA SIR ENDEC block (IrDA):\r
+ * + Initialization and de-initialization methods\r
+ * + IO operation methods\r
+ * + Peripheral Control methods\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The IRDA HAL driver can be used as follows:\r
+ \r
+ (#) Declare a IRDA_HandleTypeDef handle structure.\r
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) IRDA pins configuration:\r
+ (+++) Enable the clock for the IRDA GPIOs.\r
+ (+++) Configure these IRDA pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()\r
+ and HAL_IRDA_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()\r
+ and HAL_IRDA_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler \r
+ and Mode(Receiver/Transmitter) in the hirda Init structure.\r
+\r
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:\r
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customized HAL_IRDA_MspInit() API.\r
+ -@@- The specific IRDA interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.\r
+ \r
+ (#) Three operation modes are available within this driver :\r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() \r
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() \r
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() \r
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback\r
+\r
+ *** DMA mode IO operation *** \r
+ =============================\r
+ [..]\r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() \r
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() \r
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback \r
+\r
+ *** IRDA HAL driver macros list ***\r
+ ===================================\r
+ [..]\r
+ Below the list of most used macros in IRDA HAL driver.\r
+ \r
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral \r
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral \r
+ (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not\r
+ (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag\r
+ (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt\r
+ (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt\r
+ \r
+ (@) You can refer to the IRDA HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IRDA IRDA\r
+ * @brief HAL IRDA module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup IRDA_Private_Constants\r
+ * @{\r
+ */\r
+#define TEACK_REACK_TIMEOUT 1000\r
+#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000\r
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \\r
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup IRDA_Private_Functions\r
+ * @{\r
+ */\r
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma); \r
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);\r
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy \r
+ in IrDA mode.\r
+ (+) For the asynchronous mode only these parameters can be configured: \r
+ (++) BaudRate\r
+ (++) WordLength \r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ please refer to Reference manual for possible IRDA frame formats.\r
+ (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may\r
+ not be rejected. The receiver set up time should be managed by software. The IrDA physical layer\r
+ specification specifies a minimum of 10 ms delay between transmission and \r
+ reception (IrDA is a half duplex protocol).\r
+ (++) Mode: Receiver/transmitter modes\r
+ (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.\r
+ [..]\r
+ The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures\r
+ are available in reference manual).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the IRDA mode according to the specified\r
+ * parameters in the IRDA_InitTypeDef and create the associated handle.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Check the IRDA handle allocation */\r
+ if(hirda == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the USART/UART associated to the IRDA handle */\r
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));\r
+\r
+ if(hirda->State == HAL_IRDA_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_IRDA_MspInit(hirda);\r
+ }\r
+\r
+ hirda->State = HAL_IRDA_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral to update the configuration registers */\r
+ __HAL_IRDA_DISABLE(hirda);\r
+\r
+ /* Set the IRDA Communication parameters */\r
+ IRDA_SetConfig(hirda);\r
+\r
+ /* In IRDA mode, the following bits must be kept cleared: \r
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and HDSEL bits in the USART_CR3 register.*/\r
+ hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); \r
+ hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); \r
+\r
+ /* set the UART/USART in IRDA mode */\r
+ hirda->Instance->CR3 |= USART_CR3_IREN; \r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_IRDA_ENABLE(hirda);\r
+\r
+ /* TEACK and/or REACK to check before moving hirda->State to Ready */\r
+ return (IRDA_CheckIdleState(hirda));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the IRDA peripheral \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Check the IRDA handle allocation */\r
+ if(hirda == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); \r
+ \r
+ hirda->State = HAL_IRDA_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_IRDA_MspDeInit(hirda);\r
+ /* Disable the Peripheral */\r
+ __HAL_IRDA_DISABLE(hirda);\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ hirda->State = HAL_IRDA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief IRDA MSP Init.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_IRDA_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief IRDA MSP DeInit.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_IRDA_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions \r
+ * @brief IRDA Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.\r
+ [..]\r
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver \r
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r
+ While receiving data, transmission should be avoided as the data to be transmitted\r
+ could be corrupted.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode: the communication is performed in polling mode. \r
+ The HAL status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode: the communication is performed using Interrupts \r
+ or DMA, these API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks \r
+ will be executed respectively at the end of the Transmit or Receive process\r
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (++) HAL_IRDA_Transmit()\r
+ (++) HAL_IRDA_Receive() \r
+ \r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (++) HAL_IRDA_Transmit_IT()\r
+ (++) HAL_IRDA_Receive_IT()\r
+ (++) HAL_IRDA_IRQHandler()\r
+ (++) IRDA_Transmit_IT()\r
+ (++) IRDA_Receive_IT()\r
+\r
+ (#) Non-Blocking mode functions with DMA are :\r
+ (++) HAL_IRDA_Transmit_DMA()\r
+ (++) HAL_IRDA_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (++) HAL_IRDA_TxCpltCallback()\r
+ (++) HAL_IRDA_RxCpltCallback()\r
+ (++) HAL_IRDA_ErrorCallback()\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an amount of data in blocking mode.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Specify timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ \r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) \r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ } \r
+ \r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size;\r
+ while(hirda->TxXferCount > 0)\r
+ {\r
+ hirda->TxXferCount--;\r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData;\r
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); \r
+ pData +=2;\r
+ }\r
+ else\r
+ { \r
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); \r
+ }\r
+ } \r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ } \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Specify timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{ \r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+ \r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))\r
+ { \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ } \r
+ \r
+ hirda->RxXferSize = Size; \r
+ hirda->RxXferCount = Size;\r
+\r
+ /* Computation of the mask to apply to the RDR register \r
+ of the UART associated to the IRDA */\r
+ IRDA_MASK_COMPUTATION(hirda);\r
+ uhMask = hirda->Mask;\r
+\r
+ /* Check data remaining to be received */\r
+ while(hirda->RxXferCount > 0)\r
+ {\r
+ hirda->RxXferCount--;\r
+\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData ;\r
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);\r
+ pData +=2;\r
+ }\r
+ else\r
+ {\r
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); \r
+ } \r
+ } \r
+\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ hirda->pTxBuffPtr = pData;\r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size;\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda); \r
+ \r
+ /* Enable the IRDA Transmit Complete Interrupt */\r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{ \r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ hirda->pRxBuffPtr = pData;\r
+ hirda->RxXferSize = Size;\r
+ hirda->RxXferCount = Size;\r
+ \r
+ /* Computation of the mask to apply to the RDR register \r
+ of the UART associated to the IRDA */\r
+ IRDA_MASK_COMPUTATION(hirda); \r
+ \r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Enable the IRDA Parity Error Interrupt */\r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);\r
+ \r
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ /* Enable the IRDA Data Register not empty Interrupt */\r
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ hirda->pTxBuffPtr = pData;\r
+ hirda->TxXferSize = Size;\r
+ hirda->TxXferCount = Size; \r
+ \r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Set the IRDA DMA transfer complete callback */\r
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;\r
+ \r
+ /* Set the IRDA DMA half transfer complete callback */\r
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;\r
+\r
+ /* Enable the IRDA transmit DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);\r
+ \r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);\r
+ \r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the IRDA CR3 register */\r
+ hirda->Instance->CR3 |= USART_CR3_DMAT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in non blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ hirda->pRxBuffPtr = pData;\r
+ hirda->RxXferSize = Size;\r
+\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Set the IRDA DMA transfer complete callback */\r
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;\r
+ \r
+ /* Set the IRDA DMA half transfer complete callback */\r
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;\r
+\r
+ /* Enable the DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the IRDA CR3 register */\r
+ hirda->Instance->CR3 |= USART_CR3_DMAR;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ }\r
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)\r
+ {\r
+ /* Disable the UART DMA Rx request */\r
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+ else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Disable the UART DMA Tx & Rx requests */\r
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hirda);\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ hirda->Instance->CR3 |= USART_CR3_DMAT;\r
+ }\r
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r
+\r
+ /* Enable the UART DMA Rx request */\r
+ hirda->Instance->CR3 |= USART_CR3_DMAR;\r
+ }\r
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Clear the Overrun flag before resuming the Rx transfer*/\r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r
+ \r
+ /* Enable the UART DMA Tx & Rx request */\r
+ hirda->Instance->CR3 |= USART_CR3_DMAT;\r
+ hirda->Instance->CR3 |= USART_CR3_DMAR;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():\r
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
+ and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()\r
+ */\r
+\r
+ /* Disable the UART Tx/Rx DMA requests */\r
+ hirda->Instance->CR3 &= ~USART_CR3_DMAT;\r
+ hirda->Instance->CR3 &= ~USART_CR3_DMAR;\r
+ \r
+ /* Abort the UART DMA tx channel */\r
+ if(hirda->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hirda->hdmatx);\r
+ }\r
+ /* Abort the UART DMA rx channel */\r
+ if(hirda->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hirda->hdmarx);\r
+ }\r
+ \r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles IRDA interrupt request.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* IRDA parity error interrupt occurred -------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))\r
+ { \r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);\r
+\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;\r
+ /* Set the IRDA state ready to be able to start again the process */\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ /* IRDA frame error interrupt occurred --------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))\r
+ { \r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);\r
+\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;\r
+ /* Set the IRDA state ready to be able to start again the process */\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ /* IRDA noise error interrupt occurred --------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))\r
+ { \r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);\r
+\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE; \r
+ /* Set the IRDA state ready to be able to start again the process */\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))\r
+ { \r
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r
+\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; \r
+ /* Set the IRDA state ready to be able to start again the process */\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ /* Call IRDA Error Call back function if need be --------------------------*/\r
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)\r
+ {\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+ } \r
+\r
+ /* IRDA in mode Receiver ---------------------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))\r
+ { \r
+ IRDA_Receive_IT(hirda);\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);\r
+ }\r
+ \r
+ /* IRDA in mode Transmitter ------------------------------------------------*/\r
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))\r
+ {\r
+ IRDA_Transmit_IT(hirda);\r
+ } \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer complete callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief IRDA error callbacks.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IRDA_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions \r
+ * @brief IRDA control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the IRDA.\r
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. \r
+ (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the IRDA state.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL state\r
+ */\r
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)\r
+{\r
+ return hirda->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the IRDA error code\r
+ * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA.\r
+* @retval IRDA Error Code\r
+*/\r
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)\r
+{\r
+ return hirda->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the IRDA peripheral \r
+ * @param hirda: irda handle\r
+ * @retval None\r
+ */\r
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint32_t tmpreg = 0x00000000;\r
+ uint32_t clocksource = 0x00000000;\r
+ \r
+ /* Check the communication parameters */ \r
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); \r
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));\r
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));\r
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));\r
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); \r
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); \r
+ /*-------------------------- USART CR1 Configuration -----------------------*/ \r
+ /* Configure the IRDA Word Length, Parity and transfer Mode: \r
+ Set the M bits according to hirda->Init.WordLength value \r
+ Set PCE and PS bits according to hirda->Init.Parity value\r
+ Set TE and RE bits according to hirda->Init.Mode value */\r
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;\r
+ \r
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);\r
+ \r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);\r
+ \r
+ /*-------------------------- USART GTPR Configuration ----------------------*/ \r
+ MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);\r
+ \r
+ /*-------------------------- USART BRR Configuration -----------------------*/ \r
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case IRDA_CLOCKSOURCE_PCLK1: \r
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_PCLK2: \r
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate);\r
+ break;\r
+ case IRDA_CLOCKSOURCE_HSI: \r
+ hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); \r
+ break; \r
+ case IRDA_CLOCKSOURCE_SYSCLK: \r
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);\r
+ break; \r
+ case IRDA_CLOCKSOURCE_LSE: \r
+ hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); \r
+ break;\r
+ default:\r
+ break;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Check the IRDA Idle State\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)\r
+{\r
+ /* Initialize the IRDA ErrorCode */\r
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r
+ \r
+ /* Check if the Transmitter is enabled */\r
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ { \r
+ hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)\r
+ { \r
+ hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+ \r
+ /* Initialize the IRDA state*/\r
+ hirda->State= HAL_IRDA_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles IRDA Communication Timeout.\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @param Flag: specifies the IRDA flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) \r
+{\r
+ uint32_t tickstart = 0x00;\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ {\r
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
+\r
+ hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
+\r
+ hirda->State= HAL_IRDA_STATE_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hirda);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode. \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint16_t* tmp;\r
+ \r
+ if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))\r
+ {\r
+ if(hirda->TxXferCount == 0)\r
+ {\r
+ /* Disable the IRDA Transmit Complete Interrupt */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
+ \r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) hirda->pTxBuffPtr;\r
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);\r
+ hirda->pTxBuffPtr += 2;\r
+ }\r
+ else\r
+ {\r
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); \r
+ }\r
+ hirda->TxXferCount--;\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non blocking mode. \r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()\r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = hirda->Mask;\r
+ \r
+ if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))\r
+ {\r
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);\r
+ hirda->pRxBuffPtr +=2;\r
+ }\r
+ else\r
+ {\r
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); \r
+ }\r
+ \r
+ if(--hirda->RxXferCount == 0)\r
+ {\r
+ while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE))\r
+ {\r
+ }\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the IRDA Parity Error Interrupt */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);\r
+ \r
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);\r
+ \r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ \r
+ HAL_IRDA_RxCpltCallback(hirda);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief DMA IRDA Tx transfer completed callback \r
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IRDA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hirda->TxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the IRDA CR3 register */\r
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);\r
+ \r
+ /* Wait for IRDA TC Flag */\r
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, HAL_IRDA_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
+ {\r
+ /* Timeout Occured */ \r
+ hirda->State = HAL_IRDA_STATE_TIMEOUT;\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+ }\r
+ else\r
+ {\r
+ /* No Timeout */\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+ }\r
+ }\r
+ /* DMA Circular mode */\r
+ else\r
+ {\r
+ HAL_IRDA_TxCpltCallback(hirda);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_IRDA_TxHalfCpltCallback(hirda); \r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA Rx Transfer completed callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ /* DMA Normal mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ hirda->RxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the IRDA CR3 register */\r
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);\r
+ \r
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) \r
+ {\r
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ hirda->State = HAL_IRDA_STATE_READY;\r
+ }\r
+ }\r
+ \r
+ HAL_IRDA_RxCpltCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_IRDA_RxHalfCpltCallback(hirda); \r
+}\r
+\r
+/**\r
+ * @brief DMA IRDA communication error callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hirda->RxXferCount = 0;\r
+ hirda->TxXferCount = 0;\r
+ hirda->State= HAL_IRDA_STATE_READY;\r
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;\r
+ HAL_IRDA_ErrorCallback(hirda);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief IWDG HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Independent Watchdog (IWDG) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IWDG Generic features #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) The IWDG can be started by either software or hardware (configurable\r
+ through option byte).\r
+\r
+ (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and\r
+ thus stays active even if the main clock fails.\r
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
+ (LSI cannot be disabled too), and the counter starts counting down from\r
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
+ a system reset is generated.\r
+\r
+ (+) The IWDG counter should be refreshed at regular intervals, otherwise the\r
+ watchdog generates an MCU reset when the counter reaches 0.\r
+\r
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional\r
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG\r
+ reset occurs.\r
+\r
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s\r
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx\r
+ devices provide the capability to measure the LSI frequency (LSI clock\r
+ connected internally to TIM16 CH1 input capture). The measured value\r
+ can be used to have an IWDG timeout with an acceptable accuracy.\r
+\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ If Window option is disabled\r
+ \r
+ (+) Use IWDG using HAL_IWDG_Init() function to :\r
+ (++) Enable write access to IWDG_PR, IWDG_RLR.\r
+ (++) Configure the IWDG prescaler, counter reload value.\r
+ This reload value will be loaded in the IWDG counter each time the counter\r
+ is reloaded, then the IWDG will start counting down from this value.\r
+ (+) Use IWDG using HAL_IWDG_Start() function to :\r
+ (++) Reload IWDG counter with value defined in the IWDG_RLR register.\r
+ (++) Start the IWDG, when the IWDG is used in software mode (no need \r
+ to enable the LSI, it will be enabled by hardware).\r
+ (+) Then the application program must refresh the IWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ HAL_IWDG_Refresh() function.\r
+ [..] \r
+ if Window option is enabled:\r
+ \r
+ (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter\r
+ (+) Use IWDG using HAL_IWDG_Init() function to :\r
+ (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r
+ (++) Configure the IWDG prescaler, reload value and window value.\r
+ (+) Then the application program must refresh the IWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ HAL_IWDG_Refresh() function.\r
+\r
+ *** IWDG HAL driver macros list ***\r
+ ====================================\r
+ [..]\r
+ Below the list of most used macros in IWDG HAL driver.\r
+ \r
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral\r
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register \r
+ (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status\r
+ (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers\r
+ (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG IWDG HAL module driver\r
+ * @brief IWDG HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup IWDG_Private_Defines IWDG Private Defines\r
+ * @{\r
+ */\r
+\r
+#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the IWDG according to the specified parameters\r
+ in the IWDG_InitTypeDef and create the associated handle\r
+ (+) Manage Window option\r
+ (+) Initialize the IWDG MSP\r
+ (+) DeInitialize IWDG MSP \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the IWDG according to the specified\r
+ * parameters in the IWDG_InitTypeDef and creates the associated handle.\r
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the IWDG handle allocation */\r
+ if(hiwdg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));\r
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));\r
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));\r
+\r
+ /* Check pending flag, if previous update not done, return error */\r
+ if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)\r
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)\r
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hiwdg->State == HAL_IWDG_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hiwdg->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware */\r
+ HAL_IWDG_MspInit(hiwdg);\r
+ }\r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_BUSY;\r
+\r
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */\r
+ /* by writing 0x5555 in KR */\r
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);\r
+\r
+ /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */\r
+ MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler);\r
+ MODIFY_REG(hiwdg->Instance->RLR, (uint32_t)IWDG_RLR_RL, hiwdg->Init.Reload);\r
+\r
+ /* check if window option is enabled */\r
+ if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))\r
+ {\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for register to be updated */\r
+ while((uint32_t)(hiwdg->Instance->SR) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r
+ {\r
+ /* Set IWDG state */\r
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Write to IWDG WINR the IWDG_Window value to compare with */\r
+ MODIFY_REG(hiwdg->Instance->WINR, (uint32_t)IWDG_WINR_WIN, hiwdg->Init.Window);\r
+ }\r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the IWDG MSP.\r
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_IWDG_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Start the IWDG.\r
+ (+) Refresh the IWDG.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the IWDG.\r
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hiwdg); \r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_BUSY;\r
+\r
+ /* Reload IWDG counter with value defined in the RLR register */\r
+ if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)\r
+ {\r
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r
+ }\r
+\r
+ /* Start the IWDG peripheral */\r
+ __HAL_IWDG_START(hiwdg);\r
+\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until PVU, RVU, WVU flag are RESET */\r
+ while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)\r
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)\r
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )\r
+ {\r
+ \r
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r
+ {\r
+ /* Set IWDG state */\r
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hiwdg);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hiwdg);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Refreshes the IWDG.\r
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hiwdg);\r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_BUSY;\r
+\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until RVU flag is RESET */\r
+ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r
+ {\r
+ /* Set IWDG state */\r
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hiwdg);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reload IWDG counter with value defined in the reload register */\r
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r
+\r
+ /* Change IWDG peripheral state */\r
+ hiwdg->State = HAL_IWDG_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hiwdg);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions \r
+ * @brief Peripheral State functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the IWDG state.\r
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified IWDG module.\r
+ * @retval HAL state\r
+ */\r
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)\r
+{\r
+ return hiwdg->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_lptim.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief LPTIM HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Low Power Timer (LPTIM) peripheral:\r
+ * + Initialization and de-initialization functions.\r
+ * + Start/Stop operation functions in polling mode.\r
+ * + Start/Stop operation functions in interrupt mode.\r
+ * + Reading operation functions.\r
+ * + Peripheral State functions.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The LPTIM HAL driver can be used as follows:\r
+\r
+ (#)Initialize the LPTIM low level resources by implementing the\r
+ HAL_LPTIM_MspInit():\r
+ (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().\r
+ (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):\r
+ (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().\r
+ (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().\r
+ (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().\r
+ \r
+ (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function\r
+ configures mainly:\r
+ (##) The instance: LPTIM1.\r
+ (##) Clock: the counter clock.\r
+ - Source : it can be either the ULPTIM input (IN1) or one of\r
+ the internal clock; (APB, LSE, LSI or MSI).\r
+ - Prescaler: select the clock divider.\r
+ (##) UltraLowPowerClock : To be used only if the ULPTIM is selected\r
+ as counter clock source.\r
+ - Polarity: polarity of the active edge for the counter unit\r
+ if the ULPTIM input is selected.\r
+ - SampleTime: clock sampling time to configure the clock glitch\r
+ filter. \r
+ (##) Trigger: How the counter start.\r
+ - Source: trigger can be software or one of the hardware triggers.\r
+ - ActiveEdge : only for hardware trigger.\r
+ - SampleTime : trigger sampling time to configure the trigger\r
+ glitch filter.\r
+ (##) OutputPolarity : 2 opposite polarities are possibles.\r
+ (##) UpdateMode: specifies whether the update of the autoreload and\r
+ the compare values is done immediately or after the end of current\r
+ period. \r
+ \r
+ (#)Six modes are available:\r
+ \r
+ (##) PWM Mode: To generate a PWM signal with specified period and pulse,\r
+ call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption\r
+ mode.\r
+ \r
+ (##) One Pulse Mode: To generate pulse with specified width in response\r
+ to a stimulus, call HAL_LPTIM_OnePulse_Start() or\r
+ HAL_LPTIM_OnePulse_Start_IT() for interruption mode.\r
+ \r
+ (##) Set once Mode: In this mode, the output changes the level (from\r
+ low level to high level if the output polarity is configured high, else\r
+ the opposite) when a compare match occurs. To start this mode, call \r
+ HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for\r
+ interruption mode.\r
+ \r
+ (##) Encoder Mode: To use the encoder interface call\r
+ HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for \r
+ interruption mode.\r
+ \r
+ (##) Time out Mode: an active edge on one selected trigger input rests\r
+ the counter. The first trigger event will start the timer, any\r
+ successive trigger event will reset the counter and the timer will\r
+ restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or \r
+ HAL_LPTIM_TimeOut_Start_IT() for interruption mode.\r
+ \r
+ (##) Counter Mode: counter can be used to count external events on\r
+ the LPTIM Input1 or it can be used to count internal clock cycles.\r
+ To start this mode, call HAL_LPTIM_Counter_Start() or \r
+ HAL_LPTIM_Counter_Start_IT() for interruption mode. \r
+\r
+ \r
+ (#) User can stop any process by calling the corresponding API:\r
+ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is\r
+ already started in interruption mode.\r
+ \r
+ (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM LPTIM\r
+ * @brief LPTIM HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+/* Private types -------------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Types LPTIM Private Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup LPTIM_Private_Defines LPTIM Private Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPTIM_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the LPTIM according to the specified parameters in the\r
+ LPTIM_InitTypeDef and creates the associated handle.\r
+ (+) DeInitialize the LPTIM peripheral.\r
+ (+) Initialize the LPTIM MSP.\r
+ (+) DeInitialize LPTIM MSP. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the LPTIM according to the specified parameters in the\r
+ * LPTIM_InitTypeDef and creates the associated handle.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the LPTIM handle allocation */\r
+ if(hlptim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));\r
+ } \r
+ assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));\r
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));\r
+ } \r
+ assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); \r
+ assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));\r
+ assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));\r
+ \r
+ if(hlptim->State == HAL_LPTIM_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_LPTIM_MspInit(hlptim);\r
+ }\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+ \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));\r
+ }\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));\r
+ }\r
+ \r
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */\r
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |\r
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));\r
+ \r
+ /* Set initialization parameters */\r
+ tmpcfgr |= (hlptim->Init.Clock.Source |\r
+ hlptim->Init.Clock.Prescaler |\r
+ hlptim->Init.OutputPolarity |\r
+ hlptim->Init.UpdateMode |\r
+ hlptim->Init.CounterSource);\r
+ \r
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)\r
+ {\r
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |\r
+ hlptim->Init.UltraLowPowerClock.SampleTime);\r
+ } \r
+ \r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable External trigger and set the trigger source */\r
+ tmpcfgr |= (hlptim->Init.Trigger.Source |\r
+ hlptim->Init.Trigger.ActiveEdge |\r
+ hlptim->Init.Trigger.SampleTime);\r
+ }\r
+ \r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LPTIM peripheral. \r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the LPTIM handle allocation */\r
+ if(hlptim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the LPTIM Peripheral Clock */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* DeInit the low level hardware: CLOCK, NVIC.*/\r
+ HAL_LPTIM_MspDeInit(hlptim);\r
+ \r
+ /* Change the LPTIM state */\r
+ hlptim->State = HAL_LPTIM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hlptim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LPTIM MSP.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes LPTIM MSP.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions \r
+ * @brief Start-Stop operation functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM Start Stop operation functions #####\r
+ ============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Start the PWM mode.\r
+ (+) Stop the PWM mode.\r
+ (+) Start the One pulse mode.\r
+ (+) Stop the One pulse mode.\r
+ (+) Start the Set once mode.\r
+ (+) Stop the Set once mode.\r
+ (+) Start the Encoder mode.\r
+ (+) Stop the Encoder mode.\r
+ (+) Start the Timeout mode.\r
+ (+) Stop the Timeout mode. \r
+ (+) Start the Counter mode.\r
+ (+) Stop the Counter mode.\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Starts the LPTIM PWM generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set PWM mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM PWM generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM PWM generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set PWM mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM PWM generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM One pulse generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set one pulse mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM One pulse generation.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM One pulse generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Reset WAVE bit to set one pulse mode */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM One pulse generation in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ }\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM in Set once mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set WAVE bit to enable the set once mode */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM Set once mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the LPTIM Set once mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Pulse : Specifies the compare value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Pulse));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set WAVE bit to enable the set once mode */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Compare write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then enable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Enable external trigger interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the pulse value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_SINGLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the LPTIM Set once mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+\r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Compare write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* If external trigger source is used, then disable external trigger interrupt */\r
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)\r
+ {\r
+ /* Disable external trigger interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r
+ } \r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Encoder interface.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+\r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+\r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+\r
+ /* Clear CKPOL bits */\r
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r
+\r
+ /* Set Input polarity */\r
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;\r
+\r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Set ENC bit to enable the encoder interface */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+\r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+\r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Encoder interface.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset ENC bit to disable the encoder interface */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Encoder interface in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ uint32_t tmpcfgr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r
+ assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r
+ assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r
+\r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+\r
+ /* Configure edge sensitivity for encoder mode */\r
+ /* Get the LPTIMx CFGR value */\r
+ tmpcfgr = hlptim->Instance->CFGR;\r
+\r
+ /* Clear CKPOL bits */\r
+ tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r
+\r
+ /* Set Input polarity */\r
+ tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;\r
+\r
+ /* Write to LPTIMx CFGR */\r
+ hlptim->Instance->CFGR = tmpcfgr;\r
+\r
+ /* Set ENC bit to enable the encoder interface */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r
+\r
+ /* Enable "switch to down direction" interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);\r
+\r
+ /* Enable "switch to up direction" interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); \r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+\r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+\r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+\r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Encoder interface in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset ENC bit to disable the encoder interface */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r
+ \r
+ /* Disable "switch to down direction" interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);\r
+ \r
+ /* Disable "switch to up direction" interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); \r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Timeout function. The first trigger event will start the\r
+ * timer, any successive trigger event will reset the counter and\r
+ * the timer restarts.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Timeout : Specifies the TimeOut value to rest the counter.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Timeout));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the Timeout value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Timeout function.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Timeout function in interrupt mode. The first trigger \r
+ * event will start the timer, any successive trigger event will reset\r
+ * the counter and the timer restarts.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @param Timeout : Specifies the TimeOut value to rest the counter.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ assert_param(IS_LPTIM_PULSE(Timeout));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Set TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Enable Compare match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Load the Timeout value in the compare register */\r
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Timeout function in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Reset TIMOUT bit to enable the timeout function */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r
+ \r
+ /* Disable Compare match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Counter mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r
+ {\r
+ /* Check if clock is prescaled */\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r
+ /* Set clock prescaler to 0 */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Counter mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the Counter mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @param Period : Specifies the Autoreload value.\r
+ * This parameter must be a value between 0x0000 and 0xFFFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ assert_param(IS_LPTIM_PERIOD(Period));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r
+ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r
+ {\r
+ /* Check if clock is prescaled */\r
+ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r
+ /* Set clock prescaler to 0 */\r
+ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r
+ }\r
+ \r
+ /* Enable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Enable Autoreload match interrupt */\r
+ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_LPTIM_ENABLE(hlptim);\r
+ \r
+ /* Load the period value in the autoreload register */\r
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r
+ \r
+ /* Start timer in continuous mode */\r
+ __HAL_LPTIM_START_CONTINUOUS(hlptim);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the Counter mode in interrupt mode.\r
+ * @param hlptim : LPTIM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ /* Set the LPTIM state */\r
+ hlptim->State= HAL_LPTIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_LPTIM_DISABLE(hlptim);\r
+ \r
+ /* Disable Autoreload write complete interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r
+ \r
+ /* Disable Autoreload match interrupt */\r
+ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r
+ \r
+ /* Change the TIM state*/\r
+ hlptim->State= HAL_LPTIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group3 LPTIM Read operation functions \r
+ * @brief Read operation functions.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM Read operation functions #####\r
+ ============================================================================== \r
+[..] This section provides LPTIM Reading functions.\r
+ (+) Read the counter value.\r
+ (+) Read the period (Auto-reload) value.\r
+ (+) Read the pulse (Compare)value.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function returns the current counter value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Counter value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->CNT);\r
+}\r
+\r
+/**\r
+ * @brief This function return the current Autoreload (Period) value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Autoreload value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->ARR);\r
+}\r
+\r
+/**\r
+ * @brief This function return the current Compare (Pulse) value.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval Compare value.\r
+ */\r
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r
+ \r
+ return (hlptim->Instance->CMP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup LPTIM_Group4 LPTIM IRQ handler \r
+ * @brief LPTIM IRQ handler.\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### LPTIM IRQ handler #####\r
+ ============================================================================== \r
+[..] This section provides LPTIM IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles LPTIM interrupt request.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval None\r
+ */\r
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* Compare match interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)\r
+ {\r
+ /* Clear Compare match flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);\r
+ /* Compare match Callback */\r
+ HAL_LPTIM_CompareMatchCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Autoreload match interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)\r
+ {\r
+ /* Clear Autoreload match flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);\r
+ /* Autoreload match Callback */\r
+ HAL_LPTIM_AutoReloadMatchCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Trigger detected interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)\r
+ {\r
+ /* Clear Trigger detected flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);\r
+ /* Trigger detected callback */\r
+ HAL_LPTIM_TriggerCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Compare write interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)\r
+ {\r
+ /* Clear Compare write flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);\r
+ /* Compare write Callback */\r
+ HAL_LPTIM_CompareWriteCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Autoreload write interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)\r
+ {\r
+ /* Clear Autoreload write flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);\r
+ /* Autoreload write Callback */\r
+ HAL_LPTIM_AutoReloadWriteCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Direction counter changed from Down to Up interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)\r
+ {\r
+ /* Clear Direction counter changed from Down to Up flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);\r
+ /* Direction counter changed from Down to Up Callback */\r
+ HAL_LPTIM_DirectionUpCallback(hlptim); \r
+ }\r
+ }\r
+ \r
+ /* Direction counter changed from Up to Down interrupt */\r
+ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)\r
+ {\r
+ if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)\r
+ {\r
+ /* Clear Direction counter changed from Up to Down flag */\r
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);\r
+ /* Direction counter changed from Up to Down Callback */\r
+ HAL_LPTIM_DirectionDownCallback(hlptim); \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Compare match callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_CompareMatchCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Autoreload match callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Trigger detected callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_TriggerCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Compare write callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_CompareWriteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Autoreload write callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Direction counter changed from Down to Up callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_DirectionUpCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Direction counter changed from Up to Down callback in non blocking mode \r
+ * @param hlptim : LPTIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LPTIM_DirectionDownCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPTIM_Group5 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the LPTIM state.\r
+ * @param hlptim: LPTIM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)\r
+{\r
+ return hlptim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_ltdc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief LTDC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the LTDC peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Program the required configuration through the following parameters: \r
+ the LTDC timing, the horizontal and vertical polarity, \r
+ the pixel clock polarity, Data Enable polarity and the LTDC background color value \r
+ using HAL_LTDC_Init() function\r
+\r
+ (#) Program the required configuration through the following parameters: \r
+ the pixel format, the blending factors, input alpha value, the window size \r
+ and the image size using HAL_LTDC_ConfigLayer() function for foreground\r
+ or/and background layer. \r
+ \r
+ (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and \r
+ HAL_LTDC_EnableCLUT functions.\r
+ \r
+ (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). \r
+\r
+ (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()\r
+ and HAL_LTDC_EnableColorKeying functions.\r
+\r
+ (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()\r
+ function\r
+\r
+ (#) If needed, reconfigure and change the pixel format value, the alpha value\r
+ value, the window size, the window position and the layer start address \r
+ for foreground or/and background layer using respectively the following \r
+ functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),\r
+ HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.\r
+ \r
+ (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() \r
+\r
+ *** LTDC HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in LTDC HAL driver.\r
+ \r
+ (+) __HAL_LTDC_ENABLE: Enable the LTDC.\r
+ (+) __HAL_LTDC_DISABLE: Disable the LTDC.\r
+ (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.\r
+ (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.\r
+ (+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration.\r
+ (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.\r
+ (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.\r
+ (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. \r
+ (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.\r
+ (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.\r
+ \r
+ [..] \r
+ (@) You can refer to the LTDC HAL driver header file for more useful macros\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup LTDC LTDC\r
+ * @brief LTDC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/ \r
+/* Private function prototypes -----------------------------------------------*/\r
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the LTDC\r
+ (+) De-initialize the LTDC \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the LTDC according to the specified\r
+ * parameters in the LTDC_InitTypeDef and create the associated handle.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ uint32_t tmp = 0, tmp1 = 0;\r
+\r
+ /* Check the LTDC peripheral state */\r
+ if(hltdc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));\r
+ assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));\r
+ assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));\r
+ assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));\r
+ assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));\r
+ assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));\r
+ assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));\r
+ assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));\r
+ assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));\r
+ assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));\r
+ assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));\r
+ assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));\r
+ assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));\r
+\r
+ if(hltdc->State == HAL_LTDC_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_LTDC_MspInit(hltdc);\r
+ }\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Configures the HS, VS, DE and PC polarity */\r
+ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);\r
+ hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \\r
+ hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);\r
+\r
+ /* Sets Synchronization size */\r
+ hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);\r
+ tmp = (hltdc->Init.HorizontalSync << 16);\r
+ hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);\r
+\r
+ /* Sets Accumulated Back porch */\r
+ hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);\r
+ tmp = (hltdc->Init.AccumulatedHBP << 16);\r
+ hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);\r
+\r
+ /* Sets Accumulated Active Width */\r
+ hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);\r
+ tmp = (hltdc->Init.AccumulatedActiveW << 16);\r
+ hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);\r
+\r
+ /* Sets Total Width */\r
+ hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);\r
+ tmp = (hltdc->Init.TotalWidth << 16);\r
+ hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);\r
+\r
+ /* Sets the background color value */\r
+ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);\r
+ tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);\r
+ hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);\r
+ hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);\r
+\r
+ /* Enable the transfer Error interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);\r
+\r
+ /* Enable the FIFO underrun interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);\r
+\r
+ /* Enable LTDC by setting LTDCEN bit */\r
+ __HAL_LTDC_ENABLE(hltdc);\r
+\r
+ /* Initialize the error code */\r
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; \r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the LTDC peripheral registers to their default reset\r
+ * values.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* DeInit the low level hardware */\r
+ HAL_LTDC_MspDeInit(hltdc); \r
+\r
+ /* Initialize the error code */\r
+ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;\r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LTDC MSP.\r
+ * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LTDC MSP.\r
+ * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..] This section provides function allowing to:\r
+ (+) Handle LTDC interrupt request\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Handles LTDC interrupt request.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC. \r
+ * @retval HAL status\r
+ */\r
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer Error interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);\r
+\r
+ /* Clear the transfer error flag */\r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);\r
+\r
+ /* Update error code */\r
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ /* Transfer error Callback */\r
+ HAL_LTDC_ErrorCallback(hltdc);\r
+ }\r
+ }\r
+ /* FIFO underrun Interrupt management ***************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)\r
+ {\r
+ /* Disable the FIFO underrun interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);\r
+\r
+ /* Clear the FIFO underrun flag */\r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);\r
+\r
+ /* Update error code */\r
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+ \r
+ /* Transfer error Callback */\r
+ HAL_LTDC_ErrorCallback(hltdc);\r
+ }\r
+ }\r
+ /* Line Interrupt management ************************************************/\r
+ if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)\r
+ {\r
+ if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)\r
+ {\r
+ /* Disable the Line interrupt */\r
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);\r
+\r
+ /* Clear the Line interrupt flag */ \r
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);\r
+\r
+ /* Change LTDC state */\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ /* Line interrupt Callback */\r
+ HAL_LTDC_LineEvenCallback(hltdc);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Error LTDC callback.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Line Event callback.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_LTDC_LineEvenCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the LTDC foreground or/and background parameters.\r
+ (+) Set the active layer.\r
+ (+) Configure the color keying.\r
+ (+) Configure the C-LUT.\r
+ (+) Enable / Disable the color keying.\r
+ (+) Enable / Disable the C-LUT.\r
+ (+) Update the layer position.\r
+ (+) Update the layer size.\r
+ (+) Update pixel format on the fly. \r
+ (+) Update transparency on the fly.\r
+ (+) Update address on the fly.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the LTDC Layer according to the specified\r
+ * parameters in the LTDC_InitTypeDef and create the associated handle.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains\r
+ * the configuration information for the Layer.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+ \r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r
+ assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r
+\r
+ /* Copy new layer configuration into handle structure */\r
+ hltdc->LayerCfg[LayerIdx] = *pLayerCfg; \r
+\r
+ /* Configure the LTDC Layer */ \r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Initialize the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param RGBValue: the color key value\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Configures the default color values */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Load the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pCLUT: pointer to the color lookup table address.\r
+ * @param CLUTSize: the color lookup table size. \r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t counter = 0;\r
+ uint32_t pcounter = 0;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx)); \r
+\r
+ for(counter = 0; (counter < CLUTSize); counter++)\r
+ {\r
+ if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)\r
+ {\r
+ tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r
+ }\r
+ else\r
+ { \r
+ tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r
+ }\r
+ pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);\r
+ pCLUT = (uint32_t *)pcounter;\r
+\r
+ /* Specifies the C-LUT address and RGB value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;\r
+ }\r
+ \r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Enable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Disable the color keying.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color keying by setting COLKEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the color lookup table.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r
+{\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Disable LTDC color lookup table by setting CLUTEN bit */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables Dither.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Enable Dither by setting DTEN bit */\r
+ LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables Dither.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Disable Dither by setting DTEN bit */\r
+ LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window size.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param XSize: LTDC Pixel per line\r
+ * @param YSize: LTDC Line number\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY; \r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters (Layers parameters)*/\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+ assert_param(IS_LTDC_CFBLL(XSize));\r
+ assert_param(IS_LTDC_CFBLNBR(YSize));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = 0;\r
+ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r
+\r
+ /* update vertical start/stop */ \r
+ pLayerCfg->WindowY0 = 0;\r
+ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r
+\r
+ /* Reconfigures the color frame buffer pitch in byte */\r
+ pLayerCfg->ImageWidth = XSize;\r
+\r
+ /* Reconfigures the frame buffer line number */\r
+ pLayerCfg->ImageHeight = YSize;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the LTDC window position.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param X0: LTDC window X offset\r
+ * @param Y0: LTDC window Y offset\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r
+ assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r
+ assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r
+ assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r
+\r
+ /* update horizontal start/stop */\r
+ pLayerCfg->WindowX0 = X0;\r
+ pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r
+\r
+ /* update vertical start/stop */\r
+ pLayerCfg->WindowY0 = Y0;\r
+ pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the pixel format.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Pixelformat: new pixel format value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; \r
+\r
+ /* Reconfigure the pixel format */\r
+ pLayerCfg->PixelFormat = Pixelformat;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); \r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reconfigure the layer alpha value.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Alpha: new alpha value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_ALPHA(Alpha));\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Alpha value */\r
+ pLayerCfg->Alpha = Alpha;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Reconfigure the frame buffer Address.\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Address: new address value.\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values:\r
+ * 0 or 1.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r
+{\r
+ LTDC_LayerCfgTypeDef *pLayerCfg;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LAYER(LayerIdx));\r
+\r
+ /* Get layer configuration from handle structure */\r
+ pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r
+\r
+ /* Reconfigure the Address */\r
+ pLayerCfg->FBStartAdress = Address;\r
+\r
+ /* Set LTDC parameters */\r
+ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r
+\r
+ /* Sets the Reload type */\r
+ hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Define the position of the line interrupt .\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param Line: Line Interrupt Position.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)\r
+{\r
+ /* Process locked */\r
+ __HAL_LOCK(hltdc);\r
+\r
+ /* Change LTDC peripheral state */\r
+ hltdc->State = HAL_LTDC_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_LTDC_LIPOS(Line));\r
+\r
+ /* Enable the Line interrupt */\r
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);\r
+\r
+ /* Sets the Line Interrupt position */\r
+ LTDC->LIPCR = (uint32_t)Line;\r
+\r
+ /* Change the LTDC state*/\r
+ hltdc->State = HAL_LTDC_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hltdc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions\r
+ * @brief Peripheral State and Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the LTDC state.\r
+ (+) Get error code. \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Return the LTDC state\r
+ * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @retval HAL state\r
+ */\r
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ return hltdc->State;\r
+}\r
+\r
+/**\r
+* @brief Return the LTDC error code\r
+* @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+* @retval LTDC Error Code\r
+*/\r
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)\r
+{\r
+ return hltdc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configures the LTDC peripheral \r
+ * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains\r
+ * the configuration information for the LTDC.\r
+ * @param pLayerCfg: Pointer LTDC Layer Configuration structure\r
+ * @param LayerIdx: LTDC Layer index.\r
+ * This parameter can be one of the following values: 0 or 1\r
+ * @retval None\r
+ */\r
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t tmp1 = 0;\r
+ uint32_t tmp2 = 0;\r
+\r
+ /* Configures the horizontal start and stop position */\r
+ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);\r
+\r
+ /* Configures the vertical start and stop position */\r
+ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);\r
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); \r
+\r
+ /* Specifies the pixel format */\r
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);\r
+ LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);\r
+\r
+ /* Configures the default color values */\r
+ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);\r
+ tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);\r
+ tmp2 = (pLayerCfg->Alpha0 << 24); \r
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);\r
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); \r
+\r
+ /* Specifies the constant alpha value */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);\r
+\r
+ /* Specifies the blending factors */\r
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);\r
+ LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);\r
+\r
+ /* Configures the color frame buffer start address */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);\r
+\r
+ if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r
+ {\r
+ tmp = 4;\r
+ }\r
+ else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r
+ {\r
+ tmp = 3;\r
+ }\r
+ else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\r
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))\r
+ {\r
+ tmp = 2;\r
+ }\r
+ else\r
+ {\r
+ tmp = 1;\r
+ }\r
+\r
+ /* Configures the color frame buffer pitch in byte */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3));\r
+\r
+ /* Configures the frame buffer line number */\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);\r
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);\r
+\r
+ /* Enable LTDC_Layer by setting LEN bit */ \r
+ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_msp_template.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief HAL MSP module.\r
+ * This file template is located in the HAL folder and should be copied \r
+ * to the user folder.\r
+ * \r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ This file is generated automatically by MicroXplorer and eventually modified \r
+ by the user\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_MSP HAL MSP\r
+ * @brief HAL MSP module.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the Global MSP.\r
+ * @retval None\r
+ */\r
+void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the Global MSP. \r
+ * @retval None\r
+ */\r
+void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the PPP MSP.\r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the PPP MSP. \r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nand.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief NAND HAL module driver.\r
+ * This file provides a generic firmware to drive NAND memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control NAND flash memories. It uses the FMC/FSMC layer functions to interface \r
+ with NAND devices. This driver is used as follows:\r
+ \r
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() \r
+ with control and timing parameters for both common and attribute spaces.\r
+ \r
+ (+) Read NAND flash memory maker and device IDs using the function\r
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef \r
+ structure declared by the function caller. \r
+ \r
+ (+) Access NAND flash memory by read/write operations using the functions\r
+ HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()\r
+ to read/write page(s)/spare area(s). These functions use specific device \r
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef \r
+ structure. The read/write address information is contained by the Nand_Address_Typedef\r
+ structure passed as parameter.\r
+ \r
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().\r
+ \r
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().\r
+ The erase block address information is contained in the Nand_Address_Typedef \r
+ structure passed as parameter.\r
+ \r
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().\r
+ \r
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/\r
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction\r
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code. \r
+ \r
+ (+) You can monitor the NAND device HAL state by calling the function\r
+ HAL_NAND_GetState() \r
+\r
+ [..]\r
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.\r
+ If a NAND flash device contains different operations and/or implementations, \r
+ it should be implemented separately.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
+/** @defgroup NAND NAND \r
+ * @brief NAND HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private Constants ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup NAND_Exported_Functions NAND Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NAND Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the NAND memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Perform NAND memory Initialization sequence\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param ComSpace_Timing: pointer to Common space timing structure\r
+ * @param AttSpace_Timing: pointer to Attribute space timing structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)\r
+{\r
+ /* Check the NAND handle state */\r
+ if(hnand == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if(hnand->State == HAL_NAND_STATE_RESET)\r
+ {\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NAND_MspInit(hnand);\r
+ } \r
+\r
+ /* Initialize NAND control Interface */\r
+ FMC_NAND_Init(hnand->Instance, &(hnand->Init));\r
+ \r
+ /* Initialize NAND common space timing Interface */ \r
+ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);\r
+ \r
+ /* Initialize NAND attribute space timing Interface */ \r
+ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);\r
+ \r
+ /* Enable the NAND device */\r
+ __FMC_NAND_ENABLE(hnand->Instance);\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform NAND memory De-Initialization sequence\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) \r
+{\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NAND_MspDeInit(hnand);\r
+\r
+ /* Configure the NAND registers with their reset values */\r
+ FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);\r
+\r
+ /* Reset the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hnand);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NAND MSP Init\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NAND MSP DeInit\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+\r
+/**\r
+ * @brief This function handles NAND device interrupt request.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+*/\r
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Check NAND interrupt Rising edge flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Rising edge pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);\r
+ }\r
+ \r
+ /* Check NAND interrupt Level flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Level pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);\r
+ }\r
+\r
+ /* Check NAND interrupt Falling edge flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt Falling edge pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);\r
+ }\r
+ \r
+ /* Check NAND interrupt FIFO empty flag */\r
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))\r
+ {\r
+ /* NAND interrupt callback*/\r
+ HAL_NAND_ITCallback(hnand);\r
+ \r
+ /* Clear NAND interrupt FIFO empty pending bit */\r
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);\r
+ } \r
+\r
+}\r
+\r
+/**\r
+ * @brief NAND interrupt feature callback\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NAND_ITCallback could be implemented in the user file\r
+ */\r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NAND Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the NAND \r
+ memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Read the NAND memory electronic signature\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pNAND_ID: NAND ID structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)\r
+{\r
+ __IO uint32_t data = 0;\r
+ uint32_t deviceAddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Send Read ID command sequence */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r
+\r
+ /* Read the electronic signature from NAND flash */ \r
+ data = *(__IO uint32_t *)deviceAddress;\r
+ \r
+ /* Return the data read */\r
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);\r
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);\r
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);\r
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NAND memory reset\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)\r
+{\r
+ uint32_t deviceAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand);\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Identify the device address */ \r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Send NAND reset command */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;\r
+ \r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+ \r
+/**\r
+ * @brief Read Page(s) from NAND memory block \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to destination read buffer\r
+ * @param NumPageToRead : number of pages to read from block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)\r
+{ \r
+ __IO uint32_t index = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+\r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) read loop */ \r
+ while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);\r
+ \r
+ /* Send read page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; \r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r
+ \r
+ /* Get Data into Buffer */ \r
+ for(index = 0; index < size; index++)\r
+ {\r
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r
+ }\r
+ \r
+ /* Increment read pages number */\r
+ numPagesRead++;\r
+ \r
+ /* Decrement pages to read */\r
+ NumPageToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ \r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Write Page(s) to NAND memory block \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumPageToWrite : number of pages to write to block \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r
+ \r
+ /* Page(s) write loop */\r
+ while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);\r
+ \r
+ /* Send write page command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(index = 0; index < size; index++)\r
+ {\r
+ *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ } \r
+ } \r
+ \r
+ /* Increment written pages number */\r
+ numPagesWritten++;\r
+ \r
+ /* Decrement pages to write */\r
+ NumPageToWrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r
+ }\r
+ \r
+ /* Update the NAND controller state */ \r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read Spare area(s) from NAND memory \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer: pointer to source buffer to write \r
+ * @param NumSpareAreaToRead: Number of spare area to read \r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)\r
+{\r
+ __IO uint32_t index = 0; \r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) read loop */ \r
+ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ \r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); \r
+\r
+ /* Send read spare area command sequence */ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ } \r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; \r
+ \r
+ /* Get Data into Buffer */\r
+ for(index = 0; index < size; index++)\r
+ {\r
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r
+ }\r
+ \r
+ /* Increment read spare areas number */\r
+ numSpareAreaRead++;\r
+ \r
+ /* Decrement spare areas to read */\r
+ NumSpareAreaToRead--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));\r
+ }\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Write Spare area(s) to NAND memory \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @param pBuffer : pointer to source buffer to write \r
+ * @param NumSpareAreaTowrite : number of spare areas to write to block\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)\r
+{\r
+ __IO uint32_t index = 0;\r
+ uint32_t tickstart = 0;\r
+ uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand); \r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ deviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the FMC_NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* NAND raw address calculation */\r
+ nandAddress = ARRAY_ADDRESS(pAddress, hnand); \r
+ \r
+ /* Spare area(s) write loop */\r
+ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r
+ { \r
+ /* update the buffer size */\r
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);\r
+\r
+ /* Send write Spare area command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r
+\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); \r
+ __DSB();\r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r
+ __DSB();\r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(index = 0; index < size; index++)\r
+ {\r
+ *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r
+ __DSB();\r
+ }\r
+ \r
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r
+ __DSB();\r
+ \r
+ /* Read status until NAND is ready */\r
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r
+ {\r
+ return HAL_TIMEOUT; \r
+ }\r
+ }\r
+\r
+ /* Increment written spare areas number */\r
+ numSpareAreaWritten++;\r
+ \r
+ /* Decrement spare areas to write */\r
+ NumSpareAreaTowrite--;\r
+ \r
+ /* Increment the NAND address */\r
+ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));\r
+ }\r
+\r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief NAND memory Block erase \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress : pointer to NAND address structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r
+{\r
+ uint32_t DeviceAddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnand);\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Identify the device address */\r
+ DeviceAddress = NAND_DEVICE;\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Send Erase block command sequence */\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;\r
+\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ \r
+ /* for 512 and 1 GB devices, 4th cycle is required */ \r
+ if(hnand->Info.BlockNbr >= 1024)\r
+ {\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r
+ __DSB();\r
+ } \r
+ \r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; \r
+ __DSB();\r
+ \r
+ /* Update the NAND controller state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnand); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief NAND memory read status \r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval NAND status\r
+ */\r
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)\r
+{\r
+ uint32_t data = 0;\r
+ uint32_t DeviceAddress = 0;\r
+ \r
+ /* Identify the device address */\r
+ DeviceAddress = NAND_DEVICE;\r
+\r
+ /* Send Read status operation command */\r
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;\r
+ \r
+ /* Read status register data */\r
+ data = *(__IO uint8_t *)DeviceAddress;\r
+\r
+ /* Return the status */\r
+ if((data & NAND_ERROR) == NAND_ERROR)\r
+ {\r
+ return NAND_ERROR;\r
+ } \r
+ else if((data & NAND_READY) == NAND_READY)\r
+ {\r
+ return NAND_READY;\r
+ }\r
+\r
+ return NAND_BUSY; \r
+}\r
+\r
+/**\r
+ * @brief Increment the NAND memory address\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param pAddress: pointer to NAND address structure\r
+ * @retval The new status of the increment address operation. It can be:\r
+ * - NAND_VALID_ADDRESS: When the new address is valid address\r
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address\r
+ */\r
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r
+{\r
+ uint32_t status = NAND_VALID_ADDRESS;\r
+ \r
+ /* Increment page address */\r
+ pAddress->Page++;\r
+\r
+ /* Check NAND address is valid */\r
+ if(pAddress->Page == hnand->Info.BlockSize)\r
+ {\r
+ pAddress->Page = 0;\r
+ pAddress->Block++;\r
+ \r
+ if(pAddress->Block == hnand->Info.ZoneSize)\r
+ {\r
+ pAddress->Block = 0;\r
+ pAddress->Zone++;\r
+\r
+ if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))\r
+ {\r
+ status = NAND_INVALID_ADDRESS;\r
+ }\r
+ }\r
+ } \r
+ \r
+ return (status);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NAND Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the NAND interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ \r
+/**\r
+ * @brief Enables dynamically NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)\r
+{\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Enable ECC feature */\r
+ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) \r
+{\r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY;\r
+ \r
+ /* Disable ECC feature */\r
+ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically NAND ECC feature.\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @param ECCval: pointer to ECC value \r
+ * @param Timeout: maximum timeout to wait \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the NAND controller state */\r
+ if(hnand->State == HAL_NAND_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_BUSY; \r
+ \r
+ /* Get NAND ECC value */\r
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);\r
+ \r
+ /* Update the NAND state */\r
+ hnand->State = HAL_NAND_STATE_READY;\r
+\r
+ return status; \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+ \r
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NAND State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the NAND controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the NAND state\r
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains\r
+ * the configuration information for NAND module.\r
+ * @retval HAL state\r
+ */\r
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)\r
+{\r
+ return hnand->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_nor.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief NOR HAL module driver.\r
+ * This file provides a generic firmware to drive NOR memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control NOR flash memories. It uses the FMC layer functions to interface \r
+ with NOR devices. This driver is used as follows:\r
+ \r
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() \r
+ with control and timing parameters for both normal and extended mode.\r
+ \r
+ (+) Read NOR flash memory manufacturer code and device IDs using the function\r
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef \r
+ structure declared by the function caller. \r
+ \r
+ (+) Access NOR flash memory by read/write data unit operations using the functions\r
+ HAL_NOR_Read(), HAL_NOR_Program().\r
+ \r
+ (+) Perform NOR flash erase block/chip operations using the functions \r
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().\r
+ \r
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function\r
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef\r
+ structure declared by the function caller.\r
+ \r
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/\r
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation \r
+ \r
+ (+) You can monitor the NOR device HAL state by calling the function\r
+ HAL_NOR_GetState() \r
+ [..]\r
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.\r
+ If a NOR flash device contains different operations and/or implementations, \r
+ it should be implemented separately.\r
+\r
+ *** NOR HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in NOR HAL driver.\r
+ \r
+ (+) NOR_WRITE : NOR memory write data to specified address\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup NOR NOR\r
+ * @brief NOR driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+#if defined(STM32F756xx) || defined(STM32F746xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ \r
+/** @defgroup NOR_Private_Defines NOR Private Defines\r
+ * @{\r
+ */\r
+\r
+/* Constants to define address to set to write a command */\r
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055\r
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA\r
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555\r
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA\r
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555\r
+\r
+/* Constants to define data to program a command */\r
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0\r
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA\r
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055\r
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090\r
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA\r
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055\r
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010\r
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098\r
+\r
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25\r
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29\r
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30\r
+\r
+/* Mask on NOR STATUS REGISTER */\r
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020\r
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup NOR_Exported_Functions NOR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NOR Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the NOR memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Perform the NOR memory Initialization sequence\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Timing: pointer to NOR control timing structure \r
+ * @param ExtTiming: pointer to NOR extended mode timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r
+{\r
+ /* Check the NOR handle parameter */\r
+ if(hnor == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hnor->State == HAL_NOR_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hnor->Lock = HAL_UNLOCKED;\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_NOR_MspInit(hnor);\r
+ }\r
+ \r
+ /* Initialize NOR control Interface */\r
+ FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));\r
+\r
+ /* Initialize NOR timing Interface */\r
+ FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); \r
+\r
+ /* Initialize NOR extended mode timing Interface */\r
+ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);\r
+\r
+ /* Enable the NORSRAM device */\r
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform NOR memory De-Initialization sequence\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) \r
+{\r
+ /* De-Initialize the low level hardware (MSP) */\r
+ HAL_NOR_MspDeInit(hnor);\r
+ \r
+ /* Configure the NOR registers with their reset values */\r
+ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hnor);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief NOR MSP Init\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NOR MSP DeInit\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief NOR MSP Wait for Ready/Busy signal\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Timeout: Maximum timeout value\r
+ * @retval None\r
+ */\r
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_NOR_MspWait could be implemented in the user file\r
+ */ \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### NOR Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the NOR memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Read NOR flash IDs\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pNOR_ID : pointer to NOR ID structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read ID command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);\r
+\r
+ /* Read the NOR IDs */\r
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);\r
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);\r
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);\r
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the NOR memory to Read mode.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)\r
+{\r
+ uint32_t deviceaddress = 0; \r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read data from NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pAddress: pointer to Device address\r
+ * @param pData : pointer to read data \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r
+\r
+ /* Read the data */\r
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Program data to NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pAddress: Device address\r
+ * @param pData : pointer to the data to write \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send program data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);\r
+\r
+ /* Write the data */\r
+ NOR_WRITE(pAddress, *pData);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a half-word buffer from the NOR memory.\r
+ * @param hnor: pointer to the NOR handle\r
+ * @param uwAddress: NOR memory internal address to read from.\r
+ * @param pData: pointer to the buffer that receives the data read from the \r
+ * NOR memory.\r
+ * @param uwBufferSize : number of Half word to read.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read data command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r
+ \r
+ /* Read buffer */\r
+ while( uwBufferSize > 0) \r
+ {\r
+ *pData++ = *(__IO uint16_t *)uwAddress;\r
+ uwAddress += 2;\r
+ uwBufferSize--;\r
+ } \r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a half-word buffer to the NOR memory. This function must be used \r
+ only with S29GL128P NOR memory. \r
+ * @param hnor: pointer to the NOR handle\r
+ * @param uwAddress: NOR memory internal start write address \r
+ * @param pData: pointer to source data buffer. \r
+ * @param uwBufferSize: Size of the buffer to write\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r
+{\r
+ uint16_t * p_currentaddress = (uint16_t *)NULL;\r
+ uint16_t * p_endaddress = (uint16_t *)NULL;\r
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Initialize variables */\r
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));\r
+ p_endaddress = p_currentaddress + (uwBufferSize-1);\r
+ lastloadedaddress = (uint32_t)(uwAddress);\r
+\r
+ /* Issue unlock command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r
+\r
+ /* Write Buffer Load Command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); \r
+\r
+ /* Load Data into NOR Buffer */\r
+ while(p_currentaddress <= p_endaddress)\r
+ {\r
+ /* Store last loaded address & data value (for polling) */\r
+ lastloadedaddress = (uint32_t)p_currentaddress;\r
+ \r
+ NOR_WRITE(p_currentaddress, *pData++);\r
+ \r
+ p_currentaddress ++; \r
+ }\r
+\r
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);\r
+ \r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Erase the specified block of the NOR memory \r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param BlockAddress : Block to erase address \r
+ * @param Address: Device address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ }\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send block erase command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);\r
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);\r
+\r
+ /* Check the NOR memory status and update the controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Erase the entire NOR chip.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param Address : Device address \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ }\r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY; \r
+ \r
+ /* Send NOR chip erase command sequence */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); \r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);\r
+ \r
+ /* Check the NOR memory status and update the controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Read NOR flash CFI IDs\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @param pNOR_CFI : pointer to NOR CFI IDs structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)\r
+{\r
+ uint32_t deviceaddress = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+ \r
+ /* Check the NOR controller state */\r
+ if(hnor->State == HAL_NOR_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Select the NOR device address */\r
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS1;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS2;\r
+ }\r
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS3;\r
+ }\r
+ else /* FMC_NORSRAM_BANK4 */\r
+ {\r
+ deviceaddress = NOR_MEMORY_ADRESS4;\r
+ } \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Send read CFI query command */\r
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);\r
+\r
+ /* read the NOR CFI information */\r
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);\r
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);\r
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);\r
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);\r
+\r
+ /* Check the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NOR_Exported_Functions_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NOR Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the NOR interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables dynamically NOR write operation.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+\r
+ /* Enable write operation */\r
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically NOR write operation.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hnor);\r
+\r
+ /* Update the SRAM controller state */\r
+ hnor->State = HAL_NOR_STATE_BUSY;\r
+ \r
+ /* Disable write operation */\r
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); \r
+ \r
+ /* Update the NOR controller state */\r
+ hnor->State = HAL_NOR_STATE_PROTECTED;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hnor); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup NOR_Exported_Functions_Group4 State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### NOR State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the NOR controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief return the NOR controller state\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module.\r
+ * @retval NOR controller state\r
+ */\r
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)\r
+{\r
+ return hnor->State;\r
+}\r
+\r
+/**\r
+ * @brief Returns the NOR operation status.\r
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains\r
+ * the configuration information for NOR module. \r
+ * @param Address: Device address\r
+ * @param Timeout: NOR programming Timeout\r
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR\r
+ * or HAL_NOR_STATUS_TIMEOUT\r
+ */\r
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)\r
+{ \r
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;\r
+ uint16_t tmpSR1 = 0, tmpSR2 = 0;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/\r
+ HAL_NOR_MspWait(hnor, Timeout);\r
+ \r
+ /* Get the NOR memory operation status -------------------------------------*/\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ status = HAL_NOR_STATUS_TIMEOUT; \r
+ } \r
+ } \r
+\r
+ /* Read NOR status register (DQ6 and DQ5) */\r
+ tmpSR1 = *(__IO uint16_t *)Address;\r
+ tmpSR2 = *(__IO uint16_t *)Address;\r
+\r
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r
+ {\r
+ return HAL_NOR_STATUS_SUCCESS ;\r
+ }\r
+ \r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r
+ {\r
+ status = HAL_NOR_STATUS_ONGOING;\r
+ }\r
+ \r
+ tmpSR1 = *(__IO uint16_t *)Address;\r
+ tmpSR2 = *(__IO uint16_t *)Address;\r
+\r
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r
+ {\r
+ return HAL_NOR_STATUS_SUCCESS;\r
+ }\r
+ if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r
+ {\r
+ return HAL_NOR_STATUS_ERROR;\r
+ } \r
+ }\r
+\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F756xx || STM32F746xx */\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief PCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The PCD HAL driver can be used as follows:\r
+\r
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:\r
+ PCD_HandleTypeDef hpcd;\r
+ \r
+ (#) Fill parameters of Init structure in HCD handle\r
+ \r
+ (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) \r
+\r
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r
+ (##) Enable the PCD/USB Low Level interface clock using \r
+ (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();\r
+ (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure PCD pin-out\r
+ (##) Configure PCD NVIC interrupt\r
+ \r
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:\r
+ (##) hpcd.pData = pdev;\r
+\r
+ (#)Enable HCD transmission and reception:\r
+ (##) HAL_PCD_Start();\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCD PCD\r
+ * @brief PCD HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PCD_Private_Macros PCD Private Macros\r
+ * @{\r
+ */ \r
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/** @defgroup PCD_Private_Functions PCD Private Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup PCD_Exported_Functions PCD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the PCD according to the specified\r
+ * parameters in the PCD_InitTypeDef and create the associated handle.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ uint32_t i = 0;\r
+ \r
+ /* Check the PCD handle allocation */\r
+ if(hpcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r
+\r
+ hpcd->State = HAL_PCD_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_PCD_MspInit(hpcd);\r
+\r
+ /* Disable the Interrupts */\r
+ __HAL_PCD_DISABLE(hpcd);\r
+ \r
+ /*Init the Core (common init.) */\r
+ USB_CoreInit(hpcd->Instance, hpcd->Init);\r
+ \r
+ /* Force Device Mode*/\r
+ USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);\r
+ \r
+ /* Init endpoints structures */\r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ /* Init ep structure */\r
+ hpcd->IN_ep[i].is_in = 1;\r
+ hpcd->IN_ep[i].num = i;\r
+ hpcd->IN_ep[i].tx_fifo_num = i;\r
+ /* Control until ep is activated */\r
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r
+ hpcd->IN_ep[i].maxpacket = 0;\r
+ hpcd->IN_ep[i].xfer_buff = 0;\r
+ hpcd->IN_ep[i].xfer_len = 0;\r
+ }\r
+ \r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ hpcd->OUT_ep[i].is_in = 0;\r
+ hpcd->OUT_ep[i].num = i;\r
+ hpcd->IN_ep[i].tx_fifo_num = i;\r
+ /* Control until ep is activated */\r
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r
+ hpcd->OUT_ep[i].maxpacket = 0;\r
+ hpcd->OUT_ep[i].xfer_buff = 0;\r
+ hpcd->OUT_ep[i].xfer_len = 0;\r
+ \r
+ hpcd->Instance->DIEPTXF[i] = 0;\r
+ }\r
+ \r
+ /* Init Device */\r
+ USB_DevInit(hpcd->Instance, hpcd->Init);\r
+ \r
+ hpcd->State= HAL_PCD_STATE_READY;\r
+ \r
+ /* Activate LPM */\r
+ if (hpcd->Init.lpm_enable == 1)\r
+ {\r
+ HAL_PCDEx_ActivateLPM(hpcd);\r
+ }\r
+ \r
+ USB_DevDisconnect (hpcd->Instance); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the PCD peripheral \r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* Check the PCD handle allocation */\r
+ if(hpcd == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hpcd->State = HAL_PCD_STATE_BUSY;\r
+ \r
+ /* Stop Device */\r
+ HAL_PCD_Stop(hpcd);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_PCD_MspDeInit(hpcd);\r
+ \r
+ hpcd->State = HAL_PCD_STATE_RESET; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the PCD MSP.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes PCD MSP.\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the PCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Start The USB OTG Device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ __HAL_LOCK(hpcd); \r
+ USB_DevConnect (hpcd->Instance); \r
+ __HAL_PCD_ENABLE(hpcd);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop The USB OTG Device.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r
+{ \r
+ __HAL_LOCK(hpcd); \r
+ __HAL_PCD_DISABLE(hpcd);\r
+ USB_StopDevice(hpcd->Instance);\r
+ USB_DevDisconnect (hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles PCD interrupt request.\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r
+ uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;\r
+ uint32_t fifoemptymsk = 0, temp = 0;\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ /* ensure that we are in device mode */\r
+ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r
+ {\r
+ /* avoid spurious interrupt */\r
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) \r
+ {\r
+ return;\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r
+ {\r
+ /* incorrect mode, acknowledge the interrupt */\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r
+ {\r
+ epnum = 0;\r
+ \r
+ /* Read in the device interrupt bits */\r
+ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r
+ \r
+ while ( ep_intr )\r
+ {\r
+ if (ep_intr & 0x1)\r
+ {\r
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r
+ {\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r
+ \r
+ if(hpcd->Init.dma_enable == 1)\r
+ {\r
+ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; \r
+ }\r
+ \r
+ HAL_PCD_DataOutStageCallback(hpcd, epnum);\r
+ if(hpcd->Init.dma_enable == 1)\r
+ {\r
+ if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))\r
+ {\r
+ /* this is ZLP, so prepare EP0 for next setup */\r
+ USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r
+ } \r
+ }\r
+ }\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r
+ {\r
+ /* Inform the upper layer that a setup packet is available */\r
+ HAL_PCD_SetupStageCallback(hpcd);\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r
+ }\r
+ \r
+ if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r
+ {\r
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r
+ }\r
+ }\r
+ epnum++;\r
+ ep_intr >>= 1;\r
+ }\r
+ }\r
+ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r
+ {\r
+ /* Read in the device interrupt bits */\r
+ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r
+ \r
+ epnum = 0;\r
+ \r
+ while ( ep_intr )\r
+ {\r
+ if (ep_intr & 0x1) /* In ITR */\r
+ {\r
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);\r
+\r
+ if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r
+ {\r
+ fifoemptymsk = 0x1 << epnum;\r
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+ \r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; \r
+ }\r
+ \r
+ HAL_PCD_DataInStageCallback(hpcd, epnum);\r
+\r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ /* this is ZLP, so prepare EP0 for next setup */\r
+ if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))\r
+ {\r
+ /* prepare to rx more setup packets */\r
+ USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r
+ }\r
+ } \r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r
+ }\r
+ if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r
+ {\r
+ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r
+ } \r
+ if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r
+ {\r
+ PCD_WriteEmptyTxFifo(hpcd , epnum);\r
+ }\r
+ }\r
+ epnum++;\r
+ ep_intr >>= 1;\r
+ }\r
+ }\r
+ \r
+ /* Handle Resume Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r
+ {\r
+ /* Clear the Remote Wake-up Signaling */\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r
+ \r
+ if(hpcd->LPM_State == LPM_L1)\r
+ {\r
+ hpcd->LPM_State = LPM_L0;\r
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ HAL_PCD_ResumeCallback(hpcd);\r
+ }\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r
+ }\r
+ \r
+ /* Handle Suspend Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r
+ {\r
+\r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+ {\r
+ \r
+ HAL_PCD_SuspendCallback(hpcd);\r
+ }\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r
+ }\r
+ \r
+ /* Handle LPM Interrupt */ \r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r
+ {\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); \r
+ if( hpcd->LPM_State == LPM_L0)\r
+ {\r
+ hpcd->LPM_State = LPM_L1;\r
+ hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;\r
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r
+ }\r
+ else\r
+ {\r
+ HAL_PCD_SuspendCallback(hpcd);\r
+ }\r
+ }\r
+ \r
+ /* Handle Reset Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r
+ {\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; \r
+ USB_FlushTxFifo(hpcd->Instance , 0 );\r
+ \r
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ USBx_DEVICE->DAINTMSK |= 0x10001;\r
+ \r
+ if(hpcd->Init.use_dedicated_ep1)\r
+ {\r
+ USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); \r
+ USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); \r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);\r
+ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\r
+ }\r
+ \r
+ /* Set Default Address to 0 */\r
+ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r
+ \r
+ /* setup EP0 to receive SETUP packets */\r
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r
+ \r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r
+ }\r
+ \r
+ /* Handle Enumeration done Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r
+ {\r
+ USB_ActivateSetup(hpcd->Instance);\r
+ hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r
+ \r
+ if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)\r
+ {\r
+ hpcd->Init.speed = USB_OTG_SPEED_HIGH;\r
+ hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; \r
+ hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3);\r
+ }\r
+ else\r
+ {\r
+ hpcd->Init.speed = USB_OTG_SPEED_FULL;\r
+ hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; \r
+ hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);\r
+ }\r
+ \r
+ HAL_PCD_ResetCallback(hpcd);\r
+ \r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r
+ }\r
+ \r
+ /* Handle RxQLevel Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r
+ {\r
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ temp = USBx->GRXSTSP;\r
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r
+ \r
+ if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)\r
+ {\r
+ if((temp & USB_OTG_GRXSTSP_BCNT) != 0)\r
+ {\r
+ USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);\r
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ }\r
+ }\r
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)\r
+ {\r
+ USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);\r
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r
+ }\r
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r
+ }\r
+ \r
+ /* Handle SOF Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r
+ {\r
+ HAL_PCD_SOFCallback(hpcd);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r
+ }\r
+ \r
+ /* Handle Incomplete ISO IN Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r
+ {\r
+ HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r
+ } \r
+ \r
+ /* Handle Incomplete ISO OUT Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r
+ {\r
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r
+ } \r
+ \r
+ /* Handle Connection event Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r
+ {\r
+ HAL_PCD_ConnectCallback(hpcd);\r
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r
+ } \r
+ \r
+ /* Handle Disconnection event Interrupt */\r
+ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r
+ {\r
+ temp = hpcd->Instance->GOTGINT;\r
+ \r
+ if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r
+ {\r
+ HAL_PCD_DisconnectCallback(hpcd);\r
+ }\r
+ hpcd->Instance->GOTGINT |= temp;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Data out stage callbacks\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Data IN stage callbacks\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DataInStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+/**\r
+ * @brief Setup stage callback\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SetupStageCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief USB Start Of Frame callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SOFCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief USB Reset callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ResetCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+\r
+/**\r
+ * @brief Suspend event callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_SuspendCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Resume event callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ResumeCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Incomplete ISO OUT callbacks\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Incomplete ISO IN callbacks\r
+ * @param hpcd: PCD handle\r
+ * @param epnum: endpoint number \r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Connection event callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_ConnectCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Disconnection event callbacks\r
+ * @param hpcd: PCD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PCD_DisconnectCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the PCD data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Connect the USB device\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_DevConnect(hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disconnect the USB device\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_DevDisconnect(hpcd->Instance);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set the USB Device address \r
+ * @param hpcd: PCD handle\r
+ * @param address: new device address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ USB_SetDevAddress(hpcd->Instance, address);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Open and configure an endpoint\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param ep_mps: endpoint max packet size\r
+ * @param ep_type: endpoint type \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r
+{\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ }\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ ep->is_in = (0x80 & ep_addr) != 0;\r
+ ep->maxpacket = ep_mps;\r
+ ep->type = ep_type;\r
+ if (ep->is_in)\r
+ {\r
+ /* Assign a Tx FIFO */\r
+ ep->tx_fifo_num = ep->num;\r
+ }\r
+ /* Set initial data PID. */\r
+ if (ep_type == EP_TYPE_BULK )\r
+ {\r
+ ep->data_pid_start = 0;\r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_ActivateEndpoint(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ return ret;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Deactivate an endpoint\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{ \r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ }\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ ep->is_in = (0x80 & ep_addr) != 0;\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_DeactivateEndpoint(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive an amount of data \r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param pBuf: pointer to the reception buffer \r
+ * @param len: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r
+ \r
+ /*setup and start the Xfer */\r
+ ep->xfer_buff = pBuf; \r
+ ep->xfer_len = len;\r
+ ep->xfer_count = 0;\r
+ ep->is_in = 0;\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ ep->dma_addr = (uint32_t)pBuf; \r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x7F) == 0 )\r
+ {\r
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ else\r
+ {\r
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get Received Data Size\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval Data Size\r
+ */\r
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;\r
+}\r
+/**\r
+ * @brief Send an amount of data \r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @param pBuf: pointer to the transmission buffer \r
+ * @param len: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ \r
+ /*setup and start the Xfer */\r
+ ep->xfer_buff = pBuf; \r
+ ep->xfer_len = len;\r
+ ep->xfer_count = 0;\r
+ ep->is_in = 1;\r
+ ep->num = ep_addr & 0x7F;\r
+ \r
+ if (hpcd->Init.dma_enable == 1)\r
+ {\r
+ ep->dma_addr = (uint32_t)pBuf; \r
+ }\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x7F) == 0 )\r
+ {\r
+ USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ else\r
+ {\r
+ USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r
+ }\r
+ \r
+ __HAL_UNLOCK(hpcd);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set a STALL condition over an endpoint\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((0x80 & ep_addr) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr];\r
+ }\r
+ \r
+ ep->is_stall = 1;\r
+ ep->num = ep_addr & 0x7F;\r
+ ep->is_in = ((ep_addr & 0x80) == 0x80);\r
+ \r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_EPSetStall(hpcd->Instance , ep);\r
+ if((ep_addr & 0x7F) == 0)\r
+ {\r
+ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r
+ }\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Clear a STALL condition over in an endpoint\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ USB_OTG_EPTypeDef *ep;\r
+ \r
+ if ((0x80 & ep_addr) == 0x80)\r
+ {\r
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];\r
+ }\r
+ else\r
+ {\r
+ ep = &hpcd->OUT_ep[ep_addr];\r
+ }\r
+ \r
+ ep->is_stall = 0;\r
+ ep->num = ep_addr & 0x7F;\r
+ ep->is_in = ((ep_addr & 0x80) == 0x80);\r
+ \r
+ __HAL_LOCK(hpcd); \r
+ USB_EPClearStall(hpcd->Instance , ep);\r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Flush an endpoint\r
+ * @param hpcd: PCD handle\r
+ * @param ep_addr: endpoint address\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r
+{\r
+ __HAL_LOCK(hpcd); \r
+ \r
+ if ((ep_addr & 0x80) == 0x80)\r
+ {\r
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);\r
+ }\r
+ else\r
+ {\r
+ USB_FlushRxFifo(hpcd->Instance);\r
+ }\r
+ \r
+ __HAL_UNLOCK(hpcd); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+ {\r
+ /* Activate Remote wake-up signaling */\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ /* De-activate Remote wake-up signaling */\r
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the PCD state\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL state\r
+ */\r
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r
+{\r
+ return hpcd->State;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup PCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DCD_WriteEmptyTxFifo\r
+ * check FIFO for the next packet to be loaded\r
+ * @param hpcd: PCD handle\r
+ * @param epnum : endpoint number \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ USB_OTG_EPTypeDef *ep;\r
+ int32_t len = 0;\r
+ uint32_t len32b;\r
+ uint32_t fifoemptymsk = 0;\r
+\r
+ ep = &hpcd->IN_ep[epnum];\r
+ len = ep->xfer_len - ep->xfer_count;\r
+ \r
+ if (len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ }\r
+ \r
+ \r
+ len32b = (len + 3) / 4;\r
+ \r
+ while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&\r
+ ep->xfer_count < ep->xfer_len &&\r
+ ep->xfer_len != 0)\r
+ {\r
+ /* Write the FIFO */\r
+ len = ep->xfer_len - ep->xfer_count;\r
+ \r
+ if (len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ }\r
+ len32b = (len + 3) / 4;\r
+ \r
+ USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); \r
+ \r
+ ep->xfer_buff += len;\r
+ ep->xfer_count += len;\r
+ }\r
+ \r
+ if(len <= 0)\r
+ {\r
+ fifoemptymsk = 0x1 << epnum;\r
+ USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r
+ \r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pcd_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief PCD HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Extended features functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCDEx PCDEx\r
+ * @brief PCD Extended HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r
+ * @brief PCDEx control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Update FIFO configuration\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set Tx FIFO\r
+ * @param hpcd: PCD handle\r
+ * @param fifo: The number of Tx fifo\r
+ * @param size: Fifo size\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r
+{\r
+ uint8_t i = 0;\r
+ uint32_t Tx_Offset = 0;\r
+\r
+ /* TXn min size = 16 words. (n : Transmit FIFO index)\r
+ When a TxFIFO is not used, the Configuration should be as follows: \r
+ case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)\r
+ --> Txm can use the space allocated for Txn.\r
+ case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)\r
+ --> Txn should be configured with the minimum space of 16 words\r
+ The FIFO is used optimally when used TxFIFOs are allocated in the top \r
+ of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r
+ When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r
+ \r
+ Tx_Offset = hpcd->Instance->GRXFSIZ;\r
+ \r
+ if(fifo == 0)\r
+ {\r
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;\r
+ }\r
+ else\r
+ {\r
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r
+ for (i = 0; i < (fifo - 1); i++)\r
+ {\r
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r
+ }\r
+ \r
+ /* Multiply Tx_Size by 2 to get higher performance */\r
+ hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;\r
+ \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Set Rx FIFO\r
+ * @param hpcd: PCD handle\r
+ * @param size: Size of Rx fifo\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r
+{\r
+ hpcd->Instance->GRXFSIZ = size;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief HAL_PCDEx_ActivateLPM : active LPM Feature\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ hpcd->lpm_active = ENABLE;\r
+ hpcd->LPM_State = LPM_L0;\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r
+ USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature\r
+ * @param hpcd: PCD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r
+{\r
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; \r
+ \r
+ hpcd->lpm_active = DISABLE;\r
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r
+ USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer\r
+ * @param hpcd: PCD handle\r
+ * @param msg: LPM message\r
+ * @retval HAL status\r
+ */\r
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r
+{\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWR_Private_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */ \r
+#define PVD_MODE_IT ((uint32_t)0x00010000)\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000)\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r
+ * @{\r
+ */ \r
+#define PWR_EWUP_MASK ((uint32_t)0x00003F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted \r
+ write accesses. \r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ \r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a \r
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r
+ than the PVD threshold. This event is internally connected to the EXTI \r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** Wake-up pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r
+ forced in input pull-down configuration and is active on rising edges.\r
+ (+) There are to 6 Wake-up pin in the STM32F7 devices family\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The devices feature 3 low-power modes:\r
+ (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator \r
+ in low power mode\r
+ (+) Standby mode: 1.2V domain powered off.\r
+ \r
+ *** Sleep mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ \r
+ -@@- The Regulator parameter is not used for the STM32F7 family \r
+ and is kept as parameter just to maintain compatibility with the \r
+ lower power families (STM32L).\r
+ (+) Exit:\r
+ Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Stop mode ***\r
+ =================\r
+ [..]\r
+ In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents \r
+ are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, FLASH can be powered off before \r
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r
+ It can be switched on again by software after exiting the Stop mode using\r
+ the HAL_PWREx_DisableFlashPowerDown() function. \r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r
+ function with:\r
+ (++) Main regulator ON.\r
+ (++) Low Power regulator ON.\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ (+)\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r
+ The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r
+ the HSE oscillator are also switched off. SRAM and register contents are lost \r
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby \r
+ circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ (++) Entry:\r
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (++) Exit:\r
+ (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ \r
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event or a time-stamp event, without depending on \r
+ an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r
+ \r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+ \r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each \r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+ \r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r
+ \r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+ \r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+ \r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+ \r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values, which sets the default polarity: \r
+ * detection on high level (rising edge):\r
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r
+ * or one of the following value where the user can explicitly states the enabled pin and\r
+ * the chosen polarity \r
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+ \r
+ /* Enable wake-up pin */\r
+ SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r
+ \r
+ /* Specifies the Wake-Up pin polarity for the event detection\r
+ (rising or falling edge) */\r
+ MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r
+}\r
+\r
+/**\r
+ * @brief Disables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3\r
+ * @arg PWR_WAKEUP_PIN4\r
+ * @arg PWR_WAKEUP_PIN5\r
+ * @arg PWR_WAKEUP_PIN6 \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r
+}\r
+ \r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * \r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r
+ * systick interrupt when used as time base for Timeout \r
+ * \r
+ * @param Regulator: Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @note This parameter is not used for the STM32F7 family and is kept as parameter\r
+ * just to maintain compatibility with the lower power families.\r
+ * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters Stop mode. \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Select the regulator state in Stop mode ---------------------------------*/\r
+ tmpreg = PWR->CR1;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r
+ \r
+ /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r
+ tmpreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r
+}\r
+\r
+/**\r
+ * @brief Enters Standby mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r
+ * Alarm out, or RTC clock calibration out.\r
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. \r
+ * - WKUP pins if enabled. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Select Standby mode */\r
+ PWR->CR1 |= PWR_CR1_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+ /* Check PWR Exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+ \r
+ /* Clear PWR Exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enables CORTEX M4 SEVONPEND bit. \r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables CORTEX M4 SEVONPEND bit. \r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of PWR extension peripheral: \r
+ * + Peripheral Extended features functions\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWREx_Private_Constants\r
+ * @{\r
+ */ \r
+#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_BKPREG_TIMEOUT_VALUE 1000\r
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \r
+ * @brief Peripheral Extended features functions \r
+ *\r
+@verbatim \r
+\r
+ ===============================================================================\r
+ ##### Peripheral extended features functions #####\r
+ ===============================================================================\r
+\r
+ *** Main and Backup Regulators configuration ***\r
+ ================================================\r
+ [..] \r
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r
+ retained even in Standby or VBAT mode when the low power backup regulator\r
+ is enabled. It can be considered as an internal EEPROM when VBAT is \r
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to \r
+ enable the low power backup regulator. \r
+\r
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to \r
+ save battery life.\r
+\r
+ (+) The backup SRAM is not mass erased by a tamper event. It is read \r
+ protected to prevent confidential data, such as cryptographic private \r
+ key, from being accessed. The backup SRAM can be erased only through \r
+ the Flash interface when a protection level change from level 1 to \r
+ level 0 is requested. \r
+ -@- Refer to the description of Read protection (RDP) in the Flash \r
+ programming manual.\r
+\r
+ (+) The main internal regulator can be configured to have a tradeoff between \r
+ performance and power consumption when the device does not operate at \r
+ the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r
+ macro which configure VOS bit in PWR_CR register\r
+ \r
+ Refer to the product datasheets for more details.\r
+\r
+ *** FLASH Power Down configuration ****\r
+ =======================================\r
+ [..] \r
+ (+) By setting the FPDS bit in the PWR_CR register by using the \r
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \r
+ down mode when the device enters Stop mode. When the Flash memory \r
+ is in power down mode, an additional startup delay is incurred when \r
+ waking up from Stop mode.\r
+\r
+ *** Over-Drive and Under-Drive configuration ****\r
+ =================================================\r
+ [..] \r
+ (+) In Run mode: the main regulator has 2 operating modes available:\r
+ (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r
+ voltage scaling (scale 1, scale 2 or scale 3)\r
+ (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r
+ higher frequency than the normal mode for a given voltage scaling (scale 1, \r
+ scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r
+ disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r
+ the sequence described in Reference manual.\r
+ \r
+ (+) In Stop mode: the main regulator or low power regulator supplies a low power \r
+ voltage to the 1.2V domain, thus preserving the content of registers \r
+ and internal SRAM. 2 operating modes are available:\r
+ (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r
+ available when the main regulator or the low power regulator is used in Scale 3 or \r
+ low voltage mode.\r
+ (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r
+ available when the main regulator or the low power regulator is in low voltage mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Enable Backup regulator */\r
+ PWR->CSR1 |= PWR_CSR1_BRE;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Disable Backup regulator */\r
+ PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableFlashPowerDown(void)\r
+{\r
+ /* Enable the Flash Power Down */\r
+ PWR->CR1 |= PWR_CR1_FPDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableFlashPowerDown(void)\r
+{\r
+ /* Disable the Flash Power Down */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)\r
+{\r
+ /* Enable Main regulator low voltage */\r
+ PWR->CR1 |= PWR_CR1_MRUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)\r
+{ \r
+ /* Disable Main regulator low voltage */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Enable low power regulator */\r
+ PWR->CR1 |= PWR_CR1_LPUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Disable low power regulator */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);\r
+}\r
+\r
+/**\r
+ * @brief Activates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable the Over-drive to extend the clock frequency to 200 Mhz */\r
+ __HAL_PWR_OVERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Enable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Disable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Disable the Over-drive */\r
+ __HAL_PWR_OVERDRIVE_DISABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters in Under-Drive STOP mode.\r
+ * \r
+ * @note This mode can be selected only when the Under-Drive is already active \r
+ * \r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode\r
+ * \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ * \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * \r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced.\r
+ * \r
+ * @param Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tempreg = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ /* Enable the Under-drive Mode ---------------------------------------------*/\r
+ /* Clear Under-drive flag */\r
+ __HAL_PWR_CLEAR_ODRUDR_FLAG();\r
+ \r
+ /* Enable the Under-drive */ \r
+ __HAL_PWR_UNDERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for UnderDrive mode is ready */\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tempreg = PWR->CR1;\r
+ /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\r
+ tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);\r
+ \r
+ /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\r
+ tempreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tempreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns Voltage Scaling Range.\r
+ * @param None \r
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r
+ * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r
+ */ \r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+ return (PWR->CR1 & PWR_CR1_VOS);\r
+}\r
+\r
+/**\r
+ * @brief Configures the main internal regulator output voltage.\r
+ * @param VoltageScaling: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r
+ * typical output voltage at 1.4 V, \r
+ * system frequency up to 200 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.2 V, \r
+ * system frequency up to 180 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.00 V, \r
+ * system frequency up to 151 MHz.\r
+ * @note To update the system clock frequency(SYSCLK):\r
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\r
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.\r
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\r
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().\r
+ * @note The scale can be modified only when the HSI or HSE clock source is selected \r
+ * as system clock source, otherwise the API returns HAL_ERROR. \r
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\r
+ * value in the PWR_CR1 register are not taken in account.\r
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\r
+ * @note The new voltage scale is active only when the PLL is ON. \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r
+\r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\r
+ {\r
+ /* Disable the main PLL */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick(); \r
+ /* Wait till PLL is disabled */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set Range */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\r
+ \r
+ /* Enable the main PLL */\r
+ __HAL_RCC_PLL_ENABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_qspi.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief QSPI HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the QuadSPI interface (QSPI).\r
+ * + Initialization and de-initialization functions\r
+ * + Indirect functional mode management\r
+ * + Memory-mapped functional mode management\r
+ * + Auto-polling functional mode management\r
+ * + Interrupts and flags management\r
+ * + DMA channel configuration for indirect functional mode\r
+ * + Errors management and abort functionality\r
+ *\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ *** Initialization ***\r
+ ======================\r
+ [..]\r
+ (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r
+ (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r
+ (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r
+ (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
+ (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r
+ (+) If interrupt mode is used, enable and configure QuadSPI global\r
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel \r
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), \r
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure \r
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
+ (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r
+ clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r
+\r
+ *** Indirect functional mode ***\r
+ ================================\r
+ [..]\r
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() \r
+ functions :\r
+ (+) Instruction phase : the mode used and if present the instruction opcode.\r
+ (+) Address phase : the mode used and if present the size and the address value.\r
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (+) Data phase : the mode used and if present the number of bytes.\r
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (#) If no data is required for the command, it is sent directly to the memory :\r
+ (+) In polling mode, the output of the function is done when the transfer is complete.\r
+ (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or \r
+ HAL_QSPI_Transmit_IT() after the command configuration :\r
+ (+) In polling mode, the output of the function is done when the transfer is complete.\r
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
+ is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+ (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and \r
+ HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or \r
+ HAL_QSPI_Receive_IT() after the command configuration :\r
+ (+) In polling mode, the output of the function is done when the transfer is complete.\r
+ (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
+ is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+ (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and \r
+ HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
+\r
+ *** Auto-polling functional mode ***\r
+ ====================================\r
+ [..]\r
+ (#) Configure the command sequence and the auto-polling functional mode using the \r
+ HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r
+ (+) Instruction phase : the mode used and if present the instruction opcode.\r
+ (+) Address phase : the mode used and if present the size and the address value.\r
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (+) Data phase : the mode used.\r
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r
+ the polling interval and the automatic stop activation.\r
+ (#) After the configuration :\r
+ (+) In polling mode, the output of the function is done when the status match is reached. The\r
+ automatic stop is activated to avoid an infinite loop.\r
+ (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r
+\r
+ *** Memory-mapped functional mode ***\r
+ =====================================\r
+ [..]\r
+ (#) Configure the command sequence and the memory-mapped functional mode using the \r
+ HAL_QSPI_MemoryMapped() functions :\r
+ (+) Instruction phase : the mode used and if present the instruction opcode.\r
+ (+) Address phase : the mode used and the size.\r
+ (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
+ bytes values.\r
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
+ (+) Data phase : the mode used.\r
+ (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
+ if activated.\r
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
+ (+) The timeout activation and the timeout period.\r
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on \r
+ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r
+\r
+ *** Errors management and abort functionality ***\r
+ ==================================================\r
+ [..]\r
+ (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r
+ (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.\r
+ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r
+\r
+ *** Workarounds linked to Silicon Limitation ***\r
+ ====================================================\r
+ [..]\r
+ (#) Workarounds Implemented inside HAL Driver\r
+ (+) Extra data written in the FIFO at the end of a read transfer\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup QSPI QSPI\r
+ * @brief HAL QSPI module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Constants \r
+ * @{\r
+ */\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/\r
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Macros QSPI Private Macros\r
+ * @{\r
+ */\r
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \\r
+ ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup QSPI_Private_Functions QSPI Private Functions\r
+ * @{\r
+ */\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma); \r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Initialize the QuadSPI.\r
+ (+) De-initialize the QuadSPI.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the QSPI mode according to the specified parameters\r
+ * in the QSPI_InitTypeDef and creates the associated handle.\r
+ * @param hqspi: qspi handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the QSPI handle allocation */\r
+ if(hqspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r
+ assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r
+ assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r
+ assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r
+ assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
+ assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
+ assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
+ assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
+ assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_QSPI_MspInit(hqspi);\r
+ \r
+ /* Configure the default timeout for the QSPI memory access */\r
+ HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);\r
+ }\r
+ \r
+ /* Configure QSPI FIFO Threshold */\r
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));\r
+\r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ \r
+ /* Configure QSPI Clock Prescaler and Sample Shift */\r
+ MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));\r
+ \r
+ /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), \r
+ ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r
+ \r
+ /* Enable the QSPI peripheral */\r
+ __HAL_QSPI_ENABLE(hqspi);\r
+ \r
+ /* Set QSPI error code to none */\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; \r
+\r
+ /* Initialize the QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the QSPI peripheral \r
+ * @param hqspi: qspi handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* Check the QSPI handle allocation */\r
+ if(hqspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ /* Disable the QSPI Peripheral Clock */\r
+ __HAL_QSPI_DISABLE(hqspi);\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_QSPI_MspDeInit(hqspi);\r
+\r
+ /* Set QSPI error code to none */\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+ /* Initialize the QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP Init\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_QSPI_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief QSPI MSP DeInit\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_QSPI_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions \r
+ * @brief QSPI Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### I/O operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Handle the interrupts.\r
+ (+) Handle the command sequence.\r
+ (+) Transmit data in blocking, interrupt or DMA mode.\r
+ (+) Receive data in blocking, interrupt or DMA mode.\r
+ (+) Manage the auto-polling functional mode.\r
+ (+) Manage the memory-mapped functional mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles QSPI interrupt request.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None.\r
+ */\r
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ __IO uint32_t *data_reg;\r
+ uint32_t flag = 0, itsource = 0;\r
+\r
+ /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/\r
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);\r
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);\r
+ \r
+ if((flag != RESET) && (itsource != RESET))\r
+ {\r
+ data_reg = &hqspi->Instance->DR;\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+ {\r
+ /* Transmission process */\r
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
+ {\r
+ if (hqspi->TxXferCount > 0)\r
+ {\r
+ /* Fill the FIFO until it is full */\r
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
+ hqspi->TxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* No more data available for the transfer */\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+ {\r
+ /* Receiving Process */\r
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
+ {\r
+ if (hqspi->RxXferCount > 0)\r
+ {\r
+ /* Read the FIFO until it is empty */\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* All data have been received for the transfer */\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* FIFO Threshold callback */\r
+ HAL_QSPI_FifoThresholdCallback(hqspi);\r
+ }\r
+\r
+ /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);\r
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);\r
+ \r
+ if((flag != RESET) && (itsource != RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+ \r
+ /* Transfer complete callback */\r
+ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
+ {\r
+ /* Clear Busy bit */\r
+ HAL_QSPI_Abort(hqspi);\r
+ \r
+ /* TX Complete callback */\r
+ HAL_QSPI_TxCpltCallback(hqspi);\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
+ {\r
+ data_reg = &hqspi->Instance->DR;\r
+ while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)\r
+ {\r
+ if (hqspi->RxXferCount > 0)\r
+ {\r
+ /* Read the last data received in the FIFO until it is empty */\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ else\r
+ {\r
+ /* All data have been received for the transfer */\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+ HAL_QSPI_Abort(hqspi);\r
+ \r
+ /* RX Complete callback */\r
+ HAL_QSPI_RxCpltCallback(hqspi);\r
+ }\r
+ else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r
+ {\r
+ /* Command Complete callback */\r
+ HAL_QSPI_CmdCpltCallback(hqspi);\r
+ }\r
+\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+\r
+ /* QSPI Status Match interrupt occurred ------------------------------------*/\r
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);\r
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);\r
+ \r
+ if((flag != RESET) && (itsource != RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
+ \r
+ /* Check if the automatic poll mode stop is activated */\r
+ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)\r
+ {\r
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);\r
+\r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+\r
+ /* Status match callback */\r
+ HAL_QSPI_StatusMatchCallback(hqspi);\r
+ }\r
+\r
+ /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);\r
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);\r
+ \r
+ if((flag != RESET) && (itsource != RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);\r
+ \r
+ /* Disable all the QSPI Interrupts */\r
+ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
+\r
+ /* Set error code */\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r
+ \r
+ /* Change state of QSPI */\r
+ hqspi->State = HAL_QSPI_STATE_ERROR;\r
+\r
+ /* Error callback */\r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+\r
+ /* QSPI Time out interrupt occurred -----------------------------------------*/\r
+ flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);\r
+ itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);\r
+ \r
+ if((flag != RESET) && (itsource != RESET))\r
+ {\r
+ /* Clear interrupt */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r
+ \r
+ /* Time out callback */\r
+ HAL_QSPI_TimeOutCallback(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the command configuration. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd : structure that contains the command configuration information\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Read or Write Modes\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY; \r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ if (cmd->DataMode == QSPI_DATA_NONE)\r
+ {\r
+ /* When there is no data phase, the transfer start as soon as the configuration is done \r
+ so wait until TC flag is set to go back in idle state */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sets the command configuration in interrupt mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd : structure that contains the command configuration information\r
+ * @note This function is used only in Indirect Read or Write Modes\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY; \r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ if (cmd->DataMode == QSPI_DATA_NONE)\r
+ {\r
+ /* When there is no data phase, the transfer start as soon as the configuration is done \r
+ so activate TC and TE interrupts */\r
+ /* Enable the QSPI Transfer Error Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r
+ }\r
+ \r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ if (cmd->DataMode != QSPI_DATA_NONE)\r
+ {\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL )\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+\r
+ while(hqspi->TxXferCount > 0)\r
+ {\r
+ /* Wait until FT flag is set to send data */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
+ hqspi->TxXferCount--;\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Wait until TC flag is set to go back in idle state */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Clear Busy bit */\r
+ status = HAL_QSPI_Abort(hqspi);\r
+ }\r
+ }\r
+ \r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL )\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pRxBuffPtr = pData;\r
+\r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+ \r
+ while(hqspi->RxXferCount > 0)\r
+ {\r
+ /* Wait until FT or TC flag is set to read received data */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
+ hqspi->RxXferCount--;\r
+ }\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Wait until TC flag is set to go back in idle state */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+ status = HAL_QSPI_Abort(hqspi);\r
+ }\r
+ }\r
+\r
+ /* Update QSPI state */\r
+ hqspi->State = HAL_QSPI_STATE_READY; \r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+ }\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{ \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL )\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+ /* Configure counters and size of the handle */\r
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+ \r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY;\r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in no-blocking mode with Interrupt\r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+\r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL )\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pRxBuffPtr = pData;\r
+\r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+ /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sends an amount of data in non blocking mode with DMA. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer\r
+ * @note This function is used only in Indirect Write Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL ) \r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
+\r
+ /* Configure counters and size of the handle */\r
+ hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pTxBuffPtr = pData;\r
+ \r
+ /* Configure QSPI: CCR register with functional mode as indirect write */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
+ \r
+ /* Set the QSPI DMA transfer complete callback */\r
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r
+ \r
+ /* Set the QSPI DMA Half transfer complete callback */\r
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+ \r
+ /* Configure the direction of the DMA */\r
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
+\r
+ /* Enable the QSPI transmit DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);\r
+ \r
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+ \r
+/**\r
+ * @brief Receives an amount of data in non blocking mode with DMA. \r
+ * @param hqspi: QSPI handle\r
+ * @param pData: pointer to data buffer.\r
+ * @note This function is used only in Indirect Read Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t *tmp;\r
+ uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ if(pData != NULL ) \r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
+ \r
+ /* Configure counters and size of the handle */\r
+ hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
+ hqspi->pRxBuffPtr = pData;\r
+\r
+ /* Set the QSPI DMA transfer complete callback */\r
+ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r
+ \r
+ /* Set the QSPI DMA Half transfer complete callback */\r
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
+ \r
+ /* Configure the direction of the DMA */\r
+ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
+\r
+ /* Enable the DMA Channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);\r
+ \r
+ /* Configure QSPI: CCR register with functional as indirect read */\r
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
+\r
+ /* Start the transfer by re-writing the address in AR register */\r
+ WRITE_REG(hqspi->Instance->AR, addr_reg);\r
+\r
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the polling configuration information.\r
+ * @param Timeout : Time out duration\r
+ * @note This function is used only in Automatic Polling Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ \r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+\r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: PSMAR register with the status match value */\r
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+ \r
+ /* Configure QSPI: PSMKR register with the status mask value */\r
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+ \r
+ /* Configure QSPI: PIR register with the interval value */\r
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+ \r
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled \r
+ (otherwise there will be an infinite loop in blocking mode) */\r
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
+ (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r
+\r
+ /* Call the configuration function */\r
+ cmd->NbData = cfg->StatusBytesSize;\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+\r
+ /* Wait until SM flag is set to go back in idle state */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the polling configuration information.\r
+ * @note This function is used only in Automatic Polling Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+ assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
+ assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
+ assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
+ assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: PSMAR register with the status match value */\r
+ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
+ \r
+ /* Configure QSPI: PSMKR register with the status mask value */\r
+ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
+ \r
+ /* Configure QSPI: PIR register with the interval value */\r
+ WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
+ \r
+ /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
+ (cfg->MatchMode | cfg->AutomaticStop));\r
+\r
+ /* Call the configuration function */\r
+ cmd->NbData = cfg->StatusBytesSize;\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
+\r
+ /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Configure the Memory Mapped mode. \r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information.\r
+ * @param cfg: structure that contains the memory mapped configuration information.\r
+ * @note This function is used only in Memory mapped Mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
+ }\r
+\r
+ assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
+ assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
+\r
+ assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
+ assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
+ assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
+\r
+ assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hqspi);\r
+ \r
+ if(hqspi->State == HAL_QSPI_STATE_READY)\r
+ {\r
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r
+ \r
+ /* Wait till BUSY flag reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
+ \r
+ if (status == HAL_OK)\r
+ {\r
+ /* Configure QSPI: CR register with time out counter enable */\r
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r
+\r
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r
+ {\r
+ assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r
+\r
+ /* Configure QSPI: LPTR register with the low-power time out value */\r
+ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r
+\r
+ /* Enable the QSPI TimeOut Interrupt */\r
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r
+ }\r
+\r
+ /* Call the configuration function */\r
+ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r
+ \r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_BUSY; \r
+ \r
+ }\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hqspi);\r
+ \r
+ /* Return function status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Transfer Error callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Command completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FIFO Threshold callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Status Match callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timeout callbacks\r
+ * @param hqspi: QSPI handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_QSPI_TimeOutCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions \r
+ * @brief QSPI control and State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control and State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to :\r
+ (+) Check in run-time the state of the driver. \r
+ (+) Check the error code set during last operation.\r
+ (+) Abort any operation.\r
+..... \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the QSPI state.\r
+ * @param hqspi: QSPI handle\r
+ * @retval HAL state\r
+ */\r
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ return hqspi->State;\r
+}\r
+\r
+/**\r
+* @brief Return the QSPI error code\r
+* @param hqspi: QSPI handle\r
+* @retval QSPI Error Code\r
+*/\r
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ return hqspi->ErrorCode;\r
+}\r
+\r
+/**\r
+* @brief Abort the current transmission\r
+* @param hqspi: QSPI handle\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+\r
+ /* Configure QSPI: CR register with Abort request */\r
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
+\r
+ /* Wait until TC flag is set to go back in idle state */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
+ { \r
+ status = HAL_TIMEOUT;\r
+ }\r
+ else\r
+ {\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Wait until BUSY flag is reset */\r
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/** @brief Set QSPI timeout\r
+ * @param hqspi: QSPI handle.\r
+ * @param Timeout: Timeout for the QSPI memory access.\r
+ * @retval None\r
+ */\r
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
+{\r
+ hqspi->Timeout = Timeout;\r
+}\r
+\r
+/**\r
+* @}\r
+*/\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/**\r
+ * @brief DMA QSPI receive process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hqspi->RxXferCount = 0;\r
+ \r
+ /* Wait for QSPI TC Flag */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
+ {\r
+ /* Time out Occurred */ \r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+\r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+\r
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
+ HAL_QSPI_Abort(hqspi);\r
+ \r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ \r
+ HAL_QSPI_RxCpltCallback(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI transmit process complete callback. \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hqspi->TxXferCount = 0;\r
+ \r
+ /* Wait for QSPI TC Flag */\r
+ if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
+ {\r
+ /* Time out Occurred */ \r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
+ \r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Clear Transfer Complete bit */\r
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
+ \r
+ /* Clear Busy bit */\r
+ HAL_QSPI_Abort(hqspi);\r
+\r
+ /* Update state */\r
+ hqspi->State = HAL_QSPI_STATE_READY;\r
+ \r
+ HAL_QSPI_TxCpltCallback(hqspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI receive process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_QSPI_RxHalfCpltCallback(hqspi); \r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI transmit process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_QSPI_TxHalfCpltCallback(hqspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA QSPI communication error callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ hqspi->RxXferCount = 0;\r
+ hqspi->TxXferCount = 0;\r
+ hqspi->State = HAL_QSPI_STATE_ERROR;\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
+\r
+ HAL_QSPI_ErrorCallback(hqspi);\r
+}\r
+\r
+/**\r
+ * @brief This function wait a flag state until time out.\r
+ * @param hqspi: QSPI handle\r
+ * @param Flag: Flag checked\r
+ * @param State: Value of the flag expected\r
+ * @param Timeout: Duration of the time out\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,\r
+ FlagStatus State, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is in expected state */ \r
+ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))\r
+ {\r
+ hqspi->State = HAL_QSPI_STATE_ERROR;\r
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function configures the communication registers\r
+ * @param hqspi: QSPI handle\r
+ * @param cmd: structure that contains the command configuration information\r
+ * @param FunctionalMode: functional mode to configured\r
+ * This parameter can be a value of @ref QSPI_FunctionalMode\r
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
+ * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode \r
+ * @retval None\r
+ */\r
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r
+{\r
+ assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r
+\r
+ if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
+ {\r
+ /* Configure QSPI: DLR register with the number of data to read or write */\r
+ WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));\r
+ }\r
+ \r
+ if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
+ {\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ /* Configure QSPI: ABR register with alternate bytes value */\r
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with instruction, address and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with instruction and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
+ cmd->Instruction | FunctionalMode));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with instruction and address ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
+ cmd->Instruction | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only instruction ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | \r
+ FunctionalMode));\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
+ {\r
+ /* Configure QSPI: ABR register with alternate bytes value */\r
+ WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
+\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with address and alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
+ cmd->InstructionMode | FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only alternate bytes ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
+ cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
+ FunctionalMode));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
+ {\r
+ /*---- Command with only address ----*/\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
+ FunctionalMode));\r
+\r
+ if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
+ {\r
+ /* Configure QSPI: AR register with address value */\r
+ WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*---- Command with only data phase ----*/\r
+ if (cmd->DataMode != QSPI_DATA_NONE)\r
+ {\r
+ /* Configure QSPI: CCR register with all communications parameters */\r
+ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
+ cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and Clock Control (RCC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### RCC specific features #####\r
+ ==============================================================================\r
+ [..] \r
+ After reset the device is running from Internal High Speed oscillator \r
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache \r
+ and I-Cache are disabled, and all peripherals are off except internal\r
+ SRAM, Flash and JTAG.\r
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ all peripherals mapped on these busses are running at HSI speed.\r
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (+) All GPIOs are in input floating state, except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+ \r
+ [..] \r
+ Once the device started from reset, the user application has to: \r
+ (+) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (+) Configure the System clock frequency and Flash settings \r
+ (+) Configure the AHB and APB busses prescalers\r
+ (+) Enable the clock for the peripheral(s) to be used\r
+ (+) Configure the clock source(s) for peripherals which clocks are not\r
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r
+\r
+ ##### RCC Limitations #####\r
+ ==============================================================================\r
+ [..] \r
+ A delay between an RCC peripheral clock enable and the effective peripheral \r
+ enabling should be taken into account in order to manage the peripheral read/write \r
+ from/to registers.\r
+ (+) This delay depends on the peripheral mapping.\r
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle \r
+ after the clock enable bit is set on the hardware register\r
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle \r
+ after the clock enable bit is set on the hardware register\r
+\r
+ [..] \r
+ Workarounds:\r
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC RCC\r
+ * @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+\r
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT GPIOA\r
+#define MCO1_PIN GPIO_PIN_8\r
+\r
+#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+#define MCO2_GPIO_PORT GPIOC\r
+#define MCO2_PIN GPIO_PIN_9\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Variables RCC Private Variables\r
+ * @{\r
+ */\r
+const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to configure the internal/external oscillators\r
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 \r
+ and APB2).\r
+\r
+ [..] Internal/external clock and PLL configuration\r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+\r
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r
+ (++) The first output is used to generate the high speed system clock (up to 200 MHz)\r
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+\r
+ (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()\r
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System \r
+ clock source), the System clock is automatically switched to HSI and an interrupt\r
+ is generated if enabled. The interrupt is linked to the Cortex-M7 NMI \r
+ (Non-Maskable Interrupt) exception vector. \r
+\r
+ (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r
+ clock (through a configurable prescaler) on PA8 pin.\r
+\r
+ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r
+ clock (through a configurable prescaler) on PC9 pin.\r
+\r
+ [..] System, AHB and APB busses clocks configuration \r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable \r
+ prescaler and used to clock the CPU, memory and peripherals mapped \r
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived \r
+ from AHB clock through configurable prescalers and used to clock \r
+ the peripherals mapped on these busses. You can use \r
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. \r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r
+ from an external clock mapped on the I2S_CKIN pin. \r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r
+ (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or\r
+ from an external clock mapped on the I2S_CKIN pin. \r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. \r
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()\r
+ macros to configure this clock. \r
+ (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r
+ to work correctly, while the SDIO require a frequency equal or lower than\r
+ to 48. This clock is derived of the main PLL through PLLQ divider.\r
+ (+@) IWDG clock which is always the LSI clock.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - HSI ON and used as system clock source\r
+ * - HSE, PLL and PLLI2S OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS, MCO1 and MCO2 OFF\r
+ * - All interrupts disabled\r
+ * @note This function doesn't modify the configuration of the\r
+ * - Peripheral clocks \r
+ * - LSI, LSE and RTC clocks \r
+ * @retval None\r
+ */\r
+void HAL_RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); \r
+ \r
+ /* Reset CFGR register */\r
+ CLEAR_REG(RCC->CFGR);\r
+ \r
+ /* Reset HSEON, CSSON, PLLON, PLLI2S */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); \r
+ \r
+ /* Reset PLLCFGR register */\r
+ CLEAR_REG(RCC->PLLCFGR);\r
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); \r
+ \r
+ /* Reset PLLI2SCFGR register */\r
+ CLEAR_REG(RCC->PLLI2SCFGR);\r
+ SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);\r
+ \r
+ /* Reset HSEBYP bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r
+ \r
+ /* Disable all interrupts */\r
+ CLEAR_REG(RCC->CIR);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+ \r
+ /*------------------------------- HSE Configuration ------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is disabled */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+ \r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSE is bypassed or disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+ \r
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till HSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSI is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/ \r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+ \r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+ \r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ \r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ }\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ { \r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+ \r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLM,\r
+ RCC_OscInitStruct->PLL.PLLN,\r
+ RCC_OscInitStruct->PLL.PLLP,\r
+ RCC_OscInitStruct->PLL.PLLQ);\r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified \r
+ * parameters in the RCC_ClkInitStruct.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC peripheral.\r
+ * @param FLatency: FLASH Latency, this parameter depend on device selected\r
+ * \r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
+ *\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * \r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is\r
+ * currently used as system clock source.\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
+ * (for more details refer to section above "Initialization/de-initialization functions")\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
+ assert_param(IS_FLASH_LATENCY(FLatency));\r
+ \r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock \r
+ (HCLK) and the supply voltage of the device. */\r
+ \r
+ /* Increasing the CPU frequency */\r
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))\r
+ { \r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+ \r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+\r
+ /*------------------------- SYSCLK Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ { \r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+ \r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the HSI ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ } \r
+ }\r
+ /* Decreasing the CPU frequency */\r
+ else\r
+ {\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+\r
+ /*------------------------- SYSCLK Configuration -------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ { \r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+ \r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the HSI ready flag */ \r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+ \r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
+ }\r
+ \r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/ \r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r
+ }\r
+\r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ HAL_InitTick (TICK_INT_PRIORITY);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief RCC clocks control functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks \r
+ frequencies.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r
+ * @note PA8/PC9 should be configured in alternate function mode.\r
+ * @param RCC_MCOx: specifies the output direction for the clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r
+ * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param RCC_MCODiv: specifies the MCOx prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ * @retval None\r
+ */\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCOx));\r
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+ /* RCC_MCO1 */\r
+ if(RCC_MCOx == RCC_MCO1)\r
+ {\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+ \r
+ /* MCO1 Clock Enable */\r
+ MCO1_CLK_ENABLE();\r
+ \r
+ /* Configure the MCO1 pin in alternate function mode */ \r
+ GPIO_InitStruct.Pin = MCO1_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
+ \r
+ /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r
+ \r
+ /* MCO2 Clock Enable */\r
+ MCO2_CLK_ENABLE();\r
+ \r
+ /* Configure the MCO2 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO2_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r
+ \r
+ /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. \r
+ * @retval None\r
+ */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+ SET_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Clock Security System.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_DisableCSS(void)\r
+{\r
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SYSCLK frequency\r
+ * \r
+ * @note The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors. \r
+ * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @note This function can be used by the user application to compute the \r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ * \r
+ * @note Each time SYSCLK changes, this function must be called to update the\r
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * \r
+ * \r
+ * @retval SYSCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;\r
+ uint32_t sysclockfreq = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */\r
+ {\r
+ sysclockfreq = HSE_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */\r
+ {\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLP */\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); \r
+ }\r
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);\r
+ \r
+ sysclockfreq = pllvco/pllp;\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ }\r
+ return sysclockfreq;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HCLK frequency \r
+ * @note Each time HCLK changes, this function must be called to update the\r
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * \r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r
+ * and updated within this function\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK1 frequency \r
+ * @note Each time PCLK1 changes, this function must be called to update the\r
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{ \r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK2 frequency \r
+ * @note Each time PCLK2 changes, this function must be called to update the\r
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK2 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);\r
+} \r
+\r
+/**\r
+ * @brief Configures the RCC_OscInitStruct according to the internal \r
+ * RCC configuration registers.\r
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that \r
+ * will be configured.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ /* Set all possible values for the Oscillator type parameter ---------------*/\r
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
+ \r
+ /* Get the HSE configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+ }\r
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+ }\r
+ \r
+ /* Get the HSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+ }\r
+ \r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));\r
+ \r
+ /* Get the LSE configuration -----------------------------------------------*/\r
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+ }\r
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+ }\r
+ \r
+ /* Get the LSI configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+ }\r
+ \r
+ /* Get the PLL configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+ }\r
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\r
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));\r
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));\r
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_ClkInitStruct according to the internal \r
+ * RCC configuration registers.\r
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that \r
+ * will be configured.\r
+ * @param pFLatency: Pointer on the Flash Latency.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+ /* Set all possible values for the Clock type parameter --------------------*/\r
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
+ \r
+ /* Get the SYSCLK configuration --------------------------------------------*/ \r
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
+ \r
+ /* Get the HCLK configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); \r
+ \r
+ /* Get the APB1 configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); \r
+ \r
+ /* Get the APB2 configuration ----------------------------------------------*/ \r
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r
+ \r
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/ \r
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); \r
+}\r
+\r
+/**\r
+ * @brief This function handles the RCC CSS interrupt request.\r
+ * @note This API should be called under the NMI_Handler().\r
+ * @retval None\r
+ */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+ /* Check RCC CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+ {\r
+ /* RCC Clock Security System interrupt user callback */\r
+ HAL_RCC_CSSCallback();\r
+\r
+ /* Clear RCC CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCC Clock Security System interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_RCC_CSSCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RCC_CSSCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Extension RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities RCC extension peripheral:\r
+ * + Extended Peripheral Control functions\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx RCCEx\r
+ * @brief RCCEx HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Defines RCCEx Private Defines\r
+ * @{\r
+ */\r
+ \r
+#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */\r
+#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions \r
+ * @brief Extended Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks \r
+ frequencies.\r
+ [..] \r
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+ select the RTC clock source; in this case the Backup domain will be reset in \r
+ order to modify the RTC Clock source, as consequence RTC registers (including \r
+ the backup registers) and RCC_BDCR register will be set to their reset values.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals\r
+ * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r
+ * \r
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select \r
+ * the RTC clock source; in this case the Backup domain will be reset in \r
+ * order to modify the RTC Clock source, as consequence RTC registers (including \r
+ * the backup registers) and RCC_BDCR register are set to their reset values.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg0 = 0;\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t plli2sused = 0;\r
+ uint32_t pllsaiused = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+ \r
+ /*----------------------------------- I2S configuration ----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r
+ \r
+ /* Configure I2S Clock source */\r
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r
+ \r
+ /* Enable the PLLI2S when it's used as clock source for I2S */\r
+ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ }\r
+ \r
+ /*------------------------------------ SAI1 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r
+ \r
+ /* Configure SAI1 Clock source */\r
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+ \r
+ /*------------------------------------ SAI2 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r
+ \r
+ /* Configure SAI2 Clock source */\r
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
+ \r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1; \r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+ \r
+ /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ { \r
+ plli2sused = 1; \r
+ } \r
+ \r
+ /*------------------------------------ RTC configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r
+ {\r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait for Backup domain Write protection disable */\r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */ \r
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))\r
+ {\r
+ /* Store the content of BDCR register before the reset of Backup Domain */\r
+ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
+ \r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+ \r
+ /* Restore the Content of BDCR register */\r
+ RCC->BDCR = tmpreg0;\r
+ }\r
+ \r
+ /* If LSE is selected as RTC clock source, wait for LSE reactivation */\r
+ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till LSE is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ }\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); \r
+ }\r
+ /*------------------------------------ TIM configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r
+ \r
+ /* Configure Timer Prescaler */\r
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
+ \r
+ /* Configure the I2C1 clock source */\r
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
+ \r
+ /* Configure the I2C2 clock source */\r
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
+ \r
+ /* Configure the I2C3 clock source */\r
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- I2C4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
+ \r
+ /* Configure the I2C4 clock source */\r
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
+ \r
+ /* Configure the USART1 clock source */\r
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
+ \r
+ /* Configure the USART2 clock source */\r
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
+ \r
+ /* Configure the USART3 clock source */\r
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
+ \r
+ /* Configure the UART4 clock source */\r
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART5 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
+ \r
+ /* Configure the UART5 clock source */\r
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART6 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r
+ \r
+ /* Configure the USART6 clock source */\r
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART7 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r
+ \r
+ /* Configure the UART7 clock source */\r
+ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART8 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r
+ \r
+ /* Configure the UART8 clock source */\r
+ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r
+ }\r
+ \r
+ /*--------------------------------------- CEC Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\r
+ \r
+ /* Configure the CEC clock source */\r
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\r
+ }\r
+ \r
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r
+ \r
+ /* Configure the CLK48 source */\r
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r
+\r
+ /* Enable the PLLSAI when it's used as clock source for CK48 */\r
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- LTDC Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
+ {\r
+ pllsaiused = 1; \r
+ }\r
+ \r
+ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
+ \r
+ /* Configure the LTPIM1 clock source */\r
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+ }\r
+ \r
+ /*------------------------------------- SDMMC Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
+ \r
+ /* Configure the SDMMC1 clock source */\r
+ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r
+ if(plli2sused == 1)\r
+ {\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE(); \r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait till PLLI2S is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* check for common PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r
+ \r
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ \r
+ /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */\r
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+ \r
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) \r
+ {\r
+ /* Check for PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+ /* Check for PLLI2S/DIVQ parameters */\r
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r
+ \r
+ /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ /* Configure the PLLI2S division factors */ \r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ \r
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); \r
+ } \r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ \r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+ \r
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */\r
+ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r
+ } \r
+ \r
+ /* Enable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ } \r
+ \r
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r
+ if(pllsaiused == 1)\r
+ {\r
+ /* Disable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_DISABLE(); \r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ { \r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Check the PLLSAI division factors */\r
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r
+ \r
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ \r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r
+ {\r
+ /* check for PLLSAIQ Parameter */\r
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r
+ /* check for PLLSAI/DIVQ Parameter */\r
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r
+ \r
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ \r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r
+ } \r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ \r
+ /* In Case of PLLI2S is selected as source clock for CK48 */ \r
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r
+ /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r
+ \r
+ /* Configure the PLLSAI division factors */\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLM) */\r
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r
+ } \r
+\r
+ /*---------------------------- LTDC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r
+ {\r
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\r
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\r
+ \r
+ /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ \r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);\r
+ \r
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ \r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r
+ } \r
+ \r
+ /* Enable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_ENABLE();\r
+ \r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is ready */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ { \r
+ /* return in case of Timeout detected */ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal\r
+ * RCC configuration registers.\r
+ * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tempreg = 0;\r
+ \r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48; \r
+ \r
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));\r
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r
+ \r
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));\r
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); \r
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); \r
+ \r
+ /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));\r
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));\r
+ PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));\r
+\r
+ /* Get the SAI1 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r
+ \r
+ /* Get the SAI2 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r
+ \r
+ /* Get the I2S clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r
+ \r
+ /* Get the I2C1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r
+ \r
+ /* Get the I2C2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r
+ \r
+ /* Get the I2C3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r
+ \r
+ /* Get the I2C4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();\r
+ \r
+ /* Get the USART1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r
+ \r
+ /* Get the USART2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r
+ \r
+ /* Get the USART3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r
+ \r
+ /* Get the UART4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r
+ \r
+ /* Get the UART5 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r
+ \r
+ /* Get the USART6 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r
+ \r
+ /* Get the UART7 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r
+ \r
+ /* Get the UART8 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r
+ \r
+ /* Get the LPTIM1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+ \r
+ /* Get the CEC clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r
+ \r
+ /* Get the CK48 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r
+\r
+ /* Get the SDMMC clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r
+ \r
+ /* Get the RTC Clock configuration -----------------------------------------------*/\r
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r
+ \r
+ /* Get the TIM Prescaler configuration --------------------------------------------*/\r
+ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r
+ }\r
+ else\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..) \r
+ * @note Return 0 if peripheral clock identifier not managed by this API\r
+ * @param PeriphClk: Peripheral clock identifier\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\r
+ * @retval Frequency in KHz\r
+ */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* This variable used to store the SAI clock frequency (value in Hz) */\r
+ uint32_t frequency = 0;\r
+ /* This variable used to store the VCO Input (value in Hz) */\r
+ uint32_t vcoinput = 0;\r
+ /* This variable used to store the SAI clock source */\r
+ uint32_t saiclocksource = 0;\r
+ if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))\r
+ {\r
+ saiclocksource = RCC->DCKCFGR1; \r
+ saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL);\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLLSAI is the clock source for SAI*/ \r
+ {\r
+ /* Configure the PLLSAI division factor */\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ } \r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r
+ frequency = frequency/(tmpreg); \r
+ break; \r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/\r
+ case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/\r
+ { \r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ \r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+ \r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+ \r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); \r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/\r
+ case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break; \r
+ }\r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ return frequency;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rng.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief RNG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Random Number Generator (RNG) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The RNG HAL driver can be used as follows:\r
+\r
+ (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro \r
+ in HAL_RNG_MspInit().\r
+ (#) Activate the RNG peripheral using HAL_RNG_Init() function.\r
+ (#) Wait until the 32 bit Random Number Generator contains a valid \r
+ random data using (polling/interrupt) mode. \r
+ (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RNG \r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+\r
+#if defined(STM32F746xx) || defined(STM32F756xx)\r
+\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup RNG_Private_Constants\r
+ * @{\r
+ */\r
+#define RNG_TIMEOUT_VALUE 2\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions prototypes ----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup RNG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RNG_Exported_Functions_Group1\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize the RNG according to the specified parameters \r
+ in the RNG_InitTypeDef and create the associated handle\r
+ (+) DeInitialize the RNG peripheral\r
+ (+) Initialize the RNG MSP\r
+ (+) DeInitialize RNG MSP \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the RNG peripheral and creates the associated handle.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)\r
+{ \r
+ /* Check the RNG handle allocation */\r
+ if(hrng == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ __HAL_LOCK(hrng);\r
+ \r
+ if(hrng->State == HAL_RNG_STATE_RESET)\r
+ { \r
+ /* Allocate lock resource and initialize it */\r
+ hrng->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware */\r
+ HAL_RNG_MspInit(hrng);\r
+ }\r
+ \r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_BUSY;\r
+\r
+ /* Enable the RNG Peripheral */\r
+ __HAL_RNG_ENABLE(hrng);\r
+\r
+ /* Initialize the RNG state */\r
+ hrng->State = HAL_RNG_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RNG peripheral. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)\r
+{ \r
+ /* Check the RNG handle allocation */\r
+ if(hrng == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Disable the RNG Peripheral */\r
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);\r
+ \r
+ /* Clear RNG interrupt status flags */\r
+ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_RNG_MspDeInit(hrng);\r
+ \r
+ /* Update the RNG state */\r
+ hrng->State = HAL_RNG_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Return the function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RNG MSP.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_MspInit must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RNG MSP.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_MspDeInit must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RNG_Exported_Functions_Group2\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Get the 32 bit Random number\r
+ (+) Get the 32 bit Random number with interrupt enabled\r
+ (+) Handle RNG interrupt request \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Generates a 32-bit random number.\r
+ * @note Each time the random number data is read the RNG_FLAG_DRDY flag \r
+ * is automatically cleared.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @param random32bit: pointer to generated random number variable if successful.\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)\r
+{\r
+ uint32_t tickstart = 0; \r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrng); \r
+ \r
+ /* Check RNG peripheral state */\r
+ if(hrng->State == HAL_RNG_STATE_READY)\r
+ {\r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check if data register contains valid random data */\r
+ while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)\r
+ { \r
+ hrng->State = HAL_RNG_STATE_ERROR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Get a 32bit Random number */\r
+ hrng->RandomNumber = hrng->Instance->DR;\r
+ *random32bit = hrng->RandomNumber;\r
+ \r
+ hrng->State = HAL_RNG_STATE_READY;\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Generates a 32-bit random number in interrupt mode.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hrng);\r
+ \r
+ /* Check RNG peripheral state */\r
+ if(hrng->State == HAL_RNG_STATE_READY)\r
+ {\r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r
+ __HAL_RNG_ENABLE_IT(hrng);\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrng);\r
+ \r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Handles RNG interrupt request.\r
+ * @note In the case of a clock error, the RNG is no more able to generate \r
+ * random numbers because the PLL48CLK clock is not correct. User has \r
+ * to check that the clock controller is correctly configured to provide\r
+ * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). \r
+ * The clock error has no impact on the previously generated \r
+ * random numbers, and the RNG_DR register contents can be used.\r
+ * @note In the case of a seed error, the generation of random numbers is \r
+ * interrupted as long as the SECS bit is '1'. If a number is \r
+ * available in the RNG_DR register, it must not be used because it may \r
+ * not have enough entropy. In this case, it is recommended to clear the \r
+ * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable \r
+ * the RNG peripheral to reinitialize and restart the RNG.\r
+ * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS\r
+ * or CEIS are set. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+\r
+ */\r
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* RNG clock error interrupt occurred */\r
+ if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))\r
+ { \r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_ERROR;\r
+ \r
+ HAL_RNG_ErrorCallback(hrng);\r
+ \r
+ /* Clear the clock error flag */\r
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);\r
+ \r
+ }\r
+ \r
+ /* Check RNG data ready interrupt occurred */ \r
+ if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)\r
+ {\r
+ /* Generate random number once, so disable the IT */\r
+ __HAL_RNG_DISABLE_IT(hrng);\r
+ \r
+ /* Get the 32bit Random number (DRDY flag automatically cleared) */ \r
+ hrng->RandomNumber = hrng->Instance->DR;\r
+ \r
+ if(hrng->State != HAL_RNG_STATE_ERROR)\r
+ {\r
+ /* Change RNG peripheral state */\r
+ hrng->State = HAL_RNG_STATE_READY; \r
+ \r
+ /* Data Ready callback */ \r
+ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);\r
+ } \r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Returns generated random number in polling mode (Obsolete)\r
+ * Use HAL_RNG_GenerateRandomNumber() API instead.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval Random value\r
+ */\r
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)\r
+{\r
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)\r
+ {\r
+ return hrng->RandomNumber; \r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),\r
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval 32-bit random number\r
+ */\r
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)\r
+{\r
+ uint32_t random32bit = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hrng);\r
+ \r
+ /* Change RNG peripheral state */ \r
+ hrng->State = HAL_RNG_STATE_BUSY; \r
+ \r
+ /* Get a 32bit Random number */ \r
+ random32bit = hrng->Instance->DR;\r
+ \r
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r
+ __HAL_RNG_ENABLE_IT(hrng); \r
+ \r
+ /* Return the 32 bit random number */ \r
+ return random32bit;\r
+}\r
+\r
+/**\r
+ * @brief Read latest generated random number. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval random value\r
+ */\r
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)\r
+{\r
+ return(hrng->RandomNumber);\r
+}\r
+\r
+/**\r
+ * @brief Data Ready callback in non-blocking mode. \r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @param random32bit: generated random number.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)\r
+{\r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_ReadyDataCallback must be implemented in the user file.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief RNG error callbacks.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)\r
+{\r
+ /* NOTE : This function should not be modified. When the callback is needed,\r
+ function HAL_RNG_ErrorCallback must be implemented in the user file.\r
+ */\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ \r
+/** @addtogroup RNG_Exported_Functions_Group3\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Returns the RNG state.\r
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains\r
+ * the configuration information for RNG.\r
+ * @retval HAL state\r
+ */\r
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)\r
+{\r
+ return hrng->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F746xx || STM32F756xx */\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief RTC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Real Time Clock (RTC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + RTC Time and Date functions\r
+ * + RTC Alarm functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Backup Domain Operating Condition #####\r
+ ==============================================================================\r
+ [..] The real-time clock (RTC), the RTC backup registers, and the backup \r
+ SRAM (BKP SRAM) can be powered from the VBAT voltage when the main \r
+ VDD supply is powered off.\r
+ To retain the content of the RTC backup registers, backup SRAM, and supply \r
+ the RTC when VDD is turned off, VBAT pin can be connected to an optional \r
+ standby voltage supplied by a battery or by another source.\r
+\r
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned\r
+ off, the VBAT pin powers the following blocks:\r
+ (#) The RTC\r
+ (#) The LSE oscillator\r
+ (#) The backup SRAM when the low power backup regulator is enabled\r
+ (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)\r
+ \r
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),\r
+ the following pins are available:\r
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins\r
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin\r
+ (#) PI8 can be used as a GPIO or as the RTC_AF2 pin\r
+ \r
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT \r
+ because VDD is not present), the following pins are available:\r
+ (#) PC14 and PC15 can be used as LSE pins only\r
+ (#) PC13 can be used as the RTC_AF1 pin \r
+ (#) PI8 can be used as the RTC_AF2 pin\r
+ (#) PC1 can be used as the RTC_AF3 pin\r
+ \r
+ ##### Backup Domain Reset #####\r
+ ==================================================================\r
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register \r
+ to their reset values. The BKPSRAM is not affected by this reset. The only\r
+ way to reset the BKPSRAM is through the Flash interface by requesting \r
+ a protection level change from 1 to 0.\r
+ [..] A backup domain reset is generated when one of the following events occurs:\r
+ (#) Software reset, triggered by setting the BDRST bit in the \r
+ RCC Backup domain control register (RCC_BDCR). \r
+ (#) VDD or VBAT power on, if both supplies have previously been powered off. \r
+\r
+ ##### Backup Domain Access #####\r
+ ==================================================================\r
+ [..] After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted write \r
+ accesses. \r
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __PWR_CLK_ENABLE() function.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.\r
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.\r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==================================================================\r
+ [..] \r
+ (+) Enable the RTC domain access (see description in the section above).\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r
+ format using the HAL_RTC_Init() function.\r
+ \r
+ *** Time and Date configuration ***\r
+ ===================================\r
+ [..] \r
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() \r
+ and HAL_RTC_SetDate() functions.\r
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. \r
+ \r
+ *** Alarm configuration ***\r
+ ===========================\r
+ [..]\r
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. \r
+ You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.\r
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.\r
+ \r
+ ##### RTC and low power modes #####\r
+ ==================================================================\r
+ [..] The MCU can be woken up from a low power mode by an RTC alternate \r
+ function.\r
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r
+ These RTC alternate functions can wake up the system from the Stop and \r
+ Standby low power modes.\r
+ [..] The system can also wake up from low power modes without depending \r
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r
+ or the RTC wakeup events.\r
+ [..] The RTC provides a programmable time base for waking up from the \r
+ Stop or Standby mode at regular intervals.\r
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source\r
+ is LSE or LSI.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC RTC\r
+ * @brief RTC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Functions RTC Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RTC_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to initialize and configure the \r
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable \r
+ RTC registers Write protection, enter and exit the RTC initialization mode, \r
+ RTC registers synchronization check and reference clock detection enable.\r
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. \r
+ It is split into 2 programmable prescalers to minimize power consumption.\r
+ (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.\r
+ (++) When both prescalers are used, it is recommended to configure the \r
+ asynchronous prescaler to a high value to minimize power consumption.\r
+ (#) All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+ (#) To configure the RTC Calendar, user application should enter \r
+ initialization mode. In this mode, the calendar counter is stopped \r
+ and its value can be updated. When the initialization sequence is \r
+ complete, the calendar restarts counting after 4 RTCCLK cycles.\r
+ (#) To read the calendar through the shadow registers after Calendar \r
+ initialization, calendar update or after wakeup from low power modes \r
+ the software must first clear the RSF flag. The software must then \r
+ wait until it is set again before reading the calendar, which means \r
+ that the calendar registers have been correctly copied into the \r
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function \r
+ implements the above software sequence (RSF clear and RSF check).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the RTC peripheral \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Check the RTC peripheral state */\r
+ if(hrtc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));\r
+ assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));\r
+ assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));\r
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));\r
+ \r
+ if(hrtc->State == HAL_RTC_STATE_RESET)\r
+ {\r
+ /* Initialize RTC MSP */\r
+ HAL_RTC_MspInit(hrtc);\r
+ }\r
+ \r
+ /* Set RTC state */ \r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ { \r
+ /* Clear RTC_CR FMT, OSEL and POL Bits */\r
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));\r
+ /* Set RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);\r
+ \r
+ /* Configure the RTC PRER */\r
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);\r
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;\r
+ hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RTC peripheral \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @note This function doesn't reset the RTC Backup Data registers. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r
+\r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ hrtc->Instance->TR = (uint32_t)0x00000000;\r
+ hrtc->Instance->DR = (uint32_t)0x00002101;\r
+ /* Reset All CR bits except CR[2:0] */\r
+ hrtc->Instance->CR &= (uint32_t)0x00000007;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till WUTWF flag is set and if Time out is reached exit */\r
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Reset all RTC CR register bits */\r
+ hrtc->Instance->CR &= (uint32_t)0x00000000;\r
+ hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;\r
+ hrtc->Instance->PRER = (uint32_t)0x007F00FF;\r
+ hrtc->Instance->ALRMAR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMBR = (uint32_t)0x00000000;\r
+ hrtc->Instance->SHIFTR = (uint32_t)0x00000000;\r
+ hrtc->Instance->CALR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;\r
+ hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset ISR register and exit initialization mode */\r
+ hrtc->Instance->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ hrtc->Instance->TAMPCR = 0x00000000;\r
+ \r
+ /* Reset Option register */\r
+ hrtc->Instance->OR = 0x00000000;\r
+ \r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* De-Initialize RTC MSP */\r
+ HAL_RTC_MspDeInit(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC MSP.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the RTC MSP.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 RTC Time and Date functions\r
+ * @brief RTC Time and Date functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Time and Date functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Time and Date features\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets RTC current time.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTime: Pointer to Time structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sTime->Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sTime->TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sTime->Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));\r
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));\r
+ \r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \\r
+ (((uint32_t)sTime->TimeFormat) << 16)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); \r
+ } \r
+ else\r
+ {\r
+ sTime->TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));\r
+ tmpreg = (((uint32_t)(sTime->Hours) << 16) | \\r
+ ((uint32_t)(sTime->Minutes) << 8) | \\r
+ ((uint32_t)sTime->Seconds) | \\r
+ ((uint32_t)(sTime->TimeFormat) << 16)); \r
+ }\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+ \r
+ /* Clear the bits to be configured */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;\r
+ \r
+ /* Configure the RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets RTC current time.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTime: Pointer to Time structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Get subseconds values from the correspondent registers*/\r
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);\r
+\r
+ /* Get the TR register */\r
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+ \r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ /* Convert the time structure parameters to Binary format */\r
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);\r
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);\r
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets RTC current date.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sDate: Pointer to date structure\r
+ * @param Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r
+{\r
+ uint32_t datetmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY; \r
+ \r
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))\r
+ {\r
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);\r
+ }\r
+ \r
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ { \r
+ assert_param(IS_RTC_YEAR(sDate->Year));\r
+ assert_param(IS_RTC_MONTH(sDate->Month));\r
+ assert_param(IS_RTC_DATE(sDate->Date)); \r
+ \r
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \\r
+ ((uint32_t)sDate->WeekDay << 13)); \r
+ }\r
+ else\r
+ { \r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));\r
+ datetmpreg = RTC_Bcd2ToByte(sDate->Month);\r
+ assert_param(IS_RTC_MONTH(datetmpreg));\r
+ datetmpreg = RTC_Bcd2ToByte(sDate->Date);\r
+ assert_param(IS_RTC_DATE(datetmpreg));\r
+ \r
+ datetmpreg = ((((uint32_t)sDate->Year) << 16) | \\r
+ (((uint32_t)sDate->Month) << 8) | \\r
+ ((uint32_t)sDate->Date) | \\r
+ (((uint32_t)sDate->WeekDay) << 13)); \r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ \r
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY ;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets RTC current date.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sDate: Pointer to Date structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r
+{\r
+ uint32_t datetmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ \r
+ /* Get the DR register */\r
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ { \r
+ /* Convert the date structure parameters to Binary format */\r
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);\r
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);\r
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 RTC Alarm functions\r
+ * @brief RTC Alarm functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Alarm functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Alarm feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Sets the specified RTC Alarm.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Alarm structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ \r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ \r
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ \r
+ /* Configure the Alarm A or Alarm B Sub Second registers */\r
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the Alarm register */\r
+ if(sAlarm->Alarm == RTC_ALARM_A)\r
+ {\r
+ /* Disable the Alarm A interrupt */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm A Sub Second register */\r
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMA_ENABLE(hrtc);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Alarm B interrupt */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ } \r
+ \r
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm B Sub Second register */\r
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMB_ENABLE(hrtc); \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified RTC Alarm with Interrupt \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Alarm structure\r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()). \r
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r
+ }\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ else\r
+ {\r
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r
+ } \r
+ else\r
+ {\r
+ sAlarm->AlarmTime.TimeFormat = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r
+ \r
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ }\r
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\r
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \\r
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\r
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\r
+ ((uint32_t)sAlarm->AlarmMask)); \r
+ }\r
+ /* Configure the Alarm A or Alarm B Sub Second registers */\r
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Configure the Alarm register */\r
+ if(sAlarm->Alarm == RTC_ALARM_A)\r
+ {\r
+ /* Disable the Alarm A interrupt */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+\r
+ /* Clear flag alarm A */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm A Sub Second register */\r
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMA_ENABLE(hrtc);\r
+ /* Configure the Alarm interrupt */\r
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Alarm B interrupt */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+\r
+ /* Clear flag alarm B */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+\r
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r
+ /* Configure the Alarm B Sub Second register */\r
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r
+ /* Configure the Alarm state: Enable Alarm */\r
+ __HAL_RTC_ALARMB_ENABLE(hrtc);\r
+ /* Configure the Alarm interrupt */\r
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);\r
+ }\r
+\r
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactive the specified RTC Alarm \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Alarm: Specifies the Alarm.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_ALARM_A: AlarmA\r
+ * @arg RTC_ALARM_B: AlarmB\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALARM(Alarm));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ if(Alarm == RTC_ALARM_A)\r
+ {\r
+ /* AlarmA */\r
+ __HAL_RTC_ALARMA_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* AlarmB */\r
+ __HAL_RTC_ALARMB_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc); \r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief Gets the RTC Alarm value and masks.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sAlarm: Pointer to Date structure\r
+ * @param Alarm: Specifies the Alarm.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_ALARM_A: AlarmA\r
+ * @arg RTC_ALARM_B: AlarmB \r
+ * @param Format: Specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg FORMAT_BIN: Binary data format \r
+ * @arg FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)\r
+{\r
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+ assert_param(IS_RTC_ALARM(Alarm));\r
+ \r
+ if(Alarm == RTC_ALARM_A)\r
+ {\r
+ /* AlarmA */\r
+ sAlarm->Alarm = RTC_ALARM_A;\r
+ \r
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);\r
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);\r
+ }\r
+ else\r
+ {\r
+ sAlarm->Alarm = RTC_ALARM_B;\r
+ \r
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);\r
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);\r
+ }\r
+ \r
+ /* Fill the structure with the read parameters */\r
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);\r
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);\r
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));\r
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;\r
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);\r
+ \r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);\r
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);\r
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Alarm interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)\r
+{ \r
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)\r
+ {\r
+ /* AlarmA callback */ \r
+ HAL_RTC_AlarmAEventCallback(hrtc);\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);\r
+ }\r
+ }\r
+ \r
+ if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)\r
+ {\r
+ /* AlarmB callback */ \r
+ HAL_RTCEx_AlarmBEventCallback(hrtc);\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's line Flag for RTC Alarm */\r
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief Alarm A callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles AlarmA Polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Alarm interrupt pending bit */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 Peripheral Control functions \r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Wait for RTC Time and Date Synchronization\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Clear RSF flag */\r
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the registers to be synchronised */\r
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTC_Group5 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Get RTC state\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Returns the RTC state.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL state\r
+ */\r
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)\r
+{\r
+ return hrtc->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the\r
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)\r
+{\r
+ uint32_t tickstart = 0; \r
+ \r
+ /* Check if the Initialization mode is set */\r
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted\r
+ * @retval Converted byte\r
+ */\r
+uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint32_t bcdhigh = 0;\r
+ \r
+ while(Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Converts from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted\r
+ * @retval Converted word\r
+ */\r
+uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint32_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rtc_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief RTC HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Real Time Clock (RTC) Extension peripheral:\r
+ * + RTC Time Stamp functions\r
+ * + RTC Tamper functions \r
+ * + RTC Wake-up functions\r
+ * + Extension Control functions\r
+ * + Extension RTC features functions \r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (+) Enable the RTC domain access.\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r
+ format using the HAL_RTC_Init() function.\r
+ \r
+ *** RTC Wakeup configuration ***\r
+ ================================\r
+ [..] \r
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()\r
+ function. You can also configure the RTC Wakeup timer in interrupt mode \r
+ using the HAL_RTC_SetWakeUpTimer_IT() function.\r
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() \r
+ function.\r
+ \r
+ *** TimeStamp configuration ***\r
+ ===============================\r
+ [..]\r
+ (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.\r
+ You can also configure the RTC TimeStamp with interrupt mode using the\r
+ HAL_RTC_SetTimeStamp_IT() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r
+ function.\r
+\r
+ *** Internal TimeStamp configuration ***\r
+ ===============================\r
+ [..]\r
+ (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r
+ function.\r
+ \r
+ *** Tamper configuration ***\r
+ ============================\r
+ [..]\r
+ (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge \r
+ or Level according to the Tamper filter (if equal to 0 Edge else Level) \r
+ value, sampling frequency, NoErase, MaskFlag, precharge or discharge and\r
+ Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper\r
+ with interrupt mode using HAL_RTC_SetTamper_IT() function.\r
+ (+) The default configuration of the Tamper erases the backup registers. To avoid\r
+ erase, enable the NoErase field on the RTC_TAMPCR register.\r
+ \r
+ *** Backup Data Registers configuration ***\r
+ ===========================================\r
+ [..]\r
+ (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()\r
+ function. \r
+ (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()\r
+ function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTCEx RTCEx \r
+ * @brief RTC Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTCEx_Exported_Functions RTC Extended Exported Functions\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions\r
+ * @brief RTC TimeStamp and Tamper functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC TimeStamp and Tamper functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure TimeStamp feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets TimeStamp.\r
+ * @note This API must be called before enabling the TimeStamp feature. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the \r
+ * rising edge of the related pin.\r
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. \r
+ * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ tmpreg|= TimeStampEdge;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r
+ hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets TimeStamp with Interrupt. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @note This API must be called before enabling the TimeStamp feature.\r
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the \r
+ * rising edge of the related pin.\r
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r
+ * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. \r
+ * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ tmpreg |= TimeStampEdge;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r
+ hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r
+ \r
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r
+ \r
+ /* Enable IT timestamp */ \r
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);\r
+ \r
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates TimeStamp. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);\r
+ \r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+ \r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ hrtc->Instance->CR = (uint32_t)tmpreg;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Internal TimeStamp.\r
+ * @note This API must be called before enabling the internal TimeStamp feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the internal Time Stamp Enable bits */\r
+ __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates internal TimeStamp.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Configure the internal Time Stamp Enable bits */\r
+ __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hrtc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC TimeStamp value.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTimeStamp: Pointer to Time structure\r
+ * @param sTimeStampDate: Pointer to Date structure \r
+ * @param Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * FORMAT_BIN: Binary data format \r
+ * FORMAT_BCD: BCD data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;\r
+ \r
+ /* Fill the Date structure fields with the read parameters */\r
+ sTimeStampDate->Year = 0;\r
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if(Format == RTC_FORMAT_BIN)\r
+ {\r
+ /* Convert the TimeStamp structure parameters to Binary format */\r
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);\r
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);\r
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);\r
+ \r
+ /* Convert the DateTimeStamp structure parameters to Binary format */\r
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);\r
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);\r
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);\r
+ }\r
+ \r
+ /* Clear the TIMESTAMP Flag */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Tamper\r
+ * @note By calling this API we disable the tamper interrupt for all tampers. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTamper: Pointer to Tamper Structure.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); \r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r
+ { \r
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r
+ } \r
+ \r
+ if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r
+ { \r
+ sTamper->NoErase = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r
+ }\r
+ }\r
+\r
+ if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r
+ {\r
+ sTamper->MaskFlag = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r
+ }\r
+ }\r
+ \r
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\\r
+ (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\r
+ (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r
+\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\r
+ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\r
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r
+\r
+ hrtc->Instance->TAMPCR |= tmpreg; \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+\r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets Tamper with interrupt.\r
+ * @note By calling this API we force the tamper interrupt for all tampers.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param sTamper: Pointer to RTC Tamper.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r
+ assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));\r
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r
+ assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r
+ assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); \r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Configure the tamper trigger */\r
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r
+ { \r
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r
+ } \r
+ \r
+ if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r
+ { \r
+ sTamper->NoErase = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r
+ }\r
+ }\r
+\r
+ if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r
+ {\r
+ sTamper->MaskFlag = 0;\r
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r
+ }\r
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r
+ }\r
+ }\r
+ \r
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\\r
+ (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\r
+ (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r
+ \r
+ hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\r
+ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\r
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\r
+ (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r
+\r
+ hrtc->Instance->TAMPCR |= tmpreg;\r
+\r
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r
+\r
+ EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates Tamper.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Tamper: Selected tamper pin.\r
+ * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)\r
+{\r
+ assert_param(IS_RTC_TAMPER(Tamper)); \r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+/* Disable the selected Tamper pin */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;\r
+\r
+ if ((Tamper & RTC_TAMPER_1) != 0)\r
+ {\r
+ /* Disable the Tamper1 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);\r
+ }\r
+ if ((Tamper & RTC_TAMPER_2) != 0)\r
+ {\r
+ /* Disable the Tamper2 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);\r
+ }\r
+ if ((Tamper & RTC_TAMPER_3) != 0)\r
+ {\r
+ /* Disable the Tamper2 interrupt */\r
+ hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);\r
+ } \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles TimeStamp interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)\r
+{ \r
+ if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)\r
+ {\r
+ /* TIMESTAMP callback */ \r
+ HAL_RTCEx_TimeStampEventCallback(hrtc);\r
+\r
+ /* Clear the TIMESTAMP interrupt pending bit */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper1EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper2EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);\r
+ }\r
+ }\r
+\r
+ /* Get the status of the Interrupt */\r
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)\r
+ {\r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\r
+ (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))\r
+ {\r
+ /* Tamper callback */\r
+ HAL_RTCEx_Tamper3EventCallback(hrtc);\r
+\r
+ /* Clear the Tamper interrupt pending bit */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief TimeStamp callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_TimeStampEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 1 callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_Tamper1EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 2 callback. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_Tamper2EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tamper 3 callback. \r
+ * @param hrtc: RTC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles TimeStamp polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)\r
+ { \r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)\r
+ {\r
+ /* Clear the TIMESTAMP OverRun Flag */\r
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);\r
+ \r
+ /* Change TIMESTAMP state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR; \r
+ \r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+ \r
+/**\r
+ * @brief This function handles Tamper1 Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles Tamper2 Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Tamper3 Polling.\r
+ * @param hrtc: RTC handle\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ /* Get the status of the Interrupt */\r
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Clear the Tamper Flag */\r
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);\r
+\r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RTCEx_Group2 RTC Wake-up functions\r
+ * @brief RTC Wake-up functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RTC Wake-up functions #####\r
+ =============================================================================== \r
+ \r
+ [..] This section provides functions allowing to configure Wake-up feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets wake up timer. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param WakeUpCounter: Wake up counter\r
+ * @param WakeUpClock: Wake up clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+ \r
+ /* Configure the clock source */\r
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r
+ \r
+ /* Enable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); \r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets wake up timer with interrupt\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param WakeUpCounter: Wake up counter\r
+ * @param WakeUpClock: Wake up clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Configure the Wakeup Timer counter */\r
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r
+\r
+ /* Clear the Wakeup Timer clock source bits in CR register */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r
+\r
+ /* Configure the clock source */\r
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r
+ \r
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */\r
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();\r
+ \r
+ EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;\r
+ \r
+ /* Configure the Interrupt in the RTC_CR register */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);\r
+ \r
+ /* Enable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates wake up timer counter.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Disable the Wakeup Timer */\r
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r
+ \r
+ /* In case of interrupt mode is used, the interrupt source must disabled */ \r
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Gets wake up timer counter.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval Counter value\r
+ */\r
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* Get the counter value */\r
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); \r
+}\r
+\r
+/**\r
+ * @brief This function handles Wake Up Timer interrupt request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)\r
+{ \r
+ if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))\r
+ {\r
+ /* Get the status of the Interrupt */\r
+ if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)\r
+ {\r
+ /* WAKEUPTIMER callback */ \r
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);\r
+ \r
+ /* Clear the WAKEUPTIMER interrupt pending bit */\r
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r
+ }\r
+ }\r
+ \r
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */\r
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+}\r
+\r
+/**\r
+ * @brief Wake Up Timer callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Wake Up Timer Polling.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the WAKEUPTIMER Flag */\r
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTCEx_Group3 Extension Peripheral Control functions \r
+ * @brief Extension Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extension Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Write a data in a specified RTC Backup data register\r
+ (+) Read a data in a specified RTC Backup data register\r
+ (+) Set the Coarse calibration parameters.\r
+ (+) Deactivate the Coarse calibration parameters\r
+ (+) Set the Smooth calibration parameters.\r
+ (+) Configure the Synchronization Shift Control Settings.\r
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ (+) Enable the RTC reference clock detection.\r
+ (+) Disable the RTC reference clock detection.\r
+ (+) Enable the Bypass Shadow feature.\r
+ (+) Disable the Bypass Shadow feature.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param BackupRegister: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(BackupRegister));\r
+ \r
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r
+ tmp += (BackupRegister * 4);\r
+ \r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param BackupRegister: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval Read value\r
+ */\r
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(BackupRegister));\r
+\r
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r
+ tmp += (BackupRegister * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @brief Sets the Smooth calibration parameters.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param SmoothCalibPeriod: Select the Smooth Calibration Period.\r
+ * This parameter can be can be one of the following values :\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.\r
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.\r
+ * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.\r
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.\r
+ * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r
+ * This parameter can be one any value from 0 to 0x000001FF.\r
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses \r
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field \r
+ * SmouthCalibMinusPulsesValue must be equal to 0. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* check if a calibration is pending*/\r
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* check if a calibration is pending*/\r
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Configure the Smooth calibration settings */\r
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Synchronization Shift Control Settings.\r
+ * @note When REFCKON is set, firmware must not write to Shift control register. \r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.\r
+ * This parameter can be one of the following values :\r
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. \r
+ * @arg RTC_SHIFTADD1S_RESET: No effect.\r
+ * @param ShiftSubFS: Select the number of Second Fractions to substitute.\r
+ * This parameter can be one any value from 0 to 0x7FFF.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));\r
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));\r
+\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until the shift is completed*/\r
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r
+ { \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Check if the reference clock detection is disabled */\r
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)\r
+ {\r
+ /* Configure the Shift settings */\r
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);\r
+ \r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_ERROR; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @param CalibOutput: Select the Calibration output Selection .\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. \r
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));\r
+ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Clear flags before config */\r
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;\r
+ \r
+ /* Configure the RTC_CR register */\r
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;\r
+ \r
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the RTC reference clock detection.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);\r
+\r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the RTC reference clock detection.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)\r
+{ \r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set Initialization mode */\r
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r
+ \r
+ /* Set RTC state*/\r
+ hrtc->State = HAL_RTC_STATE_ERROR;\r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_ERROR;\r
+ } \r
+ else\r
+ {\r
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);\r
+ \r
+ /* Exit Initialization mode */\r
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Bypass Shadow feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Set the BYPSHAD bit */\r
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Bypass Shadow feature.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC. \r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)\r
+{\r
+ /* Process Locked */ \r
+ __HAL_LOCK(hrtc);\r
+ \r
+ hrtc->State = HAL_RTC_STATE_BUSY;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r
+ \r
+ /* Reset the BYPSHAD bit */\r
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ /* Process Unlocked */ \r
+ __HAL_UNLOCK(hrtc);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTCEx_Group4 Extended features functions \r
+ * @brief Extended features functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) RTC Alram B callback\r
+ (+) RTC Poll for Alarm B request\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Alarm B callback.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @retval None\r
+ */\r
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RTC_AlarmBEventCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief This function handles AlarmB Polling request.\r
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains\r
+ * the configuration information for RTC.\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0; \r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Clear the Alarm Flag */\r
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r
+ \r
+ /* Change RTC state */\r
+ hrtc->State = HAL_RTC_STATE_READY; \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SAI HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Serial Audio Interface (SAI) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ \r
+ [..]\r
+ The SAI HAL driver can be used as follows:\r
+ \r
+ (#) Declare a SAI_HandleTypeDef handle structure.\r
+ (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:\r
+ (##) Enable the SAI interface clock. \r
+ (##) SAI pins configuration:\r
+ (+++) Enable the clock for the SAI GPIOs.\r
+ (+++) Configure these SAI pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()\r
+ and HAL_SAI_Receive_IT() APIs):\r
+ (+++) Configure the SAI interrupt priority.\r
+ (+++) Enable the NVIC SAI IRQ handle.\r
+\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()\r
+ and HAL_SAI_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r
+ DMA Tx/Rx Stream.\r
+ \r
+ (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity\r
+ using HAL_SAI_Init() function.\r
+ \r
+ -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)\r
+ will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()\r
+ inside the transmit and receive process. \r
+\r
+ [..] \r
+ (@) SAI Clock Source, the configuration is managed through RCCEx_PeriphCLKConfig()\r
+ function in the HAL RCC drivers \r
+ [..] \r
+ (@) Make sure that either:\r
+ (+@) I2S PLL is configured or \r
+ (+@) SAI PLL is configured or \r
+ (+@) External clock source is configured after setting correctly \r
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. \r
+ \r
+ [..] \r
+ (@) In master Tx mode: enabling the audio block immediately generates the bit clock \r
+ for the external slaves even if there is no data in the FIFO, However FS signal \r
+ generation is conditioned by the presence of data in the FIFO.\r
+ \r
+ [..] \r
+ (@) In master Rx mode: enabling the audio block immediately generates the bit clock \r
+ and FS signal for the external slaves. \r
+ \r
+ [..] \r
+ (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: \r
+ (+@) First bit Offset <= (SLOT size - Data size)\r
+ (+@) Data size <= SLOT size\r
+ (+@) Number of SLOT x SLOT size = Frame length\r
+ (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. \r
+\r
+ [..] \r
+ Three operation modes are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() \r
+ (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT() \r
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT() \r
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback\r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA() \r
+ (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA() \r
+ (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_RxCpltCallback \r
+ (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SAI_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_SAI_DMAPause() \r
+ (+) Resume the DMA Transfer using HAL_SAI_DMAResume() \r
+ (+) Stop the DMA Transfer using HAL_SAI_DMAStop() \r
+ \r
+ *** SAI HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in USART HAL driver :\r
+ \r
+ (+) __HAL_SAI_ENABLE: Enable the SAI peripheral\r
+ (+) __HAL_SAI_DISABLE: Disable the SAI peripheral\r
+ (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts\r
+ (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts\r
+ (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is \r
+ enabled or disabled\r
+ (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAI SAI\r
+ * @brief SAI HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Typedefs SAI Private Typedefs\r
+ * @{\r
+ */\r
+typedef enum {\r
+ SAI_MODE_DMA,\r
+ SAI_MODE_IT\r
+}SAI_ModeTypedef;\r
+/**\r
+ * @}\r
+ */\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup SAI_Private_Constants SAI Private Constants\r
+ * @{\r
+ */\r
+#define SAI_FIFO_SIZE 8\r
+#define SAI_DEFAULT_TIMEOUT 4\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* SAI registers Masks */\r
+#define CR1_CLEAR_MASK ((uint32_t)0xFF04C010)\r
+#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000)\r
+#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020)\r
+\r
+#define SAI_TIMEOUT_VALUE 10\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);\r
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);\r
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r
+\r
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);\r
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);\r
+\r
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Exported_Functions SAI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the SAIx peripheral:\r
+\r
+ (+) User must implement HAL_SAI_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_SAI_Init() to configure the selected device with \r
+ the selected configuration:\r
+ (++) Mode (Master/slave TX/RX)\r
+ (++) Protocol \r
+ (++) Data Size\r
+ (++) MCLK Output\r
+ (++) Audio frequency\r
+ (++) FIFO Threshold\r
+ (++) Frame Config\r
+ (++) Slot Config\r
+\r
+ (+) Call the function HAL_SAI_DeInit() to restore the default configuration \r
+ of the selected SAI peripheral. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the structure FrameInit, SlotInit and the low part of \r
+ * Init according to the specified parameters and call the function\r
+ * HAL_SAI_Init to initialize the SAI block.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains \r
+ * the configuration information for SAI module.\r
+ * @param protocol : one of the supported protocol @ref SAI_Protocol\r
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * the configuration information for SAI module.\r
+ * @param nbslot : Number of slot.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));\r
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));\r
+ \r
+ switch(protocol)\r
+ {\r
+ case SAI_I2S_STANDARD :\r
+ case SAI_I2S_MSBJUSTIFIED :\r
+ case SAI_I2S_LSBJUSTIFIED :\r
+ status = SAI_InitI2S(hsai, protocol, datasize, nbslot);\r
+ break; \r
+ case SAI_PCM_LONG :\r
+ case SAI_PCM_SHORT :\r
+ status = SAI_InitPCM(hsai, protocol, datasize, nbslot);\r
+ break;\r
+ default :\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ status = HAL_SAI_Init(hsai);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SAI according to the specified parameters \r
+ * in the SAI_InitTypeDef and create the associated handle.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)\r
+{ \r
+ uint32_t tmpclock = 0;\r
+\r
+ /* This variable used to store the SAI_CK_x (value in Hz) */\r
+ uint32_t freq = 0;\r
+ \r
+ /* Check the SAI handle allocation */\r
+ if(hsai == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the SAI Block parameters */\r
+ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); \r
+ assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));\r
+ assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));\r
+ assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));\r
+ assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));\r
+ assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));\r
+ assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));\r
+ assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));\r
+ assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));\r
+ assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));\r
+ assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));\r
+ assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));\r
+ assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));\r
+ assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));\r
+ \r
+ /* Check the SAI Block Frame parameters */\r
+ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));\r
+ assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));\r
+ assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));\r
+ assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));\r
+ assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));\r
+ \r
+ /* Check the SAI Block Slot parameters */\r
+ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));\r
+ assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));\r
+ assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));\r
+ assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hsai->Lock = HAL_UNLOCKED;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_SAI_MspInit(hsai);\r
+ }\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY;\r
+ \r
+ /* Disable the selected SAI peripheral */\r
+ SAI_Disable(hsai);\r
+ \r
+ /* SAI Block Synchro Configuration -----------------------------------------*/\r
+ SAI_BlockSynchroConfig(hsai);\r
+ \r
+ /* Configure Master Clock using the following formula :\r
+ MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS\r
+ FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256\r
+ MCKDIV[3:0] = SAI_CK_x / FS * 512 */\r
+ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)\r
+ { \r
+ /* Get SAI clock source based on Source clock selection from RCC */\r
+ freq = SAI_GetInputClock(hsai);\r
+ \r
+ /* (saiclocksource x 10) to keep Significant digits */\r
+ tmpclock = (((freq * 10) / ((hsai->Init.AudioFrequency) * 512)));\r
+ \r
+ hsai->Init.Mckdiv = tmpclock / 10;\r
+ \r
+ /* Round result to the nearest integer */\r
+ if((tmpclock % 10) > 8) \r
+ {\r
+ hsai->Init.Mckdiv+= 1;\r
+ }\r
+ }\r
+\r
+ /* SAI Block Configuration ------------------------------------------------------------*/\r
+ /* SAI CR1 Configuration */\r
+ hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \\r
+ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\\r
+ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \\r
+ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);\r
+ \r
+ hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol | \\r
+ hsai->Init.DataSize | hsai->Init.FirstBit | \\r
+ hsai->Init.ClockStrobing | hsai->Init.Synchro | \\r
+ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \\r
+ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | hsai->Init.CompandingMode); \r
+ \r
+ /* SAI CR2 Configuration */\r
+ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP);\r
+ hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);\r
+\r
+\r
+ /* SAI Frame Configuration -----------------------------------------*/\r
+ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \\r
+ SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF));\r
+ hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | \r
+ hsai->FrameInit.FSOffset | \r
+ hsai->FrameInit.FSDefinition | \r
+ hsai->FrameInit.FSPolarity | \r
+ ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); \r
+ \r
+ /* SAI Block_x SLOT Configuration ------------------------------------------*/\r
+ /* This register has no meaning in AC\9297 and SPDIF audio protocol */\r
+ hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \\r
+ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));\r
+ \r
+ hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize\r
+ | hsai->SlotInit.SlotActive | ((hsai->SlotInit.SlotNumber - 1) << 8); \r
+ \r
+ /* Initialise the error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ \r
+ /* Initialize the SAI state */\r
+ hsai->State= HAL_SAI_STATE_READY;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SAI peripheral. \r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Check the SAI handle allocation */\r
+ if(hsai == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hsai->State = HAL_SAI_STATE_BUSY;\r
+\r
+ /* Disabled All interrupt and clear all the flag */\r
+ hsai->Instance->IMR = 0;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFF;\r
+ \r
+ /* Disable the SAI */\r
+ SAI_Disable(hsai);\r
+\r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_SAI_MspDeInit(hsai);\r
+\r
+ /* Initialize the error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ \r
+ /* Initialize the SAI state */\r
+ hsai->State = HAL_SAI_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsai);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SAI MSP Init.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SAI MSP DeInit.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SAI data \r
+ transfers.\r
+\r
+ (+) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the \r
+ dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (+) Blocking mode functions are :\r
+ (++) HAL_SAI_Transmit()\r
+ (++) HAL_SAI_Receive()\r
+ (++) HAL_SAI_TransmitReceive()\r
+ \r
+ (+) Non Blocking mode functions with Interrupt are :\r
+ (++) HAL_SAI_Transmit_IT()\r
+ (++) HAL_SAI_Receive_IT()\r
+ (++) HAL_SAI_TransmitReceive_IT()\r
+\r
+ (+) Non Blocking mode functions with DMA are :\r
+ (++) HAL_SAI_Transmit_DMA()\r
+ (++) HAL_SAI_Receive_DMA()\r
+ (++) HAL_SAI_TransmitReceive_DMA()\r
+\r
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_SAI_TxCpltCallback()\r
+ (++) HAL_SAI_RxCpltCallback()\r
+ (++) HAL_SAI_ErrorCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits an amount of data in blocking mode.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ hsai->pBuffPtr = pData;\r
+ \r
+ /* Check if the SAI is already enabled */ \r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* fill the fifo with data before to enabled the SAI */\r
+ SAI_FillFifo(hsai); \r
+ /* Enable SAI peripheral */ \r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ while(hsai->XferCount > 0)\r
+ { \r
+ /* Write data if the FIFO is not full */\r
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ { \r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 2; \r
+ }\r
+ else\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 4;\r
+ } \r
+ hsai->XferCount--; \r
+ }\r
+ else\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick(); \r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ /* Change the SAI state */\r
+ hsai->State = HAL_SAI_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ } \r
+ \r
+ hsai->State = HAL_SAI_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in blocking mode. \r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+ hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ \r
+ /* Check if the SAI is already enabled */ \r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* Enable SAI peripheral */ \r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ /* Receive data */\r
+ while(hsai->XferCount > 0)\r
+ {\r
+ \r
+ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r
+ hsai->pBuffPtr+= 2;\r
+ }\r
+ else\r
+ {\r
+ *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r
+ hsai->pBuffPtr+= 4;\r
+ } \r
+ hsai->XferCount--; \r
+ }\r
+ else\r
+ {\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ /* Change the SAI state */\r
+ hsai->State = HAL_SAI_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ } \r
+ \r
+ hsai->State = HAL_SAI_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits an amount of data in no-blocking mode with Interrupt.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+ \r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;\r
+ }\r
+ else\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;\r
+ }\r
+ \r
+ /* Enable FRQ and OVRUDR interrupts */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Check if the SAI is already enabled */ \r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* Fill the fifo before starting the communication */\r
+ SAI_FillFifo(hsai);\r
+ \r
+ /* Enable SAI peripheral */ \r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in no-blocking mode with Interrupt.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+ \r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;\r
+ }\r
+ else\r
+ {\r
+ hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;\r
+ } \r
+ /* Enable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Check if the SAI is already enabled */ \r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* Enable SAI peripheral */ \r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Pauses the audio stream playing from the Media.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ /* Pause the audio file playing by disabling the SAI DMA requests */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resumes the audio stream playing from the Media.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ /* Enable the SAI DMA requests */\r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+ \r
+ /* If the SAI peripheral is still not enabled, enable it */\r
+ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r
+ {\r
+ /* Enable SAI peripheral */ \r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the audio stream playing from the Media.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ /* Disable the SAI DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+ \r
+ /* Abort the SAI DMA Tx Stream */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hsai->hdmatx);\r
+ }\r
+ /* Abort the SAI DMA Rx Stream */\r
+ if(hsai->hdmarx != NULL)\r
+ { \r
+ HAL_DMA_Abort(hsai->hdmarx);\r
+ }\r
+\r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Abort the current transfer and disbaled the SAI.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Disable the SAI DMA request */\r
+ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r
+ \r
+ /* Abort the SAI DMA Tx Stream */\r
+ if(hsai->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hsai->hdmatx);\r
+ }\r
+ /* Abort the SAI DMA Rx Stream */\r
+ if(hsai->hdmarx != NULL)\r
+ { \r
+ HAL_DMA_Abort(hsai->hdmarx);\r
+ }\r
+\r
+ /* Disabled All interrupt and clear all the flag */\r
+ hsai->Instance->IMR = 0;\r
+ hsai->Instance->CLRFR = 0xFFFFFFFF;\r
+ \r
+ /* Disable SAI peripheral */\r
+ SAI_Disable(hsai);\r
+ \r
+ /* Flush the fifo */\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Transmits an amount of data in no-blocking mode with DMA.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ { \r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_TX;\r
+ \r
+ /* Set the SAI Tx DMA Half transfer complete callback */\r
+ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;\r
+ \r
+ /* Set the SAI TxDMA transfer complete callback */\r
+ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hsai->hdmatx->XferErrorCallback = SAI_DMAError;\r
+ \r
+ /* Enable the Tx DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize);\r
+ \r
+ /* Check if the SAI is already enabled */ \r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ /* Enable the interrupts for error handling */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ /* Enable SAI Tx DMA Request */ \r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data in no-blocking mode with DMA. \r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ if(hsai->State == HAL_SAI_STATE_READY)\r
+ { \r
+ hsai->pBuffPtr = pData;\r
+ hsai->XferSize = Size;\r
+ hsai->XferCount = Size;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsai);\r
+ \r
+ hsai->State = HAL_SAI_STATE_BUSY_RX;\r
+ \r
+ /* Set the SAI Rx DMA Half transfer complete callback */\r
+ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;\r
+ \r
+ /* Set the SAI Rx DMA transfer complete callback */\r
+ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hsai->hdmarx->XferErrorCallback = SAI_DMAError;\r
+ \r
+ /* Enable the Rx DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize);\r
+ \r
+ /* Check if the SAI is already enabled */\r
+ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)\r
+ {\r
+ /* Enable SAI peripheral */\r
+ __HAL_SAI_ENABLE(hsai);\r
+ }\r
+ \r
+ /* Enable the interrupts for error handling */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ /* Enable SAI Rx DMA Request */\r
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsai);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the tx mute mode.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param val : value sent during the mute @ref SAI_Block_Mute_Value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)\r
+{\r
+ assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));\r
+ \r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Disable the tx mute mode.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Enable the rx mute detection.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param callback : function called when the mute is detected\r
+ * @param counter : number a data before mute detection max 63.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)\r
+{\r
+ assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));\r
+ \r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ /* set the mute counter */\r
+ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);\r
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << 6));\r
+ hsai->mutecallback = callback;\r
+ /* enable the IT interrupt */\r
+ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief Disable the rx mute detection.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)\r
+{\r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ /* set the mutecallback to NULL */\r
+ hsai->mutecallback = (SAIcallback)NULL;\r
+ /* enable the IT interrupt */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);\r
+ return HAL_OK;\r
+ }\r
+ return HAL_ERROR;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SAI interrupt request.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL status\r
+ */\r
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)\r
+{ \r
+ if(hsai->State != HAL_SAI_STATE_RESET)\r
+ {\r
+ uint32_t tmpFlag = hsai->Instance->SR;\r
+ uint32_t tmpItSource = hsai->Instance->IMR; \r
+ \r
+ if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ))\r
+ {\r
+ hsai->InterruptServiceRoutine(hsai);\r
+ }\r
+ \r
+ /* check the flag only if one of them is set */\r
+ if(tmpFlag != 0x00000000)\r
+ {\r
+ /* SAI Overrun error interrupt occurred ----------------------------------*/\r
+ if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))\r
+ {\r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);\r
+ /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ \r
+ /* SAI mutedet interrupt occurred ----------------------------------*/\r
+ if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))\r
+ {\r
+ /* Clear the SAI mutedet flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);\r
+ /* call the call back function */\r
+ if(hsai->mutecallback != (SAIcallback)NULL)\r
+ {\r
+ /* inform the user that an RX mute event has been detected */\r
+ hsai->mutecallback();\r
+ }\r
+ }\r
+ \r
+ /* SAI AFSDET interrupt occurred ----------------------------------*/\r
+ if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_AFSDET;\r
+ HAL_SAI_Abort(hsai);\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ \r
+ /* SAI LFSDET interrupt occurred ----------------------------------*/\r
+ if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_LFSDET;\r
+ HAL_SAI_Abort(hsai);\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+\r
+ /* SAI WCKCFG interrupt occurred ----------------------------------*/\r
+ if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))\r
+ {\r
+ /* Change the SAI error code */\r
+ hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG;\r
+ HAL_SAI_Abort(hsai);\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer Half completed callbacks\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_TxHalfCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer half completed callbacks\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SAI error callbacks.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SAI_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the SAI state.\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)\r
+{\r
+ return hsai->State;\r
+}\r
+\r
+/**\r
+* @brief Return the SAI error code\r
+* @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SAI Block.\r
+* @retval SAI Error Code\r
+*/\r
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)\r
+{\r
+ return hsai->ErrorCode;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SAI I2S protocol according to the specified parameters \r
+ * in the SAI_InitTypeDef and create the associated handle.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param protocol : one of the supported protocol\r
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * the configuration information for SAI module.\r
+ * @param nbslot : number of slot minimum value is 2 and max is 16. \r
+ * the value must be a multiple of 2.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));\r
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));\r
+ \r
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;\r
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;\r
+ hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;\r
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;\r
+ hsai->SlotInit.FirstBitOffset = 0;\r
+ hsai->SlotInit.SlotNumber = nbslot;\r
+ \r
+ /* in IS2 the number of slot must be even */\r
+ if((nbslot & 0x1) != 0 )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ switch(protocol)\r
+ {\r
+ case SAI_I2S_STANDARD :\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;\r
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+ break;\r
+ case SAI_I2S_MSBJUSTIFIED :\r
+ case SAI_I2S_LSBJUSTIFIED :\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r
+ hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Frame definition */\r
+ hsai->Init.DataSize = 0xFFFFFFFF;\r
+ switch(datasize)\r
+ {\r
+ case SAI_PROTOCOL_DATASIZE_16BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 32*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r
+ break; \r
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r
+ if(hsai->Init.DataSize == 0xFFFFFFFF)\r
+ {\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ }\r
+ break; \r
+ case SAI_PROTOCOL_DATASIZE_24BIT:\r
+ if(hsai->Init.DataSize == 0xFFFFFFFF)\r
+ {\r
+ hsai->Init.DataSize = SAI_DATASIZE_24;\r
+ }\r
+ break;\r
+ case SAI_PROTOCOL_DATASIZE_32BIT: \r
+ if(hsai->Init.DataSize == 0xFFFFFFFF)\r
+ {\r
+ hsai->Init.DataSize = SAI_DATASIZE_32;\r
+ }\r
+ hsai->FrameInit.FrameLength = 64*(nbslot/2);\r
+ hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ if(protocol == SAI_I2S_LSBJUSTIFIED)\r
+ {\r
+ if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)\r
+ {\r
+ hsai->SlotInit.FirstBitOffset = 16;\r
+ }\r
+ if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)\r
+ {\r
+ hsai->SlotInit.FirstBitOffset = 8;\r
+ }\r
+ }\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SAI PCM protocol according to the specified parameters \r
+ * in the SAI_InitTypeDef and create the associated handle.\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param protocol : one of the supported protocol\r
+ * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize\r
+ * @param nbslot : number of slot minimum value is 1 and the max is 16.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));\r
+ assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));\r
+\r
+ hsai->Init.Protocol = SAI_FREE_PROTOCOL;\r
+ hsai->Init.FirstBit = SAI_FIRSTBIT_MSB;\r
+ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;\r
+ hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME;\r
+ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r
+ hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;\r
+ hsai->SlotInit.FirstBitOffset = 0;\r
+ hsai->SlotInit.SlotNumber = nbslot;\r
+ hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;\r
+ \r
+ switch(protocol)\r
+ {\r
+ case SAI_PCM_SHORT :\r
+ hsai->FrameInit.ActiveFrameLength = 1;\r
+ break;\r
+ case SAI_PCM_LONG :\r
+ hsai->FrameInit.ActiveFrameLength = 13;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ switch(datasize)\r
+ {\r
+ case SAI_PROTOCOL_DATASIZE_16BIT:\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 16 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r
+ break; \r
+ case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r
+ hsai->Init.DataSize = SAI_DATASIZE_16;\r
+ hsai->FrameInit.FrameLength = 32 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ \r
+ case SAI_PROTOCOL_DATASIZE_32BIT: \r
+ hsai->Init.DataSize = SAI_DATASIZE_32;\r
+ hsai->FrameInit.FrameLength = 32 * nbslot;\r
+ hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r
+ break;\r
+ default :\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Fill the fifo \r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* fill the fifo with data before to enabled the SAI */\r
+ while((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)\r
+ {\r
+ if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r
+ {\r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ }\r
+ else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 2;\r
+ }\r
+ else\r
+ {\r
+ hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r
+ hsai->pBuffPtr+= 4;\r
+ }\r
+ hsai->XferCount--;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief return the interrupt flag to set according the SAI setup \r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @param mode : SAI_MODE_DMA or SAI_MODE_IT\r
+ * @retval the list of the IT flag to enable\r
+ */\r
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)\r
+{\r
+ uint32_t tmpIT = SAI_IT_OVRUDR; \r
+ \r
+ if(mode == SAI_MODE_IT)\r
+ {\r
+ tmpIT|= SAI_IT_FREQ;\r
+ }\r
+ \r
+ if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r
+ {\r
+ tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;\r
+ }\r
+ else\r
+ {\r
+ /* hsai has been configured in master mode */\r
+ tmpIT|= SAI_IT_WCKCFG;\r
+ }\r
+ return tmpIT;\r
+}\r
+\r
+/**\r
+ * @brief disable the SAI and wait the disabling\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ __HAL_SAI_DISABLE(hsai);\r
+ while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)\r
+ { \r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+ \r
+ status = HAL_TIMEOUT;\r
+ \r
+ /* Change the SAI state */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode 8Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = (*hsai->pBuffPtr++);\r
+ hsai->XferCount--;\r
+ \r
+ /* Handle the end of the transmission */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode for 16Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;\r
+ hsai->pBuffPtr+=2;\r
+ hsai->XferCount--;\r
+ \r
+ /* Handle the end of the transmission */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit in Interrupt mode for 32Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Write data on DR register */\r
+ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;\r
+ hsai->pBuffPtr+=4;\r
+ hsai->XferCount--;\r
+ \r
+ /* Handle the end of the transmission */\r
+ if(hsai->XferCount == 0)\r
+ {\r
+ /* Disable FREQ and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode 8Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */ \r
+ (*hsai->pBuffPtr++) = hsai->Instance->DR;\r
+ hsai->XferCount--;\r
+ \r
+ /* Check end of the transfer */ \r
+ if(hsai->XferCount == 0)\r
+ { \r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode for 16Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */ \r
+ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;\r
+ hsai->pBuffPtr+=2;\r
+ hsai->XferCount--;\r
+ \r
+ /* Check end of the transfer */ \r
+ if(hsai->XferCount == 0)\r
+ { \r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai); \r
+ }\r
+}\r
+/**\r
+ * @brief Rx Handler for Receive in Interrupt mode for 32Bit transfer\r
+ * @param hsai : pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module.\r
+ * @retval None.\r
+ */\r
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)\r
+{\r
+ /* Receive data */ \r
+ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;\r
+ hsai->pBuffPtr+=4;\r
+ hsai->XferCount--;\r
+ \r
+ /* Check end of the transfer */ \r
+ if(hsai->XferCount == 0)\r
+ { \r
+ /* Disable TXE and OVRUDR interrupts */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r
+ \r
+ /* Clear the SAI Overrun flag */\r
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ HAL_SAI_RxCpltCallback(hsai); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI transmit process complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ { \r
+ hsai->XferCount = 0;\r
+ \r
+ /* Disable SAI Tx DMA Request */ \r
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */\r
+ /* Wait until FIFO is empty */ \r
+ while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE)\r
+ { \r
+ /* Update error code */\r
+ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r
+ \r
+ /* Change the SAI state */\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ }\r
+ } \r
+ \r
+ /* Stop the interrupts error handling */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ hsai->State= HAL_SAI_STATE_READY;\r
+ }\r
+ HAL_SAI_TxCpltCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI transmit process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_SAI_TxHalfCpltCallback(hsai);\r
+}\r
+\r
+/**\r
+ * @brief DMA SAI receive process complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Rx DMA Request */\r
+ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r
+ hsai->XferCount = 0;\r
+ \r
+ /* Stop the interrupts error handling */\r
+ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r
+ \r
+ hsai->State = HAL_SAI_STATE_READY;\r
+ }\r
+ HAL_SAI_RxCpltCallback(hsai); \r
+}\r
+\r
+/**\r
+ * @brief DMA SAI receive process half complete callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_SAI_RxHalfCpltCallback(hsai); \r
+}\r
+/**\r
+ * @brief DMA SAI communication error callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SAI_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Stop the DMA transfer */\r
+ HAL_SAI_DMAStop(hsai);\r
+ \r
+ /* Set the SAI state ready to be able to start again the process */\r
+ hsai->State= HAL_SAI_STATE_READY;\r
+ HAL_SAI_ErrorCallback(hsai);\r
+ \r
+ hsai->XferCount = 0;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sai_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SAI Extension HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of SAI extension peripheral:\r
+ * + Extension features functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### SAI peripheral extension features #####\r
+ ==============================================================================\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to manage several sources to clock SAI\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAIEx SAIEx\r
+ * @brief SAI Extension HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SAI registers Masks */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SAI_Private_Functions SAI Private Functions\r
+ * @{\r
+ */\r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions \r
+ * @brief Extension features functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extension features Functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the possible \r
+ SAI clock sources.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure SAI Block synchronization mode\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module. \r
+ * @retval SAI Clock Input \r
+ */\r
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)\r
+{\r
+ uint32_t tmpregisterGCR = 0;\r
+ \r
+ /* This setting must be done with both audio block (A & B) disabled */\r
+ switch(hsai->Init.SynchroExt)\r
+ {\r
+ case SAI_SYNCEXT_DISABLE :\r
+ tmpregisterGCR = 0;\r
+ break;\r
+ case SAI_SYNCEXT_IN_ENABLE :\r
+ tmpregisterGCR = SAI_GCR_SYNCIN_0;\r
+ break;\r
+ case SAI_SYNCEXT_OUTBLOCKA_ENABLE :\r
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;\r
+ break;\r
+ case SAI_SYNCEXT_OUTBLOCKB_ENABLE :\r
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+ \r
+ if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))\r
+ {\r
+ SAI1->GCR = tmpregisterGCR;\r
+ }\r
+ else \r
+ {\r
+ SAI2->GCR = tmpregisterGCR;\r
+ }\r
+}\r
+ /**\r
+ * @brief Get SAI Input Clock based on SAI source clock selection\r
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains\r
+ * the configuration information for SAI module. \r
+ * @retval SAI Clock Input \r
+ */\r
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) \r
+{\r
+ /* This variable used to store the SAI_CK_x (value in Hz) */\r
+ uint32_t saiclocksource = 0;\r
+\r
+ if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))\r
+ {\r
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);\r
+ }\r
+ else /* SAI2_Block_A || SAI2_Block_B*/\r
+ {\r
+ saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); \r
+ }\r
+ /* the return result is the value of SAI clock */\r
+ return saiclocksource; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sd.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SD card HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Secure Digital (SD) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver implements a high level communication layer for read and write from/to \r
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by \r
+ the user in HAL_SD_MspInit() function (MSP layer). \r
+ Basically, the MSP layer configuration should be the same as we provide in the \r
+ examples.\r
+ You can easily tailor this configuration according to hardware resources.\r
+\r
+ [..]\r
+ This driver is a generic layered driver for SDMMC memories which uses the HAL \r
+ SDMMC driver functions to interface with SD and uSD cards devices. \r
+ It is used as follows:\r
+ \r
+ (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:\r
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); \r
+ (##) SDMMC pins configuration for SD card\r
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()\r
+ and according to your pin assignment;\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()\r
+ and HAL_SD_WriteBlocks_DMA() APIs).\r
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); \r
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. \r
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.\r
+ (+++) Configure the SDMMC and DMA interrupt priorities using functions\r
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority\r
+ (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()\r
+ (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() \r
+ and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.\r
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()\r
+ and __HAL_SD_SDMMC_CLEAR_IT()\r
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization \r
+\r
+ \r
+ *** SD Card Initialization and configuration ***\r
+ ================================================ \r
+ [..]\r
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes \r
+ the SD Card and put it into StandBy State (Ready for data transfer). \r
+ This function provide the following operations:\r
+ \r
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card \r
+ type (Standard Capacity or High Capacity). You can change or adapt this \r
+ frequency by adjusting the "ClockDiv" field. \r
+ The SD Card frequency (SDMMC_CK) is computed as follows:\r
+ \r
+ SDMMC_CK = SDMMCCLK / (ClockDiv + 2)\r
+ \r
+ In initialization mode and according to the SD Card standard, \r
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.\r
+ \r
+ (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo \r
+ structure. This structure provide also ready computed SD Card capacity \r
+ and Block size.\r
+ \r
+ -@- These information are stored in SD handle structure in case of future use. \r
+ \r
+ (#) Configure the SD Card Data transfer frequency. By Default, the card transfer \r
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting \r
+ the "ClockDiv" field.\r
+ In transfer mode and according to the SD Card standard, make sure that the \r
+ SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.\r
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC \r
+ peripheral in bypass mode. Refer to the corresponding reference manual \r
+ for more details.\r
+ \r
+ (#) Select the corresponding SD Card according to the address read with the step 2.\r
+ \r
+ (#) Configure the SD Card in wide bus mode: 4-bits data.\r
+ \r
+ *** SD Card Read operation ***\r
+ ==============================\r
+ [..] \r
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). \r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+\r
+ (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().\r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+ After this, you have to call the function HAL_SD_CheckReadOperation(), to insure\r
+ that the read transfer is done correctly in both DMA and SD sides.\r
+ \r
+ *** SD Card Write operation ***\r
+ =============================== \r
+ [..] \r
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). \r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 bytes).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+\r
+ (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().\r
+ This function support only 512-bytes block length (the block size should be \r
+ chosen as 512 byte).\r
+ You can choose either one block read operation or multiple block read operation \r
+ by adjusting the "NumberOfBlocks" parameter.\r
+ After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure\r
+ that the write transfer is done correctly in both DMA and SD sides. \r
+ \r
+ *** SD card status ***\r
+ ====================== \r
+ [..]\r
+ (+) At any time, you can check the SD Card status and get the SD card state \r
+ by using the HAL_SD_GetStatus() function. This function checks first if the \r
+ SD card is still connected and then get the internal SD Card transfer state. \r
+ (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() \r
+ function. \r
+\r
+ *** SD HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in SD HAL driver.\r
+ \r
+ (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device\r
+ (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device\r
+ (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer\r
+ (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer\r
+ (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt\r
+ (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt\r
+ (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not\r
+ (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags\r
+ \r
+ (@) You can refer to the SD HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SD \r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup SD_Private_Defines\r
+ * @{\r
+ */\r
+/** \r
+ * @brief SDMMC Data block size \r
+ */ \r
+#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))\r
+/** \r
+ * @brief SDMMC Static flags, Timeout, FIFO Address \r
+ */\r
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\\r
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\\r
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\\r
+ SDMMC_FLAG_DBCKEND)) \r
+\r
+#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief Mask for errors Card Status R1 (OCR Register) \r
+ */\r
+#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)\r
+#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)\r
+#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)\r
+#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)\r
+#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)\r
+#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)\r
+#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)\r
+#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)\r
+#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)\r
+#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)\r
+#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)\r
+#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)\r
+#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)\r
+#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)\r
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)\r
+#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)\r
+#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)\r
+#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)\r
+#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)\r
+#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)\r
+\r
+/** \r
+ * @brief Masks for R6 Response \r
+ */\r
+#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)\r
+#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)\r
+#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)\r
+\r
+#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)\r
+#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)\r
+#define SD_STD_CAPACITY ((uint32_t)0x00000000)\r
+#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)\r
+\r
+#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)\r
+#define SD_ALLZERO ((uint32_t)0x00000000)\r
+\r
+#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)\r
+#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)\r
+#define SD_CARD_LOCKED ((uint32_t)0x02000000)\r
+\r
+#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)\r
+#define SD_0TO7BITS ((uint32_t)0x000000FF)\r
+#define SD_8TO15BITS ((uint32_t)0x0000FF00)\r
+#define SD_16TO23BITS ((uint32_t)0x00FF0000)\r
+#define SD_24TO31BITS ((uint32_t)0xFF000000)\r
+#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)\r
+\r
+#define SD_HALFFIFO ((uint32_t)0x00000008)\r
+#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)\r
+\r
+/** \r
+ * @brief Command Class Supported \r
+ */\r
+#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)\r
+#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)\r
+#define SD_CCCC_ERASE ((uint32_t)0x00000020)\r
+\r
+/** \r
+ * @brief Following commands are SD Card Specific commands.\r
+ * SDMMC_APP_CMD should be sent before sending these commands. \r
+ */\r
+#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup SD_Private_Functions SD Private Functions\r
+ * @{\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);\r
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); \r
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);\r
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);\r
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);\r
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);\r
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);\r
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); \r
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);\r
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SD_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group1\r
+ * @brief Initialization and de-initialization functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize the SD\r
+ card device to be ready for use.\r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SD card according to the specified parameters in the \r
+ SD_HandleTypeDef and create the associated handle.\r
+ * @param hsd: SD handle\r
+ * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information \r
+ * @retval HAL SD error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)\r
+{ \r
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SD_InitTypeDef tmpinit;\r
+ \r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SD_MspInit(hsd);\r
+ \r
+ /* Default SDMMC peripheral configuration for SD card initialization */\r
+ tmpinit.ClockEdge = SDMMC_CLOCK_EDGE_RISING;\r
+ tmpinit.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE;\r
+ tmpinit.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;\r
+ tmpinit.BusWide = SDMMC_BUS_WIDE_1B;\r
+ tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;\r
+ tmpinit.ClockDiv = SDMMC_INIT_CLK_DIV;\r
+ \r
+ /* Initialize SDMMC peripheral interface with default configuration */\r
+ SDMMC_Init(hsd->Instance, tmpinit);\r
+ \r
+ /* Identify card operating voltage */\r
+ errorstate = SD_PowerON(hsd); \r
+ \r
+ if(errorstate != SD_OK) \r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Initialize the present SDMMC card(s) and put them in idle state */\r
+ errorstate = SD_Initialize_Cards(hsd);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Read CSD/CID MSD registers */\r
+ errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* Select the Card */\r
+ errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));\r
+ }\r
+ \r
+ /* Configure SDMMC peripheral interface */\r
+ SDMMC_Init(hsd->Instance, hsd->Init); \r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the SD card.\r
+ * @param hsd: SD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)\r
+{\r
+ \r
+ /* Set SD power state to off */ \r
+ SD_PowerOFF(hsd);\r
+ \r
+ /* De-Initialize the MSP layer */\r
+ HAL_SD_MspDeInit(hsd);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the SD MSP.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief De-Initialize SD MSP.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group2\r
+ * @brief Data transfer functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the data \r
+ transfer from/to SD card.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in a card. The Data transfer \r
+ * is managed by polling mode. \r
+ * @param hsd: SD handle\r
+ * @param pReadBuffer: pointer to the buffer that will contain the received data\r
+ * @param ReadAddr: Address from where data is to be read \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of SD blocks to read \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ ReadAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t) BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize;\r
+ sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD17 READ_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; \r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Read block(s) in polling mode */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Poll on SDMMC flags */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ /* Read data from SDMMC Rx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); \r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ } \r
+ \r
+ /* In case of single block transfer, no need of stop transfer at all */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ /* Read data from SDMMC Rx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Send stop transmission command in case of multiblock read */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r
+ { \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\\r
+ (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send stop transmission command */\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ }\r
+ \r
+ /* Get error state */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ count = SD_DATATIMEOUT;\r
+ \r
+ /* Empty FIFO if there is still any data */\r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r
+ tempbuff++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Allows to write block(s) to a specified address in a card. The Data\r
+ * transfer is managed by polling mode. \r
+ * @param hsd: SD handle\r
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be written \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of SD blocks to write \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;\r
+ uint32_t *tempbuff = (uint32_t *)pWriteBuffer;\r
+ uint8_t cardstate = 0;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ WriteAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD24 WRITE_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r
+ } \r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Set total number of bytes to write */\r
+ totalnumberofbytes = NumberOfBlocks * BlockSize;\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = NumberOfBlocks * BlockSize;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Write block(s) in polling mode */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r
+ {\r
+ if ((totalnumberofbytes - bytestransferred) < 32)\r
+ {\r
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);\r
+ \r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < restwords; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r
+ tempbuff++;\r
+ bytestransferred += 4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ bytestransferred += 32;\r
+ }\r
+ }\r
+ } \r
+ }\r
+ else\r
+ {\r
+ /* In case of single data block transfer no need of stop command at all */ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r
+ {\r
+ if ((totalnumberofbytes - bytestransferred) < 32)\r
+ {\r
+ restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);\r
+ \r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < restwords; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r
+ tempbuff++; \r
+ bytestransferred += 4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Write data to SDMMC Tx FIFO */\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ bytestransferred += 32;\r
+ }\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Send stop transmission command in case of multiblock write */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r
+ { \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send stop transmission command */\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ }\r
+ \r
+ /* Get error state */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r
+ \r
+ errorstate = SD_TX_UNDERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Wait till the card is in programming state */\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ \r
+ while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r
+ {\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Reads block(s) from a specified address in a card. The Data transfer \r
+ * is managed by DMA mode. \r
+ * @note This API should be followed by the function HAL_SD_CheckReadOperation()\r
+ * to check the completion of the read process \r
+ * @param hsd: SD handle \r
+ * @param pReadBuffer: Pointer to the buffer that will contain the received data\r
+ * @param ReadAddr: Address from where data is to be read \r
+ * @param BlockSize: SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of blocks to read.\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Initialize handle flags */\r
+ hsd->SdTransferCplt = 0;\r
+ hsd->DmaTransferCplt = 0;\r
+ hsd->SdTransferErr = SD_OK; \r
+ \r
+ /* Initialize SD Read operation */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ hsd->SdOperation = SD_READ_SINGLE_BLOCK;\r
+ }\r
+ \r
+ /* Enable transfer interrupts */\r
+ __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\r
+ SDMMC_IT_DTIMEOUT |\\r
+ SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_RXOVERR));\r
+ \r
+ /* Enable SDMMC DMA transfer */\r
+ __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt;\r
+ hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;\r
+ \r
+ /* Enable the DMA Channel */\r
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ ReadAddr /= 512;\r
+ }\r
+ \r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Check number of blocks command */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ /* Send CMD18 READ_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD17 READ_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);\r
+ }\r
+ \r
+ /* Update the SD transfer error in SD handle */\r
+ hsd->SdTransferErr = errorstate;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Writes block(s) to a specified address in a card. The Data transfer \r
+ * is managed by DMA mode. \r
+ * @note This API should be followed by the function HAL_SD_CheckWriteOperation()\r
+ * to check the completion of the write process (by SD current status polling). \r
+ * @param hsd: SD handle\r
+ * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit\r
+ * @param WriteAddr: Address from where data is to be read \r
+ * @param BlockSize: the SD card Data block size \r
+ * @note BlockSize must be 512 bytes.\r
+ * @param NumberOfBlocks: Number of blocks to write\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Initialize data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Initialize handle flags */\r
+ hsd->SdTransferCplt = 0;\r
+ hsd->DmaTransferCplt = 0;\r
+ hsd->SdTransferErr = SD_OK;\r
+ \r
+ /* Initialize SD Write operation */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;\r
+ } \r
+ \r
+ /* Enable transfer interrupts */\r
+ __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\r
+ SDMMC_IT_DTIMEOUT |\\r
+ SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_TXUNDERR)); \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;\r
+ hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;\r
+ \r
+ /* Enable the DMA Channel */\r
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r
+\r
+ /* Enable SDMMC DMA transfer */\r
+ __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r
+ \r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ BlockSize = 512;\r
+ WriteAddr /= 512;\r
+ }\r
+\r
+ /* Set Block Size for Card */ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)BlockSize;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+\r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+\r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Check number of blocks command */\r
+ if(NumberOfBlocks <= 1)\r
+ {\r
+ /* Send CMD24 WRITE_SINGLE_BLOCK */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r
+ }\r
+ else\r
+ {\r
+ /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r
+ }\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+\r
+ /* Check for error conditions */\r
+ if(NumberOfBlocks > 1)\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r
+ }\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = BlockSize * NumberOfBlocks;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ hsd->SdTransferErr = errorstate;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function waits until the SD DMA data read transfer is finished. \r
+ * This API should be called after HAL_SD_ReadBlocks_DMA() function\r
+ * to insure that all data sent by the card is already transferred by the \r
+ * DMA controller.\r
+ * @param hsd: SD handle\r
+ * @param Timeout: Timeout duration \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout = Timeout;\r
+ uint32_t tmp1, tmp2;\r
+ HAL_SD_ErrorTypedef tmp3;\r
+ \r
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ \r
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r
+ {\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; \r
+ timeout--;\r
+ }\r
+\r
+ timeout = Timeout;\r
+ \r
+ /* Wait until the Rx transfer is no longer active */\r
+ while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))\r
+ {\r
+ timeout--; \r
+ }\r
+ \r
+ /* Send stop command in multiblock read */\r
+ if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)\r
+ {\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ \r
+ if ((timeout == 0) && (errorstate == SD_OK))\r
+ {\r
+ errorstate = SD_DATA_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Return error state */\r
+ if (hsd->SdTransferErr != SD_OK)\r
+ {\r
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function waits until the SD DMA data write transfer is finished. \r
+ * This API should be called after HAL_SD_WriteBlocks_DMA() function\r
+ * to insure that all data sent by the card is already transferred by the \r
+ * DMA controller.\r
+ * @param hsd: SD handle\r
+ * @param Timeout: Timeout duration \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout = Timeout;\r
+ uint32_t tmp1, tmp2;\r
+ HAL_SD_ErrorTypedef tmp3;\r
+\r
+ /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ \r
+ while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r
+ {\r
+ tmp1 = hsd->DmaTransferCplt; \r
+ tmp2 = hsd->SdTransferCplt;\r
+ tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r
+ timeout--;\r
+ }\r
+ \r
+ timeout = Timeout;\r
+ \r
+ /* Wait until the Tx transfer is no longer active */\r
+ while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT)) && (timeout > 0))\r
+ {\r
+ timeout--; \r
+ }\r
+\r
+ /* Send stop command in multiblock write */\r
+ if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)\r
+ {\r
+ errorstate = HAL_SD_StopTransfer(hsd);\r
+ }\r
+ \r
+ if ((timeout == 0) && (errorstate == SD_OK))\r
+ {\r
+ errorstate = SD_DATA_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Return error state */\r
+ if (hsd->SdTransferErr != SD_OK)\r
+ {\r
+ return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r
+ }\r
+ \r
+ /* Wait until write is complete */\r
+ while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)\r
+ { \r
+ }\r
+\r
+ return errorstate; \r
+}\r
+\r
+/**\r
+ * @brief Erases the specified memory area of the given SD card.\r
+ * @param hsd: SD handle \r
+ * @param startaddr: Start byte address\r
+ * @param endaddr: End byte address\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ \r
+ uint32_t delay = 0;\r
+ __IO uint32_t maxdelay = 0;\r
+ uint8_t cardstate = 0;\r
+ \r
+ /* Check if the card command class supports erase command */\r
+ if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get max delay value */\r
+ maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get start and end block for high capacity cards */\r
+ if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ startaddr /= 512;\r
+ endaddr /= 512;\r
+ }\r
+ \r
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */\r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */\r
+ sdmmc_cmdinitstructure.Argument =(uint32_t)startaddr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)endaddr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ }\r
+ \r
+ /* Send CMD38 ERASE */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ERASE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ for (; delay < maxdelay; delay++)\r
+ {\r
+ }\r
+ \r
+ /* Wait until the card is in programming state */\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ \r
+ delay = SD_DATATIMEOUT;\r
+ \r
+ while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r
+ {\r
+ errorstate = SD_IsCardProgramming(hsd, &cardstate);\r
+ delay--;\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SD card interrupt request.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)\r
+{ \r
+ /* Check for SDMMC interrupt flags */\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND); \r
+ \r
+ /* SD transfer is complete */\r
+ hsd->SdTransferCplt = 1;\r
+\r
+ /* No transfer error */ \r
+ hsd->SdTransferErr = SD_OK;\r
+\r
+ HAL_SD_XferCpltCallback(hsd); \r
+ } \r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ hsd->SdTransferErr = SD_DATA_CRC_FAIL;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ \r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ hsd->SdTransferErr = SD_DATA_TIMEOUT;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ hsd->SdTransferErr = SD_RX_OVERRUN;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r
+ \r
+ hsd->SdTransferErr = SD_TX_UNDERRUN;\r
+ \r
+ HAL_SD_XferErrorCallback(hsd);\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+\r
+ /* Disable all SDMMC peripheral interrupt sources */\r
+ __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND |\\r
+ SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\\r
+ SDMMC_IT_RXOVERR); \r
+}\r
+\r
+\r
+/**\r
+ * @brief SD end of transfer callback.\r
+ * @param hsd: SD handle \r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer Error callback.\r
+ * @param hsd: SD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer complete Rx callback in non blocking mode.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_RxCpltCallback could be implemented in the user file\r
+ */ \r
+} \r
+\r
+/**\r
+ * @brief SD DMA transfer complete Rx error callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_RxErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SD Transfer complete Tx callback in non blocking mode.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_TxCpltCallback could be implemented in the user file\r
+ */ \r
+} \r
+\r
+/**\r
+ * @brief SD DMA transfer complete error Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SD_DMA_TxErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group3\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SD card \r
+ operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns information about specific card.\r
+ * @param hsd: SD handle\r
+ * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that \r
+ * contains all SD cardinformation \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t tmp = 0;\r
+ \r
+ pCardInfo->CardType = (uint8_t)(hsd->CardType);\r
+ pCardInfo->RCA = (uint16_t)(hsd->RCA);\r
+ \r
+ /* Byte 0 */\r
+ tmp = (hsd->CSD[0] & 0xFF000000) >> 24;\r
+ pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);\r
+ pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);\r
+ pCardInfo->SD_csd.Reserved1 = tmp & 0x03;\r
+ \r
+ /* Byte 1 */\r
+ tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;\r
+ pCardInfo->SD_csd.TAAC = (uint8_t)tmp;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;\r
+ pCardInfo->SD_csd.NSAC = (uint8_t)tmp;\r
+ \r
+ /* Byte 3 */\r
+ tmp = hsd->CSD[0] & 0x000000FF;\r
+ pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (hsd->CSD[1] & 0xFF000000) >> 24;\r
+ pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);\r
+ \r
+ /* Byte 5 */\r
+ tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;\r
+ pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);\r
+ pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);\r
+ \r
+ /* Byte 6 */\r
+ tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;\r
+ pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);\r
+ pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);\r
+ pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);\r
+ pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4);\r
+ pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */\r
+ \r
+ if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))\r
+ {\r
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;\r
+ \r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);\r
+ pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;\r
+ \r
+ pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;\r
+ pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;\r
+ pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;\r
+ pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;\r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;\r
+ \r
+ pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;\r
+ pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));\r
+ pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);\r
+ pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;\r
+ }\r
+ else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r
+ {\r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);\r
+ pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);\r
+ \r
+ pCardInfo->SD_csd.DeviceSize |= (tmp << 8);\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);\r
+ \r
+ pCardInfo->SD_csd.DeviceSize |= (tmp);\r
+ \r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);\r
+ \r
+ pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;\r
+ pCardInfo->CardBlockSize = 512; \r
+ }\r
+ else\r
+ {\r
+ /* Not supported card type */\r
+ errorstate = SD_ERROR;\r
+ }\r
+ \r
+ pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;\r
+ pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);\r
+ pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);\r
+ \r
+ /* Byte 12 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;\r
+ pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;\r
+ pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;\r
+ pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;\r
+ pCardInfo->SD_csd.Reserved3 = 0;\r
+ pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);\r
+ \r
+ /* Byte 14 */\r
+ tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;\r
+ pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;\r
+ pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;\r
+ pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;\r
+ pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;\r
+ pCardInfo->SD_csd.ECC = (tmp & 0x03);\r
+ \r
+ /* Byte 15 */\r
+ tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);\r
+ pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;\r
+ pCardInfo->SD_csd.Reserved4 = 1;\r
+ \r
+ /* Byte 0 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_cid.ManufacturerID = tmp;\r
+ \r
+ /* Byte 1 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.OEM_AppliID = tmp << 8;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);\r
+ pCardInfo->SD_cid.OEM_AppliID |= tmp;\r
+ \r
+ /* Byte 3 */\r
+ tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdName1 = tmp << 24;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp << 16;\r
+ \r
+ /* Byte 5 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp << 8;\r
+ \r
+ /* Byte 6 */\r
+ tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ProdName1 |= tmp;\r
+ \r
+ /* Byte 7 */\r
+ tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdName2 = tmp;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_cid.ProdRev = tmp;\r
+ \r
+ /* Byte 9 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.ProdSN = tmp << 24;\r
+ \r
+ /* Byte 10 */\r
+ tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ProdSN |= tmp << 16;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);\r
+ pCardInfo->SD_cid.ProdSN |= tmp << 8;\r
+ \r
+ /* Byte 12 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);\r
+ pCardInfo->SD_cid.ProdSN |= tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);\r
+ pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;\r
+ pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;\r
+ \r
+ /* Byte 14 */\r
+ tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);\r
+ pCardInfo->SD_cid.ManufactDate |= tmp;\r
+ \r
+ /* Byte 15 */\r
+ tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);\r
+ pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;\r
+ pCardInfo->SD_cid.Reserved2 = 1;\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enables wide bus operation for the requested card if supported by \r
+ * card.\r
+ * @param hsd: SD handle \r
+ * @param WideMode: Specifies the SD card wide bus mode \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)\r
+ * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer\r
+ * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_InitTypeDef tmpinit;\r
+ \r
+ /* MMC Card does not support this feature */\r
+ if (hsd->CardType == MULTIMEDIA_CARD)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ if (WideMode == SDMMC_BUS_WIDE_8B)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ }\r
+ else if (WideMode == SDMMC_BUS_WIDE_4B)\r
+ {\r
+ errorstate = SD_WideBus_Enable(hsd);\r
+ }\r
+ else if (WideMode == SDMMC_BUS_WIDE_1B)\r
+ {\r
+ errorstate = SD_WideBus_Disable(hsd);\r
+ }\r
+ else\r
+ {\r
+ /* WideMode is not a valid argument*/\r
+ errorstate = SD_INVALID_PARAMETER;\r
+ }\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* Configure the SDMMC peripheral */\r
+ tmpinit.ClockEdge = hsd->Init.ClockEdge;\r
+ tmpinit.ClockBypass = hsd->Init.ClockBypass;\r
+ tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave;\r
+ tmpinit.BusWide = WideMode;\r
+ tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;\r
+ tmpinit.ClockDiv = hsd->Init.ClockDiv;\r
+ SDMMC_Init(hsd->Instance, tmpinit);\r
+ }\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Aborts an ongoing data transfer.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Send CMD12 STOP_TRANSMISSION */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Switches the SD card to High Speed mode.\r
+ * This API must be used after "Transfer State"\r
+ * @note This operation should be followed by the configuration \r
+ * of PLL to have SDMMCCK clock between 67 and 75 MHz\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ \r
+ uint8_t SD_hs[64] = {0};\r
+ uint32_t SD_scr[2] = {0, 0};\r
+ uint32_t SD_SPEC = 0 ;\r
+ uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;\r
+ \r
+ /* Initialize the Data control register */\r
+ hsd->Instance->DCTRL = 0;\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, SD_scr);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Test the Version supported by the card*/ \r
+ SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000);\r
+ \r
+ if (SD_SPEC != SD_ALLZERO)\r
+ {\r
+ /* Set Block Size for Card */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)64;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 64;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send CMD6 switch mode */\r
+ sdmmc_cmdinitstructure.Argument = 0x80FFFF01;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); \r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ tempbuff += 8;\r
+ }\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ count = SD_DATATIMEOUT;\r
+ \r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r
+ tempbuff++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* Test if the switch mode HS is ok */\r
+ if ((SD_hs[13]& 2) != 2)\r
+ {\r
+ errorstate = SD_UNSUPPORTED_FEATURE;\r
+ } \r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SD_Exported_Functions_Group4\r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in runtime the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the current SD card's status.\r
+ * @param hsd: SD handle\r
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status \r
+ * SD Status register)\r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t count = 0;\r
+ \r
+ /* Check SD response */\r
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Set block size for card if it is not equal to current block size for card */\r
+ sdmmc_cmdinitstructure.Argument = 64;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD55 */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Configure the SD DPSM (Data Path State Machine) */ \r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 64;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get status data */\r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r
+ {\r
+ for (count = 0; count < 8; count++)\r
+ {\r
+ *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);\r
+ }\r
+ \r
+ pSDstatus += 8;\r
+ }\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ count = SD_DATATIMEOUT;\r
+ while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r
+ {\r
+ *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);\r
+ pSDstatus++;\r
+ count--;\r
+ }\r
+ \r
+ /* Clear all the static status flags*/\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Gets the current sd card data status.\r
+ * @param hsd: SD handle\r
+ * @retval Data Transfer state\r
+ */\r
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER;\r
+\r
+ /* Get SD card state */\r
+ cardstate = SD_GetState(hsd);\r
+ \r
+ /* Find SD status according to card state*/\r
+ if (cardstate == SD_CARD_TRANSFER)\r
+ {\r
+ return SD_TRANSFER_OK;\r
+ }\r
+ else if(cardstate == SD_CARD_ERROR)\r
+ {\r
+ return SD_TRANSFER_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return SD_TRANSFER_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the SD card status.\r
+ * @param hsd: SD handle \r
+ * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that \r
+ * will contain the SD card status information \r
+ * @retval SD Card error state\r
+ */\r
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t tmp = 0;\r
+ uint32_t sd_status[16];\r
+ \r
+ errorstate = HAL_SD_SendSDStatus(hsd, sd_status);\r
+ \r
+ if (errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Byte 0 */\r
+ tmp = (sd_status[0] & 0xC0) >> 6;\r
+ pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;\r
+ \r
+ /* Byte 0 */\r
+ tmp = (sd_status[0] & 0x20) >> 5;\r
+ pCardStatus->SECURED_MODE = (uint8_t)tmp;\r
+ \r
+ /* Byte 2 */\r
+ tmp = (sd_status[2] & 0xFF);\r
+ pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);\r
+ \r
+ /* Byte 3 */\r
+ tmp = (sd_status[3] & 0xFF);\r
+ pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;\r
+ \r
+ /* Byte 4 */\r
+ tmp = (sd_status[4] & 0xFF);\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);\r
+ \r
+ /* Byte 5 */\r
+ tmp = (sd_status[5] & 0xFF);\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);\r
+ \r
+ /* Byte 6 */\r
+ tmp = (sd_status[6] & 0xFF);\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);\r
+ \r
+ /* Byte 7 */\r
+ tmp = (sd_status[7] & 0xFF);\r
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;\r
+ \r
+ /* Byte 8 */\r
+ tmp = (sd_status[8] & 0xFF);\r
+ pCardStatus->SPEED_CLASS = (uint8_t)tmp;\r
+ \r
+ /* Byte 9 */\r
+ tmp = (sd_status[9] & 0xFF);\r
+ pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;\r
+ \r
+ /* Byte 10 */\r
+ tmp = (sd_status[10] & 0xF0) >> 4;\r
+ pCardStatus->AU_SIZE = (uint8_t)tmp;\r
+ \r
+ /* Byte 11 */\r
+ tmp = (sd_status[11] & 0xFF);\r
+ pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);\r
+ \r
+ /* Byte 12 */\r
+ tmp = (sd_status[12] & 0xFF);\r
+ pCardStatus->ERASE_SIZE |= (uint8_t)tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (sd_status[13] & 0xFC) >> 2;\r
+ pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;\r
+ \r
+ /* Byte 13 */\r
+ tmp = (sd_status[13] & 0x3);\r
+ pCardStatus->ERASE_OFFSET = (uint8_t)tmp;\r
+ \r
+ return errorstate;\r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private function ----------------------------------------------------------*/ \r
+/** @addtogroup SD_Private_Functions\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief SD DMA transfer complete Rx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* DMA transfer is complete */\r
+ hsd->DmaTransferCplt = 1;\r
+ \r
+ /* Wait until SD transfer is complete */\r
+ while(hsd->SdTransferCplt == 0)\r
+ {\r
+ }\r
+ \r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); \r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer Error Rx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);\r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer complete Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ /* DMA transfer is complete */\r
+ hsd->DmaTransferCplt = 1;\r
+ \r
+ /* Wait until SD transfer is complete */\r
+ while(hsd->SdTransferCplt == 0)\r
+ {\r
+ }\r
+ \r
+ /* Disable the DMA channel */\r
+ HAL_DMA_Abort(hdma);\r
+\r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); \r
+}\r
+\r
+/**\r
+ * @brief SD DMA transfer Error Tx callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Transfer complete user callback */\r
+ HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SD current state.\r
+ * @param hsd: SD handle\r
+ * @retval SD card current state\r
+ */\r
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)\r
+{\r
+ uint32_t resp1 = 0;\r
+ \r
+ if (SD_SendStatus(hsd, &resp1) != SD_OK)\r
+ {\r
+ return SD_CARD_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes all cards or single card as the case may be Card(s) come \r
+ * into standby state.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint16_t sd_rca = 1;\r
+ \r
+ if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if(hsd->CardType != SECURE_DIGITAL_IO_CARD)\r
+ {\r
+ /* Send CMD2 ALL_SEND_CID */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp2Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get Card identification number data */\r
+ hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r
+ hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r
+ hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r
+ }\r
+ \r
+ if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\r
+ (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r
+ {\r
+ /* Send CMD3 SET_REL_ADDR with argument 0 */\r
+ /* SD Card publishes its RCA. */\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ }\r
+ \r
+ if (hsd->CardType != SECURE_DIGITAL_IO_CARD)\r
+ {\r
+ /* Get the SD card RCA */\r
+ hsd->RCA = sd_rca;\r
+ \r
+ /* Send CMD9 SEND_CSD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_LONG;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp2Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get Card Specific Data */\r
+ hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r
+ hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r
+ hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r
+ }\r
+ \r
+ /* All cards are initialized */\r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Selects od Deselects the corresponding card.\r
+ * @param hsd: SD handle\r
+ * @param addr: Address of the card to be selected \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Send CMD7 SDMMC_SEL_DESEL_CARD */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)addr;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enquires cards about their operating voltage and configures clock\r
+ * controls and stores SD information that will be needed in future\r
+ * in the SD handle.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r
+ __IO HAL_SD_ErrorTypedef errorstate = SD_OK; \r
+ uint32_t response = 0, count = 0, validvoltage = 0;\r
+ uint32_t sdtype = SD_STD_CAPACITY;\r
+ \r
+ /* Power ON Sequence -------------------------------------------------------*/\r
+ /* Disable SDMMC Clock */\r
+ __HAL_SD_SDMMC_DISABLE(hsd); \r
+ \r
+ /* Set Power State to ON */\r
+ SDMMC_PowerState_ON(hsd->Instance);\r
+\r
+ /* 1ms: required power up waiting time before starting the SD initialization \r
+ sequence */\r
+ HAL_Delay(1);\r
+ \r
+ /* Enable SDMMC Clock */\r
+ __HAL_SD_SDMMC_ENABLE(hsd);\r
+ \r
+ /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/\r
+ /* No CMD response required */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_NO;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdError(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ /* CMD Response Timeout (wait for CMDSENT flag) */\r
+ return errorstate;\r
+ }\r
+ \r
+ /* CMD8: SEND_IF_COND ------------------------------------------------------*/\r
+ /* Send CMD8 to verify SD card interface operating condition */\r
+ /* Argument: - [31:12]: Reserved (shall be set to '0')\r
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)\r
+ - [7:0]: Check Pattern (recommended 0xAA) */\r
+ /* CMD Response: R7 */\r
+ sdmmc_cmdinitstructure.Argument = SD_CHECK_PATTERN;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_SDMMC_SEND_IF_COND;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */ \r
+ errorstate = SD_CmdResp7Error(hsd);\r
+ \r
+ if (errorstate == SD_OK)\r
+ {\r
+ /* SD Card 2.0 */\r
+ hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; \r
+ sdtype = SD_HIGH_CAPACITY;\r
+ }\r
+ \r
+ /* Send CMD55 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ /* If errorstate is Command Timeout, it is a MMC card */\r
+ /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)\r
+ or SD card 1.x */\r
+ if(errorstate == SD_OK)\r
+ {\r
+ /* SD CARD */\r
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\r
+ while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))\r
+ {\r
+ \r
+ /* SEND CMD55 APP_CMD with RCA as 0 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD41 */\r
+ sdmmc_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp3Error(hsd);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get command response */\r
+ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ /* Get operating voltage*/\r
+ validvoltage = (((response >> 31) == 1) ? 1 : 0);\r
+ \r
+ count++;\r
+ }\r
+ \r
+ if(count >= SD_MAX_VOLT_TRIAL)\r
+ {\r
+ errorstate = SD_INVALID_VOLTRANGE;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */\r
+ {\r
+ hsd->CardType = HIGH_CAPACITY_SD_CARD;\r
+ }\r
+ \r
+ } /* else MMC Card */\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Turns the SDMMC output signals off.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ /* Set Power State to OFF */\r
+ SDMMC_PowerState_OFF(hsd->Instance);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Returns the current card's status.\r
+ * @param hsd: SD handle\r
+ * @param pCardStatus: pointer to the buffer that will contain the SD card \r
+ * status (Card Status register) \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ if(pCardStatus == NULL)\r
+ {\r
+ errorstate = SD_INVALID_PARAMETER;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send Status command */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SD card status */\r
+ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for CMD0.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t timeout, tmp;\r
+ \r
+ timeout = SDMMC_CMD0TIMEOUT;\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r
+ \r
+ while((timeout > 0) && (!tmp))\r
+ {\r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r
+ timeout--;\r
+ }\r
+ \r
+ if(timeout == 0)\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R7 response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_ERROR;\r
+ uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); \r
+ \r
+ while((!tmp) && (timeout > 0))\r
+ {\r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);\r
+ timeout--;\r
+ }\r
+ \r
+ tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); \r
+ \r
+ if((timeout == 0) || tmp)\r
+ {\r
+ /* Card is not V2.0 compliant or card does not support the set voltage range */\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))\r
+ {\r
+ /* Card is SD V2.0 compliant */\r
+ errorstate = SD_OK;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R1 response.\r
+ * @param hsd: SD handle\r
+ * @param SD_CMD: The sent command index \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t response_r1;\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Check response received is of desired command */\r
+ if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* We have received response, retrieve it for analysis */\r
+ response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r
+ {\r
+ return(SD_ADDR_OUT_OF_RANGE);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r
+ {\r
+ return(SD_ADDR_MISALIGNED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r
+ {\r
+ return(SD_BLOCK_LEN_ERR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r
+ {\r
+ return(SD_ERASE_SEQ_ERR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r
+ {\r
+ return(SD_BAD_ERASE_PARAM);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r
+ {\r
+ return(SD_WRITE_PROT_VIOLATION);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r
+ {\r
+ return(SD_LOCK_UNLOCK_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r
+ {\r
+ return(SD_CARD_ECC_FAILED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r
+ {\r
+ return(SD_CC_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r
+ {\r
+ return(SD_STREAM_READ_UNDERRUN);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r
+ {\r
+ return(SD_STREAM_WRITE_OVERRUN);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r
+ {\r
+ return(SD_CID_CSD_OVERWRITE);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r
+ {\r
+ return(SD_WP_ERASE_SKIP);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r
+ {\r
+ return(SD_CARD_ECC_DISABLED);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r
+ {\r
+ return(SD_ERASE_RESET);\r
+ }\r
+ \r
+ if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r
+ {\r
+ return(SD_AKE_SEQ_ERROR);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R3 (OCR) response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R2 (CID or CSD) response.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks for error conditions for R6 (RCA) response.\r
+ * @param hsd: SD handle\r
+ * @param SD_CMD: The sent command index\r
+ * @param pRCA: Pointer to the variable that will contain the SD card relative \r
+ * address RCA \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)\r
+{\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t response_r1;\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ } \r
+ \r
+ /* Check response received is of desired command */\r
+ if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ /* We have received response, retrieve it. */\r
+ response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)\r
+ {\r
+ *pRCA = (uint16_t) (response_r1 >> 16);\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Enables the SDMMC wide bus mode.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ uint32_t scr[2] = {0, 0};\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, scr);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* If requested card supports wide bus operation */\r
+ if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)\r
+ {\r
+ /* Send CMD55 APP_CMD with argument as card's RCA.*/\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\r
+ sdmmc_cmdinitstructure.Argument = 2;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Disables the SDMMC wide bus mode.\r
+ * @param hsd: SD handle\r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ \r
+ uint32_t scr[2] = {0, 0};\r
+ \r
+ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r
+ {\r
+ errorstate = SD_LOCK_UNLOCK_FAILED;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Get SCR Register */\r
+ errorstate = SD_FindSCR(hsd, scr);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* If requested card supports 1 bit mode operation */\r
+ if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)\r
+ {\r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ errorstate = SD_REQUEST_NOT_APPLICABLE;\r
+ \r
+ return errorstate;\r
+ }\r
+}\r
+ \r
+ \r
+/**\r
+ * @brief Finds the SD card SCR register value.\r
+ * @param hsd: SD handle\r
+ * @param pSCR: pointer to the buffer that will contain the SCR value \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ uint32_t index = 0;\r
+ uint32_t tempscr[2] = {0, 0};\r
+ \r
+ /* Set Block Size To 8 Bytes */\r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)8;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ /* Send CMD55 APP_CMD with argument as card's RCA */\r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ sdmmc_datainitstructure.DataTimeOut = SD_DATATIMEOUT;\r
+ sdmmc_datainitstructure.DataLength = 8;\r
+ sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;\r
+ sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;\r
+ sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;\r
+ sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;\r
+ SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r
+ \r
+ /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */\r
+ sdmmc_cmdinitstructure.Argument = 0;\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ /* Check for error conditions */\r
+ errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);\r
+ \r
+ if(errorstate != SD_OK)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r
+ {\r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))\r
+ {\r
+ *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);\r
+ index++;\r
+ }\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r
+ \r
+ errorstate = SD_DATA_TIMEOUT;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r
+ \r
+ errorstate = SD_DATA_CRC_FAIL;\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r
+ {\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r
+ \r
+ errorstate = SD_RX_OVERRUN;\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\\r
+ ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);\r
+ \r
+ *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\\r
+ ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);\r
+ \r
+ return errorstate;\r
+}\r
+\r
+/**\r
+ * @brief Checks if the SD card is in programming state.\r
+ * @param hsd: SD handle\r
+ * @param pStatus: pointer to the variable that will contain the SD card state \r
+ * @retval SD Card error state\r
+ */\r
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)\r
+{\r
+ SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r
+ HAL_SD_ErrorTypedef errorstate = SD_OK;\r
+ __IO uint32_t responseR1 = 0;\r
+ \r
+ sdmmc_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);\r
+ sdmmc_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;\r
+ sdmmc_cmdinitstructure.Response = SDMMC_RESPONSE_SHORT;\r
+ sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r
+ sdmmc_cmdinitstructure.CPSM = SDMMC_CPSM_ENABLE;\r
+ SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r
+ \r
+ while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ }\r
+ \r
+ if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r
+ {\r
+ errorstate = SD_CMD_RSP_TIMEOUT;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r
+ \r
+ return errorstate;\r
+ }\r
+ else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r
+ {\r
+ errorstate = SD_CMD_CRC_FAIL;\r
+ \r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r
+ \r
+ return errorstate;\r
+ }\r
+ else\r
+ {\r
+ /* No error flag set */\r
+ }\r
+ \r
+ /* Check response received is of desired command */\r
+ if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)\r
+ {\r
+ errorstate = SD_ILLEGAL_CMD;\r
+ \r
+ return errorstate;\r
+ }\r
+ \r
+ /* Clear all the static flags */\r
+ __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r
+ \r
+ \r
+ /* We have received response, retrieve it for analysis */\r
+ responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r
+ \r
+ /* Find out card status */\r
+ *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);\r
+ \r
+ if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r
+ {\r
+ return errorstate;\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r
+ {\r
+ return(SD_ADDR_OUT_OF_RANGE);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r
+ {\r
+ return(SD_ADDR_MISALIGNED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r
+ {\r
+ return(SD_BLOCK_LEN_ERR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r
+ {\r
+ return(SD_ERASE_SEQ_ERR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r
+ {\r
+ return(SD_BAD_ERASE_PARAM);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r
+ {\r
+ return(SD_WRITE_PROT_VIOLATION);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r
+ {\r
+ return(SD_LOCK_UNLOCK_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r
+ {\r
+ return(SD_COM_CRC_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r
+ {\r
+ return(SD_ILLEGAL_CMD);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r
+ {\r
+ return(SD_CARD_ECC_FAILED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r
+ {\r
+ return(SD_CC_ERROR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r
+ {\r
+ return(SD_GENERAL_UNKNOWN_ERROR);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r
+ {\r
+ return(SD_STREAM_READ_UNDERRUN);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r
+ {\r
+ return(SD_STREAM_WRITE_OVERRUN);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r
+ {\r
+ return(SD_CID_CSD_OVERWRITE);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r
+ {\r
+ return(SD_WP_ERASE_SKIP);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r
+ {\r
+ return(SD_CARD_ECC_DISABLED);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r
+ {\r
+ return(SD_ERASE_RESET);\r
+ }\r
+ \r
+ if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r
+ {\r
+ return(SD_AKE_SEQ_ERROR);\r
+ }\r
+ \r
+ return errorstate;\r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sdram.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SDRAM HAL module driver.\r
+ * This file provides a generic firmware to drive SDRAM memories mounted \r
+ * as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control SDRAM memories. It uses the FMC layer functions to interface \r
+ with SDRAM devices. \r
+ The following sequence should be followed to configure the FMC to interface\r
+ with SDRAM memories: \r
+ \r
+ (#) Declare a SDRAM_HandleTypeDef handle structure, for example:\r
+ SDRAM_HandleTypeDef hdsram \r
+ \r
+ (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed \r
+ values of the structure member.\r
+ \r
+ (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined \r
+ base register instance for NOR or SDRAM device \r
+ \r
+ (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:\r
+ FMC_SDRAM_TimingTypeDef Timing;\r
+ and fill its fields with the allowed values of the structure member.\r
+ \r
+ (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function\r
+ performs the following sequence:\r
+ \r
+ (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()\r
+ (##) Control register configuration using the FMC SDRAM interface function \r
+ FMC_SDRAM_Init()\r
+ (##) Timing register configuration using the FMC SDRAM interface function \r
+ FMC_SDRAM_Timing_Init()\r
+ (##) Program the SDRAM external device by applying its initialization sequence\r
+ according to the device plugged in your hardware. This step is mandatory\r
+ for accessing the SDRAM device. \r
+\r
+ (#) At this stage you can perform read/write accesses from/to the memory connected \r
+ to the SDRAM Bank. You can perform either polling or DMA transfer using the\r
+ following APIs:\r
+ (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access\r
+ (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer\r
+ \r
+ (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/\r
+ HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or \r
+ the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM\r
+ device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef \r
+ structure. \r
+ \r
+ (#) You can continuously monitor the SDRAM device HAL state by calling the function\r
+ HAL_SDRAM_GetState() \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDRAM SDRAM\r
+ * @brief SDRAM driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to initialize/de-initialize\r
+ the SDRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Performs the SDRAM device initialization sequence.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param Timing: Pointer to SDRAM control timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)\r
+{ \r
+ /* Check the SDRAM handle parameter */\r
+ if(hsdram == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsdram->State == HAL_SDRAM_STATE_RESET)\r
+ { \r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SDRAM_MspInit(hsdram);\r
+ }\r
+ \r
+ /* Initialize the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Initialize SDRAM control Interface */\r
+ FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));\r
+ \r
+ /* Initialize SDRAM timing Interface */\r
+ FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); \r
+ \r
+ /* Update the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Perform the SDRAM device initialization sequence.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SDRAM_MspDeInit(hsdram);\r
+\r
+ /* Configure the SDRAM registers with their reset values */\r
+ FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);\r
+\r
+ /* Reset the SDRAM controller state */\r
+ hsdram->State = HAL_SDRAM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsdram);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SDRAM MSP Init.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SDRAM MSP DeInit.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief This function handles SDRAM refresh error interrupt request.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+*/\r
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Check SDRAM interrupt Rising edge flag */\r
+ if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))\r
+ {\r
+ /* SDRAM refresh error interrupt callback */\r
+ HAL_SDRAM_RefreshErrorCallback(hsdram);\r
+ \r
+ /* Clear SDRAM refresh error interrupt pending bit */\r
+ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief SDRAM Refresh error callback.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete error callback.\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the SDRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads 8-bit data buffer from the SDRAM memory.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint8_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Writes 8-bit data buffer to SDRAM memory.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Reads 16-bit data buffer from the SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint16_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 16-bit data buffer to SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 32-bit data buffer from the SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Read data from source */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint32_t *)pSdramAddress; \r
+ pDstBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 32-bit data buffer to SDRAM memory. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */\r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;\r
+ pSrcBuffer++;\r
+ pSdramAddress++; \r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a Words data from the SDRAM memory using DMA transfer. \r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */ \r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if(tmp == HAL_SDRAM_STATE_PRECHARGED)\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;\r
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsdram);\r
+ \r
+ /* Check the SDRAM controller state */ \r
+ tmp = hsdram->State;\r
+ \r
+ if(tmp == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;\r
+ hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsdram);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SDRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the SDRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically SDRAM write protection.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)\r
+{ \r
+ /* Check the SDRAM controller state */ \r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Enable write protection */\r
+ FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically SDRAM write protection.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Disable write protection */\r
+ FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sends Command to the SDRAM bank.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @param Command: SDRAM command structure\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Send SDRAM command */\r
+ FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);\r
+ \r
+ /* Update the SDRAM controller state state */\r
+ if(Command->CommandMode == FMC_SDRAM_CMD_PALL)\r
+ {\r
+ hsdram->State = HAL_SDRAM_STATE_PRECHARGED;\r
+ }\r
+ else\r
+ {\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Programs the SDRAM Memory Refresh rate.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @param RefreshRate: The SDRAM refresh rate value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Program the refresh rate */\r
+ FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module. \r
+ * @param AutoRefreshNumber: The SDRAM auto Refresh number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)\r
+{\r
+ /* Check the SDRAM controller state */\r
+ if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r
+ {\r
+ return HAL_BUSY;\r
+ } \r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_BUSY;\r
+ \r
+ /* Set the Auto-Refresh number */\r
+ FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);\r
+ \r
+ /* Update the SDRAM state */\r
+ hsdram->State = HAL_SDRAM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the SDRAM memory current mode.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval The SDRAM memory mode. \r
+ */\r
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ /* Return the SDRAM memory current mode */\r
+ return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SDRAM State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the SDRAM controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the SDRAM state.\r
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SDRAM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)\r
+{\r
+ return hsdram->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SMARTCARD HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the SMARTCARD peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions \r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The SMARTCARD HAL driver can be used as follow:\r
+ \r
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure.\r
+ (#) Associate a USART to the SMARTCARD handle hsc.\r
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) SMARTCARD pins configuration:\r
+ (+++) Enable the clock for the SMARTCARD GPIOs.\r
+ (+++) Configure these SMARTCARD pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()\r
+ and HAL_SMARTCARD_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (@) The specific USART interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()\r
+ and HAL_SMARTCARD_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,\r
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission\r
+ error enabling or disabling in the hsc Init structure.\r
+ \r
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)\r
+ in the hsc AdvancedInit structure.\r
+\r
+ (#) Initialize the SMARTCARD associated USART registers by calling\r
+ the HAL_SMARTCARD_Init() API. \r
+ \r
+ (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by \r
+ calling the customized HAL_SMARTCARD_MspInit() API.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARD SMARTCARD\r
+ * @brief HAL USART SMARTCARD module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r
+ * @{\r
+ */\r
+#define TEACK_REACK_TIMEOUT 1000\r
+#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) \r
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))\r
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) \r
+/**\r
+ * @}\r
+ */\r
+/* Private macros -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup SMARTCARD_Private_Functions\r
+ * @{\r
+ */\r
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);\r
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);\r
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART\r
+ associated to the SmartCard.\r
+ (+) These parameters can be configured: \r
+ (++) Baud Rate\r
+ (++) Parity: parity should be enabled,\r
+ Frame Length is fixed to 8 bits plus parity:\r
+ the USART frame format is given in the following table:\r
+ +---------------------------------------------------------------+\r
+ | M1M0 bits | PCE bit | USART frame |\r
+ |-----------------------|---------------------------------------|\r
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +---------------------------------------------------------------+\r
+ (++) Receiver/transmitter modes\r
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)\r
+ (++) Prescaler value\r
+ (++) Guard bit time \r
+ (++) NACK enabling or disabling on transmission error \r
+\r
+ (+) The following advanced features can be configured as well:\r
+ (++) TX and/or RX pin level inversion\r
+ (++) data logical level inversion\r
+ (++) RX and TX pins swap\r
+ (++) RX overrun detection disabling\r
+ (++) DMA disabling on RX error\r
+ (++) MSB first on communication line\r
+ (++) Time out enabling (and if activated, timeout value)\r
+ (++) Block length\r
+ (++) Auto-retry counter \r
+ \r
+ [..] \r
+ The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures \r
+ (details for the procedures are available in reference manual).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SMARTCARD mode according to the specified\r
+ * parameters in the SMARTCARD_InitTypeDef and create the associated handle .\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Check the SMARTCARD handle allocation */\r
+ if(hsc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+ \r
+ if(hsc->State == HAL_SMARTCARD_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r
+ HAL_SMARTCARD_MspInit(hsc);\r
+ }\r
+ \r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_SMARTCARD_DISABLE(hsc);\r
+\r
+ /* Set the SMARTCARD Communication parameters */\r
+ SMARTCARD_SetConfig(hsc);\r
+\r
+ if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)\r
+ {\r
+ SMARTCARD_AdvFeatureConfig(hsc);\r
+ }\r
+\r
+ /* In SmartCard mode, the following bits must be kept cleared: \r
+ - LINEN in the USART_CR2 register,\r
+ - HDSEL and IREN bits in the USART_CR3 register.*/\r
+ hsc->Instance->CR2 &= ~(USART_CR2_LINEN); \r
+ hsc->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); \r
+\r
+ /* set the USART in SMARTCARD mode */ \r
+ hsc->Instance->CR3 |= USART_CR3_SCEN; \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_SMARTCARD_ENABLE(hsc);\r
+ \r
+ /* TEACK and/or REACK to check before moving hsc->State to Ready */\r
+ return (SMARTCARD_CheckIdleState(hsc));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SMARTCARD peripheral \r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Check the SMARTCARD handle allocation */\r
+ if(hsc == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_SMARTCARD_MspDeInit(hsc);\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ hsc->State = HAL_SMARTCARD_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD MSP Init\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD MSP DeInit\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions \r
+ * @brief SMARTCARD Transmit and Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ =============================================================================== \r
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode. \r
+ The HAL status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (+) No-Blocking mode: The communication is performed using Interrupts \r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks \r
+ will be executed respectively at the end of the Transmit or Receive process\r
+ The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_SMARTCARD_Transmit()\r
+ (+) HAL_SMARTCARD_Receive() \r
+ \r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_SMARTCARD_Transmit_IT()\r
+ (+) HAL_SMARTCARD_Receive_IT()\r
+ (+) HAL_SMARTCARD_IRQHandler()\r
+ (+) SMARTCARD_Transmit_IT()\r
+ (+) SMARTCARD_Receive_IT() \r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (+) HAL_SMARTCARD_Transmit_DMA()\r
+ (+) HAL_SMARTCARD_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (+) HAL_SMARTCARD_TxCpltCallback()\r
+ (+) HAL_SMARTCARD_RxCpltCallback()\r
+ (+) HAL_SMARTCARD_ErrorCallback()\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in blocking mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; \r
+ /* Check if a non-blocking receive process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+ \r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+ while(hsc->TxXferCount > 0)\r
+ {\r
+ hsc->TxXferCount--;\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ hsc->Instance->TDR = (*pData++ & (uint8_t)0xFF); \r
+ }\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Check if a non-blocking receive Process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+ \r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ /* Check if a non-blocking transmit process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+\r
+ hsc->RxXferSize = Size;\r
+ hsc->RxXferCount = Size;\r
+ /* Check the remain data to be received */\r
+ while(hsc->RxXferCount > 0)\r
+ {\r
+ hsc->RxXferCount--;\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FF); \r
+ }\r
+\r
+ /* Check if a non-blocking transmit process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pTxBuffPtr = pData;\r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ /* Check if a receive process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+\r
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ /* Enable the SMARTCARD Transmit Complete Interrupt */\r
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pRxBuffPtr = pData;\r
+ hsc->RxXferSize = Size;\r
+ hsc->RxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ /* Check if a transmit process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Enable the SMARTCARD Parity Error Interrupt */\r
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);\r
+\r
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ /* Enable the SMARTCARD Data Register not empty Interrupt */\r
+ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pTxBuffPtr = pData;\r
+ hsc->TxXferSize = Size;\r
+ hsc->TxXferCount = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ /* Check if a receive process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+\r
+ /* Set the SMARTCARD DMA transfer complete callback */\r
+ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;\r
+\r
+ /* Set the SMARTCARD error callback */\r
+ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;\r
+\r
+ /* Enable the SMARTCARD transmit DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);\r
+ \r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the SMARTCARD associated USART CR3 register */\r
+ hsc->Instance->CR3 |= USART_CR3_DMAT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode \r
+ * @param hsc: SMARTCARD handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), \r
+ * the received data contain the parity bit (MSB position) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->pRxBuffPtr = pData;\r
+ hsc->RxXferSize = Size;\r
+\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+ /* Check if a transmit process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+\r
+ /* Set the SMARTCARD DMA transfer complete callback */\r
+ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;\r
+\r
+ /* Set the SMARTCARD DMA error callback */\r
+ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;\r
+\r
+ /* Enable the DMA Stream */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the SMARTCARD associated USART CR3 register */\r
+ hsc->Instance->CR3 |= USART_CR3_DMAR;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief SMARTCARD interrupt requests handling.\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* SMARTCARD parity error interrupt occurred -------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE) != RESET))\r
+ { \r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_PEF);\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;\r
+ /* Set the SMARTCARD state ready to be able to start again the process */\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ /* SMARTCARD frame error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))\r
+ { \r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_FEF);\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;\r
+ /* Set the SMARTCARD state ready to be able to start again the process */\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ /* SMARTCARD noise error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))\r
+ { \r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_NEF);\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; \r
+ /* Set the SMARTCARD state ready to be able to start again the process */\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET))\r
+ { \r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_OREF);\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; \r
+ /* Set the SMARTCARD state ready to be able to start again the process */\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ /* SMARTCARD receiver timeout interrupt occurred ----------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RTO) != RESET))\r
+ { \r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_RTOF);\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; \r
+ /* Set the SMARTCARD state ready to be able to start again the process */\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ /* Call SMARTCARD Error Call back function if need be ----------------------*/\r
+ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)\r
+ {\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+ } \r
+ \r
+ /* SMARTCARD in mode Receiver ----------------------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE) != RESET))\r
+ { \r
+ SMARTCARD_Receive_IT(hsc);\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_SMARTCARD_SEND_REQ(hsc, SMARTCARD_RXDATA_FLUSH_REQUEST);\r
+ }\r
+ \r
+ /* SMARTCARD in mode Receiver, end of block interruption -------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_EOB) != RESET))\r
+ { \r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ HAL_SMARTCARD_RxCpltCallback(hsc);\r
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information\r
+ * to be available during HAL_SMARTCARD_RxCpltCallback() processing */\r
+ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_EOBF);\r
+ } \r
+ \r
+ /* SMARTCARD in mode Transmitter -------------------------------------------*/\r
+ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_TC) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC) != RESET))\r
+ {\r
+ SMARTCARD_Transmit_IT(hsc);\r
+ } \r
+} \r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SMARTCARD error callbacks\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SMARTCARD_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions \r
+ * @brief SMARTCARD State functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.\r
+ (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral \r
+ (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral \r
+ (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief return the SMARTCARD state\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL state\r
+ */\r
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ return hsc->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the SMARTCARD error code\r
+ * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SMARTCARD.\r
+ * @retval SMARTCARD Error Code\r
+ */\r
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ return hsc->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in non blocking mode \r
+ * @param hsc: SMARTCARD handle.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) \r
+ {\r
+ if(hsc->TxXferCount == 0)\r
+ {\r
+ /* Disable the SMARTCARD Transmit Complete Interrupt */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC);\r
+ \r
+ /* Check if a receive Process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+ \r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ HAL_SMARTCARD_TxCpltCallback(hsc);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ { \r
+ hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFF); \r
+ hsc->TxXferCount--;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in non blocking mode \r
+ * @param hsc: SMARTCARD handle.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ if((hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))\r
+ {\r
+ *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFF); \r
+ \r
+ if(--hsc->RxXferCount == 0)\r
+ {\r
+ while(HAL_IS_BIT_SET(hsc->Instance->ISR, SMARTCARD_FLAG_RXNE))\r
+ {\r
+ }\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);\r
+ \r
+ /* Check if a transmit Process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SMARTCARD Parity Error Interrupt */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);\r
+ \r
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+ \r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ HAL_SMARTCARD_RxCpltCallback(hsc);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the SMARTCARD associated USART peripheral \r
+ * @param hsc: SMARTCARD handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ uint32_t tmpreg = 0x00000000;\r
+ uint32_t clocksource = 0x00000000;\r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r
+ assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); \r
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)); \r
+ assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)); \r
+ assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));\r
+ assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));\r
+ assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));\r
+ assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));\r
+ assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); \r
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));\r
+ assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));\r
+ assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));\r
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount)); \r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).\r
+ * Oversampling is forced to 16 (OVER8 = 0).\r
+ * Configure the Parity and Mode: \r
+ * set PS bit according to hsc->Init.Parity value\r
+ * set TE and RE bits according to hsc->Init.Mode value */\r
+ tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;\r
+ /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor \r
+ the bidirectional line to detect a NACK signal in case of parity error. \r
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */\r
+ if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))\r
+ {\r
+ tmpreg |= USART_CR1_RE; \r
+ }\r
+ tmpreg |= (uint32_t) hsc->Init.WordLength;\r
+ MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Stop bits are forced to 1.5 (STOP = 11) */\r
+ tmpreg = hsc->Init.StopBits;\r
+ /* Synchronous mode is activated by default */\r
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity; \r
+ tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;\r
+ tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg); \r
+ \r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure \r
+ * - one-bit sampling method versus three samples' majority rule \r
+ * according to hsc->Init.OneBitSampling \r
+ * - NACK transmission in case of parity error according \r
+ * to hsc->Init.NACKEnable \r
+ * - autoretry counter according to hsc->Init.AutoRetryCount */\r
+ tmpreg = (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;\r
+ tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);\r
+ MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);\r
+ \r
+ /*-------------------------- USART GTPR Configuration ----------------------*/\r
+ tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));\r
+ MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg); \r
+ \r
+ /*-------------------------- USART RTOR Configuration ----------------------*/ \r
+ tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);\r
+ if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)\r
+ {\r
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r
+ tmpreg |= (uint32_t) hsc->Init.TimeOutValue;\r
+ }\r
+ MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);\r
+ \r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case SMARTCARD_CLOCKSOURCE_PCLK1: \r
+ hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate);\r
+ break;\r
+ case SMARTCARD_CLOCKSOURCE_PCLK2: \r
+ hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate);\r
+ break;\r
+ case SMARTCARD_CLOCKSOURCE_HSI: \r
+ hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate); \r
+ break; \r
+ case SMARTCARD_CLOCKSOURCE_SYSCLK: \r
+ hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate);\r
+ break; \r
+ case SMARTCARD_CLOCKSOURCE_LSE: \r
+ hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate); \r
+ break;\r
+ default:\r
+ break;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Check the SMARTCARD Idle State\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ \r
+ /* Initialize the SMARTCARD ErrorCode */\r
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r
+\r
+ /* Check if the Transmitter is enabled */\r
+ if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+ \r
+ /* Initialize the SMARTCARD state*/\r
+ hsc->State= HAL_SMARTCARD_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features \r
+ * @param hsc: SMARTCARD handle \r
+ * @retval None\r
+ */\r
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)\r
+{ \r
+ /* Check whether the set of advanced features to configure is properly set */ \r
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit));\r
+ \r
+ /* if required, configure TX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure RX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure data inversion */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert);\r
+ }\r
+ \r
+ /* if required, configure RX/TX pins swap */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap));\r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap);\r
+ }\r
+ \r
+ /* if required, configure RX overrun detection disabling */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable)); \r
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable);\r
+ }\r
+ \r
+ /* if required, configure DMA disabling on reception error */\r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError)); \r
+ MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError);\r
+ }\r
+ \r
+ /* if required, configure MSB first on communication line */ \r
+ if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))\r
+ {\r
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst)); \r
+ MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst);\r
+ }\r
+}\r
+ \r
+/**\r
+ * @brief This function handles SMARTCARD Communication Timeout.\r
+ * @param hsc: SMARTCARD handle\r
+ * @param Flag: specifies the SMARTCARD flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0x00;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ { \r
+ while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+\r
+ hsc->State= HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);\r
+ __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r
+\r
+ hsc->State= HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD transmit process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->TxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the SMARTCARD associated USART CR3 register */\r
+ hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);\r
+ \r
+ /* Wait for SMARTCARD TC Flag */\r
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, HAL_SMARTCARD_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
+ {\r
+ /* Timeout Occurred */ \r
+ hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+ }\r
+ else\r
+ {\r
+ /* No Timeout */\r
+ /* Check if a receive Process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ HAL_SMARTCARD_TxCpltCallback(hsc);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD receive process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->RxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the SMARTCARD associated USART CR3 register */\r
+ hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);\r
+ \r
+ /* Check if a transmit Process is ongoing or not */\r
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) \r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+ }\r
+ \r
+ HAL_SMARTCARD_RxCpltCallback(hsc);\r
+}\r
+\r
+/**\r
+ * @brief DMA SMARTCARD communication error callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ hsc->RxXferCount = 0;\r
+ hsc->TxXferCount = 0;\r
+ hsc->State= HAL_SMARTCARD_STATE_READY;\r
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;\r
+ HAL_SMARTCARD_ErrorCallback(hsc);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_smartcard_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SMARTCARD HAL module driver.\r
+ *\r
+ * This file provides extended firmware functions to manage the following \r
+ * functionalities of the SmartCard.\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The Extended SMARTCARD HAL driver can be used as follow:\r
+\r
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), \r
+ then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, \r
+ auto-retry counter,...) in the hsc AdvancedInit structure.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARDEx SMARTCARDEx\r
+ * @brief SMARTCARD Extended HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SMARTCARDEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions\r
+ * @brief Extended control functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.\r
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly \r
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly \r
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature\r
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Update on the fly the SMARTCARD block length in RTOR register\r
+ * @param hsc: SMARTCARD handle\r
+ * @param BlockLength: SMARTCARD block length (8-bit long at most) \r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)\r
+{\r
+ MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));\r
+}\r
+\r
+/**\r
+ * @brief Update on the fly the receiver timeout value in RTOR register\r
+ * @param hsc: SMARTCARD handle\r
+ * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout\r
+ * value must be less or equal to 0x0FFFFFFFF. \r
+ * @retval None\r
+ */\r
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)\r
+{\r
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r
+ MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); \r
+}\r
+\r
+/**\r
+ * @brief Enable the SMARTCARD receiver timeout feature\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Set the USART RTOEN bit */\r
+ hsc->Instance->CR2 |= USART_CR2_RTOEN;\r
+\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable the SMARTCARD receiver timeout feature\r
+ * @param hsc: SMARTCARD handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsc);\r
+\r
+ hsc->State = HAL_SMARTCARD_STATE_BUSY;\r
+\r
+ /* Clear the USART RTOEN bit */\r
+ hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);\r
+\r
+ hsc->State = HAL_SMARTCARD_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hsc);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spdifrx.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SPDIFRX audio interface:\r
+ * + Initialization and Configuration\r
+ * + Data transfers functions\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management \r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The SPDIFRX HAL driver can be used as follow:\r
+ \r
+ (#) Declare SPDIFRX_HandleTypeDef handle structure.\r
+ (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:\r
+ (##) Enable the SPDIFRX interface clock. \r
+ (##) SPDIFRX pins configuration:\r
+ (+++) Enable the clock for the SPDIFRX GPIOs.\r
+ (+++) Configure these SPDIFRX pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).\r
+ (+++) Configure the SPDIFRX interrupt priority.\r
+ (+++) Enable the NVIC SPDIFRX IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).\r
+ (+++) Declare a DMA handle structure for the reception of the Data Flow channel.\r
+ (+++) Declare a DMA handle structure for the reception of the Control Flow channel.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.\r
+ (+++) Configure the DMA Channel.\r
+ (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r
+ DMA CtrlRx/DataRx channel.\r
+ \r
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits\r
+ using HAL_SPDIFRX_Init() function.\r
+\r
+ -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros\r
+ __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.\r
+ -@- Make sure that ck_spdif clock is configured. \r
+ \r
+ (#) Three operation modes are available within this driver :\r
+ \r
+ *** Polling mode for reception operation (for debug purpose) ***\r
+ ================================================================\r
+ [..] \r
+ (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()\r
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()\r
+ \r
+ *** Interrupt mode for reception operation ***\r
+ =========================================\r
+ [..] \r
+ (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() \r
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() \r
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r
+\r
+ *** DMA mode for reception operation ***\r
+ ========================================\r
+ [..] \r
+ (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() \r
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() \r
+ (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r
+ (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()\r
+\r
+ *** SPDIFRX HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in USART HAL driver.\r
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)\r
+ (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) \r
+ (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)\r
+ (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts\r
+ (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts\r
+ (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.\r
+\r
+ [..]\r
+ (@) You can refer to the SPDIFRX HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @defgroup SPDIFRX SPDIFRX\r
+* @brief SPDIFRX HAL module driver\r
+* @{\r
+*/\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFF\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup SPDIFRX_Private_Functions\r
+ * @{\r
+ */\r
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);\r
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and \r
+ de-initialize the SPDIFRX peripheral:\r
+ \r
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures \r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+ \r
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with \r
+ the selected configuration:\r
+ (++) Input Selection (IN0, IN1,...)\r
+ (++) Maximum allowed re-tries during synchronization phase\r
+ (++) Wait for activity on SPDIF selected input\r
+ (++) Channel status selection (from channel A or B)\r
+ (++) Data format (LSB, MSB, ...)\r
+ (++) Stereo mode\r
+ (++) User bits masking (PT,C,U,V,...)\r
+ \r
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration \r
+ of the selected SPDIFRXx peripheral. \r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SPDIFRX according to the specified parameters \r
+ * in the SPDIFRX_InitTypeDef and create the associated handle.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the SPDIFRX parameters */\r
+ assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));\r
+ assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));\r
+ assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));\r
+ assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));\r
+ assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));\r
+ assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));\r
+ assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));\r
+ assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));\r
+ assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));\r
+ assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_SPDIFRX_MspInit(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX peripheral state is BUSY*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY; \r
+ \r
+ /* Disable SPDIFRX interface (IDLE State) */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+ \r
+ /* Reset the old SPDIFRX CR configuration */\r
+ tmpreg = hspdif->Instance->CR;\r
+ \r
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |\r
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |\r
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |\r
+ SPDIFRX_CR_INSEL); \r
+ \r
+ /* Sets the new configuration of the SPDIFRX peripheral */\r
+ tmpreg |= ((uint16_t) hspdif->Init.StereoMode |\r
+ hspdif->Init.InputSelection |\r
+ hspdif->Init.Retries |\r
+ hspdif->Init.WaitForActivity |\r
+ hspdif->Init.ChannelSelection |\r
+ hspdif->Init.DataFormat |\r
+ hspdif->Init.PreambleTypeMask |\r
+ hspdif->Init.ChannelStatusMask |\r
+ hspdif->Init.ValidityBitMask |\r
+ hspdif->Init.ParityErrorMask);\r
+\r
+ hspdif->Instance->CR = tmpreg; \r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* SPDIFRX peripheral state is READY*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SPDIFRX peripheral \r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));\r
+\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+ \r
+ /* Disable SPDIFRX interface (IDLE state) */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_SPDIFRX_MspDeInit(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* SPDIFRX peripheral state is RESET*/\r
+ hspdif->State = HAL_SPDIFRX_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX MSP Init\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX MSP DeInit\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Sets the SPDIFRX dtat format according to the specified parameters \r
+ * in the SPDIFRX_InitTypeDef.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param sDataFormat: SPDIFRX data format\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the SPDIFRX handle allocation */\r
+ if(hspdif == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the SPDIFRX parameters */\r
+ assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));\r
+ assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));\r
+ assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));\r
+ assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));\r
+ assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));\r
+ assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));\r
+ \r
+ /* Reset the old SPDIFRX CR configuration */\r
+ tmpreg = hspdif->Instance->CR;\r
+ \r
+ if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&\r
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||\r
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |\r
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); \r
+ \r
+ /* Sets the new configuration of the SPDIFRX peripheral */\r
+ tmpreg |= ((uint16_t) sDataFormat.StereoMode |\r
+ sDataFormat.DataFormat |\r
+ sDataFormat.PreambleTypeMask |\r
+ sDataFormat.ChannelStatusMask |\r
+ sDataFormat.ValidityBitMask |\r
+ sDataFormat.ParityErrorMask);\r
+\r
+ hspdif->Instance->CR = tmpreg; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### IO operation functions #####\r
+=============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SPDIFRX data \r
+ transfers.\r
+\r
+ (#) There is two mode of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode. \r
+ The status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (++) No-Blocking mode : The communication is performed using Interrupts \r
+ or DMA. These functions return the status of the transfer start-up.\r
+ The end of the data processing will be indicated through the \r
+ dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow()\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow()\r
+ (+@) Do not use blocking mode to receive both control and data flow at the same time.\r
+\r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow_IT()\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()\r
+ (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (++) HAL_SPDIFRX_RxCpltCallback()\r
+ (++) HAL_SPDIFRX_ErrorCallback()\r
+\r
+@endverbatim\r
+* @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Receives an amount of data (Data Flow) in blocking mode. \r
+ * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains\r
+ * the configuration information for SPDIFRX module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+\r
+ /* Start synchronisation */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ \r
+ /* Receive data flow */\r
+ while(Size > 0)\r
+ { \r
+ /* Wait until RXNE flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ (*pData++) = hspdif->Instance->DR;\r
+ Size--; \r
+ } \r
+\r
+ /* SPDIFRX ready */\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives an amount of data (Control Flow) in blocking mode. \r
+ * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains\r
+ * the configuration information for SPDIFRX module.\r
+ * @param pData: Pointer to data buffer\r
+ * @param Size: Amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ \r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r
+ { \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r
+ \r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ \r
+ /* Receive control flow */\r
+ while(Size > 0)\r
+ { \r
+ /* Wait until CSRNE flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ (*pData++) = hspdif->Instance->CSR;\r
+ Size--; \r
+ } \r
+\r
+ /* SPDIFRX ready */\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be received .\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+\r
+ hspdif->pRxBuffPtr = pData;\r
+ hspdif->RxXferSize = Size;\r
+ hspdif->RxXferCount = Size;\r
+\r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* Check if a receive process is ongoing or not */\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r
+\r
+ \r
+ /* Enable the SPDIFRX PE Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+\r
+ /* Enable the SPDIFRX OVR Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ /* Enable the SPDIFRX RXNE interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample (Control Flow) to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+\r
+ hspdif->pCsBuffPtr = pData;\r
+ hspdif->CsXferSize = Size;\r
+ hspdif->CsXferCount = Size;\r
+\r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ \r
+ /* Check if a receive process is ongoing or not */\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r
+\r
+\r
+ /* Enable the SPDIFRX PE Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+\r
+ /* Enable the SPDIFRX OVR Error Interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ /* Enable the SPDIFRX CSRNE interrupt */\r
+ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) mode with DMA \r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data sample to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r
+ { \r
+ hspdif->pRxBuffPtr = pData;\r
+ hspdif->RxXferSize = Size;\r
+ hspdif->RxXferCount = Size;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r
+ \r
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r
+ hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;\r
+ \r
+ /* Set the SPDIFRX Rx DMA transfer complete callback */\r
+ hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;\r
+ \r
+ /* Enable the DMA request */\r
+ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);\r
+\r
+ /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/\r
+ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with DMA \r
+ * @param hspdif: SPDIFRX handle\r
+ * @param pData: a 32-bit pointer to the Receive data buffer.\r
+ * @param Size: number of data (Control Flow) sample to be received :\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r
+{\r
+ \r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ } \r
+ \r
+ if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r
+ { \r
+ hspdif->pCsBuffPtr = pData;\r
+ hspdif->CsXferSize = Size;\r
+ hspdif->CsXferCount = Size;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r
+ \r
+ /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r
+ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;\r
+ \r
+ /* Set the SPDIFRX Rx DMA transfer complete callback */\r
+ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;\r
+ \r
+ /* Enable the DMA request */\r
+ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);\r
+\r
+ /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/\r
+ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;\r
+ \r
+ if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) \r
+ {\r
+ /* Start synchronization */\r
+ __HAL_SPDIFRX_SYNC(hspdif);\r
+ \r
+ /* Wait until SYNCD flag is set */\r
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ } \r
+ \r
+ /* Start reception */ \r
+ __HAL_SPDIFRX_RCV(hspdif);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief stop the audio stream receive from the Media.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspdif);\r
+ \r
+ /* Disable the SPDIFRX DMA requests */\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r
+ \r
+ /* Disable the SPDIFRX DMA channel */\r
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);\r
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);\r
+ \r
+ /* Disable SPDIFRX peripheral */\r
+ __HAL_SPDIFRX_IDLE(hspdif);\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPDIFRX interrupt request.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)\r
+{ \r
+ /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ SPDIFRX_ReceiveDataFlow_IT(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ SPDIFRX_ReceiveControlFlow_IT(hspdif);\r
+ }\r
+ \r
+ /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);\r
+ \r
+ /* Change the SPDIFRX error code */\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;\r
+ \r
+ /* the transfer is not stopped */\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+ } \r
+ \r
+ /* SPDIFRX Parity error interrupt occurred ---------------------------------*/\r
+ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))\r
+ {\r
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);\r
+ \r
+ /* Change the SPDIFRX error code */\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;\r
+ \r
+ /* the transfer is not stopped */\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+ } \r
+ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Data flow) half completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Data flow) completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx (Control flow) Transfer half completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer (Control flow) completed callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPDIFRX error callbacks\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+##### Peripheral State and Errors functions #####\r
+=============================================================================== \r
+[..]\r
+This subsection permit to get in run-time the status of the peripheral \r
+and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the SPDIFRX state\r
+ * @param hspdif : SPDIFRX handle\r
+ * @retval HAL state\r
+ */\r
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ return hspdif->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the SPDIFRX error code\r
+ * @param hspdif : SPDIFRX handle\r
+ * @retval SPDIFRX Error Code\r
+ */\r
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ return hspdif->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Data flow) complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx DMA Request */\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r
+ hspdif->RxXferCount = 0;\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+ HAL_SPDIFRX_RxCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Data flow) half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ HAL_SPDIFRX_RxHalfCpltCallback(hspdif); \r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Control flow) complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Cb DMA Request */\r
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r
+ hspdif->CsXferCount = 0;\r
+ \r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+ HAL_SPDIFRX_CxCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX receive process (Control flow) half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+ \r
+ HAL_SPDIFRX_CxHalfCpltCallback(hspdif); \r
+}\r
+\r
+/**\r
+ * @brief DMA SPDIFRX communication error callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* Disable Rx and Cb DMA Request */\r
+ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));\r
+ hspdif->RxXferCount = 0;\r
+ \r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+ \r
+ /* Set the error code and execute error callback*/\r
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;\r
+ HAL_SPDIFRX_ErrorCallback(hspdif);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Receive an amount of data (Data Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Receive data */\r
+ (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;\r
+ hspdif->RxXferCount--;\r
+\r
+ if(hspdif->RxXferCount == 0)\r
+ { \r
+ /* Disable RXNE/PE and OVR interrupts */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);\r
+\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ HAL_SPDIFRX_RxCpltCallback(hspdif);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data (Control Flow) with Interrupt\r
+ * @param hspdif: SPDIFRX handle\r
+ * @retval None\r
+ */\r
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r
+{\r
+ /* Receive data */\r
+ (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;\r
+ hspdif->CsXferCount--;\r
+\r
+ if(hspdif->CsXferCount == 0)\r
+ { \r
+ /* Disable CSRNE interrupt */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+\r
+ hspdif->State = HAL_SPDIFRX_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ HAL_SPDIFRX_CxCpltCallback(hspdif);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPDIFRX Communication Timeout.\r
+ * @param hspdif: SPDIFRX handle\r
+ * @param Flag: Flag checked\r
+ * @param Status: Value of the flag expected\r
+ * @param Timeout: Duration of the timeout\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ {\r
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r
+\r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r
+\r
+ hspdif->State= HAL_SPDIFRX_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspdif);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+* @}\r
+*/\r
+\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spi.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SPI HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The SPI HAL driver can be used as follows:\r
+\r
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:\r
+ SPI_HandleTypeDef hspi;\r
+\r
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:\r
+ (##) Enable the SPIx interface clock\r
+ (##) SPI pins configuration\r
+ (+++) Enable the clock for the SPI GPIOs\r
+ (+++) Configure these SPI pins as alternate function push-pull\r
+ (##) NVIC configuration if you need to use interrupt process\r
+ (+++) Configure the SPIx interrupt priority\r
+ (+++) Enable the NVIC SPI IRQ handle\r
+ (##) DMA Configuration if you need to use DMA process\r
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel\r
+ (+++) Enable the DMAx clock\r
+ (+++) Configure the DMA handle parameters\r
+ (+++) Configure the DMA Tx or Rx channel\r
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel\r
+\r
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r
+\r
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customed HAL_SPI_MspInit() API.\r
+ [..]\r
+ Circular mode restriction:\r
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
+ (##) Master 2Lines RxOnly\r
+ (##) Master 1Line Rx\r
+ (#) The CRC feature is not managed when the DMA circular mode is enabled\r
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+ \r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI SPI \r
+ * @brief SPI HAL module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines -----------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Constants SPI Private Constants\r
+ * @{\r
+ */\r
+#define SPI_DEFAULT_TIMEOUT 50\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup SPI_Private_Functions SPI Private Functions\r
+ * @{\r
+ */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Functions SPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and\r
+ de-initialize the SPIx peripheral:\r
+\r
+ (+) User must implement HAL_SPI_MspInit() function in which he configures\r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_SPI_Init() to configure the selected device with\r
+ the selected configuration:\r
+ (++) Mode\r
+ (++) Direction\r
+ (++) Data Size\r
+ (++) Clock Polarity and Phase\r
+ (++) NSS Management\r
+ (++) BaudRate Prescaler\r
+ (++) FirstBit\r
+ (++) TIMode\r
+ (++) CRC Calculation\r
+ (++) CRC Polynomial if CRC enabled\r
+ (++) CRC Length, used only with Data8 and Data16\r
+ (++) FIFO reception threshold\r
+\r
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r
+ of the selected SPIx peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SPI according to the specified parameters\r
+ * in the SPI_InitTypeDef and create the associated handle.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r
+{\r
+ uint32_t frxth;\r
+\r
+ /* Check the SPI handle allocation */\r
+ if(hspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));\r
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));\r
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r
+\r
+ if(hspi->State == HAL_SPI_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hspi->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
+ HAL_SPI_MspInit(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+ /* Disable the selected SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+\r
+ /* Align by default the rs fifo threshold on the data size */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ frxth = SPI_RXFIFO_THRESHOLD_HF;\r
+ }\r
+ else\r
+ {\r
+ frxth = SPI_RXFIFO_THRESHOLD_QF;\r
+ }\r
+\r
+ /* CRC calculation is valid only for 16Bit and 8 Bit */\r
+ if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))\r
+ {\r
+ /* CRC must be disabled */\r
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
+ }\r
+\r
+ /* Align the CRC Length on the data size */\r
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r
+ {\r
+ /* CRC Length aligned on the data size : value set by default */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r
+ }\r
+ else\r
+ {\r
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r
+ }\r
+ }\r
+\r
+ /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/\r
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r
+ Communication speed, First bit, CRC calculation state, CRC Length */\r
+ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |\r
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);\r
+\r
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ hspi->Instance->CR1|= SPI_CR1_CRCL;\r
+ }\r
+\r
+ /* Configure : NSS management */\r
+ /* Configure : Rx Fifo Threshold */\r
+ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |\r
+ hspi->Init.DataSize ) | frxth;\r
+\r
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Configure : CRC Polynomial */\r
+ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->State= HAL_SPI_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SPI peripheral\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Check the SPI handle allocation */\r
+ if(hspi == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY;\r
+\r
+ /* check flag before the SPI disable */\r
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);\r
+ SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);\r
+ SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);\r
+\r
+ /* Disable the SPI Peripheral Clock */\r
+ __HAL_SPI_DISABLE(hspi);\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
+ HAL_SPI_MspDeInit(hspi);\r
+\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->State = HAL_SPI_STATE_RESET;\r
+\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SPI MSP Init\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r
+ {\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_MspInit should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPI MSP DeInit\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_MspDeInit should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the SPI\r
+ data transfers.\r
+\r
+ [..] The SPI supports master and slave mode :\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These APIs return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmit an amount of data in blocking mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set the transaction information */\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+\r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Transmit data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* Transmit data in 16 Bit mode */\r
+ while (hspi->TxXferCount > 0)\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+ }\r
+ }\r
+ /* Transmit data in 8 Bit mode */\r
+ else\r
+ {\r
+ while (hspi->TxXferCount > 0)\r
+ {\r
+ if(hspi->TxXferCount != 0x1)\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ else\r
+ {\r
+ /* Wait until TXE flag is set to send data */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--; \r
+ }\r
+ }\r
+ }\r
+\r
+ /* Enable CRC Transmission */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;\r
+ }\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+ \r
+ hspi->State = HAL_SPI_STATE_READY; \r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ { \r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ __IO uint16_t tmpreg;\r
+ \r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this case we call the transmitReceive process */\r
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = (uint8_t *)NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ /* this is done to handle the CRCNEXT before the latest data */\r
+ hspi->RxXferCount--;\r
+ }\r
+\r
+ /* Set the Rx Fido thresold */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Configure communication direction 1Line and enabled SPI if needed */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Receive data in 8 Bit mode */\r
+ if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r
+ {\r
+ while(hspi->RxXferCount > 1)\r
+ {\r
+ /* Wait until the RXNE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;\r
+ hspi->RxXferCount--; \r
+ }\r
+ }\r
+ else /* Receive data in 16 Bit mode */\r
+ { \r
+ while(hspi->RxXferCount > 1 )\r
+ {\r
+ /* Wait until RXNE flag is reset to read data */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+ } \r
+ }\r
+ \r
+ /* Enable CRC Transmission */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) \r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ } \r
+\r
+ /* Wait until RXNE flag is set */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ /* Receive last data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ { \r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ }\r
+ /* Receive last data in 8 Bit mode */\r
+ else \r
+ {\r
+ (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ }\r
+ hspi->RxXferCount--;\r
+ \r
+ /* Read CRC from DR to close CRC calculation process */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) \r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ { \r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY; \r
+ \r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ { \r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in blocking mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @param Size: amount of data to be sent and received\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ __IO uint16_t tmpreg = 0;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+ \r
+ if(hspi->State != HAL_SPI_STATE_READY) \r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi); \r
+ \r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pRxData;\r
+ hspi->RxXferCount = Size;\r
+ hspi->RxXferSize = Size;\r
+ hspi->pTxBuffPtr = pTxData;\r
+ hspi->TxXferCount = Size;\r
+ hspi->TxXferSize = Size;\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+\r
+ /* Set the Rx Fido threshold */\r
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+\r
+ /* Check if the SPI is already enabled */\r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */\r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Transmit and Receive data in 16 Bit mode */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))\r
+ {\r
+ /* Check TXE flag */\r
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))\r
+ {\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+\r
+ /* Enable CRC Transmission */\r
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+ } \r
+ }\r
+\r
+ /* Check RXNE flag */\r
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r
+ {\r
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+ }\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) \r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Transmit and Receive data in 8 Bit mode */\r
+ else\r
+ {\r
+ while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))\r
+ {\r
+ /* check TXE flag */\r
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))\r
+ {\r
+ if(hspi->TxXferCount > 1)\r
+ {\r
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ }\r
+\r
+ /* Enable CRC Transmission */\r
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
+ }\r
+ }\r
+\r
+ /* Wait until RXNE flag is reset */\r
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r
+ {\r
+ if(hspi->RxXferCount > 1)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount -= 2;\r
+ if(hspi->RxXferCount <= 1)\r
+ {\r
+ /* set fiforxthresold before to switch on 8 bit data size */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ hspi->RxXferCount--;\r
+ }\r
+ }\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ __HAL_UNLOCK(hspi);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Read CRC from DR to close CRC calculation process */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+\r
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
+ {\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check the end of the transaction */\r
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ \r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ /* Clear CRC Flag */\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ { \r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in no-blocking mode with Interrupt\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+ \r
+ if(hspi->State == HAL_SPI_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+\r
+ /* Set the function for IT treatement */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ hspi->RxISR = NULL;\r
+ hspi->TxISR = SPI_TxISR_16BIT;\r
+ }\r
+ else\r
+ {\r
+ hspi->RxISR = NULL;\r
+ hspi->TxISR = SPI_TxISR_8BIT;\r
+ }\r
+ \r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+ \r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi); \r
+ }\r
+ \r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ /* Note : The SPI must be enabled after unlocking current process \r
+ to avoid the risk of SPI interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in no-blocking mode with Interrupt\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hspi->State == HAL_SPI_STATE_READY)\r
+ {\r
+ if((pData == NULL) || (Size == 0))\r
+ { \r
+ return HAL_ERROR; \r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ /* Configure communication */\r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this we call the transmitReceive process */\r
+ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);\r
+ }\r
+ \r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->CRCSize = 1;\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ hspi->CRCSize = 2;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ hspi->CRCSize = 0;\r
+ }\r
+ \r
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16 bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ hspi->RxISR = SPI_RxISR_16BIT;\r
+ hspi->TxISR = NULL;\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8 bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ hspi->RxISR = SPI_RxISR_8BIT;\r
+ hspi->TxISR = NULL;\r
+ }\r
+ \r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+ \r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ /* Enable TXE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ /* Note : The SPI must be enabled after unlocking current process \r
+ to avoid the risk of SPI interrupt handle execution before current\r
+ process unlock */\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @param Size: amount of data to be sent and received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+ \r
+ if((hspi->State == HAL_SPI_STATE_READY) || \\r
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))\r
+ {\r
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ hspi->CRCSize = 0;\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->CRCSize = 1;\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
+ {\r
+ hspi->CRCSize = 2;\r
+ }\r
+ }\r
+ \r
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ }\r
+ \r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pTxData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = pRxData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ \r
+ /* Set the function for IT treatement */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_16BIT;\r
+ hspi->TxISR = SPI_2linesTxISR_16BIT; \r
+ }\r
+ else\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_8BIT;\r
+ hspi->TxISR = SPI_2linesTxISR_8BIT;\r
+ }\r
+ \r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ /* check if packing mode is enabled and if there is more than 2 data to receive */\r
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16 bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8 bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ \r
+ /* Enable TXE, RXNE and ERR interrupt */\r
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit an amount of data in no-blocking mode with DMA\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{ \r
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
+\r
+ if(hspi->State != HAL_SPI_STATE_READY) \r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ hspi->State = HAL_SPI_STATE_BUSY_TX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = pData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)NULL;\r
+ hspi->RxXferSize = 0;\r
+ hspi->RxXferCount = 0;\r
+ \r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_TX(hspi);\r
+ }\r
+ \r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ /* Set the SPI TxDMA Half transfer complete callback */\r
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r
+ \r
+ /* Set the SPI TxDMA transfer complete callback */\r
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+ \r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ /* packing mode is enabled only if the DMA setting is HALWORD */\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
+ {\r
+ /* Check the even/odd of the data size + crc if enabled */\r
+ if((hspi->TxXferCount & 0x1) == 0)\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1);\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r
+ }\r
+ }\r
+ \r
+ /* Enable the Tx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+\r
+ /* Enable Tx DMA Request */\r
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+* @brief Receive an amount of data in no-blocking mode with DMA \r
+* @param hspi: SPI handle\r
+* @param pData: pointer to data buffer\r
+* @param Size: amount of data to be sent\r
+* @retval HAL status\r
+*/\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
+{\r
+ if(hspi->State != HAL_SPI_STATE_READY)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ if((pData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ hspi->State = HAL_SPI_STATE_BUSY_RX;\r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pRxBuffPtr = pData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ hspi->pTxBuffPtr = (uint8_t *)NULL;\r
+ hspi->TxXferSize = 0;\r
+ hspi->TxXferCount = 0;\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ /* the receive process is not supported in 2Lines direction master mode */\r
+ /* in this case we call the transmitReceive process */\r
+ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);\r
+ }\r
+ \r
+ /* Configure communication direction : 1Line */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
+ {\r
+ SPI_1LINE_RX(hspi);\r
+ }\r
+ \r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ /* packing mode management is enabled by the DMA settings */\r
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hspi);\r
+ /* Restriction the DMA data received is not allowed in this mode */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ \r
+ /* Set the SPI RxDMA Half transfer complete callback */\r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+\r
+ /* Set the SPI Rx DMA transfer complete callback */\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+ \r
+ /* Enable Rx DMA Request */ \r
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;\r
+ \r
+ /* Enable the Rx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Transmit and Receive an amount of data in no-blocking mode with DMA\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param pTxData: pointer to transmission data buffer\r
+ * @param pRxData: pointer to reception data buffer\r
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
+ \r
+ if((hspi->State == HAL_SPI_STATE_READY) ||\r
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))\r
+ {\r
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hspi);\r
+ \r
+ /* check if the transmit Receive function is not called by a receive master */\r
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r
+ { \r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
+ }\r
+ \r
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
+ hspi->TxXferSize = Size;\r
+ hspi->TxXferCount = Size;\r
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
+ hspi->RxXferSize = Size;\r
+ hspi->RxXferCount = Size;\r
+ \r
+ /* Reset CRC Calculation + increase the rxsize */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ /* Reset the threshold bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ \r
+ /* the packing mode management is enabled by the DMA settings according the spi data size */\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ {\r
+ /* set fiforxthreshold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ else\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ \r
+ if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ if((hspi->TxXferSize & 0x1) == 0x0 )\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = hspi->TxXferCount >> 1;\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r
+ } \r
+ }\r
+ \r
+ if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ /* set fiforxthresold according the reception data length: 16bit */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ \r
+ /* Size must include the CRC length */\r
+ if((hspi->RxXferCount & 0x1) == 0x0 )\r
+ {\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ hspi->RxXferCount = hspi->RxXferCount >> 1;\r
+ }\r
+ else\r
+ {\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
+ hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; \r
+ } \r
+ }\r
+ } \r
+ \r
+ /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is \r
+ the reception request (RXNE) */\r
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+ { \r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
+ }\r
+ else\r
+ { \r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r
+ }\r
+ /* Set the DMA error callback */\r
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
+ \r
+ /* Enable Rx DMA Request */ \r
+ hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;\r
+ \r
+ /* Enable the Rx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);\r
+ \r
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
+ is performed in DMA reception complete callback */\r
+ hspi->hdmatx->XferHalfCpltCallback = NULL;\r
+ hspi->hdmatx->XferCpltCallback = NULL;\r
+ \r
+ /* Set the DMA error callback */\r
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
+ \r
+ /* Enable the Tx DMA channel */\r
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
+ \r
+ /* Check if the SPI is already enabled */ \r
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r
+ {\r
+ /* Enable SPI peripheral */ \r
+ __HAL_SPI_ENABLE(hspi);\r
+ }\r
+ \r
+ /* Enable Tx DMA Request */ \r
+ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ /* Disable the SPI DMA Tx & Rx requests */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hspi);\r
+\r
+ /* Enable the SPI DMA Tx & Rx requests */\r
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* The Lock is not implemented on this API to allow the user application\r
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r
+ */\r
+ \r
+ /* Abort the SPI DMA tx Stream */\r
+ if(hspi->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hspi->hdmatx);\r
+ }\r
+ /* Abort the SPI DMA rx Stream */\r
+ if(hspi->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(hspi->hdmarx);\r
+ }\r
+\r
+ /* Disable the SPI DMA Tx & Rx requests */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPI interrupt request.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for the specified SPI module.\r
+ * @retval None\r
+ */\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* SPI in mode Receiver ----------------------------------------------------*/\r
+ if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&\r
+ (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))\r
+ {\r
+ hspi->RxISR(hspi);\r
+ return;\r
+ }\r
+ \r
+ /* SPI in mode Tramitter ---------------------------------------------------*/\r
+ if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))\r
+ { \r
+ hspi->TxISR(hspi);\r
+ return;\r
+ }\r
+ \r
+ /* SPI in Erreur Treatment ---------------------------------------------------*/\r
+ if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) \r
+ {\r
+ /* SPI Overrun error interrupt occured -------------------------------------*/\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) \r
+ {\r
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_OVR;\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+ \r
+ /* SPI Mode Fault error interrupt occured -------------------------------------*/\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)\r
+ { \r
+ hspi->ErrorCode |= HAL_SPI_ERROR_MODF;\r
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);\r
+ }\r
+ \r
+ /* SPI Frame error interrupt occured ----------------------------------------*/\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)\r
+ { \r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FRE;\r
+ __HAL_SPI_CLEAR_FREFLAG(hspi);\r
+ }\r
+ \r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ \r
+ return;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_RxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx and Rx Transfer completed callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx and Rx Half Transfer callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief SPI error callback\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_SPI_ErrorCallback should be implemented in the user file\r
+ */\r
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r
+ and user can use HAL_SPI_GetError() API to check the latest error occurred\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
+ * @brief SPI control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SPI.\r
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the SPI state\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval SPI state\r
+ */\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r
+{\r
+ return hspi->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the SPI error code\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval SPI error code in bitmap format\r
+ */\r
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r
+{\r
+ return hspi->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Private_Functions\r
+ * @brief Private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @brief DMA SPI transmit process complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* DMA Normal Mode */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r
+ {\r
+ /* Disable Tx DMA Request */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+\r
+ /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+\r
+ hspi->TxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ return;\r
+ }\r
+ }\r
+ HAL_SPI_TxCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI receive process complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ __IO uint16_t tmpreg;\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* CRC handling */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Wait until TXE flag */\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
+ { \r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
+ {\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ } \r
+ }\r
+\r
+ /* Disable Rx DMA Request */\r
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r
+ /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
+ hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r
+\r
+ /* Check the end of the transaction */\r
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);\r
+ \r
+ hspi->RxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ \r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi); \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI transmit receive process complete callback\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ __IO int16_t tmpreg;\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ /* CRC handling */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r
+ { \r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Error on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ else\r
+ {\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r
+ {\r
+ /* Erreur on the CRC reception */\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; \r
+ }\r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+ } \r
+ \r
+ /* Check the end of the transaction */\r
+ SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);\r
+ \r
+ /* Disable Tx DMA Request */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
+ \r
+ /* Disable Rx DMA Request */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
+ \r
+ hspi->TxXferCount = 0;\r
+ hspi->RxXferCount = 0;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ \r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ { \r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_TxRxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI half transmit process complete callback\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_SPI_TxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI half receive process complete callback\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_SPI_RxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI Half transmit receive process complete callback\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ HAL_SPI_TxRxHalfCpltCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief DMA SPI communication error callback\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ /* Stop the disable DMA transfer on SPI side */\r
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
+\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_DMA;\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_ErrorCallback(hspi);\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in packing mode */\r
+ if(hspi->RxXferCount > 1)\r
+ {\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount -= 2;\r
+ if(hspi->RxXferCount == 1)\r
+ {\r
+ /* set fiforxthresold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
+ }\r
+ }\r
+ /* Receive data in 8 Bit mode */\r
+ else\r
+ {\r
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);\r
+ hspi->RxXferCount--;\r
+ }\r
+ \r
+ /* check end of the reception */\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;\r
+ return;\r
+ }\r
+ \r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx Handler for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint8_t tmpreg;\r
+ \r
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ hspi->CRCSize--;\r
+ \r
+ /* check end of the reception */\r
+ if(hspi->CRCSize == 0)\r
+ {\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Transmit data in packing Bit mode */\r
+ if(hspi->TxXferCount >= 2)\r
+ {\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount -= 2;\r
+ }\r
+ /* Transmit data in 8 Bit mode */\r
+ else\r
+ { \r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ }\r
+ \r
+ /* check the end of the transmission */\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+ /* Disable TXE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+ \r
+ if(hspi->RxXferCount == 0)\r
+ { \r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in 16 Bit mode */\r
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;\r
+ return;\r
+ }\r
+ \r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Receive data in 16 Bit mode */\r
+ __IO uint16_t tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ /* Disable RXNE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
+\r
+ SPI_CloseRxTx_ISR(hspi);\r
+}\r
+\r
+/**\r
+ * @brief Tx Handler for Transmit and Receive in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Transmit data in 16 Bit mode */\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+ \r
+ /* Enable CRC Transmission */\r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+ /* Disable TXE interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ SPI_CloseRxTx_ISR(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Manage the CRC receive in Interrupt context\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint8_t tmpreg;\r
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ hspi->CRCSize--;\r
+ \r
+ if(hspi->CRCSize == 0)\r
+ { \r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Manage the receive in Interrupt context\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);\r
+ hspi->RxXferCount--;\r
+\r
+ /* Enable CRC Transmission */\r
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+\r
+ if(hspi->RxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_RxISR_8BITCRC;\r
+ return;\r
+ }\r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Manage the CRC 16bit receive in Interrupt context\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ __IO uint16_t tmpreg;\r
+ \r
+ tmpreg = hspi->Instance->DR;\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+ \r
+ SPI_CloseRx_ISR(hspi);\r
+}\r
+\r
+/**\r
+ * @brief Manage the 16Bit receive in Interrupt context\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r
+ hspi->pRxBuffPtr += sizeof(uint16_t);\r
+ hspi->RxXferCount--;\r
+ \r
+ /* Enable CRC Transmission */\r
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
+ {\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+ \r
+ if(hspi->RxXferCount == 0)\r
+ { \r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ hspi->RxISR = SPI_RxISR_16BITCRC;\r
+ return;\r
+ }\r
+ SPI_CloseRx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle the data 8Bit transmit in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
+{\r
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r
+ hspi->TxXferCount--;\r
+ \r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Enable CRC Transmission */\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+ SPI_CloseTx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handle the data 16Bit transmit in Interrupt mode\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
+{ \r
+ /* Transmit data in 16 Bit mode */\r
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
+ hspi->pTxBuffPtr += sizeof(uint16_t);\r
+ hspi->TxXferCount--;\r
+ \r
+ if(hspi->TxXferCount == 0)\r
+ {\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ /* Enable CRC Transmission */\r
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r
+ }\r
+ SPI_CloseTx_ISR(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SPI Communication Timeout.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Flag : SPI flag to check\r
+ * @param State : flag state to check\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ while((hspi->Instance->SR & Flag) != State)\r
+ {\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+ on both master and slave sides in order to resynchronize the master\r
+ and slave for their respective CRC calculation */\r
+\r
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+ \r
+ hspi->State= HAL_SPI_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief This function handles SPI Communication Timeout.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Fifo : Fifo to check\r
+ * @param State : Fifo state to check\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)\r
+{\r
+ __IO uint8_t tmpreg;\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ while((hspi->Instance->SR & Fifo) != State)\r
+ {\r
+ if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r
+ {\r
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r
+ UNUSED(tmpreg); /* To avoid GCC warning */\r
+ }\r
+\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
+ on both master and slave sides in order to resynchronize the master\r
+ and slave for their respective CRC calculation */\r
+\r
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
+\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+\r
+ /* Reset CRC Calculation */\r
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
+ {\r
+ SPI_RESET_CRC(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hspi);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles the check of the RX transaction complete.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @param Timeout : Timeout duration\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)\r
+{\r
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
+ {\r
+ /* Disable SPI peripheral */\r
+ __HAL_SPI_DISABLE(hspi);\r
+ }\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r
+ { \r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) \r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief This function handles the check of the RXTX or TX transaction complete.\r
+ * @param hspi: SPI handle\r
+ * @param Timeout : Timeout duration\r
+ */\r
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)\r
+{\r
+ /* Procedure to check the transaction complete */\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)\r
+ {\r
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r
+ return HAL_TIMEOUT;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles the close of the RXTX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
+\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_TxRxCpltCallback(hspi);\r
+ } \r
+ }\r
+ else\r
+ {\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles the close of the RX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable RXNE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
+ \r
+ /* Check the end of the transaction */\r
+ SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+\r
+ /* Check if CRC error occurred */\r
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
+ {\r
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_RxCpltCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles the close of the TX transaction.\r
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\r
+ * the configuration information for SPI module.\r
+ * @retval None\r
+ */\r
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r
+{\r
+ /* Disable TXE and ERR interrupt */\r
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
+\r
+ /* Clear OVERUN flag in 2 Lines communication mode because received is not read */\r
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
+ {\r
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
+ }\r
+\r
+ hspi->State = HAL_SPI_STATE_READY;\r
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
+ {\r
+ HAL_SPI_ErrorCallback(hspi);\r
+ }\r
+ else\r
+ {\r
+ HAL_SPI_TxCpltCallback(hspi);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sram.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SRAM HAL module driver.\r
+ * This file provides a generic firmware to drive SRAM memories \r
+ * mounted as external device.\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ This driver is a generic layered driver which contains a set of APIs used to \r
+ control SRAM memories. It uses the FMC layer functions to interface \r
+ with SRAM devices. \r
+ The following sequence should be followed to configure the FMC to interface\r
+ with SRAM/PSRAM memories: \r
+ \r
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:\r
+ SRAM_HandleTypeDef hsram; and: \r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed \r
+ values of the structure member.\r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined \r
+ base register instance for NOR or SRAM device \r
+ \r
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined\r
+ base register instance for NOR or SRAM extended mode \r
+ \r
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended \r
+ mode timings; for example:\r
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;\r
+ and fill its fields with the allowed values of the structure member.\r
+ \r
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function\r
+ performs the following sequence:\r
+ \r
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()\r
+ (##) Control register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Init()\r
+ (##) Timing register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Timing_Init()\r
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function \r
+ FMC_NORSRAM_Extended_Timing_Init()\r
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() \r
+\r
+ (#) At this stage you can perform read/write accesses from/to the memory connected \r
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the\r
+ following APIs:\r
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access\r
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer\r
+ \r
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/\r
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation \r
+ \r
+ (#) You can continuously monitor the SRAM device HAL state by calling the function\r
+ HAL_SRAM_GetState() \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SRAM SRAM \r
+ * @brief SRAM driver modules\r
+ * @{\r
+ */\r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions.\r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SRAM Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to initialize/de-initialize\r
+ the SRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Performs the SRAM device initialization sequence\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param Timing: Pointer to SRAM control timing structure \r
+ * @param ExtTiming: Pointer to SRAM extended mode timing structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r
+{ \r
+ /* Check the SRAM handle parameter */\r
+ if(hsram == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(hsram->State == HAL_SRAM_STATE_RESET)\r
+ { \r
+ /* Initialize the low level hardware (MSP) */\r
+ HAL_SRAM_MspInit(hsram);\r
+ }\r
+ \r
+ /* Initialize SRAM control Interface */\r
+ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));\r
+\r
+ /* Initialize SRAM timing Interface */\r
+ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); \r
+\r
+ /* Initialize SRAM extended mode timing Interface */\r
+ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); \r
+ \r
+ /* Enable the NORSRAM device */\r
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Performs the SRAM device De-initialization sequence.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)\r
+{ \r
+ /* De-Initialize the low level hardware (MSP) */\r
+ HAL_SRAM_MspDeInit(hsram);\r
+ \r
+ /* Configure the SRAM registers with their reset values */\r
+ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);\r
+\r
+ hsram->State = HAL_SRAM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hsram);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief SRAM MSP Init.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief SRAM MSP DeInit.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete callback.\r
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DMA transfer complete error callback.\r
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions \r
+ * @brief Input Output and memory control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### SRAM Input and Output functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to use and control the SRAM memory\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads 8-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint8_t *)psramaddress;\r
+ pDstBuffer++;\r
+ psramaddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 8-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r
+ \r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint8_t *)psramaddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ psramaddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 16-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint16_t *)psramaddress;\r
+ pDstBuffer++;\r
+ psramaddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 16-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress; \r
+ \r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint16_t *)psramaddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ psramaddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads 32-bit buffer from SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Read data from memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *pDstBuffer = *(__IO uint32_t *)pAddress;\r
+ pDstBuffer++;\r
+ pAddress++;\r
+ }\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes 32-bit buffer to SRAM memory. \r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+\r
+ /* Write data to memory */\r
+ for(; BufferSize != 0; BufferSize--)\r
+ {\r
+ *(__IO uint32_t *)pAddress = *pSrcBuffer; \r
+ pSrcBuffer++;\r
+ pAddress++; \r
+ } \r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to read start address\r
+ * @param pDstBuffer: Pointer to destination buffer \r
+ * @param BufferSize: Size of the buffer to read from memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;\r
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r
+\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @param pAddress: Pointer to write start address\r
+ * @param pSrcBuffer: Pointer to source buffer to write \r
+ * @param BufferSize: Size of the buffer to write to memory\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r
+{\r
+ /* Check the SRAM controller state */\r
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY; \r
+ \r
+ /* Configure DMA user callbacks */\r
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;\r
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r
+\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY; \r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions \r
+ * @brief Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the SRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables dynamically SRAM write operation.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+\r
+ /* Enable write operation */\r
+ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically SRAM write operation.\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hsram);\r
+\r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_BUSY;\r
+ \r
+ /* Disable write operation */\r
+ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); \r
+ \r
+ /* Update the SRAM controller state */\r
+ hsram->State = HAL_SRAM_STATE_PROTECTED;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hsram); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### SRAM State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the SRAM controller \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Returns the SRAM controller state\r
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains\r
+ * the configuration information for SRAM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)\r
+{\r
+ return hsram->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Timer (TIM) peripheral:\r
+ * + Time Base Initialization\r
+ * + Time Base Start\r
+ * + Time Base Start Interruption\r
+ * + Time Base Start DMA\r
+ * + Time Output Compare/PWM Initialization\r
+ * + Time Output Compare/PWM Channel Configuration\r
+ * + Time Output Compare/PWM Start\r
+ * + Time Output Compare/PWM Start Interruption\r
+ * + Time Output Compare/PWM Start DMA\r
+ * + Time Input Capture Initialization\r
+ * + Time Input Capture Channel Configuration\r
+ * + Time Input Capture Start\r
+ * + Time Input Capture Start Interruption \r
+ * + Time Input Capture Start DMA\r
+ * + Time One Pulse Initialization\r
+ * + Time One Pulse Channel Configuration\r
+ * + Time One Pulse Start \r
+ * + Time Encoder Interface Initialization\r
+ * + Time Encoder Interface Start\r
+ * + Time Encoder Interface Start Interruption\r
+ * + Time Encoder Interface Start DMA\r
+ * + Commutation Event configuration with Interruption and DMA\r
+ * + Time OCRef clear configuration\r
+ * + Time External Clock configuration\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### TIMER Generic features #####\r
+ ==============================================================================\r
+ [..] The Timer features include: \r
+ (#) 16-bit up, down, up/down auto-reload counter.\r
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the \r
+ counter clock frequency either by any factor between 1 and 65536.\r
+ (#) Up to 4 independent channels for:\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions \r
+ depending from feature used :\r
+ (++) Time Base : HAL_TIM_Base_MspInit() \r
+ (++) Input Capture : HAL_TIM_IC_MspInit()\r
+ (++) Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+ \r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); \r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the \r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before \r
+ any start function.\r
+ \r
+ (#) Configure the TIM in the desired functioning mode using one of the \r
+ initialization function of this driver:\r
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an \r
+ Output Compare signal.\r
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a \r
+ PWM signal.\r
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an \r
+ external signal.\r
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer \r
+ in One Pulse Mode.\r
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+ \r
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used: \r
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+ (#) The DMA Burst is managed with the two following functions:\r
+ HAL_TIM_DMABurst_WriteStart()\r
+ HAL_TIM_DMABurst_ReadStart()\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM TIM\r
+ * @brief TIM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef * sSlaveConfig);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions \r
+ * @brief Time Base functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Base functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM base. \r
+ (+) De-initialize the TIM base.\r
+ (+) Start the Time Base.\r
+ (+) Stop the Time Base.\r
+ (+) Start the Time Base and enable interrupt.\r
+ (+) Stop the Time Base and disable interrupt.\r
+ (+) Start the Time Base and enable DMA transfer.\r
+ (+) Stop the Time Base and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Time base Unit according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance)); \r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Set the Time Base configuration */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Base peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Base MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Base MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Change the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the TIM Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ /* Disable the TIM Update interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);\r
+ \r
+ /* Enable the TIM Update DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions \r
+ * @brief Time Output Compare functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Output Compare. \r
+ (+) De-initialize the TIM Output Compare.\r
+ (+) Start the Time Output Compare.\r
+ (+) Stop the Time Output Compare.\r
+ (+) Start the Time Output Compare and enable interrupt.\r
+ (+) Stop the Time Output Compare and disable interrupt.\r
+ (+) Start the Time Output Compare and enable DMA transfer.\r
+ (+) Stop the Time Output Compare and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Output Compare according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Init the base time for the Output Compare */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Output Compare MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ } \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ } \r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ } \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions \r
+ * @brief Time PWM functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time PWM functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM OPWM. \r
+ (+) De-initialize the TIM PWM.\r
+ (+) Start the Time PWM.\r
+ (+) Stop the Time PWM.\r
+ (+) Start the Time PWM and enable interrupt.\r
+ (+) Stop the Time PWM and disable interrupt.\r
+ (+) Start the Time PWM and enable DMA transfer.\r
+ (+) Stop the Time PWM and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM PWM Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspInit(htim);\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Init the base time for the PWM */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM PWM MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Output Capture/Compare 3 request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions \r
+ * @brief Time Input Capture functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Input Capture functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Input Capture. \r
+ (+) De-initialize the TIM Input Capture.\r
+ (+) Start the Time Input Capture.\r
+ (+) Stop the Time Input Capture.\r
+ (+) Start the Time Input Capture and enable interrupt.\r
+ (+) Stop the Time Input Capture and disable interrupt.\r
+ (+) Start the Time Input Capture and enable DMA transfer.\r
+ (+) Stop the Time Input Capture and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Input Capture Time base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); \r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Init the base time for the input capture */ \r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM INput Capture MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Input Capture MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+\r
+ /* Return function status */\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+\r
+ /* Return function status */\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ } \r
+ \r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement on in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */ \r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement on in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions \r
+ * @brief Time One Pulse functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time One Pulse functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM One Pulse. \r
+ (+) De-initialize the TIM One Pulse.\r
+ (+) Start the Time One Pulse.\r
+ (+) Stop the Time One Pulse.\r
+ (+) Start the Time One Pulse and enable interrupt.\r
+ (+) Stop the Time One Pulse and disable interrupt.\r
+ (+) Start the Time One Pulse and enable DMA transfer.\r
+ (+) Stop the Time One Pulse and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM One Pulse Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OnePulseMode: Select the One pulse mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+ \r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OnePulse_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Configure the Time base in the One Pulse Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+ \r
+ /* Reset the OPM Bit */\r
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+ /* Configure the OPM Mode */\r
+ htim->Instance->CR1 |= OnePulseMode;\r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM One Pulse \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_OnePulse_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM One Pulse MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Enable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
+ \r
+ No need to enable the counter, it's enabled automatically by hardware \r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Disable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Enable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r
+ \r
+ No need to enable the counter, it's enabled automatically by hardware \r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+ \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel : TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); \r
+ \r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Disable the Capture compare and the Input Capture channels \r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) \r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions \r
+ * @brief Time Encoder functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Time Encoder functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Encoder. \r
+ (+) De-initialize the TIM Encoder.\r
+ (+) Start the Time Encoder.\r
+ (+) Stop the Time Encoder.\r
+ (+) Start the Time Encoder and enable interrupt.\r
+ (+) Stop the Time Encoder and disable interrupt.\r
+ (+) Start the Time Encoder and enable DMA transfer.\r
+ (+) Stop the Time Encoder and disable DMA transfer.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Encoder Interface configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+ if(htim->State == HAL_TIM_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_Encoder_MspInit(htim);\r
+ }\r
+ \r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY; \r
+ \r
+ /* Reset the SMS bits */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ \r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init); \r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = htim->Instance->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr |= sConfig->EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));\r
+ \r
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);\r
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);\r
+ \r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+ /* Write to TIMx CCER */\r
+ htim->Instance->CCER = tmpccer;\r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Encoder interface \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Encoder_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET;\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Encoder Interface MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the encoder interface channels */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break; \r
+ }\r
+ } \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break; \r
+ }\r
+ } \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the encoder interface channels */\r
+ /* Enable the capture compare Interrupts 1 and/or 2 */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break; \r
+ }\r
+ case TIM_CHANNEL_2:\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); \r
+ break;\r
+ } \r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break; \r
+ }\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ if(Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 1 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ } \r
+ else if(Channel == TIM_CHANNEL_2)\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ } \r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts 1 and 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @param pData1: The destination Buffer address for IC1.\r
+ * @param pData2: The destination Buffer address for IC2.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); \r
+ \r
+ /* Enable the TIM Input Capture DMA request */ \r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;\r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
+ \r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_ALL:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);\r
+ \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ \r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r
+ if(Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 1 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ } \r
+ else if(Channel == TIM_CHANNEL_2)\r
+ { \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ } \r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare DMA Request 1 and 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management \r
+ * @brief IRQ handler management \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IRQ handler management #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides Timer IRQ handler function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles TIM interrupts requests.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Capture compare 1 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)\r
+ {\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ \r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)\r
+ {\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ }\r
+ /* Capture compare 2 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 3 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim); \r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 4 event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ /* Input capture event */\r
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)\r
+ { \r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* TIM Update event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+ }\r
+ }\r
+ /* TIM Break input event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+ HAL_TIMEx_BreakCallback(htim);\r
+ }\r
+ }\r
+ \r
+ /* TIM Break input event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+ HAL_TIMEx_BreakCallback(htim);\r
+ }\r
+ }\r
+\r
+ /* TIM Trigger detection event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+ HAL_TIM_TriggerCallback(htim);\r
+ }\r
+ }\r
+ /* TIM commutation event */\r
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
+ {\r
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
+ HAL_TIMEx_CommutationCallback(htim);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the DMA Burst Mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Output Compare configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture Channels according to the specified\r
+ * parameters in the TIM_IC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Input Capture configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TIM_TI1_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI2_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Set the IC2PSC value */\r
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI3_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+ /* Set the IC3PSC value */\r
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI4_SetConfig(htim->Instance, \r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+ /* Set the IC4PSC value */\r
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);\r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM PWM configuration structure\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse Channels according to the specified\r
+ * parameters in the TIM_OnePulse_InitTypeDef.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM One Pulse configuration structure\r
+ * @param OutputChannel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @param InputChannel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)\r
+{\r
+ TIM_OC_InitTypeDef temp1;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+ if(OutputChannel != InputChannel) \r
+ {\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Extract the Output compare configuration from sConfig structure */ \r
+ temp1.OCMode = sConfig->OCMode;\r
+ temp1.Pulse = sConfig->Pulse;\r
+ temp1.OCPolarity = sConfig->OCPolarity;\r
+ temp1.OCNPolarity = sConfig->OCNPolarity;\r
+ temp1.OCIdleState = sConfig->OCIdleState;\r
+ temp1.OCNIdleState = sConfig->OCNIdleState; \r
+ \r
+ switch (OutputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ TIM_OC1_SetConfig(htim->Instance, &temp1); \r
+ }\r
+ break;\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ } \r
+ switch (InputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+ \r
+ /* Select the Slave Mode */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ }\r
+ break;\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+ \r
+ /* Select the Slave Mode */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMABASE_CR1 \r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT \r
+ * @arg TIM_DMABASE_PSC \r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3 \r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_DCR\r
+ * @param BurstRequestSrc: TIM DMA Request sources.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer: The Buffer address.\r
+ * @param BurstLength: DMA Burst length. This parameter can be one value\r
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t* BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((BurstBuffer == 0 ) && (BurstLength > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = BurstBaseAddress | BurstLength; \r
+ \r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); \r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM DMA Burst mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstRequestSrc: TIM DMA Request sources to disable\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ \r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMABASE_CR1 \r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT \r
+ * @arg TIM_DMABASE_PSC \r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3 \r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_DCR\r
+ * @param BurstRequestSrc: TIM DMA Request sources.\r
+ * This parameters can be on of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer: The Buffer address.\r
+ * @param BurstLength: DMA Burst length. This parameter can be one value\r
+ * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if((BurstBuffer == 0 ) && (BurstLength > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); \r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = BurstBaseAddress | BurstLength; \r
+ \r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA burst reading \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param BurstRequestSrc: TIM DMA Request sources to disable.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ \r
+ /* Abort the DMA transfer (at least disable the DMA channel) */\r
+ switch(BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC1:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC2:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC3:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r
+ }\r
+ break;\r
+ case TIM_DMA_CC4:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r
+ }\r
+ break;\r
+ case TIM_DMA_COM:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ }\r
+ break;\r
+ case TIM_DMA_TRIGGER:\r
+ { \r
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ }\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Generate a software event\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param EventSource: specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source \r
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source \r
+ * @note TIM6 and TIM7 can only generate an update event. \r
+ * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.\r
+ * @retval HAL status\r
+ */ \r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Set the event sources */\r
+ htim->Instance->EGR = EventSource;\r
+ \r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral. \r
+ * @param Channel: specifies the TIM Channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */ \r
+__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)\r
+ {\r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+ \r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ }\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_2: \r
+ { \r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_3: \r
+ { \r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_4: \r
+ { \r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ if(sClearInputConfig->ClearInputState != RESET) \r
+ {\r
+ /* Enable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; \r
+ }\r
+ } \r
+ break;\r
+ default: \r
+ break;\r
+ } \r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Configures the clock source to be used\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that\r
+ * contains the clock source information for the TIM peripheral. \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) \r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+ \r
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ switch (sClockSourceConfig->ClockSource)\r
+ {\r
+ case TIM_CLOCKSOURCE_INTERNAL:\r
+ { \r
+ assert_param(IS_TIM_INSTANCE(htim->Instance)); \r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_ETRMODE1:\r
+ {\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClockSourceConfig->ClockPrescaler, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ /* Reset the SMS and TS Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ /* Select the External clock mode1 and the ETRF trigger */\r
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_ETRMODE2:\r
+ {\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sClockSourceConfig->ClockPrescaler, \r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ /* Enable the External clock mode2 */\r
+ htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLOCKSOURCE_TI1:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ TIM_TI1_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_TI2:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ TIM_TI2_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity, \r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_TI1ED:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+ TIM_TI1_ConfigInputStage(htim->Instance, \r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR0:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR1:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR2:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);\r
+ }\r
+ break;\r
+ case TIM_CLOCKSOURCE_ITR3:\r
+ {\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
+ * or a XOR combination between CH1_input, CH2_input & CH3_input\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param TI1_Selection: Indicate whether or not channel 1 is connected to the\r
+ * output of a XOR gate.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+ * pins are connected to the TI1 input (XOR combination)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+ uint32_t tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); \r
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Reset the TI1 selection */\r
+ tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+ /* Set the TI1 selection */\r
+ tmpcr2 |= TI1_Selection;\r
+ \r
+ /* Write to TIMxCR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the ) and the Slave \r
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sSlaveConfig->TriggerPrescaler, \r
+ sSlaveConfig->TriggerPolarity, \r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer; \r
+ \r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR0:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR1:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR2:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode in interrupt mode\r
+ * @param htim: TIM handle.\r
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the ) and the Slave \r
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, \r
+ TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r
+ \r
+ /* Enable Trigger Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+ \r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read the captured value from Capture Compare unit\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channels to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval Captured value\r
+ */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 1 value */\r
+ tmpreg = htim->Instance->CCR1;\r
+ \r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 2 value */\r
+ tmpreg = htim->Instance->CCR2;\r
+ \r
+ break;\r
+ }\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 3 value */\r
+ tmpreg = htim->Instance->CCR3;\r
+ \r
+ break;\r
+ }\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+ \r
+ /* Return the capture 4 value */\r
+ tmpreg = htim->Instance->CCR4;\r
+ \r
+ break;\r
+ }\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### TIM Callbacks functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides TIM callback functions:\r
+ (+) Timer Period elapsed callback\r
+ (+) Timer Output Compare callback\r
+ (+) Timer Input capture callback\r
+ (+) Timer Trigger callback\r
+ (+) Timer Error callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+ */\r
+ \r
+}\r
+/**\r
+ * @brief Output Compare callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @brief Input Capture callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timer error callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIM_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions \r
+ * @brief Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Base state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM OC state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM PWM state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Input Capture state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM One Pulse Mode state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Encoder Mode state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA error callback \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIM_ErrorCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+/**\r
+ * @brief TIM DMA Capture complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ \r
+ HAL_TIM_IC_CaptureCallback(htim); \r
+ \r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse complete callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; \r
+ \r
+ htim->State= HAL_TIM_STATE_READY; \r
+ \r
+ HAL_TIM_TriggerCallback(htim);\r
+}\r
+\r
+/**\r
+ * @brief Time Base configuration\r
+ * @param TIMx: TIM peripheral\r
+ * @param Structure: pointer on TIM Time Base required parameters \r
+ * @retval None\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+ uint32_t tmpcr1 = 0;\r
+ tmpcr1 = TIMx->CR1;\r
+ \r
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+ if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+ tmpcr1 |= Structure->CounterMode;\r
+ }\r
+ \r
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= ~TIM_CR1_CKD;\r
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Auto-reload value */\r
+ TIMx->ARR = (uint32_t)Structure->Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = (uint32_t)Structure->Prescaler;\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) \r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = Structure->RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler \r
+ and the repetition counter(only for TIM1 and TIM8) value immediately */\r
+ TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 1 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= OC_Config->OCPolarity;\r
+\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ { \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= OC_Config->OCNPolarity;\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC1NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS1;\r
+ tmpcr2 &= ~TIM_CR2_OIS1N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= OC_Config->OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= OC_Config->OCNIdleState;\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+} \r
+\r
+/**\r
+ * @brief Time Output Compare 2 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 4);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 4);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC2NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS2;\r
+ tmpcr2 &= ~TIM_CR2_OIS2N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 2);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 3 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the Channel 3: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC3S; \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 8);\r
+ \r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 8);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC3NE;\r
+ \r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS3;\r
+ tmpcr2 &= ~TIM_CR2_OIS3N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 4);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 4 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC4P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 12);\r
+ \r
+ /*if((TIMx == TIM1) || (TIMx == TIM8))*/\r
+ if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r
+ {\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS4;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 6);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Time Output Compare 4 configuration\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sSlaveConfig: The slave configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef * sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ \r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance, \r
+ sSlaveConfig->TriggerPrescaler, \r
+ sSlaveConfig->TriggerPolarity, \r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer; \r
+ \r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ \r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR0:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR1:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR2:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None \r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 \r
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+ {\r
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+ tmpccmr1 |= TIM_ICSelection;\r
+ } \r
+ else\r
+ {\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+ }\r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI1.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = TIMx->CCER;\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1; \r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= (TIM_ICFilter << 4);\r
+ \r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_ICPolarity;\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+ tmpccmr1 |= (TIM_ICSelection << 8);\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI2.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+uint32_t tmpccmr1 = 0;\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= (TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= (TIM_ICPolarity << 4);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+ tmpccmr2 |= TIM_ICSelection;\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);\r
+\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @arg TIM_ICPolarity_BothEdge \r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 \r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r
+ * protected against un-initialized filter and polarity values. \r
+ */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2 = 0;\r
+ uint32_t tmpccer = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+ tmpccmr2 |= (TIM_ICSelection << 8);\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ITRx: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source and the slave mode*/\r
+ tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+ uint32_t tmpsmcr = 0;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));\r
+\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param ChannelState: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); \r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1E << Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim_ex.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Timer extension peripheral:\r
+ * + Time Hall Sensor Interface Initialization\r
+ * + Time Hall Sensor Interface Start\r
+ * + Time Complementary signal bread and dead time configuration \r
+ * + Time Master and Slave synchronization configuration\r
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
+ * + Time OCRef clear configuration\r
+ * + Timer remapping capabilities configuration \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### TIMER Extended features #####\r
+ ==============================================================================\r
+ [..] \r
+ The Timer Extension features include: \r
+ (#) Complementary outputs with programmable dead-time for :\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to \r
+ interconnect several timers together.\r
+ (#) Break input to put the timer output signals in reset state or in a known state.\r
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for \r
+ positioning purposes \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions \r
+ depending from feature used :\r
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()\r
+ \r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __GPIOx_CLK_ENABLE(); \r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); \r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the \r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before \r
+ any start function.\r
+ \r
+ (#) Configure the TIM in the desired functioning mode using one of the \r
+ initialization function of this driver:\r
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the \r
+ Timer Hall Sensor Interface and the commutation event with the corresponding \r
+ Interrupt and DMA request if needed (Note that One Timer is used to interface \r
+ with the Hall sensor Interface and another Timer should be used to use \r
+ the commutation event).\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions: \r
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
+\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx TIM Extended HAL module driver\r
+ * @brief TIM Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define BDTR_BKF_SHIFT (16)\r
+#define BDTR_BK2F_SHIFT (20)\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIMEx_Private_Functions\r
+ * @{\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); \r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIMEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Hall Sensor functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure TIM HAL Sensor. \r
+ (+) De-initialize TIM HAL Sensor.\r
+ (+) Start the Hall Sensor Interface.\r
+ (+) Stop the Hall Sensor Interface.\r
+ (+) Start the Hall Sensor Interface and enable interrupts.\r
+ (+) Stop the Hall Sensor Interface and disable interrupts.\r
+ (+) Start the Hall Sensor Interface and enable DMA transfers.\r
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sConfig: TIM Hall Sensor configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)\r
+{\r
+ TIM_OC_InitTypeDef OC_Config;\r
+ \r
+ /* Check the TIM handle allocation */\r
+ if(htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+\r
+ /* Set the TIM state */\r
+ htim->State= HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIMEx_HallSensor_MspInit(htim);\r
+ \r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+ \r
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
+ \r
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
+ htim->Instance->CR2 |= TIM_CR2_TI1S;\r
+ \r
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
+ \r
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ \r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
+ \r
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+ OC_Config.OCMode = TIM_OCMODE_PWM2;\r
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+ OC_Config.Pulse = sConfig->Commutation_Delay; \r
+ \r
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
+ \r
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
+ register to 101 */\r
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF; \r
+ \r
+ /* Initialize the TIM state*/\r
+ htim->State= HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Hall Sensor interface \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIMEx_HallSensor_MspDeInit(htim);\r
+ \r
+ /* Change TIM state */ \r
+ htim->State = HAL_TIM_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Hall Sensor MSP.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall sensor Interface.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1, 2 and 3\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Enable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ /* Disable the capture compare Interrupts event */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param pData: The destination Buffer address.\r
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ /* Enable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r
+ \r
+ /* Set the DMA Input Capture 1 Callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream for Capture 1*/\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r
+ \r
+ /* Enable the capture compare 1 Interrupt */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ \r
+ /* Disable the Input Capture channels 1\r
+ (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ \r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r
+ \r
+ \r
+ /* Disable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary Output Compare functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary Output Compare/PWM.\r
+ (+) Stop the Complementary Output Compare/PWM.\r
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+ \r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer = 0; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+{\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode \r
+ * on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary PWM functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary PWM.\r
+ (+) Stop the Complementary PWM.\r
+ (+) Start the Complementary PWM and enable interrupts.\r
+ (+) Stop the Complementary PWM and disable interrupts.\r
+ (+) Start the Complementary PWM and enable DMA transfers.\r
+ (+) Stop the Complementary PWM and disable DMA transfers.\r
+ (+) Start the Complementary Input Capture measurement.\r
+ (+) Stop the Complementary Input Capture.\r
+ (+) Start the Complementary Input Capture and enable interrupts.\r
+ (+) Stop the Complementary Input Capture and disable interrupts.\r
+ (+) Start the Complementary Input Capture and enable DMA transfers.\r
+ (+) Stop the Complementary Input Capture and disable DMA transfers.\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation on the complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); \r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode on the \r
+ * complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+ \r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode on the \r
+ * complementary output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+} \r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode on the \r
+ * complementary output\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData: The source Buffer address.\r
+ * @param Length: The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ if((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if(((uint32_t)pData == 0 ) && (Length > 0)) \r
+ {\r
+ return HAL_ERROR; \r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ } \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA Period elapsed callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r
+ \r
+ /* Enable the DMA Stream */\r
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r
+ \r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary\r
+ * output\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param Channel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ { \r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ } \r
+ \r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+ \r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Timer Complementary One Pulse functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation on the complemetary \r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+ \r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation on the complementary \r
+ * output.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r
+ \r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ } \r
+ \r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param OutputChannel: TIM Channel to be disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ \r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ \r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+ \r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim); \r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the commutation event in case of use of the Hall sensor interface.\r
+ (+) Configure the DMA Burst Mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configure the TIM commutation event sequence.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed \r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with interrupt.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ /* Enable the Commutation Interrupt Request */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with DMA.\r
+ * @note This function is mandatory to use the commutation event in order to \r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer) \r
+ * configured in Hall sensor interface, this interface Timer will generate the \r
+ * commutation at its TRGO output (connected to Timer used in this function) each time \r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource: the Commutation Event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+ \r
+ __HAL_LOCK(htim);\r
+ \r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ { \r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+ \r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+ \r
+ /* Enable the Commutation DMA Request */\r
+ /* Set the DMA Commutation Callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; \r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;\r
+ \r
+ /* Enable the Commutation DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: TIM Output Compare handle\r
+ * @param sConfig: TIM Output Compare configuration structure\r
+ * @param Channel : TIM Channels to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected \r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected \r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected \r
+ * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim); \r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 5 in Output Compare */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the TIM Channel 6 in Output Compare */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim: TIM PWM handle\r
+ * @param sConfig: TIM PWM configuration structure\r
+ * @param Channel : TIM Channels to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected \r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected \r
+ * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, \r
+ TIM_OC_InitTypeDef* sConfig, \r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel)); \r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel5*/\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode; \r
+ }\r
+ break;\r
+ \r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r
+ \r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ \r
+ /* Set the Preload enable bit for channel6 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
+ \r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break; \r
+ }\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim: TIM handle\r
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral. \r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @arg TIM_Channel_5: TIM Channel 5\r
+ * @arg TIM_Channel_6: TIM Channel 6\r
+ * @retval None\r
+ */ \r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel)\r
+{ \r
+ uint32_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ switch (sClearInputConfig->ClearInputSource)\r
+ {\r
+ case TIM_CLEARINPUTSOURCE_NONE:\r
+ {\r
+ /* Clear the OCREF clear selection bit */\r
+ tmpsmcr &= ~TIM_SMCR_OCCS;\r
+ \r
+ /* Clear the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ \r
+ /* Set TIMx_SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:\r
+ {\r
+ /* Clear the OCREF clear selection bit */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_OCCS;\r
+ }\r
+ break;\r
+ \r
+ case TIM_CLEARINPUTSOURCE_ETR:\r
+ {\r
+ /* Check the parameters */ \r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+ \r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ \r
+ /* Set the OCREF clear selection bit */\r
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;\r
+ }\r
+ break;\r
+ default: \r
+ break;\r
+ }\r
+ \r
+ switch (Channel)\r
+ { \r
+ case TIM_CHANNEL_1:\r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_2: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 2 */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_3: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 3 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_4: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 4 */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_5: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; \r
+ }\r
+ } \r
+ break;\r
+ case TIM_CHANNEL_6: \r
+ {\r
+ if(sClearInputConfig->ClearInputState != RESET)\r
+ {\r
+ /* Enable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Ocref clear feature for Channel 1 */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; \r
+ }\r
+ } \r
+ break;\r
+ default: \r
+ break;\r
+ } \r
+ \r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK; \r
+} \r
+\r
+/**\r
+ * @brief Configures the TIM in master mode.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module. \r
+ * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that\r
+ * contains the selected trigger output (TRGO) and the Master/Slave \r
+ * mode. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)\r
+{\r
+ uint32_t tmpcr2; \r
+ uint32_t tmpsmcr; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
+ \r
+ /* Clear the MMS2 bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS2;\r
+ /* Select the TRGO2 source*/\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
+ }\r
+ \r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS;\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;\r
+\r
+ /* Reset the MSM Bit */\r
+ tmpsmcr &= ~TIM_SMCR_MSM;\r
+ /* Set master mode */\r
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+ \r
+ /* Update TIMx CR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+ \r
+ /* Update TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+} \r
+ \r
+/**\r
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
+ * and the AOE(automatic output enable).\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral. \r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, \r
+ TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)\r
+{\r
+ uint32_t tmpbdtr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
+ \r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+ \r
+ /* Clear the BDTR bits */\r
+ tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | \r
+ TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | \r
+ TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |\r
+ TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);\r
+\r
+ /* Set the BDTR bits */\r
+ tmpbdtr |= sBreakDeadTimeConfig->DeadTime;\r
+ tmpbdtr |= sBreakDeadTimeConfig->LockLevel;\r
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;\r
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;\r
+ tmpbdtr |= sBreakDeadTimeConfig->BreakState;\r
+ tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;\r
+ tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;\r
+ tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);\r
+ tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);\r
+ tmpbdtr |= sBreakDeadTimeConfig->Break2State;\r
+ tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;\r
+ \r
+ /* Set TIMx_BDTR */\r
+ htim->Instance->BDTR = tmpbdtr;\r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @param TIM_Remap: specifies the TIM input remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.\r
+ * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. \r
+ * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. \r
+ * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)\r
+ * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.\r
+ * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.\r
+ * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.\r
+ * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) \r
+ * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous \r
+ * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock\r
+ * (HSE divided by a programmable prescaler) \r
+ * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+ __HAL_LOCK(htim);\r
+ \r
+ /* Check parameters */\r
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_REMAP(Remap));\r
+ \r
+ /* Set the Timer remapping configuration */\r
+ htim->Instance->OR = Remap;\r
+ \r
+ htim->State = HAL_TIM_STATE_READY;\r
+ \r
+ __HAL_UNLOCK(htim); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Group channel 5 and channel 1, 2 or 3\r
+ * @param htim: TIM handle.\r
+ * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.\r
+ * This parameter can be any combination of the following values:\r
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_GROUPCH5(OCRef));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+ \r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ \r
+ /* Clear GC5Cx bit fields */\r
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);\r
+ \r
+ /* Set GC5Cx bit fields */\r
+ htim->Instance->CCR5 |= OCRef;\r
+ \r
+ htim->State = HAL_TIM_STATE_READY; \r
+ \r
+ __HAL_UNLOCK(htim);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions \r
+ * @brief Extended Callbacks functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extension Callbacks functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides Extension TIM callback functions:\r
+ (+) Timer Commutation callback\r
+ (+) Timer Break callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Hall commutation changed callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break detection callback in non blocking mode \r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_BreakCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions \r
+ * @brief Extended Peripheral State functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Extension Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Hall Sensor interface state\r
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA Commutation callback. \r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA module.\r
+ * @retval None\r
+ */\r
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ \r
+ htim->State= HAL_TIM_STATE_READY;\r
+ \r
+ HAL_TIMEx_CommutationCallback(htim); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. \r
+ * @retval None\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));\r
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1NE << Channel;\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */ \r
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 5 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC5E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2; \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC5P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 16);\r
+\r
+ if(IS_TIM_BREAK_INSTANCE(TIMx))\r
+ { \r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS5;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 8);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR5 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 6 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config: The output configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx = 0;\r
+ uint32_t tmpccer = 0;\r
+ uint32_t tmpcr2 = 0; \r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC6E;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2; \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 20);\r
+\r
+ if(IS_TIM_BREAK_INSTANCE(TIMx))\r
+ { \r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS6;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 10);\r
+ }\r
+ \r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+ \r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR6 = OC_Config->Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer; \r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_uart.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief UART HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions \r
+ * \r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The UART HAL driver can be used as follows:\r
+ \r
+ (#) Declare a UART_HandleTypeDef handle structure.\r
+ \r
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) UART pins configuration:\r
+ (+++) Enable the clock for the UART GPIOs.\r
+ (+++) Configure these UART pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r
+ and HAL_UART_Receive_IT() APIs):\r
+ (+++) Configure the USARTx interrupt priority.\r
+ (+++) Enable the NVIC USART IRQ handle.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r
+ and HAL_UART_Receive_DMA() APIs):\r
+ (+++) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+++) Enable the DMAx interface clock.\r
+ (+++) Configure the declared DMA handle structure with the required \r
+ Tx/Rx parameters. \r
+ (+++) Configure the DMA Tx/Rx Stream.\r
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete \r
+ interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware \r
+ flow control and Mode(Receiver/Transmitter) in the Init structure.\r
+\r
+ (#) For the UART asynchronous mode, initialize the UART registers by calling\r
+ the HAL_UART_Init() API.\r
+ \r
+ (#) For the UART Half duplex mode, initialize the UART registers by calling \r
+ the HAL_HalfDuplex_Init() API.\r
+ \r
+ (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\r
+ \r
+ (#) For the Multi-Processor mode, initialize the UART registers by calling \r
+ the HAL_MultiProcessor_Init() API.\r
+ \r
+ [..] \r
+ (@) The specific UART interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit \r
+ and receive process.\r
+ \r
+ [..] \r
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the \r
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized \r
+ HAL_UART_MspInit() API.\r
+ \r
+ [..] \r
+ Three operation modes are available within this driver : \r
+ \r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit() \r
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() \r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() \r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+\r
+ *** DMA mode IO operation *** \r
+ ==============================\r
+ [..] \r
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() \r
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback \r
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback\r
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() \r
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback \r
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback\r
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_UART_ErrorCallback\r
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause() \r
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume() \r
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop() \r
+ \r
+ *** UART HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in UART HAL driver.\r
+ \r
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral \r
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral \r
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\r
+ (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag\r
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\r
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\r
+ (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\r
+ \r
+ [..] \r
+ (@) You can refer to the UART HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup UART UART\r
+ * @brief HAL UART module driver\r
+ * @{\r
+ */\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define HAL_UART_TXDMA_TIMEOUTVALUE 22000\r
+#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma); \r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup UART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_UART_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy \r
+ in asynchronous mode.\r
+ (+) For the asynchronous mode only these parameters can be configured: \r
+ (++) Baud Rate\r
+ (++) Word Length \r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ please refer to Reference manual for possible UART frame formats. \r
+ (++) Hardware flow control\r
+ (++) Receiver/transmitter modes\r
+ (++) Over Sampling Method\r
+ [..]\r
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs \r
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor\r
+ configuration procedures (details for the procedures are available in reference manual (RM0329)).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the UART mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ }\r
+ \r
+ if(huart->State == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ huart->Lock = HAL_UNLOCKED;\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->State = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+ \r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In asynchronous mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\r
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);\r
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->State to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the half-duplex mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ if(huart->State == HAL_UART_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+\r
+ huart->State = HAL_UART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+\r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+\r
+ /* In half-duplex mode, the following bits must be kept cleared:\r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);\r
+ huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);\r
+\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ huart->Instance->CR3 |= USART_CR3_HDSEL;\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+\r
+ /* TEACK and/or REACK to check before moving huart->State to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the LIN mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle .\r
+ * @param huart: uart handle\r
+ * @param BreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection\r
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r
+ assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));\r
+ \r
+ if(huart->State == HAL_UART_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+ \r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+ \r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+ \r
+ /* In LIN mode, the following bits must be kept cleared: \r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN and IREN bits in the USART_CR3 register.*/\r
+ huart->Instance->CR2 &= ~(USART_CR2_CLKEN);\r
+ huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);\r
+ \r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ huart->Instance->CR2 |= USART_CR2_LINEN;\r
+ \r
+ /* Set the USART LIN Break detection length. */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+ \r
+ /* TEACK and/or REACK to check before moving huart->State to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Initializes the multiprocessor mode according to the specified\r
+ * parameters in the UART_InitTypeDef and creates the associated handle.\r
+ * @param huart: UART handle \r
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long)\r
+ * @param WakeUpMethod: specifies the UART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection\r
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark\r
+ * @note If the user resorts to idle line detection wake up, the Address parameter\r
+ * is useless and ignored by the initialization function. \r
+ * @note If the user resorts to address mark wake up, the address length detection \r
+ * is configured by default to 4 bits only. For the UART to be able to \r
+ * manage 6-, 7- or 8-bit long addresses detection \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the wake up method parameter */\r
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r
+ \r
+ if(huart->State == HAL_UART_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_UART_MspInit(huart);\r
+ }\r
+ \r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+ \r
+ /* Set the UART Communication parameters */\r
+ if (UART_SetConfig(huart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r
+ {\r
+ UART_AdvFeatureConfig(huart);\r
+ }\r
+ \r
+ /* In multiprocessor mode, the following bits must be kept cleared: \r
+ - LINEN and CLKEN bits in the USART_CR2 register,\r
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */\r
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);\r
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);\r
+ \r
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r
+ {\r
+ /* If address mark wake up method is chosen, set the USART address node */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r
+ }\r
+ \r
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */\r
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_UART_ENABLE(huart); \r
+ \r
+ /* TEACK and/or REACK to check before moving huart->State to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief DeInitializes the UART peripheral \r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the UART handle allocation */\r
+ if(huart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+\r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Disable the Peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+ \r
+ huart->Instance->CR1 = 0x0;\r
+ huart->Instance->CR2 = 0x0;\r
+ huart->Instance->CR3 = 0x0;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_UART_MspDeInit(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ huart->State = HAL_UART_STATE_RESET;\r
+ \r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief UART MSP Init\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief UART MSP DeInit\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_MspDeInit can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Group2 IO operation functions \r
+ * @brief UART Transmit/Receive functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### I/O operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the UART asynchronous\r
+ and Half duplex data transfers.\r
+\r
+ (#) There are two mode of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode. \r
+ The HAL status of all data processing is returned by the same function \r
+ after finishing transfer. \r
+ (+) No-Blocking mode: The communication is performed using Interrupts \r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the \r
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when \r
+ using DMA mode.\r
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks \r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_UART_Transmit()\r
+ (+) HAL_UART_Receive() \r
+ \r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_UART_Transmit_IT()\r
+ (+) HAL_UART_Receive_IT()\r
+ (+) HAL_UART_IRQHandler()\r
+ (+) UART_Transmit_IT()\r
+ (+) UART_Receive_IT()\r
+\r
+ (#) No-Blocking mode API's with DMA are :\r
+ (+) HAL_UART_Transmit_DMA()\r
+ (+) HAL_UART_Receive_DMA()\r
+ (+) HAL_UART_DMAPause()\r
+ (+) HAL_UART_DMAResume()\r
+ (+) HAL_UART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (+) HAL_UART_TxHalfCpltCallback()\r
+ (+) HAL_UART_TxCpltCallback()\r
+ (+) HAL_UART_RxHalfCpltCallback()\r
+ (+) HAL_UART_RxCpltCallback()\r
+ (+) HAL_UART_ErrorCallback()\r
+\r
+\r
+ -@- In the Half duplex communication, it is forbidden to run the transmit \r
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Send an amount of data in blocking mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a non-blocking receive process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+ while(huart->TxXferCount > 0)\r
+ {\r
+ huart->TxXferCount--;\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData;\r
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);\r
+ pData += 2;\r
+ }\r
+ else\r
+ {\r
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);\r
+ }\r
+ }\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) \r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+ /* Check if a non-blocking receive Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+\r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a non-blocking transmit process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+\r
+ huart->RxXferSize = Size; \r
+ huart->RxXferCount = Size;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+ uhMask = huart->Mask;\r
+\r
+ /* as long as data have to be received */\r
+ while(huart->RxXferCount > 0)\r
+ {\r
+ huart->RxXferCount--;\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) \r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pData ;\r
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r
+ pData +=2; \r
+ }\r
+ else\r
+ {\r
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); \r
+ }\r
+ }\r
+\r
+ /* Check if a non-blocking transmit Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{ \r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size;\r
+ \r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a receive process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart); \r
+ \r
+ /* Enable the UART Transmit Data Register Empty Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+ huart->RxXferCount = Size;\r
+\r
+ /* Computation of UART mask to apply to RDR register */\r
+ UART_MASK_COMPUTATION(huart);\r
+\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a transmit process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+\r
+ /* Enable the UART Parity Error Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);\r
+\r
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ /* Enable the UART Data Register not empty Interrupt */\r
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->pTxBuffPtr = pData;\r
+ huart->TxXferSize = Size;\r
+ huart->TxXferCount = Size; \r
+ \r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a receive process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r
+ \r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ huart->hdmatx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Enable the UART transmit DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);\r
+\r
+ \r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 |= USART_CR3_DMAT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode \r
+ * @param huart: uart handle\r
+ * @param pData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @note When the UART parity is enabled (PCE = 1), the received data contain \r
+ * the parity bit (MSB position) \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+ \r
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))\r
+ {\r
+ if((pData == NULL ) || (Size == 0)) \r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->pRxBuffPtr = pData;\r
+ huart->RxXferSize = Size;\r
+ \r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ /* Check if a transmit process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Set the UART DMA transfer complete callback */\r
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r
+ \r
+ /* Set the UART DMA Half transfer complete callback */\r
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r
+ \r
+ /* Set the DMA error callback */\r
+ huart->hdmarx->XferErrorCallback = UART_DMAError;\r
+\r
+ /* Enable the DMA channel */\r
+ tmp = (uint32_t*)&pData;\r
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 |= USART_CR3_DMAR;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ if(huart->State == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ }\r
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ /* Disable the UART DMA Rx request */\r
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Disable the UART DMA Tx request */\r
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ /* Disable the UART DMA Rx request */\r
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the UART DMA Tx request */\r
+ huart->Instance->CR3 |= USART_CR3_DMAT;\r
+ }\r
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)\r
+ {\r
+ /* Enable the UART DMA Rx request */\r
+ huart->Instance->CR3 |= USART_CR3_DMAR;\r
+ }\r
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Enable the UART DMA Rx request before the DMA Tx request */\r
+ huart->Instance->CR3 |= USART_CR3_DMAR;\r
+ /* Enable the UART DMA Tx request */\r
+ huart->Instance->CR3 |= USART_CR3_DMAT;\r
+ }\r
+\r
+ /* If the UART peripheral is still not enabled, enable it */\r
+ if ((huart->Instance->CR1 & USART_CR1_UE) == 0)\r
+ {\r
+ /* Enable UART peripheral */\r
+ __HAL_UART_ENABLE(huart);\r
+ }\r
+\r
+ /* TEACK and/or REACK to check before moving huart->State to Ready */\r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ /* Disable the UART Tx/Rx DMA requests */\r
+ huart->Instance->CR3 &= ~USART_CR3_DMAT;\r
+ huart->Instance->CR3 &= ~USART_CR3_DMAR;\r
+ \r
+ /* Abort the UART DMA tx channel */\r
+ if(huart->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmatx);\r
+ }\r
+ /* Abort the UART DMA rx channel */\r
+ if(huart->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(huart->hdmarx);\r
+ }\r
+ \r
+ /* Disable UART peripheral */\r
+ __HAL_UART_DISABLE(huart);\r
+ \r
+ huart->State = HAL_UART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles UART interrupt request.\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r
+{\r
+ /* UART parity error interrupt occurred -------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))\r
+ { \r
+ __HAL_UART_CLEAR_PEFLAG(huart);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_PE;\r
+ /* Set the UART state ready to be able to start again the process */\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ \r
+ /* UART frame error interrupt occurred --------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))\r
+ { \r
+ __HAL_UART_CLEAR_FEFLAG(huart);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_FE;\r
+ /* Set the UART state ready to be able to start again the process */\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ \r
+ /* UART noise error interrupt occurred --------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))\r
+ { \r
+ __HAL_UART_CLEAR_NEFLAG(huart);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_NE;\r
+ /* Set the UART state ready to be able to start again the process */\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ \r
+ /* UART Over-Run interrupt occurred -----------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))\r
+ { \r
+ __HAL_UART_CLEAR_OREFLAG(huart);\r
+\r
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;\r
+ /* Set the UART state ready to be able to start again the process */\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+\r
+ /* Call UART Error Call back function if need be --------------------------*/\r
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)\r
+ {\r
+ HAL_UART_ErrorCallback(huart);\r
+ }\r
+\r
+ /* UART in mode Receiver ---------------------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))\r
+ { \r
+ UART_Receive_IT(huart);\r
+ /* Clear RXNE interrupt flag */\r
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r
+ }\r
+ \r
+\r
+ /* UART in mode Transmitter ------------------------------------------------*/\r
+ if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))\r
+ {\r
+ UART_Transmit_IT(huart);\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief This function handles UART Communication Timeout.\r
+ * @param huart: UART handle\r
+ * @param Flag: specifies the UART flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ { \r
+ while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+ \r
+ huart->State= HAL_UART_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+ \r
+ huart->State= HAL_UART_STATE_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief DMA UART transmit process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ huart->TxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
+ \r
+ /* Wait for UART TC Flag */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
+ {\r
+ /* Timeout Occured */ \r
+ huart->State = HAL_UART_STATE_TIMEOUT;\r
+ HAL_UART_ErrorCallback(huart);\r
+ }\r
+ else\r
+ {\r
+ /* No Timeout */\r
+ /* Check if a receive process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)\r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ HAL_UART_TxCpltCallback(huart);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA UART transmit process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_UART_TxHalfCpltCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process complete callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) \r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ huart->RxXferCount = 0;\r
+ \r
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r
+ in the UART CR3 register */\r
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
+ \r
+ /* Check if a transmit Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ HAL_UART_RxCpltCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief DMA UART receive process half complete callback \r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_UART_RxHalfCpltCallback(huart); \r
+}\r
+\r
+/**\r
+ * @brief DMA UART communication error callback \r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void UART_DMAError(DMA_HandleTypeDef *hdma) \r
+{\r
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+ huart->RxXferCount = 0;\r
+ huart->TxXferCount = 0;\r
+ huart->State= HAL_UART_STATE_READY;\r
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;\r
+ HAL_UART_ErrorCallback(huart);\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks.\r
+ * @param huart: UART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief UART error callbacks\r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_UART_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode \r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Transmit_IT()\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))\r
+ {\r
+\r
+ if(huart->TxXferCount == 0)\r
+ {\r
+ /* Disable the UART Transmit Data Register Empty Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);\r
+\r
+ /* Check if a receive Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+ \r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ \r
+ /* Wait on TC flag to be able to start a second transfer */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r
+ { \r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ HAL_UART_TxCpltCallback(huart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) huart->pTxBuffPtr;\r
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);\r
+ huart->pTxBuffPtr += 2;\r
+ } \r
+ else\r
+ {\r
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);\r
+ }\r
+\r
+ huart->TxXferCount--;\r
+ \r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in interrupt mode \r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_UART_Receive_IT()\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = huart->Mask;\r
+\r
+ if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))\r
+ {\r
+ \r
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) huart->pRxBuffPtr ;\r
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r
+ huart->pRxBuffPtr +=2;\r
+ }\r
+ else\r
+ {\r
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); \r
+ }\r
+\r
+ if(--huart->RxXferCount == 0)\r
+ {\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);\r
+\r
+ /* Check if a transmit Process is ongoing or not */\r
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) \r
+ {\r
+ huart->State = HAL_UART_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the UART Parity Error Interrupt */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);\r
+\r
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\r
+\r
+ huart->State = HAL_UART_STATE_READY;\r
+ }\r
+ \r
+ HAL_UART_RxCpltCallback(huart);\r
+ \r
+ return HAL_OK;\r
+ }\r
+ \r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY; \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Group3 Peripheral Control functions \r
+ * @brief UART control functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the UART.\r
+ (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. \r
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r
+ (+) UART_SetConfig() API configures the UART peripheral\r
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features \r
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization \r
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter \r
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver \r
+ (+) HAL_LIN_SendBreak() API transmits the break characters \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;\r
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */\r
+ huart->Instance->CR1 |= USART_CR1_MME;\r
+ \r
+ huart->State = HAL_UART_STATE_READY;\r
+ \r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,\r
+ * as it may not have been in mute mode at this very moment).\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r
+{ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r
+ huart->Instance->CR1 &= ~(USART_CR1_MME);\r
+ \r
+ huart->State = HAL_UART_STATE_READY;\r
+ \r
+ return (UART_CheckIdleState(huart));\r
+}\r
+\r
+/**\r
+ * @brief Enter UART mute mode (means UART actually enters mute mode).\r
+ * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. \r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r
+{ \r
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief return the UART state\r
+ * @param huart: uart handle\r
+ * @retval HAL state\r
+ */\r
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r
+{\r
+ return huart->State;\r
+}\r
+\r
+/**\r
+* @brief Return the UART error code\r
+* @param huart : pointer to a UART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified UART.\r
+* @retval UART Error Code\r
+*/\r
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r
+{\r
+ return huart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @brief Configure the UART peripheral \r
+ * @param huart: uart handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r
+{\r
+ uint32_t tmpreg = 0x00000000;\r
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;\r
+ uint16_t brrtemp = 0x0000;\r
+ uint16_t usartdiv = 0x0000;\r
+ HAL_StatusTypeDef ret = HAL_OK; \r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); \r
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r
+ assert_param(IS_UART_PARITY(huart->Init.Parity));\r
+ assert_param(IS_UART_MODE(huart->Init.Mode));\r
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); \r
+\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure \r
+ * the UART Word Length, Parity, Mode and oversampling: \r
+ * set the M bits according to huart->Init.WordLength value \r
+ * set PCE and PS bits according to huart->Init.Parity value\r
+ * set TE and RE bits according to huart->Init.Mode value\r
+ * set OVER8 bit according to huart->Init.OverSampling value */\r
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR2 Configuration -----------------------*/\r
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according \r
+ * to huart->Init.StopBits value */\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r
+ \r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* Configure \r
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according \r
+ * to huart->Init.HwFlowCtl value \r
+ * - one-bit sampling method versus three samples' majority rule according\r
+ * to huart->Init.OneBitSampling */\r
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;\r
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);\r
+ \r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ UART_GETCLOCKSOURCE(huart, clocksource);\r
+\r
+ /* Check UART Over Sampling to set Baud Rate Register */\r
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r
+ { \r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_PCLK1:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_PCLK2:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); \r
+ break;\r
+ case UART_CLOCKSOURCE_SYSCLK:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_LSE:\r
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); \r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED: \r
+ default:\r
+ ret = HAL_ERROR; \r
+ break;\r
+ }\r
+ \r
+ brrtemp = usartdiv & 0xFFF0;\r
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);\r
+ huart->Instance->BRR = brrtemp;\r
+ }\r
+ else\r
+ {\r
+ switch (clocksource)\r
+ {\r
+ case UART_CLOCKSOURCE_PCLK1: \r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_PCLK2: \r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r
+ break;\r
+ case UART_CLOCKSOURCE_HSI: \r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); \r
+ break; \r
+ case UART_CLOCKSOURCE_SYSCLK: \r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r
+ break; \r
+ case UART_CLOCKSOURCE_LSE:\r
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); \r
+ break;\r
+ case UART_CLOCKSOURCE_UNDEFINED: \r
+ default:\r
+ ret = HAL_ERROR; \r
+ break;\r
+ }\r
+ }\r
+\r
+ return ret; \r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the UART peripheral advanced features \r
+ * @param huart: uart handle \r
+ * @retval None\r
+ */\r
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check whether the set of advanced features to configure is properly set */ \r
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r
+ \r
+ /* if required, configure TX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure RX pin active level inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r
+ }\r
+ \r
+ /* if required, configure data inversion */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r
+ }\r
+ \r
+ /* if required, configure RX/TX pins swap */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r
+ }\r
+ \r
+ /* if required, configure RX overrun detection disabling */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r
+ {\r
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); \r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r
+ }\r
+ \r
+ /* if required, configure DMA disabling on reception error */\r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); \r
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r
+ }\r
+ \r
+ /* if required, configure auto Baud rate detection scheme */ \r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r
+ /* set auto Baudrate detection parameters if detection is enabled */\r
+ if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r
+ }\r
+ }\r
+ \r
+ /* if required, configure MSB first on communication line */ \r
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r
+ {\r
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); \r
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r
+ }\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Check the UART Idle State\r
+ * @param huart: uart handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r
+{\r
+ /* Initialize the UART ErrorCode */\r
+ huart->ErrorCode = HAL_UART_ERROR_NONE;\r
+ \r
+ /* Check if the Transmitter is enabled */\r
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) \r
+ {\r
+ /* Timeout Occured */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) \r
+ { \r
+ /* Timeout Occured */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Initialize the UART State */\r
+ huart->State= HAL_UART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART transmitter and disables the UART receiver.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r
+ \r
+ huart->State= HAL_UART_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the UART receiver and disables the UART transmitter.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ huart->State = HAL_UART_STATE_BUSY;\r
+\r
+ /* Clear TE and RE bits */\r
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r
+\r
+ huart->State = HAL_UART_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param huart: UART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART_INSTANCE(huart->Instance));\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(huart);\r
+ \r
+ huart->State = HAL_UART_STATE_BUSY;\r
+ \r
+ /* Send break characters */\r
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST; \r
+ \r
+ huart->State = HAL_UART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(huart);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_usart.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief USART HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter\r
+ * Peripheral (USART).\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ The USART HAL driver can be used as follows:\r
+\r
+ (#) Declare a USART_HandleTypeDef handle structure.\r
+ (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:\r
+ (##) Enable the USARTx interface clock.\r
+ (##) USART pins configuration:\r
+ (+) Enable the clock for the USART GPIOs.\r
+ (+) Configure these USART pins as alternate function pull-up.\r
+ (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),\r
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r
+ (+) Configure the USARTx interrupt priority.\r
+ (+) Enable the NVIC USART IRQ handle.\r
+ (@) The specific USART interrupts (Transmission complete interrupt, \r
+ RXNE interrupt and Error Interrupts) will be managed using the macros\r
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.\r
+ (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()\r
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r
+ (+) Declare a DMA handle structure for the Tx/Rx stream.\r
+ (+) Enable the DMAx interface clock.\r
+ (+) Configure the declared DMA handle structure with the required Tx/Rx parameters. \r
+ (+) Configure the DMA Tx/Rx Stream.\r
+ (+) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.\r
+ (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r
+\r
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware \r
+ flow control and Mode(Receiver/Transmitter) in the husart Init structure.\r
+\r
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:\r
+ (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
+ by calling the customed HAL_USART_MspInit(&husart) API.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART USART\r
+ * @brief HAL USART Synchronous module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup USART_Private_Constants\r
+ * @{\r
+ */\r
+#define DUMMY_DATA ((uint16_t) 0xFFFF)\r
+#define TEACK_REACK_TIMEOUT ((uint32_t) 1000)\r
+#define USART_TXDMA_TIMEOUTVALUE 22000\r
+#define USART_TIMEOUT_VALUE 22000\r
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\r
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \\r
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup USART_Private_Functions\r
+ * @{\r
+ */\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);\r
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Functions USART Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART\r
+ in asynchronous and in synchronous modes.\r
+ (+) For the asynchronous mode only these parameters can be configured:\r
+ (++) Baud Rate\r
+ (++) Word Length\r
+ (++) Stop Bit\r
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,\r
+ 8-bit or 9-bit), the possible USART frame formats are as listed in the\r
+ following table:\r
+\r
+ +---------------------------------------------------------------+\r
+ | M1M0 bits | PCE bit | USART frame |\r
+ |-----------------------|---------------------------------------|\r
+ | 10 | 0 | | SB | 7-bit data | STB | |\r
+ |-----------|-----------|---------------------------------------|\r
+ | 10 | 1 | | SB | 6-bit data | PB | STB | |\r
+ +---------------------------------------------------------------+\r
+ (++) USART polarity\r
+ (++) USART phase\r
+ (++) USART LastBit\r
+ (++) Receiver/transmitter modes\r
+\r
+ [..]\r
+ The HAL_USART_Init() function follows the USART synchronous configuration\r
+ procedure (details for the procedure are available in reference manual).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USART mode according to the specified\r
+ * parameters in the USART_InitTypeDef and create the associated handle.\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if(husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ if(husart->State == HAL_USART_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK */\r
+ HAL_USART_MspInit(husart);\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ /* Set the Usart Communication parameters */\r
+ if (USART_SetConfig(husart) == HAL_ERROR)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* In Synchronous mode, the following bits must be kept cleared:\r
+ - LINEN bit in the USART_CR2 register\r
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;\r
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_USART_ENABLE(husart);\r
+\r
+ /* TEACK and/or REACK to check before moving husart->State to Ready */\r
+ return (USART_CheckIdleState(husart));\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the USART peripheral\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* Check the USART handle allocation */\r
+ if(husart == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_INSTANCE(husart->Instance));\r
+\r
+ husart->State = HAL_USART_STATE_BUSY;\r
+\r
+ husart->Instance->CR1 = 0x0;\r
+ husart->Instance->CR2 = 0x0;\r
+ husart->Instance->CR3 = 0x0;\r
+\r
+ /* DeInit the low level hardware */\r
+ HAL_USART_MspDeInit(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_RESET;\r
+\r
+ /* Process Unlock */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USART MSP Init\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART MSP DeInit\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_MspDeInit can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions \r
+ * @brief USART Transmit and Receive functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ This subsection provides a set of functions allowing to manage the USART synchronous\r
+ data transfers.\r
+\r
+ [..] The USART supports master mode only: it cannot receive or send data related to an input\r
+ clock (SCLK is always an output).\r
+\r
+ (#) There are two mode of transfer:\r
+ (+) Blocking mode: The communication is performed in polling mode.\r
+ The HAL status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (+) No-Blocking mode: The communication is performed using Interrupts\r
+ or DMA, These API's return the HAL status.\r
+ The end of the data processing will be indicated through the\r
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks\r
+ will be executed respectively at the end of the transmit or Receive process\r
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected\r
+\r
+ (#) Blocking mode API's are :\r
+ (+) HAL_USART_Transmit()in simplex mode\r
+ (+) HAL_USART_Receive() in full duplex receive only\r
+ (+) HAL_USART_TransmitReceive() in full duplex mode\r
+\r
+ (#) Non-Blocking mode API's with Interrupt are :\r
+ (+) HAL_USART_Transmit_IT()in simplex mode\r
+ (+) HAL_USART_Receive_IT() in full duplex receive only\r
+ (+) HAL_USART_TransmitReceive_IT()in full duplex mode\r
+ (+) HAL_USART_IRQHandler()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (+) HAL_USART_Transmit_DMA()in simplex mode\r
+ (+) HAL_USART_Receive_DMA() in full duplex receive only\r
+ (+) HAL_USART_TransmitReceive_DMA() in full duplex mode\r
+ (+) HAL_USART_DMAPause()\r
+ (+) HAL_USART_DMAResume()\r
+ (+) HAL_USART_DMAStop()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r
+ (+) HAL_USART_TxCpltCallback()\r
+ (+) HAL_USART_RxCpltCallback()\r
+ (+) HAL_USART_TxHalfCpltCallback()\r
+ (+) HAL_USART_RxHalfCpltCallback()\r
+ (+) HAL_USART_ErrorCallback()\r
+ (+) HAL_USART_TxRxCpltCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Simplex Send an amount of data in blocking mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* Check the remaining data to be sent */\r
+ while(husart->TxXferCount > 0)\r
+ {\r
+ husart->TxXferCount--;\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pTxData;\r
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);\r
+ pTxData += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);\r
+ }\r
+ }\r
+\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode\r
+ * @note To receive synchronous data, dummy data are simultaneously transmitted\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* as long as data have to be received */\r
+ while(husart->RxXferCount > 0)\r
+ {\r
+ husart->RxXferCount--;\r
+\r
+ /* Wait until TC flag is set to send dummy byte in order to generate the\r
+ * clock for the slave to send data.\r
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value\r
+ * can be written for all the cases. */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF);\r
+\r
+ /* Wait for RXNE Flag */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pRxData ;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ pRxData +=2;\r
+ }\r
+ else\r
+ {\r
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be sent (same amount to be received)\r
+ * @param Timeout : Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ husart->RxXferSize = Size;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+ uhMask = husart->Mask;\r
+\r
+ /* Check the remain data to be sent */\r
+ while(husart->TxXferCount > 0)\r
+ {\r
+ husart->TxXferCount--;\r
+ husart->RxXferCount--;\r
+\r
+ /* Wait until TC flag is set to send data */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pTxData;\r
+ husart->Instance->TDR = (*tmp & uhMask);\r
+ pTxData += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);\r
+ }\r
+\r
+ /* Wait for RXNE Flag */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) pRxData ;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ pRxData +=2;\r
+ }\r
+ else\r
+ {\r
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ }\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in interrupt mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)\r
+ are not managed by the USART Transmit Process to avoid the overrun interrupt\r
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"\r
+ to benefit for the frame error and noise interrupts the usart mode should be\r
+ configured only for transmit "USART_MODE_TX" */\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in blocking mode\r
+ * To receive synchronous data, dummy data are simultaneously transmitted\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);\r
+\r
+ /* Enable the USART Data Register not empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+\r
+ /* Send dummy byte in order to generate the clock for the Slave to send the next data */\r
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)\r
+ {\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF); \r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be sent (same amount to be received)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->RxXferCount = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ /* Computation of USART mask to apply to RDR register */\r
+ __HAL_USART_MASK_COMPUTATION(husart);\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ /* Enable the USART Data Register not empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);\r
+\r
+ /* Enable the USART Parity Error Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);\r
+\r
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ /* Enable the USART Transmit Data Register Empty Interrupt */\r
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Send an amount of data in DMA mode\r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to data buffer\r
+ * @param Size: amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+ husart->TxXferCount = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX;\r
+\r
+ /* Set the USART DMA transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART transmit DMA channel */\r
+ tmp = (uint32_t*)&pTxData;\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 |= USART_CR3_DMAT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive an amount of data in DMA mode\r
+ * @param husart: USART handle\r
+ * @param pRxData: pointer to data buffer\r
+ * @param Size: amount of data to be received\r
+ * @note When the USART parity is enabled (PCE = 1), the received data contain\r
+ * the parity bit (MSB position)\r
+ * @retval HAL status\r
+ * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.\r
+ */\r
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pRxData == NULL ) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pRxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_RX;\r
+\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ tmp = (uint32_t*)&pRxData;\r
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the USART transmit DMA channel: the transmit stream is used in order\r
+ to generate in the non-blocking mode the clock to the slave device,\r
+ this mode isn't a simplex receive mode but a full-duplex receive mode */\r
+ tmp = (uint32_t*)&pRxData;\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 |= USART_CR3_DMAR;\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 |= USART_CR3_DMAT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode \r
+ * @param husart: USART handle\r
+ * @param pTxData: pointer to TX data buffer\r
+ * @param pRxData: pointer to RX data buffer\r
+ * @param Size: amount of data to be received/sent\r
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
+{\r
+ uint32_t *tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_READY)\r
+ {\r
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ husart->pRxBuffPtr = pRxData;\r
+ husart->RxXferSize = Size;\r
+ husart->pTxBuffPtr = pTxData;\r
+ husart->TxXferSize = Size;\r
+\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;\r
+\r
+ /* Set the USART DMA Rx transfer complete callback */\r
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer complete callback */\r
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r
+\r
+ /* Set the USART DMA Half transfer complete callback */\r
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r
+\r
+ /* Set the USART DMA Tx transfer error callback */\r
+ husart->hdmatx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Set the USART DMA Rx transfer error callback */\r
+ husart->hdmarx->XferErrorCallback = USART_DMAError;\r
+\r
+ /* Enable the USART receive DMA channel */\r
+ tmp = (uint32_t*)&pRxData;\r
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r
+\r
+ /* Enable the USART transmit DMA channel */\r
+ tmp = (uint32_t*)&pTxData;\r
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r
+\r
+ /* Clear the TC flag in the SR register by writing 0 to it */\r
+ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r
+\r
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 |= USART_CR3_DMAR;\r
+\r
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 |= USART_CR3_DMAT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Pauses the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Disable the USART DMA Rx request */\r
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Disable the USART DMA Tx request */\r
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);\r
+ /* Disable the USART DMA Rx request */\r
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Enable the USART DMA Tx request */\r
+ husart->Instance->CR3 |= USART_CR3_DMAT;\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ /* Enable the USART DMA Rx request */\r
+ husart->Instance->CR3 |= USART_CR3_DMAR;\r
+ }\r
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ /* Enable the USART DMA Rx request before the DMA Tx request */\r
+ husart->Instance->CR3 |= USART_CR3_DMAR;\r
+ /* Enable the USART DMA Tx request */\r
+ husart->Instance->CR3 |= USART_CR3_DMAT;\r
+ }\r
+\r
+ /* If the USART peripheral is still not enabled, enable it */\r
+ if((husart->Instance->CR1 & USART_CR1_UE) == 0)\r
+ {\r
+ /* Enable USART peripheral */\r
+ __HAL_USART_ENABLE(husart);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the DMA Transfer.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(husart);\r
+\r
+ /* Disable the USART Tx/Rx DMA requests */\r
+ husart->Instance->CR3 &= ~USART_CR3_DMAT;\r
+ husart->Instance->CR3 &= ~USART_CR3_DMAR;\r
+\r
+ /* Abort the USART DMA tx Stream */\r
+ if(husart->hdmatx != NULL)\r
+ {\r
+ HAL_DMA_Abort(husart->hdmatx);\r
+ }\r
+ /* Abort the USART DMA rx Stream */\r
+ if(husart->hdmarx != NULL)\r
+ {\r
+ HAL_DMA_Abort(husart->hdmarx);\r
+ }\r
+\r
+ /* Disable USART peripheral */\r
+ __HAL_USART_DISABLE(husart);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles USART interrupt request.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)\r
+{\r
+\r
+ /* USART parity error interrupt occurred ------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_PE;\r
+ /* Set the USART state ready to be able to start again the process */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ }\r
+\r
+ /* USART frame error interrupt occurred -------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_FE;\r
+ /* Set the USART state ready to be able to start again the process */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ }\r
+\r
+ /* USART noise error interrupt occurred -------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_NE;\r
+ /* Set the USART state ready to be able to start again the process */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ }\r
+\r
+ /* USART Over-Run interrupt occurred ----------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))\r
+ {\r
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;\r
+ /* Set the USART state ready to be able to start again the process */\r
+ husart->State = HAL_USART_STATE_READY;\r
+ }\r
+\r
+ /* Call USART Error Call back function if need be --------------------------*/\r
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)\r
+ {\r
+ HAL_USART_ErrorCallback(husart);\r
+ }\r
+\r
+ /* USART in mode Receiver --------------------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+ USART_Receive_IT(husart);\r
+ }\r
+ else\r
+ {\r
+ USART_TransmitReceive_IT(husart);\r
+ }\r
+ }\r
+\r
+ /* USART in mode Transmitter -----------------------------------------------*/\r
+ if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))\r
+ {\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ USART_Transmit_IT(husart);\r
+ }\r
+ else\r
+ {\r
+ USART_TransmitReceive_IT(husart);\r
+ }\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxCpltCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Tx Half Transfer completed callbacks.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE: This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Half Transfer completed callbacks\r
+ * @param husart: usart handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief USART error callbacks\r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_USART_ErrorCallback can be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief USART State and Errors functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Errors functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to return the State of \r
+ USART communication\r
+ process, return Peripheral Errors occurred during communication process\r
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state \r
+ of the USART peripheral.\r
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during \r
+ communication. \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the USART state\r
+ * @param husart: USART handle\r
+ * @retval HAL state\r
+ */\r
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the USART error code\r
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains\r
+ * the configuration information for the specified USART.\r
+ * @retval USART Error Code\r
+ */\r
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)\r
+{\r
+ return husart->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+\r
+/**\r
+ * @brief Simplex Send an amount of data in non-blocking mode.\r
+ * @note Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Transmit_IT().\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ * @note The USART errors are not managed to avoid the overrun error.\r
+ */\r
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+\r
+ if(husart->TxXferCount == 0)\r
+ {\r
+ /* Disable the USART Transmit Complete Interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_TxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); \r
+ husart->pTxBuffPtr += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); \r
+ }\r
+\r
+ husart->TxXferCount--;\r
+\r
+ return HAL_OK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Simplex Receive an amount of data in non-blocking mode.\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_Receive_IT()\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_RX)\r
+ {\r
+\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2;\r
+ }\r
+ else\r
+ {\r
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r
+ husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);\r
+\r
+ if(--husart->RxXferCount == 0)\r
+ {\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);\r
+\r
+ /* Disable the USART Parity Error Interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_RxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).\r
+ * Function called under interruption only, once\r
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT() \r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)\r
+{\r
+ uint16_t* tmp;\r
+ uint16_t uhMask = husart->Mask;\r
+\r
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r
+ {\r
+ if(husart->TxXferCount != 0x00)\r
+ {\r
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pTxBuffPtr;\r
+ husart->Instance->TDR = (uint16_t)(*tmp & uhMask);\r
+ husart->pTxBuffPtr += 2;\r
+ }\r
+ else\r
+ {\r
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);\r
+ }\r
+ husart->TxXferCount--;\r
+\r
+ /* Check the latest data transmitted */\r
+ if(husart->TxXferCount == 0)\r
+ {\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+ }\r
+ }\r
+ }\r
+\r
+ if(husart->RxXferCount != 0x00)\r
+ {\r
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)\r
+ {\r
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r
+ {\r
+ tmp = (uint16_t*) husart->pRxBuffPtr;\r
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r
+ husart->pRxBuffPtr += 2;\r
+ }\r
+ else\r
+ {\r
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r
+ }\r
+ husart->RxXferCount--;\r
+ }\r
+ }\r
+\r
+ /* Check the latest data received */\r
+ if(husart->RxXferCount == 0)\r
+ {\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);\r
+\r
+ /* Disable the USART Parity Error Interrupt */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
+\r
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ husart->State = HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_TxRxCpltCallback(husart);\r
+\r
+ return HAL_OK;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles USART Communication Timeout.\r
+ * @param husart: USART handle\r
+ * @param Flag: specifies the USART flag to check.\r
+ * @param Status: The new Flag status (SET or RESET).\r
+ * @param Timeout: Timeout duration\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) \r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+\r
+ /* Wait until flag is set */\r
+ if(Status == RESET)\r
+ {\r
+ while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ husart->State= HAL_USART_STATE_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))\r
+ {\r
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);\r
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);\r
+\r
+ husart->State= HAL_USART_STATE_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA USART transmit process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ husart->TxXferCount = 0;\r
+ \r
+ if(husart->State == HAL_USART_STATE_BUSY_TX)\r
+ {\r
+ /* Wait for USART TC Flag */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK)\r
+ {\r
+ /* Timeout occurred */ \r
+ husart->State = HAL_USART_STATE_TIMEOUT;\r
+ HAL_USART_ErrorCallback(husart);\r
+ }\r
+ else\r
+ {\r
+ /* No Timeout */\r
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit\r
+ in the USART CR3 register */\r
+ husart->Instance->CR3 &= ~(USART_CR3_DMAT);\r
+ husart->State= HAL_USART_STATE_READY;\r
+ }\r
+ }\r
+ /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/\r
+ else\r
+ {\r
+ husart->State= HAL_USART_STATE_BUSY_RX;\r
+ HAL_USART_TxCpltCallback(husart);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief DMA USART transmit process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_USART_TxHalfCpltCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process complete callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ husart->RxXferCount = 0;\r
+\r
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r
+ in USART CR3 register */\r
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);\r
+ /* similarly, disable the DMA TX transfer that was started to provide the\r
+ clock to the slave device */\r
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);\r
+\r
+ husart->State= HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_RxCpltCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART receive process half complete callback\r
+ * @param hdma : DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
+\r
+ HAL_USART_RxHalfCpltCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief DMA USART communication error callback\r
+ * @param hdma: DMA handle\r
+ * @retval None\r
+ */\r
+static void USART_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
+\r
+ husart->RxXferCount = 0;\r
+ husart->TxXferCount = 0;\r
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;\r
+ husart->State= HAL_USART_STATE_READY;\r
+\r
+ HAL_USART_ErrorCallback(husart);\r
+}\r
+\r
+/**\r
+ * @brief Configure the USART peripheral \r
+ * @param husart: USART handle\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)\r
+{\r
+ uint32_t tmpreg = 0x0;\r
+ USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));\r
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));\r
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));\r
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));\r
+ assert_param(IS_USART_PARITY(husart->Init.Parity));\r
+ assert_param(IS_USART_MODE(husart->Init.Mode));\r
+ assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling)); \r
+\r
+\r
+ /*-------------------------- USART CR1 Configuration -----------------------*/\r
+ /* Clear M, PCE, PS, TE and RE bits and configure \r
+ * the USART Word Length, Parity, Mode and OverSampling: \r
+ * set the M bits according to husart->Init.WordLength value \r
+ * set PCE and PS bits according to husart->Init.Parity value\r
+ * set TE and RE bits according to husart->Init.Mode value\r
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */\r
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;\r
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r
+ \r
+ /*---------------------------- USART CR2 Configuration ---------------------*/\r
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:\r
+ * set CPOL bit according to husart->Init.CLKPolarity value\r
+ * set CPHA bit according to husart->Init.CLKPhase value\r
+ * set LBCL bit according to husart->Init.CLKLastBit value\r
+ * set STOP[13:12] bits according to husart->Init.StopBits value */\r
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); \r
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);\r
+ tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);\r
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);\r
+\r
+ /*-------------------------- USART CR3 Configuration -----------------------*/\r
+ /* no CR3 register configuration */\r
+\r
+ /*-------------------------- USART BRR Configuration -----------------------*/\r
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */\r
+ USART_GETCLOCKSOURCE(husart, clocksource);\r
+ switch (clocksource)\r
+ {\r
+ case USART_CLOCKSOURCE_PCLK1: \r
+ husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_PCLK2: \r
+ husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK2Freq() / husart->Init.BaudRate);\r
+ break;\r
+ case USART_CLOCKSOURCE_HSI: \r
+ husart->Instance->BRR = (uint16_t)(2*HSI_VALUE / husart->Init.BaudRate); \r
+ break; \r
+ case USART_CLOCKSOURCE_SYSCLK: \r
+ husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate);\r
+ break; \r
+ case USART_CLOCKSOURCE_LSE: \r
+ husart->Instance->BRR = (uint16_t)(2*LSE_VALUE / husart->Init.BaudRate); \r
+ break;\r
+ case USART_CLOCKSOURCE_UNDEFINED: \r
+ default:\r
+ ret = HAL_ERROR; \r
+ break; \r
+ } \r
+ \r
+ return ret; \r
+}\r
+\r
+/**\r
+ * @brief Check the USART Idle State\r
+ * @param husart: USART handle\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)\r
+{\r
+ /* Initialize the USART ErrorCode */\r
+ husart->ErrorCode = HAL_USART_ERROR_NONE;\r
+ \r
+ /* Check if the Transmitter is enabled */\r
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r
+ {\r
+ /* Wait until TEACK flag is set */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ husart->State= HAL_USART_STATE_TIMEOUT; \r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ /* Check if the Receiver is enabled */\r
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r
+ {\r
+ /* Wait until REACK flag is set */\r
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) \r
+ { \r
+ husart->State= HAL_USART_STATE_TIMEOUT; \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Initialize the USART state*/\r
+ husart->State= HAL_USART_STATE_READY;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(husart);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief WWDG HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Window Watchdog (WWDG) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State functions \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### WWDG specific features #####\r
+ ==============================================================================\r
+ [..] \r
+ Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ time period, unless the program refreshes the counter (downcounter) \r
+ before reaching 0x3F value (i.e. a reset is generated when the counter\r
+ value rolls over from 0x40 to 0x3F). \r
+ \r
+ (+) An MCU reset is also generated if the counter value is refreshed\r
+ before the counter has reached the refresh window value. This \r
+ implies that the counter must be refreshed in a limited window.\r
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.\r
+ (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
+ reset occurs. \r
+ (+) The WWDG counter input clock is derived from the APB clock divided \r
+ by a programmable prescaler.\r
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)\r
+ (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock\r
+ (+) WWDG Counter refresh is allowed between the following limits :\r
+ (++) min time (mS) = 1000 * (Counter \96 Window) / WWDG clock\r
+ (++) max time (mS) = 1000 * (Counter \96 0x40) / WWDG clock\r
+ \r
+ (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms \r
+\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().\r
+ (+) Set the WWDG prescaler, refresh window and counter value \r
+ using HAL_WWDG_Init() function.\r
+ (+) Start the WWDG using HAL_WWDG_Start() function.\r
+ When the WWDG is enabled the counter value should be configured to \r
+ a value greater than 0x40 to prevent generating an immediate reset.\r
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is \r
+ generated when the counter reaches 0x40, and then start the WWDG using\r
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can \r
+ add his own code by customization of function pointer HAL_WWDG_WakeupCallback\r
+ Once enabled, EWI interrupt cannot be disabled except by a system reset. \r
+ (+) Then the application program must refresh the WWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ HAL_WWDG_Refresh() function. This operation must occur only when\r
+ the counter is lower than the refresh window value already programmed.\r
+ \r
+ *** WWDG HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in WWDG HAL driver.\r
+ \r
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral \r
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status\r
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags \r
+ (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wake-up interrupt \r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG WWDG\r
+ * @brief WWDG HAL module driver.\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize the WWDG according to the specified parameters \r
+ in the WWDG_InitTypeDef and create the associated handle\r
+ (+) DeInitialize the WWDG peripheral\r
+ (+) Initialize the WWDG MSP\r
+ (+) DeInitialize the WWDG MSP \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the WWDG according to the specified\r
+ * parameters in the WWDG_InitTypeDef and creates the associated handle.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Check the WWDG handle allocation */\r
+ if(hwwdg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));\r
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));\r
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); \r
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); \r
+ \r
+ if(hwwdg->State == HAL_WWDG_STATE_RESET)\r
+ {\r
+ /* Init the low level hardware */\r
+ HAL_WWDG_MspInit(hwwdg);\r
+ }\r
+ \r
+ /* Change WWDG peripheral state */\r
+ hwwdg->State = HAL_WWDG_STATE_BUSY;\r
+\r
+ /* Set WWDG Prescaler and Window */\r
+ MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));\r
+ /* Set WWDG Counter */\r
+ MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);\r
+\r
+ /* Change WWDG peripheral state */\r
+ hwwdg->State = HAL_WWDG_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the WWDG peripheral. \r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)\r
+{ \r
+ /* Check the WWDG handle allocation */\r
+ if(hwwdg == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));\r
+\r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_WWDG_MspDeInit(hwwdg);\r
+ \r
+ /* Reset WWDG Control register */\r
+ hwwdg->Instance->CR = (uint32_t)0x0000007F;\r
+ \r
+ /* Reset WWDG Configuration register */\r
+ hwwdg->Instance->CFR = (uint32_t)0x0000007F;\r
+ \r
+ /* Reset WWDG Status register */\r
+ hwwdg->Instance->SR = 0; \r
+ \r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_RESET; \r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hwwdg);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the WWDG MSP.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_WWDG_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the WWDG MSP.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_WWDG_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions \r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ============================================================================== \r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Start the WWDG.\r
+ (+) Refresh the WWDG.\r
+ (+) Handle WWDG interrupt request. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the WWDG.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hwwdg); \r
+ \r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_BUSY;\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_WWDG_ENABLE(hwwdg); \r
+ \r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hwwdg);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the WWDG with interrupt enabled.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hwwdg); \r
+\r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_BUSY;\r
+\r
+ /* Enable the Early Wakeup Interrupt */ \r
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_WWDG_ENABLE(hwwdg); \r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Refreshes the WWDG.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @param Counter: value of counter to put in WWDG counter\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK(hwwdg); \r
+ \r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_BUSY;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ \r
+ /* Write to WWDG CR the WWDG Counter value to refresh with */\r
+ MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);\r
+ \r
+ /* Change WWDG peripheral state */ \r
+ hwwdg->State = HAL_WWDG_STATE_READY; \r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hwwdg);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles WWDG interrupt request.\r
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations \r
+ * or data logging must be performed before the actual reset is generated. \r
+ * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.\r
+ * When the downcounter reaches the value 0x40, and EWI interrupt is \r
+ * generated and the corresponding Interrupt Service Routine (ISR) can \r
+ * be used to trigger specific actions (such as communications or data \r
+ * logging), before resetting the device. \r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)\r
+{ \r
+ /* Check if Early Wakeup Interrupt is enable */\r
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)\r
+ {\r
+ /* Check if WWDG Early Wakeup Interrupt occurred */\r
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)\r
+ {\r
+ /* Early Wakeup callback */ \r
+ HAL_WWDG_WakeupCallback(hwwdg);\r
+ \r
+ /* Change WWDG peripheral state */\r
+ hwwdg->State = HAL_WWDG_STATE_READY; \r
+ \r
+ /* Clear the WWDG Early Wakeup flag */\r
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hwwdg);\r
+ }\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Early Wakeup WWDG callback.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval None\r
+ */\r
+__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)\r
+{\r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_WWDG_WakeupCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions \r
+ * @brief Peripheral State functions. \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral \r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the WWDG state.\r
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains\r
+ * the configuration information for the specified WWDG module.\r
+ * @retval HAL state\r
+ */\r
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)\r
+{\r
+ return hwwdg->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_fmc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief FMC Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FMC peripheral features #####\r
+ ==============================================================================\r
+ [..] The Flexible memory controller (FMC) includes three memory controllers:\r
+ (+) The NOR/PSRAM memory controller\r
+ (+) The NAND memory controller\r
+ (+) The Synchronous DRAM (SDRAM) controller \r
+ \r
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static\r
+ memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\r
+ (+) to translate AHB transactions into the appropriate external device protocol\r
+ (+) to meet the access time requirements of the external memory devices\r
+ \r
+ [..] All external memories share the addresses, data and control signals with the controller.\r
+ Each external device is accessed by means of a unique Chip Select. The FMC performs\r
+ only one access at a time to an external device.\r
+ The main features of the FMC controller are the following:\r
+ (+) Interface with static-memory mapped devices including:\r
+ (++) Static random access memory (SRAM)\r
+ (++) Read-only memory (ROM)\r
+ (++) NOR Flash memory/OneNAND Flash memory\r
+ (++) PSRAM (4 memory banks)\r
+ (++) 16-bit PC Card compatible devices\r
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of\r
+ data\r
+ (+) Interface with synchronous DRAM (SDRAM) memories\r
+ (+) Independent Chip Select control for each memory bank\r
+ (+) Independent configuration for each memory bank\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL FMC Low Layer\r
+ * @brief FMC driver modules\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions\r
+ * @brief NORSRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ============================================================================== \r
+ ##### How to use NORSRAM device driver #####\r
+ ==============================================================================\r
+ \r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order\r
+ to run the NORSRAM external devices.\r
+ \r
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() \r
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()\r
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()\r
+ (+) FMC NORSRAM bank extended timing configuration using the function \r
+ FMC_NORSRAM_Extended_Timing_Init()\r
+ (+) FMC NORSRAM bank enable/disable write operation using the functions\r
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NORSRAM interface\r
+ (+) De-initialize the FMC NORSRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the FMC_NORSRAM device according to the specified\r
+ * control parameters in the FMC_NORSRAM_InitTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Init: Pointer to NORSRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));\r
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));\r
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));\r
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));\r
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));\r
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));\r
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));\r
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));\r
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));\r
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));\r
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));\r
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); \r
+ assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));\r
+ assert_param(IS_FMC_PAGESIZE(Init->PageSize));\r
+\r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Init->NSBank];\r
+ \r
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,\r
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */\r
+ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \\r
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \\r
+ FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \\r
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \\r
+ FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));\r
+ \r
+ /* Set NORSRAM device control parameters */\r
+ tmpr |= (uint32_t)(Init->DataAddressMux |\\r
+ Init->MemoryType |\\r
+ Init->MemoryDataWidth |\\r
+ Init->BurstAccessMode |\\r
+ Init->WaitSignalPolarity |\\r
+ Init->WaitSignalActive |\\r
+ Init->WriteOperation |\\r
+ Init->WaitSignal |\\r
+ Init->ExtendedMode |\\r
+ Init->AsynchronousWait |\\r
+ Init->WriteBurst |\\r
+ Init->ContinuousClock |\\r
+ Init->PageSize |\\r
+ Init->WriteFifo);\r
+ \r
+ if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)\r
+ {\r
+ tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;\r
+ }\r
+ \r
+ Device->BTCR[Init->NSBank] = tmpr;\r
+\r
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */\r
+ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))\r
+ { \r
+ Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; \r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\\r
+ Init->ContinuousClock);\r
+ }\r
+ if(Init->NSBank != FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitialize the FMC_NORSRAM peripheral \r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param ExDevice: Pointer to NORSRAM extended mode device instance \r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable the FMC_NORSRAM device */\r
+ __FMC_NORSRAM_DISABLE(Device, Bank);\r
+ \r
+ /* De-initialize the FMC_NORSRAM device */\r
+ /* FMC_NORSRAM_BANK1 */\r
+ if(Bank == FMC_NORSRAM_BANK1)\r
+ {\r
+ Device->BTCR[Bank] = 0x000030DB; \r
+ }\r
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */\r
+ else\r
+ { \r
+ Device->BTCR[Bank] = 0x000030D2; \r
+ }\r
+ \r
+ Device->BTCR[Bank + 1] = 0x0FFFFFFF;\r
+ ExDevice->BWTR[Bank] = 0x0FFFFFFF;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Get the BTCR register value */\r
+ tmpr = Device->BTCR[Bank + 1];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \\r
+ FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \\r
+ FMC_BTR1_ACCMOD));\r
+ \r
+ /* Set FMC_NORSRAM device timing parameters */ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (((Timing->CLKDivision)-1) << 20) |\\r
+ (((Timing->DataLatency)-2) << 24) |\\r
+ (Timing->AccessMode)\r
+ );\r
+ \r
+ Device->BTCR[Bank + 1] = tmpr;\r
+ \r
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */\r
+ if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))\r
+ {\r
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); \r
+ tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);\r
+ Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified\r
+ * parameters in the FMC_NORSRAM_TimingTypeDef\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Timing: Pointer to NORSRAM Timing structure\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)\r
+{ \r
+ uint32_t tmpr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));\r
+ \r
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */\r
+ if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); \r
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank)); \r
+ \r
+ /* Get the BWTR register value */\r
+ tmpr = Device->BWTR[Bank];\r
+\r
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r
+ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \\r
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));\r
+ \r
+ tmpr |= (uint32_t)(Timing->AddressSetupTime |\\r
+ ((Timing->AddressHoldTime) << 4) |\\r
+ ((Timing->DataSetupTime) << 8) |\\r
+ ((Timing->BusTurnAroundDuration) << 16) |\\r
+ (Timing->AccessMode));\r
+\r
+ Device->BWTR[Bank] = tmpr;\r
+ }\r
+ else\r
+ {\r
+ Device->BWTR[Bank] = 0x0FFFFFFF;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NORSRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NORSRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Enable write operation */\r
+ Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NORSRAM write operation.\r
+ * @param Device: Pointer to NORSRAM device instance\r
+ * @param Bank: NORSRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));\r
+ \r
+ /* Disable write operation */\r
+ Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions\r
+ * @brief NAND Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use NAND device driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver contains a set of APIs to interface with the FMC NAND banks in order\r
+ to run the NAND external devices.\r
+ \r
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit() \r
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()\r
+ (+) FMC NAND bank common space timing configuration using the function \r
+ FMC_NAND_CommonSpace_Timing_Init()\r
+ (+) FMC NAND bank attribute space timing configuration using the function \r
+ FMC_NAND_AttributeSpace_Timing_Init()\r
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions\r
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()\r
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC NAND interface\r
+ (+) De-initialize the FMC NAND interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND device according to the specified\r
+ * control parameters in the FMC_NAND_HandleTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Init: Pointer to NAND Initialization structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));\r
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));\r
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));\r
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));\r
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));\r
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); \r
+\r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PCR;\r
+\r
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */\r
+ tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \\r
+ FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \\r
+ FMC_PCR_TAR | FMC_PCR_ECCPS)); \r
+ /* Set NAND device control parameters */\r
+ tmpr |= (uint32_t)(Init->Waitfeature |\\r
+ FMC_PCR_MEMORY_TYPE_NAND |\\r
+ Init->MemoryDataWidth |\\r
+ Init->EccComputation |\\r
+ Init->ECCPageSize |\\r
+ ((Init->TCLRSetupTime) << 9) |\\r
+ ((Init->TARSetupTime) << 13)); \r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PCR = tmpr;\r
+ \r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_NAND_DEVICE(Device));\r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PMEM;\r
+\r
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \\r
+ FMC_PMEM_MEMHIZ3)); \r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24)\r
+ );\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PMEM = tmpr;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified\r
+ * parameters in the FMC_NAND_PCC_TimingTypeDef\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Timing: Pointer to NAND timing structure\r
+ * @param Bank: NAND bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr = 0; \r
+ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Get the NAND bank 3 register value */\r
+ tmpr = Device->PATT;\r
+\r
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */\r
+ tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \\r
+ FMC_PATT_ATTHIZ3));\r
+ /* Set FMC_NAND device timing parameters */\r
+ tmpr |= (uint32_t)(Timing->SetupTime |\\r
+ ((Timing->WaitSetupTime) << 8) |\\r
+ ((Timing->HoldSetupTime) << 16) |\\r
+ ((Timing->HiZSetupTime) << 24));\r
+ \r
+ /* NAND bank 3 registers configuration */\r
+ Device->PATT = tmpr;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_NAND device \r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable the NAND Bank */\r
+ __FMC_NAND_DISABLE(Device);\r
+ \r
+ /* Set the FMC_NAND_BANK3 registers to their reset values */\r
+ Device->PCR = 0x00000018;\r
+ Device->SR = 0x00000040;\r
+ Device->PMEM = 0xFCFCFCFC;\r
+ Device->PATT = 0xFCFCFCFC; \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FMC_NAND_Group3 Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_NAND Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC NAND interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+ \r
+/**\r
+ * @brief Enables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Enable ECC feature */\r
+ Device->PCR |= FMC_PCR_ECCEN;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param Bank: NAND bank number\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) \r
+{ \r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+ \r
+ /* Disable ECC feature */\r
+ Device->PCR &= ~FMC_PCR_ECCEN;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_NAND ECC feature.\r
+ * @param Device: Pointer to NAND device instance\r
+ * @param ECCval: Pointer to ECC value\r
+ * @param Bank: NAND bank number\r
+ * @param Timeout: Timeout wait value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */ \r
+ assert_param(IS_FMC_NAND_DEVICE(Device)); \r
+ assert_param(IS_FMC_NAND_BANK(Bank));\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait until FIFO is empty */\r
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ /* Get the ECCR register value */\r
+ *ECCval = (uint32_t)Device->ECCR;\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FMC_LL_SDRAM\r
+ * @brief SDRAM Controller functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use SDRAM device driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver contains a set of APIs to interface with the FMC SDRAM banks in order\r
+ to run the SDRAM external devices.\r
+ \r
+ (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() \r
+ (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()\r
+ (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()\r
+ (+) FMC SDRAM bank enable/disable write operation using the functions\r
+ FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() \r
+ (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de_initialization functions #####\r
+ ==============================================================================\r
+ [..] \r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the FMC SDRAM interface\r
+ (+) De-initialize the FMC SDRAM interface \r
+ (+) Configure the FMC clock and associated GPIOs\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device according to the specified\r
+ * control parameters in the FMC_SDRAM_InitTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Init: Pointer to SDRAM Initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));\r
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));\r
+ assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));\r
+ assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));\r
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));\r
+ assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));\r
+ assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));\r
+ assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));\r
+ assert_param(IS_FMC_READ_BURST(Init->ReadBurst));\r
+ assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); \r
+\r
+ /* Set SDRAM bank configuration parameters */\r
+ if (Init->SDBank != FMC_SDRAM_BANK2) \r
+ { \r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection |\\r
+ Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay\r
+ ); \r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */ \r
+ {\r
+ tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+ \r
+ tmpr1 |= (uint32_t)(Init->SDClockPeriod |\\r
+ Init->ReadBurst |\\r
+ Init->ReadPipeDelay); \r
+ \r
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\r
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \\r
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r
+\r
+ tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\\r
+ Init->RowBitsNumber |\\r
+ Init->MemoryDataWidth |\\r
+ Init->InternalBankNumber |\\r
+ Init->CASLatency |\\r
+ Init->WriteProtection);\r
+\r
+ Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r
+ Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FMC_SDRAM device timing according to the specified\r
+ * parameters in the FMC_SDRAM_TimingTypeDef\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)\r
+{\r
+ uint32_t tmpr1 = 0;\r
+ uint32_t tmpr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));\r
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));\r
+ assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));\r
+ assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));\r
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));\r
+ assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));\r
+ assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Set SDRAM device timing parameters */ \r
+ if (Bank != FMC_SDRAM_BANK2) \r
+ { \r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RPDelay)-1) << 20) |\\r
+ (((Timing->RCDDelay)-1) << 24));\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r
+ }\r
+ else /* FMC_Bank2_SDRAM */\r
+ { \r
+ tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ \r
+ tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\\r
+ (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\r
+ (((Timing->SelfRefreshTime)-1) << 8) |\\r
+ (((Timing->WriteRecoveryTime)-1) <<16) |\\r
+ (((Timing->RCDDelay)-1) << 24)); \r
+ \r
+ tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];\r
+ \r
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\r
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\r
+ FMC_SDTR1_TRCD));\r
+ tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\\r
+ (((Timing->RPDelay)-1) << 20)); \r
+\r
+ Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;\r
+ Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;\r
+ } \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the FMC_SDRAM peripheral \r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* De-initialize the SDRAM device */\r
+ Device->SDCR[Bank] = 0x000002D0;\r
+ Device->SDTR[Bank] = 0x0FFFFFFF; \r
+ Device->SDCMR = 0x00000000;\r
+ Device->SDRTR = 0x00000000;\r
+ Device->SDSR = 0x00000000;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2\r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### FMC_SDRAM Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control dynamically\r
+ the FMC SDRAM interface.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables dynamically FMC_SDRAM write protection.\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Bank: SDRAM bank number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Enable write protection */\r
+ Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Disables dynamically FMC_SDRAM write protection.\r
+ * @param hsdram: FMC_SDRAM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+ \r
+ /* Disable write protection */\r
+ Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r
+ \r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief Send Command to the FMC SDRAM bank\r
+ * @param Device: Pointer to SDRAM device instance\r
+ * @param Command: Pointer to SDRAM command structure \r
+ * @param Timing: Pointer to SDRAM Timing structure\r
+ * @param Timeout: Timeout wait value\r
+ * @retval HAL state\r
+ */ \r
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r
+{\r
+ __IO uint32_t tmpr = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));\r
+ assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));\r
+ assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); \r
+\r
+ /* Set command register */\r
+ tmpr = (uint32_t)((Command->CommandMode) |\\r
+ (Command->CommandTarget) |\\r
+ (((Command->AutoRefreshNumber)-1) << 5) |\\r
+ ((Command->ModeRegisterDefinition) << 9)\r
+ );\r
+ \r
+ Device->SDCMR = tmpr;\r
+\r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+\r
+ /* wait until command is send */\r
+ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Program the SDRAM Memory Refresh rate.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param RefreshRate: The SDRAM refresh rate value. \r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_REFRESH_RATE(RefreshRate));\r
+ \r
+ /* Set the refresh rate in command register */\r
+ Device->SDRTR |= (RefreshRate<<1);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param AutoRefreshNumber: Specifies the auto Refresh number. \r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));\r
+ \r
+ /* Set the Auto-refresh number in command register */\r
+ Device->SDCMR |= (AutoRefreshNumber << 5); \r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns the indicated FMC SDRAM bank mode status.\r
+ * @param Device: Pointer to SDRAM device instance \r
+ * @param Bank: Defines the FMC SDRAM bank. This parameter can be \r
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. \r
+ * @retval The FMC SDRAM bank mode status, could be on of the following values:\r
+ * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or \r
+ * FMC_SDRAM_POWER_DOWN_MODE. \r
+ */\r
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FMC_SDRAM_DEVICE(Device));\r
+ assert_param(IS_FMC_SDRAM_BANK(Bank));\r
+\r
+ /* Get the corresponding bank mode */\r
+ if(Bank == FMC_SDRAM_BANK1)\r
+ {\r
+ tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);\r
+ }\r
+ \r
+ /* Return the mode status */\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_sdmmc.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief SDMMC Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the SDMMC peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### SDMMC peripheral features #####\r
+ ============================================================================== \r
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2\r
+ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA\r
+ devices.\r
+ \r
+ [..] The SDMMC features include the following:\r
+ (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\r
+ for three different databus modes: 1-bit (default), 4-bit and 8-bit\r
+ (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\r
+ (+) Full compliance with SD Memory Card Specifications Version 2.0\r
+ (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\r
+ different data bus modes: 1-bit (default) and 4-bit\r
+ (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\r
+ Rev1.1)\r
+ (+) Data transfer up to 48 MHz for the 8 bit mode\r
+ (+) Data and command output enable signals to control external bidirectional drivers.\r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ This driver is a considered as a driver of service for external devices drivers \r
+ that interfaces with the SDMMC peripheral.\r
+ According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs \r
+ is used in the device's driver to perform SDMMC operations and functionalities.\r
+ \r
+ This driver is almost transparent for the final user, it is only used to implement other\r
+ functionalities of the external device.\r
+ \r
+ [..]\r
+ (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL \r
+ (PLL48CLK). Before start working with SDMMC peripheral make sure that the\r
+ PLL is well configured.\r
+ The SDMMC peripheral uses two clock signals:\r
+ (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)\r
+ (++) APB2 bus clock (PCLK2)\r
+ \r
+ -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:\r
+ Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))\r
+ \r
+ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC\r
+ peripheral.\r
+\r
+ (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) \r
+ function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).\r
+ \r
+ (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.\r
+ \r
+ (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) \r
+ and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. \r
+ \r
+ (+) When using the DMA mode \r
+ (++) Configure the DMA in the MSP layer of the external device\r
+ (++) Active the needed channel Request \r
+ (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro\r
+ __SDMMC_DMA_DISABLE().\r
+ \r
+ (+) To control the CPSM (Command Path State Machine) and send \r
+ commands to the card use the SDMMC_SendCommand(SDMMCx), \r
+ SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has\r
+ to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according \r
+ to the selected command to be sent.\r
+ The parameters that should be filled are:\r
+ (++) Command Argument\r
+ (++) Command Index\r
+ (++) Command Response type\r
+ (++) Command Wait\r
+ (++) CPSM Status (Enable or Disable).\r
+ \r
+ -@@- To check if the command is well received, read the SDMMC_CMDRESP\r
+ register using the SDMMC_GetCommandResponse().\r
+ The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the\r
+ SDMMC_GetResponse() function.\r
+ \r
+ (+) To control the DPSM (Data Path State Machine) and send/receive \r
+ data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), \r
+ SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.\r
+ \r
+ *** Read Operations ***\r
+ =======================\r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to\r
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.\r
+ The parameters that should be filled are:\r
+ (++) Data TimeOut\r
+ (++) Data Length\r
+ (++) Data Block size\r
+ (++) Data Transfer direction: should be from card (To SDMMC)\r
+ (++) Data Transfer mode\r
+ (++) DPSM Status (Enable or Disable)\r
+ \r
+ (#) Configure the SDMMC resources to receive the data from the card\r
+ according to selected transfer mode (Refer to Step 8, 9 and 10).\r
+ \r
+ (#) Send the selected Read command (refer to step 11).\r
+ \r
+ (#) Use the SDMMC flags/interrupts to check the transfer status.\r
+ \r
+ *** Write Operations ***\r
+ ========================\r
+ [..]\r
+ (#) First, user has to fill the data structure (pointer to\r
+ SDMMC_DataInitTypeDef) according to the selected data type to be received.\r
+ The parameters that should be filled are:\r
+ (++) Data TimeOut\r
+ (++) Data Length\r
+ (++) Data Block size\r
+ (++) Data Transfer direction: should be to card (To CARD)\r
+ (++) Data Transfer mode\r
+ (++) DPSM Status (Enable or Disable)\r
+ \r
+ (#) Configure the SDMMC resources to send the data to the card according to \r
+ selected transfer mode.\r
+ \r
+ (#) Send the selected Write command.\r
+ \r
+ (#) Use the SDMMC flags/interrupts to check the transfer status.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDMMC_LL SDMMC Low Layer\r
+ * @brief Low layer module for SD\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the SDMMC according to the specified\r
+ * parameters in the SDMMC_InitTypeDef and create the associated handle.\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param Init: SDMMC initialization structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)\r
+{\r
+ uint32_t tmpreg = 0; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));\r
+ assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); \r
+ assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));\r
+ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));\r
+ assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));\r
+ assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\r
+ assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));\r
+ \r
+ /* Set SDMMC configuration parameters */\r
+ tmpreg |= (Init.ClockEdge |\\r
+ Init.ClockBypass |\\r
+ Init.ClockPowerSave |\\r
+ Init.BusWide |\\r
+ Init.HardwareFlowControl |\\r
+ Init.ClockDiv\r
+ ); \r
+ \r
+ /* Write to SDMMC CLKCR */\r
+ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions \r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### I/O operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the SDMMC data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Read data (word) from Rx FIFO in blocking mode (polling) \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ /* Read data from Rx FIFO */ \r
+ return (SDMMCx->FIFO);\r
+}\r
+\r
+/**\r
+ * @brief Write data (word) to Tx FIFO in blocking mode (polling) \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param pWriteData: pointer to data to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)\r
+{ \r
+ /* Write data to FIFO */ \r
+ SDMMCx->FIFO = *pWriteData;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the SDMMC data \r
+ transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set SDMMC Power state to ON. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)\r
+{ \r
+ /* Set power state to ON */ \r
+ SDMMCx->POWER = SDMMC_POWER_PWRCTRL;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Set SDMMC Power state to OFF. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ /* Set power state to OFF */\r
+ SDMMCx->POWER = (uint32_t)0x00000000;\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get SDMMC Power state. \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Power status of the controller. The returned value can be one of the \r
+ * following values:\r
+ * - 0x00: Power OFF\r
+ * - 0x02: Power UP\r
+ * - 0x03: Power ON \r
+ */\r
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) \r
+{\r
+ return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);\r
+}\r
+\r
+/**\r
+ * @brief Configure the SDMMC command path according to the specified parameters in\r
+ * SDMMC_CmdInitTypeDef structure and send the command \r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains \r
+ * the configuration information for the SDMMC command\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));\r
+ assert_param(IS_SDMMC_RESPONSE(Command->Response));\r
+ assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));\r
+ assert_param(IS_SDMMC_CPSM(Command->CPSM));\r
+\r
+ /* Set the SDMMC Argument value */\r
+ SDMMCx->ARG = Command->Argument;\r
+\r
+ /* Set SDMMC command parameters */\r
+ tmpreg |= (uint32_t)(Command->CmdIndex |\\r
+ Command->Response |\\r
+ Command->WaitForInterrupt |\\r
+ Command->CPSM);\r
+ \r
+ /* Write to SDMMC CMD register */\r
+ MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Return the command index of last command for which response received\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Command index of the last command response received\r
+ */\r
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (uint8_t)(SDMMCx->RESPCMD);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Return the response received from the card for the last command\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param Response: Specifies the SDMMC response register. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDMMC_RESP1: Response Register 1\r
+ * @arg SDMMC_RESP2: Response Register 2\r
+ * @arg SDMMC_RESP3: Response Register 3\r
+ * @arg SDMMC_RESP4: Response Register 4 \r
+ * @retval The Corresponding response register value\r
+ */\r
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_RESP(Response));\r
+ \r
+ /* Get the response */\r
+ tmp = (uint32_t)&(SDMMCx->RESP1) + Response;\r
+ \r
+ return (*(__IO uint32_t *) tmp);\r
+} \r
+\r
+/**\r
+ * @brief Configure the SDMMC data path according to the specified \r
+ * parameters in the SDMMC_DataInitTypeDef.\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param Data : pointer to a SDMMC_DataInitTypeDef structure \r
+ * that contains the configuration information for the SDMMC data.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));\r
+ assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));\r
+ assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));\r
+ assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));\r
+ assert_param(IS_SDMMC_DPSM(Data->DPSM));\r
+\r
+ /* Set the SDMMC Data TimeOut value */\r
+ SDMMCx->DTIMER = Data->DataTimeOut;\r
+\r
+ /* Set the SDMMC DataLength value */\r
+ SDMMCx->DLEN = Data->DataLength;\r
+\r
+ /* Set the SDMMC data configuration parameters */\r
+ tmpreg |= (uint32_t)(Data->DataBlockSize |\\r
+ Data->TransferDir |\\r
+ Data->TransferMode |\\r
+ Data->DPSM);\r
+ \r
+ /* Write to SDMMC DCTRL */\r
+ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);\r
+\r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Returns number of remaining data bytes to be transferred.\r
+ * @param SDMMCx: Pointer to SDMMC register base\r
+ * @retval Number of remaining data bytes to be transferred\r
+ */\r
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (SDMMCx->DCOUNT);\r
+}\r
+\r
+/**\r
+ * @brief Get the FIFO data\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @retval Data received\r
+ */\r
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)\r
+{\r
+ return (SDMMCx->FIFO);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets one of the two options of inserting read wait interval.\r
+ * @param SDMMCx: Pointer to SDMMC register base \r
+ * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.\r
+ * This parameter can be:\r
+ * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK\r
+ * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));\r
+ \r
+ /* Set SDMMC read wait mode */\r
+ SDMMCx->DCTRL |= SDMMC_ReadWaitMode;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_ll_usb.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief USB Low Layer HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
+ \r
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
+\r
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_LL_USB_DRIVER\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/** @defgroup PCD_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USB Core\r
+ * @param USBx: USB Instance\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ \r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+ /* Init The ULPI Interface */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
+ \r
+ /* Select vbus source */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
+ if(cfg.use_external_vbus == 1)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
+ }\r
+ /* Reset after a PHY select */\r
+ USB_CoreReset(USBx); \r
+ }\r
+ else /* FS interface (embedded Phy) */\r
+ {\r
+ \r
+ /* Select FS Embedded PHY */\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
+ \r
+ /* Reset after a PHY select and set Host mode */\r
+ USB_CoreReset(USBx);\r
+ \r
+ /* Deactivate the power down*/\r
+ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\r
+ }\r
+ \r
+ if(cfg.dma_enable == ENABLE)\r
+ {\r
+ USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\r
+ } \r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EnableGlobalInt\r
+ * Enables the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_DisableGlobalInt\r
+ * Disable the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+ \r
+/**\r
+ * @brief USB_SetCurrentMode : Set functional mode\r
+ * @param USBx : Selected device\r
+ * @param mode : current core mode\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_DEVICE_MODE: Peripheral mode\r
+ * @arg USB_OTG_HOST_MODE: Host mode\r
+ * @arg USB_OTG_DRD_MODE: Dual Role Device mode \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)\r
+{\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); \r
+ \r
+ if ( mode == USB_OTG_HOST_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; \r
+ }\r
+ else if ( mode == USB_OTG_DEVICE_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; \r
+ }\r
+ HAL_Delay(50);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers \r
+ * for device mode\r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i = 0;\r
+\r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ if (cfg.vbus_sensing_enable == 0)\r
+ {\r
+ /*Desactivate VBUS Sensing B */\r
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* B-peripheral session valid override enable*/ \r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
+ }\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+\r
+ /* Device mode configuration */\r
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
+ \r
+ if(cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ if(cfg.speed == USB_OTG_SPEED_HIGH)\r
+ { \r
+ /* Set High speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);\r
+ }\r
+ else \r
+ {\r
+ /* set High speed phy in Full speed mode */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set Full speed phy */\r
+ USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);\r
+ }\r
+\r
+ /* Flush the FIFOs */\r
+ USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+\r
+ \r
+ /* Clear all pending Device Interrupts */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = 0;\r
+ }\r
+ \r
+ USBx_INEP(i)->DIEPTSIZ = 0;\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ }\r
+ \r
+ for (i = 0; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = 0;\r
+ }\r
+ \r
+ USBx_OUTEP(i)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ \r
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
+ \r
+ if (cfg.dma_enable == 1)\r
+ {\r
+ /*Set threshold parameters */\r
+ USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);\r
+ USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);\r
+ \r
+ i= USBx_DEVICE->DTHRCTL;\r
+ }\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xBFFFFFFF;\r
+\r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Device mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\\r
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\\r
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+ \r
+ if(cfg.Sof_enable)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
+ }\r
+\r
+ if (cfg.vbus_sensing_enable == ENABLE)\r
+ {\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); \r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
+ * @param USBx : Selected device\r
+ * @param num : FIFO number\r
+ * This parameter can be a value from 1 to 15\r
+ 15 means Flush all Tx FIFOs\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 )); \r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_FlushRxFifo : Flush Rx FIFO\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
+ \r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register \r
+ * depending the PHY type and the enumeration speed of the device.\r
+ * @param USBx : Selected device\r
+ * @param speed : device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @retval Hal status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)\r
+{\r
+ USBx_DEVICE->DCFG |= speed;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_GetDevSpeed :Return the Dev Speed \r
+ * @param USBx : Selected device\r
+ * @retval speed : device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t speed = 0;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_HIGH;\r
+ }\r
+ else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||\r
+ ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
+ {\r
+ speed = USB_OTG_SPEED_FULL;\r
+ }\r
+ else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ speed = USB_OTG_SPEED_LOW;\r
+ }\r
+ \r
+ return speed;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ \r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+\r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ \r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief Activate and configure a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ static __IO uint32_t debug = 0;\r
+ \r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ } \r
+ \r
+ \r
+ debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));\r
+ \r
+ debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);\r
+ debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;\r
+ debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\r
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); \r
+ } \r
+ \r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @brief De-activate and de-initialize an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); \r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; \r
+ }\r
+ else\r
+ {\r
+\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); \r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize a dedicated endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ uint16_t pktcnt = 0;\r
+ \r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); \r
+ } \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ } \r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); \r
+ } \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; \r
+ }\r
+ else\r
+ {\r
+ pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); \r
+ }\r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;\r
+ }\r
+ \r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ }\r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r
+{\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r
+ \r
+ if(ep->xfer_len > ep->maxpacket)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r
+ \r
+ }\r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r
+ }\r
+ else\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);\r
+ }\r
+ }\r
+ \r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); \r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r
+ \r
+ if (ep->xfer_len > 0)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ \r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));\r
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); \r
+ \r
+\r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);\r
+ }\r
+ \r
+ /* EP enable */\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : pointer to source buffer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to write\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)\r
+{\r
+ uint32_t count32b= 0 , i= 0;\r
+ \r
+ if (dma == 0)\r
+ {\r
+ count32b = (len + 3) / 4;\r
+ for (i = 0; i < count32b; i++, src += 4)\r
+ {\r
+ USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated \r
+ * with the EP/channel\r
+ * @param USBx : Selected device \r
+ * @param src : source pointer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to read\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval pointer to destination buffer\r
+ */\r
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+ uint32_t i=0;\r
+ uint32_t count32b = (len + 3) / 4;\r
+ \r
+ for ( i = 0; i < count32b; i++, dest += 4 )\r
+ {\r
+ *(__packed uint32_t *)dest = USBx_DFIFO(0);\r
+ \r
+ }\r
+ return ((void *)dest);\r
+}\r
+\r
+/**\r
+ * @brief USB_EPSetStall : set a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); \r
+ } \r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); \r
+ } \r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_EPClearStall : Clear a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in == 1)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+ if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r
+ {\r
+ USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_StopDevice : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Clear Pending interrupt */\r
+ for (i = 0; i < 15 ; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFF;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFF;\r
+ }\r
+ USBx_DEVICE->DAINT = 0xFFFFFFFF;\r
+ \r
+ /* Clear interrupt masks */\r
+ USBx_DEVICE->DIEPMSK = 0;\r
+ USBx_DEVICE->DOEPMSK = 0;\r
+ USBx_DEVICE->DAINTMSK = 0;\r
+ \r
+ /* Flush the FIFO */\r
+ USB_FlushRxFifo(USBx);\r
+ USB_FlushTxFifo(USBx , 0x10 ); \r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevAddress : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @param address : new device address to be assigned\r
+ * This parameter can be a value from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
+{\r
+ USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);\r
+ USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;\r
+ HAL_Delay(3);\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadInterrupts: return the global USB interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v = 0;\r
+ \r
+ v = USBx->GINTSTS;\r
+ v &= USBx->GINTMSK;\r
+ return v; \r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xffff0000) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t v;\r
+ v = USBx_DEVICE->DAINT;\r
+ v &= USBx_DEVICE->DAINTMSK;\r
+ return ((v & 0xFFFF));\r
+}\r
+\r
+/**\r
+ * @brief Returns Device OUT EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device OUT EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v;\r
+ v = USBx_OUTEP(epnum)->DOEPINT;\r
+ v &= USBx_DEVICE->DOEPMSK;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief Returns Device IN EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device IN EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r
+{\r
+ uint32_t v, msk, emp;\r
+ \r
+ msk = USBx_DEVICE->DIEPMSK;\r
+ emp = USBx_DEVICE->DIEPEMPMSK;\r
+ msk |= ((emp >> epnum) & 0x1) << 7;\r
+ v = USBx_INEP(epnum)->DIEPINT & msk;\r
+ return v;\r
+}\r
+\r
+/**\r
+ * @brief USB_ClearInterrupts: clear a USB interrupt\r
+ * @param USBx : Selected device\r
+ * @param interrupt : interrupt flag\r
+ * @retval None\r
+ */\r
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
+{\r
+ USBx->GINTSTS |= interrupt; \r
+}\r
+\r
+/**\r
+ * @brief Returns USB core mode\r
+ * @param USBx : Selected device\r
+ * @retval return core mode : Host or Device\r
+ * This parameter can be one of the these values:\r
+ * 0 : Host \r
+ * 1 : Device\r
+ */\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx->GINTSTS ) & 0x1);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Activate EP0 for Setup transactions\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ /* Set the MPS of the IN EP based on the enumeration speed */\r
+ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
+ \r
+ if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ USBx_INEP(0)->DIEPCTL |= 3;\r
+ }\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Prepare the EP0 to start the first control setup\r
+ * @param USBx : Selected device\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @param psetup : pointer to setup packet\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\r
+{\r
+ USBx_OUTEP(0)->DOEPTSIZ = 0;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;\r
+ USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);\r
+ USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; \r
+ \r
+ if (dma == 1)\r
+ {\r
+ USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;\r
+ /* EP enable */\r
+ USBx_OUTEP(0)->DOEPCTL = 0x80008000;\r
+ }\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+\r
+/**\r
+ * @brief Reset the USB Core (needed after USB clock settings change)\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+\r
+ /* Wait for AHB master IDLE state. */\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\r
+ \r
+ /* Core Soft Reset */\r
+ count = 0;\r
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
+\r
+ do\r
+ {\r
+ if (++count > 200000)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief USB_HostInit : Initializes the USB OTG controller registers \r
+ * for Host mode \r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t i;\r
+ \r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0;\r
+ \r
+ /*Activate VBUS Sensing B */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ \r
+ /* Disable the FS/LS support mode only */\r
+ if((cfg.speed == USB_OTG_SPEED_FULL)&&\r
+ (USBx != USB_OTG_FS))\r
+ {\r
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; \r
+ }\r
+ else\r
+ {\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); \r
+ }\r
+\r
+ /* Make sure the FIFOs are flushed. */\r
+ USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */\r
+ USB_FlushRxFifo(USBx);\r
+\r
+ /* Clear all pending HC Interrupts */\r
+ for (i = 0; i < cfg.Host_channels; i++)\r
+ {\r
+ USBx_HC(i)->HCINT = 0xFFFFFFFF;\r
+ USBx_HC(i)->HCINTMSK = 0;\r
+ }\r
+ \r
+ /* Enable VBUS driving */\r
+ USB_DriveVbus(USBx, 1);\r
+ \r
+ HAL_Delay(200);\r
+ \r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0;\r
+ \r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+\r
+ \r
+ if(USBx == USB_OTG_FS)\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x80; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);\r
+\r
+ }\r
+\r
+ else\r
+ {\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = (uint32_t )0x200; \r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);\r
+ USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);\r
+ }\r
+ \r
+ /* Enable the common interrupts */\r
+ if (cfg.dma_enable == DISABLE)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r
+ }\r
+ \r
+ /* Enable interrupts matching to the Host mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\\r
+ USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the \r
+ * HCFG register on the PHY type and set the right frame interval\r
+ * @param USBx : Selected device\r
+ * @param freq : clock frequency\r
+ * This parameter can be one of the these values:\r
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock \r
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)\r
+{\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
+ USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);\r
+ \r
+ if (freq == HCFG_48_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)48000;\r
+ }\r
+ else if (freq == HCFG_6_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = (uint32_t)6000;\r
+ } \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+* @brief USB_OTG_ResetPort : Reset Host Port\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ * @note : (1)The application must wait at least 10 ms\r
+ * before clearing the reset bit.\r
+ */\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ \r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); \r
+ HAL_Delay (10); /* See Note #1 */\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DriveVbus : activate or de-activate vbus\r
+ * @param state : VBUS state\r
+ * This parameter can be one of the these values:\r
+ * 0 : VBUS Active \r
+ * 1 : VBUS Inactive\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
+{\r
+ __IO uint32_t hprt0;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r
+ \r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))\r
+ {\r
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); \r
+ }\r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))\r
+ {\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); \r
+ }\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Return Host Core speed\r
+ * @param USBx : Selected device\r
+ * @retval speed : Host speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ */\r
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ __IO uint32_t hprt0;\r
+ \r
+ hprt0 = USBx_HPRT0;\r
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
+}\r
+\r
+/**\r
+ * @brief Return Host Current Frame number\r
+ * @param USBx : Selected device\r
+ * @retval current frame number\r
+*/\r
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel\r
+ * @param USBx : Selected device\r
+ * @param ch_num : Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum : Endpoint number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address : Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed : Current device speed\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_OTG_SPEED_HIGH: High speed mode\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @param ep_type : Endpoint Type\r
+ * This parameter can be one of the these values:\r
+ * @arg EP_TYPE_CTRL: Control type\r
+ * @arg EP_TYPE_ISOC: Isochronous type\r
+ * @arg EP_TYPE_BULK: Bulk type\r
+ * @arg EP_TYPE_INTR: Interrupt type\r
+ * @param mps : Max Packet Size\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, \r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ \r
+ /* Clear old interrupt conditions for this host channel. */\r
+ USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;\r
+ \r
+ /* Enable channel interrupts required for this transfer. */\r
+ switch (ep_type) \r
+ {\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_NAKM ;\r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ } \r
+ else \r
+ {\r
+ if(USBx != USB_OTG_FS)\r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ }\r
+ }\r
+ break;\r
+ case EP_TYPE_INTR:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_STALLM |\\r
+ USB_OTG_HCINTMSK_TXERRM |\\r
+ USB_OTG_HCINTMSK_DTERRM |\\r
+ USB_OTG_HCINTMSK_NAKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ }\r
+ \r
+ break;\r
+ case EP_TYPE_ISOC:\r
+ \r
+ USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\\r
+ USB_OTG_HCINTMSK_ACKM |\\r
+ USB_OTG_HCINTMSK_AHBERR |\\r
+ USB_OTG_HCINTMSK_FRMORM ; \r
+ \r
+ if (epnum & 0x80) \r
+ {\r
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); \r
+ }\r
+ break;\r
+ }\r
+ \r
+ /* Enable the top level host channel interrupt. */\r
+ USBx_HOST->HAINTMSK |= (1 << ch_num);\r
+ \r
+ /* Make sure host channel interrupts are enabled. */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
+ \r
+ /* Program the HCCHAR register */\r
+ USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\\r
+ (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\\r
+ ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\\r
+ (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\\r
+ ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\\r
+ (mps & USB_OTG_HCCHAR_MPSIZ));\r
+ \r
+ if (ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
+ }\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Start a transfer over a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc : pointer to host channel structure\r
+ * @param dma: USB dma enabled or disabled \r
+ * This parameter can be one of the these values:\r
+ * 0 : DMA feature not used \r
+ * 1 : DMA feature used \r
+ * @retval HAL state\r
+ */\r
+#if defined (__CC_ARM) /*!< ARM Compiler */\r
+#pragma O0\r
+#elif defined (__GNUC__) /*!< GNU Compiler */\r
+#pragma GCC optimize ("O0")\r
+#endif /* __CC_ARM */\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\r
+{\r
+ uint8_t is_oddframe = 0; \r
+ uint16_t len_words = 0; \r
+ uint16_t num_packets = 0;\r
+ uint16_t max_hc_pkt_count = 256;\r
+ \r
+ if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))\r
+ {\r
+ if((dma == 0) && (hc->do_ping == 1))\r
+ {\r
+ USB_DoPing(USBx, hc->ch_num);\r
+ return HAL_OK;\r
+ }\r
+ else if(dma == 1)\r
+ {\r
+ USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r
+ hc->do_ping = 0;\r
+ }\r
+ }\r
+ \r
+ /* Compute the expected number of packets associated to the transfer */\r
+ if (hc->xfer_len > 0)\r
+ {\r
+ num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;\r
+ \r
+ if (num_packets > max_hc_pkt_count)\r
+ {\r
+ num_packets = max_hc_pkt_count;\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ num_packets = 1;\r
+ }\r
+ if (hc->ep_is_in)\r
+ {\r
+ hc->xfer_len = num_packets * hc->max_packet;\r
+ }\r
+ \r
+ \r
+ \r
+ /* Initialize the HCTSIZn register */\r
+ USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\\r
+ ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);\r
+ \r
+ if (dma)\r
+ {\r
+ /* xfer_buff MUST be 32-bits aligned */\r
+ USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\r
+ }\r
+ \r
+ is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;\r
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
+ USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);\r
+ \r
+ /* Set host channel enable */\r
+ USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;\r
+ USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ \r
+ if (dma == 0) /* Slave mode */\r
+ { \r
+ if((hc->ep_is_in == 0) && (hc->xfer_len > 0))\r
+ {\r
+ switch(hc->ep_type) \r
+ {\r
+ /* Non periodic transfer */\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ \r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ \r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx->HNPTXSTS & 0xFFFF))\r
+ {\r
+ /* need to process data in nptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
+ }\r
+ break;\r
+ /* Periodic transfer */\r
+ case EP_TYPE_INTR:\r
+ case EP_TYPE_ISOC:\r
+ len_words = (hc->xfer_len + 3) / 4;\r
+ /* check if there is enough space in FIFO space */\r
+ if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */\r
+ {\r
+ /* need to process data in ptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; \r
+ }\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+ \r
+ /* Write packet into the Tx FIFO. */\r
+ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read all host channel interrupts status\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx_HOST->HAINT) & 0xFFFF);\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)\r
+{\r
+ uint32_t count = 0;\r
+ \r
+ /* Check for space in the request queue to issue the halt. */\r
+ if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx->HNPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+ \r
+ if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); \r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initiate Do Ping protocol\r
+ * @param USBx : Selected device\r
+ * @param hc_num : Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)\r
+{\r
+ uint8_t num_packets = 1;\r
+\r
+ USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\r
+ USB_OTG_HCTSIZ_DOPING;\r
+ \r
+ /* Set host channel enable */\r
+ USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;\r
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Stop Host Core\r
+ * @param USBx : Selected device\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint8_t i;\r
+ uint32_t count = 0;\r
+ uint32_t value;\r
+ \r
+ USB_DisableGlobalInt(USBx);\r
+ \r
+ /* Flush FIFO */\r
+ USB_FlushTxFifo(USBx, 0x10);\r
+ USB_FlushRxFifo(USBx);\r
+ \r
+ /* Flush out any leftover queued requests. */\r
+ for (i = 0; i <= 15; i++)\r
+ { \r
+\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value &= ~USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ USBx_HC(i)->HCCHAR = value;\r
+ }\r
+ \r
+ /* Halt all channels to put them into a known state. */ \r
+ for (i = 0; i <= 15; i++)\r
+ { \r
+\r
+ value = USBx_HC(i)->HCCHAR ;\r
+ \r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value |= USB_OTG_HCCHAR_CHENA; \r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ \r
+ USBx_HC(i)->HCCHAR = value;\r
+ do \r
+ {\r
+ if (++count > 1000) \r
+ {\r
+ break;\r
+ }\r
+ } \r
+ while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+\r
+ /* Clear any pending Host interrupts */\r
+ USBx_HOST->HAINT = 0xFFFFFFFF;\r
+ USBx->GINTSTS = 0xFFFFFFFF;\r
+ USB_EnableGlobalInt(USBx);\r
+ return HAL_OK; \r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************\r
+;* File Name : startup_stm32f756xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V0.3.0\r
+;* Date : 06-March-2015\r
+;* Description : STM32F756xx devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == _iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* - Branches to main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the Cortex-M7 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* \r
+;* Redistribution and use in source and binary forms, with or without modification,\r
+;* are permitted provided that the following conditions are met:\r
+;* 1. Redistributions of source code must retain the above copyright notice,\r
+;* this list of conditions and the following disclaimer.\r
+;* 2. Redistributions in binary form must reproduce the above copyright notice,\r
+;* this list of conditions and the following disclaimer in the documentation\r
+;* and/or other materials provided with the distribution.\r
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+;* may be used to endorse or promote products derived from this software\r
+;* without specific prior written permission.\r
+;*\r
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+;* \r
+;*******************************************************************************\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog \r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection \r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line \r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line \r
+ DCD FLASH_IRQHandler ; FLASH \r
+ DCD RCC_IRQHandler ; RCC \r
+ DCD EXTI0_IRQHandler ; EXTI Line0 \r
+ DCD EXTI1_IRQHandler ; EXTI Line1 \r
+ DCD EXTI2_IRQHandler ; EXTI Line2 \r
+ DCD EXTI3_IRQHandler ; EXTI Line3 \r
+ DCD EXTI4_IRQHandler ; EXTI Line4 \r
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 \r
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 \r
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 \r
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 \r
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 \r
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 \r
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 \r
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s \r
+ DCD CAN1_TX_IRQHandler ; CAN1 TX \r
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0 \r
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1 \r
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE \r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s \r
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 \r
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 \r
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare \r
+ DCD TIM2_IRQHandler ; TIM2 \r
+ DCD TIM3_IRQHandler ; TIM3 \r
+ DCD TIM4_IRQHandler ; TIM4 \r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event \r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error \r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event \r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error \r
+ DCD SPI1_IRQHandler ; SPI1 \r
+ DCD SPI2_IRQHandler ; SPI2 \r
+ DCD USART1_IRQHandler ; USART1 \r
+ DCD USART2_IRQHandler ; USART2 \r
+ DCD USART3_IRQHandler ; USART3 \r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s \r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line \r
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line \r
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 \r
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 \r
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare \r
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 \r
+ DCD FMC_IRQHandler ; FMC \r
+ DCD SDMMC1_IRQHandler ; SDMMC1 \r
+ DCD TIM5_IRQHandler ; TIM5 \r
+ DCD SPI3_IRQHandler ; SPI3 \r
+ DCD UART4_IRQHandler ; UART4 \r
+ DCD UART5_IRQHandler ; UART5 \r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors \r
+ DCD TIM7_IRQHandler ; TIM7 \r
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 \r
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 \r
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 \r
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 \r
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 \r
+ DCD ETH_IRQHandler ; Ethernet \r
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line \r
+ DCD CAN2_TX_IRQHandler ; CAN2 TX \r
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0 \r
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1 \r
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE \r
+ DCD OTG_FS_IRQHandler ; USB OTG FS \r
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 \r
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 \r
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 \r
+ DCD USART6_IRQHandler ; USART6 \r
+ DCD I2C3_EV_IRQHandler ; I2C3 event \r
+ DCD I2C3_ER_IRQHandler ; I2C3 error \r
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out \r
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In \r
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI \r
+ DCD OTG_HS_IRQHandler ; USB OTG HS \r
+ DCD DCMI_IRQHandler ; DCMI \r
+ DCD CRYP_IRQHandler ; CRYP crypto \r
+ DCD HASH_RNG_IRQHandler ; Hash and Rng\r
+ DCD FPU_IRQHandler ; FPU\r
+ DCD UART7_IRQHandler ; UART7\r
+ DCD UART8_IRQHandler ; UART8\r
+ DCD SPI4_IRQHandler ; SPI4\r
+ DCD SPI5_IRQHandler ; SPI5\r
+ DCD SPI6_IRQHandler ; SPI6\r
+ DCD SAI1_IRQHandler ; SAI1\r
+ DCD LTDC_IRQHandler ; LTDC\r
+ DCD LTDC_ER_IRQHandler ; LTDC error\r
+ DCD DMA2D_IRQHandler ; DMA2D\r
+ DCD SAI2_IRQHandler ; SAI2\r
+ DCD QUADSPI_IRQHandler ; QUADSPI\r
+ DCD LPTIM1_IRQHandler ; LPTIM1\r
+ DCD CEC_IRQHandler ; HDMI_CEC\r
+ DCD I2C4_EV_IRQHandler ; I2C4 Event \r
+ DCD I2C4_ER_IRQHandler ; I2C4 Error \r
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(2)\r
+Reset_Handler\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+ PUBWEAK MemManage_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+MemManage_Handler\r
+ B MemManage_Handler\r
+\r
+ PUBWEAK BusFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+BusFault_Handler\r
+ B BusFault_Handler\r
+\r
+ PUBWEAK UsageFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UsageFault_Handler\r
+ B UsageFault_Handler\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+ PUBWEAK DebugMon_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DebugMon_Handler\r
+ B DebugMon_Handler\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler \r
+ B WWDG_IRQHandler\r
+\r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_IRQHandler \r
+ B PVD_IRQHandler\r
+\r
+ PUBWEAK TAMP_STAMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TAMP_STAMP_IRQHandler \r
+ B TAMP_STAMP_IRQHandler\r
+\r
+ PUBWEAK RTC_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+RTC_WKUP_IRQHandler \r
+ B RTC_WKUP_IRQHandler\r
+\r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler \r
+ B FLASH_IRQHandler\r
+\r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler \r
+ B RCC_IRQHandler\r
+\r
+ PUBWEAK EXTI0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_IRQHandler \r
+ B EXTI0_IRQHandler\r
+\r
+ PUBWEAK EXTI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI1_IRQHandler \r
+ B EXTI1_IRQHandler\r
+\r
+ PUBWEAK EXTI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_IRQHandler \r
+ B EXTI2_IRQHandler\r
+\r
+ PUBWEAK EXTI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI3_IRQHandler\r
+ B EXTI3_IRQHandler\r
+\r
+ PUBWEAK EXTI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI4_IRQHandler \r
+ B EXTI4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream0_IRQHandler \r
+ B DMA1_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream1_IRQHandler \r
+ B DMA1_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream2_IRQHandler \r
+ B DMA1_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream3_IRQHandler \r
+ B DMA1_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream4_IRQHandler \r
+ B DMA1_Stream4_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream5_IRQHandler \r
+ B DMA1_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream6_IRQHandler \r
+ B DMA1_Stream6_IRQHandler\r
+\r
+ PUBWEAK ADC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC_IRQHandler \r
+ B ADC_IRQHandler\r
+\r
+ PUBWEAK CAN1_TX_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN1_TX_IRQHandler \r
+ B CAN1_TX_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN1_RX0_IRQHandler \r
+ B CAN1_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN1_RX1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN1_RX1_IRQHandler \r
+ B CAN1_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN1_SCE_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN1_SCE_IRQHandler \r
+ B CAN1_SCE_IRQHandler\r
+\r
+ PUBWEAK EXTI9_5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI9_5_IRQHandler \r
+ B EXTI9_5_IRQHandler\r
+\r
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_BRK_TIM9_IRQHandler \r
+ B TIM1_BRK_TIM9_IRQHandler\r
+\r
+ PUBWEAK TIM1_UP_TIM10_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_UP_TIM10_IRQHandler \r
+ B TIM1_UP_TIM10_IRQHandler\r
+\r
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_TRG_COM_TIM11_IRQHandler \r
+ B TIM1_TRG_COM_TIM11_IRQHandler\r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM1_CC_IRQHandler \r
+ B TIM1_CC_IRQHandler\r
+\r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler \r
+ B TIM2_IRQHandler\r
+\r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler \r
+ B TIM3_IRQHandler\r
+\r
+ PUBWEAK TIM4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM4_IRQHandler \r
+ B TIM4_IRQHandler\r
+\r
+ PUBWEAK I2C1_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C1_EV_IRQHandler \r
+ B I2C1_EV_IRQHandler\r
+\r
+ PUBWEAK I2C1_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C1_ER_IRQHandler \r
+ B I2C1_ER_IRQHandler\r
+\r
+ PUBWEAK I2C2_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C2_EV_IRQHandler \r
+ B I2C2_EV_IRQHandler\r
+\r
+ PUBWEAK I2C2_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C2_ER_IRQHandler \r
+ B I2C2_ER_IRQHandler\r
+\r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler \r
+ B SPI1_IRQHandler\r
+\r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler \r
+ B SPI2_IRQHandler\r
+\r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler \r
+ B USART1_IRQHandler\r
+\r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler \r
+ B USART2_IRQHandler\r
+\r
+ PUBWEAK USART3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART3_IRQHandler \r
+ B USART3_IRQHandler\r
+\r
+ PUBWEAK EXTI15_10_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+EXTI15_10_IRQHandler \r
+ B EXTI15_10_IRQHandler\r
+\r
+ PUBWEAK RTC_Alarm_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+RTC_Alarm_IRQHandler \r
+ B RTC_Alarm_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_FS_WKUP_IRQHandler \r
+ B OTG_FS_WKUP_IRQHandler\r
+ \r
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_BRK_TIM12_IRQHandler \r
+ B TIM8_BRK_TIM12_IRQHandler\r
+\r
+ PUBWEAK TIM8_UP_TIM13_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_UP_TIM13_IRQHandler \r
+ B TIM8_UP_TIM13_IRQHandler\r
+\r
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_TRG_COM_TIM14_IRQHandler \r
+ B TIM8_TRG_COM_TIM14_IRQHandler\r
+\r
+ PUBWEAK TIM8_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM8_CC_IRQHandler \r
+ B TIM8_CC_IRQHandler\r
+\r
+ PUBWEAK DMA1_Stream7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA1_Stream7_IRQHandler \r
+ B DMA1_Stream7_IRQHandler\r
+\r
+ PUBWEAK FMC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FMC_IRQHandler \r
+ B FMC_IRQHandler\r
+\r
+ PUBWEAK SDMMC1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SDMMC1_IRQHandler \r
+ B SDMMC1_IRQHandler\r
+\r
+ PUBWEAK TIM5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM5_IRQHandler \r
+ B TIM5_IRQHandler\r
+\r
+ PUBWEAK SPI3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI3_IRQHandler \r
+ B SPI3_IRQHandler\r
+\r
+ PUBWEAK UART4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART4_IRQHandler \r
+ B UART4_IRQHandler\r
+\r
+ PUBWEAK UART5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+UART5_IRQHandler \r
+ B UART5_IRQHandler\r
+\r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM6_DAC_IRQHandler \r
+ B TIM6_DAC_IRQHandler\r
+\r
+ PUBWEAK TIM7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+TIM7_IRQHandler \r
+ B TIM7_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream0_IRQHandler \r
+ B DMA2_Stream0_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream1_IRQHandler \r
+ B DMA2_Stream1_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream2_IRQHandler \r
+ B DMA2_Stream2_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream3_IRQHandler \r
+ B DMA2_Stream3_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream4_IRQHandler \r
+ B DMA2_Stream4_IRQHandler\r
+\r
+ PUBWEAK ETH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ETH_IRQHandler \r
+ B ETH_IRQHandler\r
+\r
+ PUBWEAK ETH_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+ETH_WKUP_IRQHandler \r
+ B ETH_WKUP_IRQHandler\r
+\r
+ PUBWEAK CAN2_TX_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN2_TX_IRQHandler \r
+ B CAN2_TX_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX0_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN2_RX0_IRQHandler \r
+ B CAN2_RX0_IRQHandler\r
+\r
+ PUBWEAK CAN2_RX1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN2_RX1_IRQHandler \r
+ B CAN2_RX1_IRQHandler\r
+\r
+ PUBWEAK CAN2_SCE_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CAN2_SCE_IRQHandler \r
+ B CAN2_SCE_IRQHandler\r
+\r
+ PUBWEAK OTG_FS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_FS_IRQHandler \r
+ B OTG_FS_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream5_IRQHandler \r
+ B DMA2_Stream5_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream6_IRQHandler \r
+ B DMA2_Stream6_IRQHandler\r
+\r
+ PUBWEAK DMA2_Stream7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2_Stream7_IRQHandler \r
+ B DMA2_Stream7_IRQHandler\r
+\r
+ PUBWEAK USART6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART6_IRQHandler \r
+ B USART6_IRQHandler\r
+\r
+ PUBWEAK I2C3_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C3_EV_IRQHandler \r
+ B I2C3_EV_IRQHandler\r
+\r
+ PUBWEAK I2C3_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C3_ER_IRQHandler \r
+ B I2C3_ER_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_HS_EP1_OUT_IRQHandler \r
+ B OTG_HS_EP1_OUT_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_HS_EP1_IN_IRQHandler \r
+ B OTG_HS_EP1_IN_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_WKUP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+OTG_HS_WKUP_IRQHandler \r
+ B OTG_HS_WKUP_IRQHandler\r
+\r
+ PUBWEAK OTG_HS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+OTG_HS_IRQHandler \r
+ B OTG_HS_IRQHandler\r
+\r
+ PUBWEAK DCMI_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DCMI_IRQHandler \r
+ B DCMI_IRQHandler\r
+\r
+ PUBWEAK CRYP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CRYP_IRQHandler \r
+ B CRYP_IRQHandler\r
+\r
+ PUBWEAK HASH_RNG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+HASH_RNG_IRQHandler \r
+ B HASH_RNG_IRQHandler\r
+\r
+ PUBWEAK FPU_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+FPU_IRQHandler \r
+ B FPU_IRQHandler\r
+\r
+ PUBWEAK UART7_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+UART7_IRQHandler \r
+ B UART7_IRQHandler \r
+\r
+ PUBWEAK UART8_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+UART8_IRQHandler \r
+ B UART8_IRQHandler\r
+ \r
+ PUBWEAK SPI4_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI4_IRQHandler\r
+ B SPI4_IRQHandler \r
+\r
+ PUBWEAK SPI5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI5_IRQHandler \r
+ B SPI5_IRQHandler \r
+\r
+ PUBWEAK SPI6_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPI6_IRQHandler \r
+ B SPI6_IRQHandler \r
+\r
+ PUBWEAK SAI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI1_IRQHandler \r
+ B SAI1_IRQHandler \r
+\r
+ PUBWEAK LTDC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LTDC_IRQHandler \r
+ B LTDC_IRQHandler \r
+\r
+ PUBWEAK LTDC_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LTDC_ER_IRQHandler \r
+ B LTDC_ER_IRQHandler \r
+\r
+ PUBWEAK DMA2D_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+DMA2D_IRQHandler \r
+ B DMA2D_IRQHandler \r
+\r
+ PUBWEAK SAI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SAI2_IRQHandler \r
+ B SAI2_IRQHandler \r
+\r
+ PUBWEAK QUADSPI_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+QUADSPI_IRQHandler \r
+ B QUADSPI_IRQHandler \r
+ \r
+ PUBWEAK LPTIM1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+LPTIM1_IRQHandler \r
+ B LPTIM1_IRQHandler \r
+ \r
+ PUBWEAK CEC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+CEC_IRQHandler \r
+ B CEC_IRQHandler \r
+\r
+ PUBWEAK I2C4_EV_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C4_EV_IRQHandler \r
+ B I2C4_EV_IRQHandler \r
+ \r
+ PUBWEAK I2C4_ER_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+I2C4_ER_IRQHandler \r
+ B I2C4_ER_IRQHandler \r
+ \r
+ PUBWEAK SPDIF_RX_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1) \r
+SPDIF_RX_IRQHandler \r
+ B SPDIF_RX_IRQHandler \r
+ END\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_msp_template.c\r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief HAL MSP module.\r
+ * This file template is located in the HAL folder and should be copied \r
+ * to the user folder.\r
+ * \r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ This file is generated automatically by MicroXplorer and eventually modified \r
+ by the user\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_MSP\r
+ * @brief HAL MSP module.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_MSP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the Global MSP.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the Global MSP.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the PPP MSP.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the PPP MSP.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Template/stm32f7xx_it.c \r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief Main Interrupt Service Routines.\r
+ * This file provides template for all exceptions handler and \r
+ * peripherals interrupt service routine.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_it.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Examples\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup Templates\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M7 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SVCall exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles PendSVC exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles SysTick Handler.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SysTick_Handler(void)\r
+{\r
+}\r
+ \r
+\r
+/******************************************************************************/\r
+/* STM32F7xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32f7xx.s). */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles PPP interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Template/stm32f7xx_it.h \r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_IT_H\r
+#define __STM32F7xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f7xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F7xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f7xx.h"\r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted\r
+ on EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */ \r
+/* #define DATA_IN_ExtSDRAM */\r
+\r
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)\r
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " \r
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 16000000;\r
+ __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f7xx.s before jump to main.\r
+ * This function configures the external memories (SRAM/SDRAM)\r
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+#if defined (DATA_IN_ExtSDRAM)\r
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;\r
+ register uint32_t index;\r
+\r
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \r
+ clock */\r
+ RCC->AHB1ENR |= 0x000001F8;\r
+ \r
+ /* Connect PDx pins to FMC Alternate function */\r
+ GPIOD->AFR[0] = 0x000000CC;\r
+ GPIOD->AFR[1] = 0xCC000CCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xA02A000A;\r
+ /* Configure PDx pins speed to 50 MHz */ \r
+ GPIOD->OSPEEDR = 0xA02A000A;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x50150005;\r
+\r
+ /* Connect PEx pins to FMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00000CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAA800A;\r
+ /* Configure PEx pins speed to 50 MHz */ \r
+ GPIOE->OSPEEDR = 0xAAAA800A;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x55554005;\r
+\r
+ /* Connect PFx pins to FMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCCC000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAA800AAA;\r
+ /* Configure PFx pins speed to 50 MHz */ \r
+ GPIOF->OSPEEDR = 0xAA800AAA;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x55400555;\r
+\r
+ /* Connect PGx pins to FMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CC00CC;\r
+ GPIOG->AFR[1] = 0xC000000C;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x80020A0A;\r
+ /* Configure PGx pins speed to 50 MHz */ \r
+ GPIOG->OSPEEDR = 0x80020A0A;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x40010505;\r
+ \r
+ /* Connect PHx pins to FMC Alternate function */\r
+ GPIOH->AFR[0] = 0x00C0CC00;\r
+ GPIOH->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PHx pins in Alternate function mode */ \r
+ GPIOH->MODER = 0xAAAA08A0;\r
+ /* Configure PHx pins speed to 50 MHz */ \r
+ GPIOH->OSPEEDR = 0xAAAA08A0;\r
+ /* Configure PHx pins Output type to push-pull */ \r
+ GPIOH->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PHx pins */ \r
+ GPIOH->PUPDR = 0x55550450;\r
+ \r
+ /* Connect PIx pins to FMC Alternate function */\r
+ GPIOI->AFR[0] = 0xCCCCCCCC;\r
+ GPIOI->AFR[1] = 0x00000CC0;\r
+ /* Configure PIx pins in Alternate function mode */ \r
+ GPIOI->MODER = 0x0028AAAA;\r
+ /* Configure PIx pins speed to 50 MHz */ \r
+ GPIOI->OSPEEDR = 0x0028AAAA;\r
+ /* Configure PIx pins Output type to push-pull */ \r
+ GPIOI->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PIx pins */ \r
+ GPIOI->PUPDR = 0x00145555;\r
+ \r
+/*-- FMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FMC interface clock */\r
+ RCC->AHB3ENR |= 0x00000001;\r
+ \r
+ /* Configure and enable SDRAM bank1 */\r
+ FMC_Bank5_6->SDCR[0] = 0x000019E5;\r
+ FMC_Bank5_6->SDTR[0] = 0x01116361; \r
+ \r
+ /* SDRAM initialization sequence */\r
+ /* Clock enable command */\r
+ FMC_Bank5_6->SDCMR = 0x00000011; \r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+\r
+ /* Delay */\r
+ for (index = 0; index<1000; index++);\r
+ \r
+ /* PALL command */\r
+ FMC_Bank5_6->SDCMR = 0x00000012; \r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+ \r
+ /* Auto refresh command */\r
+ FMC_Bank5_6->SDCMR = 0x000000F3;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+ \r
+ /* MRD register program */\r
+ FMC_Bank5_6->SDCMR = 0x00046014;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ } \r
+ \r
+ /* Set refresh count */\r
+ tmpreg = FMC_Bank5_6->SDRTR;\r
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));\r
+ \r
+ /* Disable write protection */\r
+ tmpreg = FMC_Bank5_6->SDCR[0]; \r
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\r
+#endif /* DATA_IN_ExtSDRAM */\r
+\r
+#if defined(DATA_IN_ExtSRAM)\r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR |= 0x00000078;\r
+ \r
+ /* Connect PDx pins to FMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00CCC0CC;\r
+ GPIOD->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xAAAA0A8A;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xFFFF0FCF;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x55550545;\r
+\r
+ /* Connect PEx pins to FMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00CC0CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAA828A;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xFFFFC3CF;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x55554145;\r
+\r
+ /* Connect PFx pins to FMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCC0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAA000AAA;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xFF000FFF;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x55000555;\r
+\r
+ /* Connect PGx pins to FMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CCCCCC;\r
+ GPIOG->AFR[1] = 0x000000C0;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00200AAA;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0x00300FFF;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00100555;\r
+ \r
+/*-- FMC/FSMC Configuration --------------------------------------------------*/ \r
+ /* Enable the FMC/FSMC interface clock */\r
+ RCC->AHB3ENR |= 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FMC_Bank1->BTCR[4] = 0x00001091;\r
+ FMC_Bank1->BTCR[5] = 0x00110212;\r
+ FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; \r
+\r
+#endif /* DATA_IN_ExtSRAM */\r
+}\r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************\r
+;* File Name : startup_stm32f756xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V0.3.0\r
+;* Date : 06-March-2015\r
+;* Description : STM32F756xx devices vector table for MDK-ARM toolchain. \r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == Reset_Handler\r
+;* - Set the vector table entries with the exceptions ISR address\r
+;* - Branches to __main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the CortexM7 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;* <<< Use Configuration Wizard in Context Menu >>> \r
+;*******************************************************************************\r
+; \r
+;* Redistribution and use in source and binary forms, with or without modification,\r
+;* are permitted provided that the following conditions are met:\r
+;* 1. Redistributions of source code must retain the above copyright notice,\r
+;* this list of conditions and the following disclaimer.\r
+;* 2. Redistributions in binary form must reproduce the above copyright notice,\r
+;* this list of conditions and the following disclaimer in the documentation\r
+;* and/or other materials provided with the distribution.\r
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+;* may be used to endorse or promote products derived from this software\r
+;* without specific prior written permission.\r
+;*\r
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+; \r
+;*******************************************************************************\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000200\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window WatchDog \r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection \r
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line \r
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line \r
+ DCD FLASH_IRQHandler ; FLASH \r
+ DCD RCC_IRQHandler ; RCC \r
+ DCD EXTI0_IRQHandler ; EXTI Line0 \r
+ DCD EXTI1_IRQHandler ; EXTI Line1 \r
+ DCD EXTI2_IRQHandler ; EXTI Line2 \r
+ DCD EXTI3_IRQHandler ; EXTI Line3 \r
+ DCD EXTI4_IRQHandler ; EXTI Line4 \r
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 \r
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 \r
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 \r
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 \r
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 \r
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 \r
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 \r
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s \r
+ DCD CAN1_TX_IRQHandler ; CAN1 TX \r
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0 \r
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1 \r
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE \r
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s \r
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 \r
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 \r
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare \r
+ DCD TIM2_IRQHandler ; TIM2 \r
+ DCD TIM3_IRQHandler ; TIM3 \r
+ DCD TIM4_IRQHandler ; TIM4 \r
+ DCD I2C1_EV_IRQHandler ; I2C1 Event \r
+ DCD I2C1_ER_IRQHandler ; I2C1 Error \r
+ DCD I2C2_EV_IRQHandler ; I2C2 Event \r
+ DCD I2C2_ER_IRQHandler ; I2C2 Error \r
+ DCD SPI1_IRQHandler ; SPI1 \r
+ DCD SPI2_IRQHandler ; SPI2 \r
+ DCD USART1_IRQHandler ; USART1 \r
+ DCD USART2_IRQHandler ; USART2 \r
+ DCD USART3_IRQHandler ; USART3 \r
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s \r
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line \r
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line \r
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 \r
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 \r
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14\r
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare \r
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 \r
+ DCD FMC_IRQHandler ; FMC \r
+ DCD SDMMC1_IRQHandler ; SDMMC1 \r
+ DCD TIM5_IRQHandler ; TIM5 \r
+ DCD SPI3_IRQHandler ; SPI3 \r
+ DCD UART4_IRQHandler ; UART4 \r
+ DCD UART5_IRQHandler ; UART5 \r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors \r
+ DCD TIM7_IRQHandler ; TIM7 \r
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 \r
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 \r
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 \r
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 \r
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 \r
+ DCD ETH_IRQHandler ; Ethernet \r
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line \r
+ DCD CAN2_TX_IRQHandler ; CAN2 TX \r
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0 \r
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1 \r
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE \r
+ DCD OTG_FS_IRQHandler ; USB OTG FS \r
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 \r
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 \r
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 \r
+ DCD USART6_IRQHandler ; USART6 \r
+ DCD I2C3_EV_IRQHandler ; I2C3 event \r
+ DCD I2C3_ER_IRQHandler ; I2C3 error \r
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out \r
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In \r
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI \r
+ DCD OTG_HS_IRQHandler ; USB OTG HS \r
+ DCD DCMI_IRQHandler ; DCMI \r
+ DCD CRYP_IRQHandler ; CRYP crypto \r
+ DCD HASH_RNG_IRQHandler ; Hash and Rng\r
+ DCD FPU_IRQHandler ; FPU\r
+ DCD UART7_IRQHandler ; UART7\r
+ DCD UART8_IRQHandler ; UART8\r
+ DCD SPI4_IRQHandler ; SPI4\r
+ DCD SPI5_IRQHandler ; SPI5\r
+ DCD SPI6_IRQHandler ; SPI6\r
+ DCD SAI1_IRQHandler ; SAI1\r
+ DCD LTDC_IRQHandler ; LTDC\r
+ DCD LTDC_ER_IRQHandler ; LTDC error\r
+ DCD DMA2D_IRQHandler ; DMA2D\r
+ DCD SAI2_IRQHandler ; SAI2\r
+ DCD QUADSPI_IRQHandler ; QUADSPI\r
+ DCD LPTIM1_IRQHandler ; LPTIM1\r
+ DCD CEC_IRQHandler ; HDMI_CEC\r
+ DCD I2C4_EV_IRQHandler ; I2C4 Event \r
+ DCD I2C4_ER_IRQHandler ; I2C4 Error \r
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+; Reset handler\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT WWDG_IRQHandler [WEAK] \r
+ EXPORT PVD_IRQHandler [WEAK] \r
+ EXPORT TAMP_STAMP_IRQHandler [WEAK] \r
+ EXPORT RTC_WKUP_IRQHandler [WEAK] \r
+ EXPORT FLASH_IRQHandler [WEAK] \r
+ EXPORT RCC_IRQHandler [WEAK] \r
+ EXPORT EXTI0_IRQHandler [WEAK] \r
+ EXPORT EXTI1_IRQHandler [WEAK] \r
+ EXPORT EXTI2_IRQHandler [WEAK] \r
+ EXPORT EXTI3_IRQHandler [WEAK] \r
+ EXPORT EXTI4_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream0_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream1_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream2_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream3_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream4_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream5_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream6_IRQHandler [WEAK] \r
+ EXPORT ADC_IRQHandler [WEAK] \r
+ EXPORT CAN1_TX_IRQHandler [WEAK] \r
+ EXPORT CAN1_RX0_IRQHandler [WEAK] \r
+ EXPORT CAN1_RX1_IRQHandler [WEAK] \r
+ EXPORT CAN1_SCE_IRQHandler [WEAK] \r
+ EXPORT EXTI9_5_IRQHandler [WEAK] \r
+ EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] \r
+ EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] \r
+ EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] \r
+ EXPORT TIM1_CC_IRQHandler [WEAK] \r
+ EXPORT TIM2_IRQHandler [WEAK] \r
+ EXPORT TIM3_IRQHandler [WEAK] \r
+ EXPORT TIM4_IRQHandler [WEAK] \r
+ EXPORT I2C1_EV_IRQHandler [WEAK] \r
+ EXPORT I2C1_ER_IRQHandler [WEAK] \r
+ EXPORT I2C2_EV_IRQHandler [WEAK] \r
+ EXPORT I2C2_ER_IRQHandler [WEAK] \r
+ EXPORT SPI1_IRQHandler [WEAK] \r
+ EXPORT SPI2_IRQHandler [WEAK] \r
+ EXPORT USART1_IRQHandler [WEAK] \r
+ EXPORT USART2_IRQHandler [WEAK] \r
+ EXPORT USART3_IRQHandler [WEAK] \r
+ EXPORT EXTI15_10_IRQHandler [WEAK] \r
+ EXPORT RTC_Alarm_IRQHandler [WEAK] \r
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK] \r
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] \r
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] \r
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] \r
+ EXPORT TIM8_CC_IRQHandler [WEAK] \r
+ EXPORT DMA1_Stream7_IRQHandler [WEAK] \r
+ EXPORT FMC_IRQHandler [WEAK] \r
+ EXPORT SDMMC1_IRQHandler [WEAK] \r
+ EXPORT TIM5_IRQHandler [WEAK] \r
+ EXPORT SPI3_IRQHandler [WEAK] \r
+ EXPORT UART4_IRQHandler [WEAK] \r
+ EXPORT UART5_IRQHandler [WEAK] \r
+ EXPORT TIM6_DAC_IRQHandler [WEAK] \r
+ EXPORT TIM7_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream0_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream1_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream2_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream3_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream4_IRQHandler [WEAK] \r
+ EXPORT ETH_IRQHandler [WEAK] \r
+ EXPORT ETH_WKUP_IRQHandler [WEAK] \r
+ EXPORT CAN2_TX_IRQHandler [WEAK] \r
+ EXPORT CAN2_RX0_IRQHandler [WEAK] \r
+ EXPORT CAN2_RX1_IRQHandler [WEAK] \r
+ EXPORT CAN2_SCE_IRQHandler [WEAK] \r
+ EXPORT OTG_FS_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream5_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream6_IRQHandler [WEAK] \r
+ EXPORT DMA2_Stream7_IRQHandler [WEAK] \r
+ EXPORT USART6_IRQHandler [WEAK] \r
+ EXPORT I2C3_EV_IRQHandler [WEAK] \r
+ EXPORT I2C3_ER_IRQHandler [WEAK] \r
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] \r
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] \r
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK] \r
+ EXPORT OTG_HS_IRQHandler [WEAK] \r
+ EXPORT DCMI_IRQHandler [WEAK] \r
+ EXPORT CRYP_IRQHandler [WEAK] \r
+ EXPORT HASH_RNG_IRQHandler [WEAK]\r
+ EXPORT FPU_IRQHandler [WEAK]\r
+ EXPORT UART7_IRQHandler [WEAK]\r
+ EXPORT UART8_IRQHandler [WEAK]\r
+ EXPORT SPI4_IRQHandler [WEAK]\r
+ EXPORT SPI5_IRQHandler [WEAK]\r
+ EXPORT SPI6_IRQHandler [WEAK]\r
+ EXPORT SAI1_IRQHandler [WEAK]\r
+ EXPORT LTDC_IRQHandler [WEAK]\r
+ EXPORT LTDC_ER_IRQHandler [WEAK]\r
+ EXPORT DMA2D_IRQHandler [WEAK]\r
+ EXPORT SAI2_IRQHandler [WEAK] \r
+ EXPORT QUADSPI_IRQHandler [WEAK]\r
+ EXPORT LPTIM1_IRQHandler [WEAK]\r
+ EXPORT CEC_IRQHandler [WEAK] \r
+ EXPORT I2C4_EV_IRQHandler [WEAK]\r
+ EXPORT I2C4_ER_IRQHandler [WEAK] \r
+ EXPORT SPDIF_RX_IRQHandler [WEAK]\r
+ \r
+WWDG_IRQHandler \r
+PVD_IRQHandler \r
+TAMP_STAMP_IRQHandler \r
+RTC_WKUP_IRQHandler \r
+FLASH_IRQHandler \r
+RCC_IRQHandler \r
+EXTI0_IRQHandler \r
+EXTI1_IRQHandler \r
+EXTI2_IRQHandler \r
+EXTI3_IRQHandler \r
+EXTI4_IRQHandler \r
+DMA1_Stream0_IRQHandler \r
+DMA1_Stream1_IRQHandler \r
+DMA1_Stream2_IRQHandler \r
+DMA1_Stream3_IRQHandler \r
+DMA1_Stream4_IRQHandler \r
+DMA1_Stream5_IRQHandler \r
+DMA1_Stream6_IRQHandler \r
+ADC_IRQHandler \r
+CAN1_TX_IRQHandler \r
+CAN1_RX0_IRQHandler \r
+CAN1_RX1_IRQHandler \r
+CAN1_SCE_IRQHandler \r
+EXTI9_5_IRQHandler \r
+TIM1_BRK_TIM9_IRQHandler \r
+TIM1_UP_TIM10_IRQHandler \r
+TIM1_TRG_COM_TIM11_IRQHandler \r
+TIM1_CC_IRQHandler \r
+TIM2_IRQHandler \r
+TIM3_IRQHandler \r
+TIM4_IRQHandler \r
+I2C1_EV_IRQHandler \r
+I2C1_ER_IRQHandler \r
+I2C2_EV_IRQHandler \r
+I2C2_ER_IRQHandler \r
+SPI1_IRQHandler \r
+SPI2_IRQHandler \r
+USART1_IRQHandler \r
+USART2_IRQHandler \r
+USART3_IRQHandler \r
+EXTI15_10_IRQHandler \r
+RTC_Alarm_IRQHandler \r
+OTG_FS_WKUP_IRQHandler \r
+TIM8_BRK_TIM12_IRQHandler \r
+TIM8_UP_TIM13_IRQHandler \r
+TIM8_TRG_COM_TIM14_IRQHandler \r
+TIM8_CC_IRQHandler \r
+DMA1_Stream7_IRQHandler \r
+FMC_IRQHandler \r
+SDMMC1_IRQHandler \r
+TIM5_IRQHandler \r
+SPI3_IRQHandler \r
+UART4_IRQHandler \r
+UART5_IRQHandler \r
+TIM6_DAC_IRQHandler \r
+TIM7_IRQHandler \r
+DMA2_Stream0_IRQHandler \r
+DMA2_Stream1_IRQHandler \r
+DMA2_Stream2_IRQHandler \r
+DMA2_Stream3_IRQHandler \r
+DMA2_Stream4_IRQHandler \r
+ETH_IRQHandler \r
+ETH_WKUP_IRQHandler \r
+CAN2_TX_IRQHandler \r
+CAN2_RX0_IRQHandler \r
+CAN2_RX1_IRQHandler \r
+CAN2_SCE_IRQHandler \r
+OTG_FS_IRQHandler \r
+DMA2_Stream5_IRQHandler \r
+DMA2_Stream6_IRQHandler \r
+DMA2_Stream7_IRQHandler \r
+USART6_IRQHandler \r
+I2C3_EV_IRQHandler \r
+I2C3_ER_IRQHandler \r
+OTG_HS_EP1_OUT_IRQHandler \r
+OTG_HS_EP1_IN_IRQHandler \r
+OTG_HS_WKUP_IRQHandler \r
+OTG_HS_IRQHandler \r
+DCMI_IRQHandler \r
+CRYP_IRQHandler \r
+HASH_RNG_IRQHandler\r
+FPU_IRQHandler \r
+UART7_IRQHandler \r
+UART8_IRQHandler \r
+SPI4_IRQHandler \r
+SPI5_IRQHandler \r
+SPI6_IRQHandler \r
+SAI1_IRQHandler \r
+LTDC_IRQHandler \r
+LTDC_ER_IRQHandler \r
+DMA2D_IRQHandler \r
+SAI2_IRQHandler \r
+QUADSPI_IRQHandler\r
+LPTIM1_IRQHandler\r
+CEC_IRQHandler\r
+I2C4_EV_IRQHandler\r
+I2C4_ER_IRQHandler\r
+SPDIF_RX_IRQHandler\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+ \r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_msp_template.c\r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief HAL MSP module.\r
+ * This file template is located in the HAL folder and should be copied \r
+ * to the user folder.\r
+ * \r
+ @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ This file is generated automatically by MicroXplorer and eventually modified \r
+ by the user\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_MSP\r
+ * @brief HAL MSP module.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_MSP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the Global MSP.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the Global MSP.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the PPP MSP.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the PPP MSP.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void HAL_PPP_MspDeInit(void)\r
+{\r
+ /* NOTE : This function is generated automatically by MicroXplorer and eventually \r
+ modified by the user\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Template/stm32f7xx_it.c \r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief Main Interrupt Service Routines.\r
+ * This file provides template for all exceptions handler and \r
+ * peripherals interrupt service routine.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_it.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Examples\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup Templates\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/* Cortex-M7 Processor Exceptions Handlers */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles NMI exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Hard Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory Manage exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* Go to infinite loop when Memory Manage exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Bus Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Bus Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Usage Fault exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* Go to infinite loop when Usage Fault exception occurs */\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SVCall exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug Monitor exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles PendSVC exception.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+ * @brief This function handles SysTick Handler.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+__weak void SysTick_Handler(void)\r
+{\r
+}\r
+ \r
+\r
+/******************************************************************************/\r
+/* STM32F7xx Peripherals Interrupt Handlers */\r
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */\r
+/* available peripheral interrupt handler's name please refer to the startup */\r
+/* file (startup_stm32f7xx.s). */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief This function handles PPP interrupt request.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Template/stm32f7xx_it.h \r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_IT_H\r
+#define __STM32F7xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.c\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f7xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F7xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f7xx.h"\r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted\r
+ on EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */ \r
+/* #define DATA_IN_ExtSDRAM */\r
+\r
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)\r
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " \r
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 16000000;\r
+ __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f7xx.s before jump to main.\r
+ * This function configures the external memories (SRAM/SDRAM)\r
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+#if defined (DATA_IN_ExtSDRAM)\r
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;\r
+ register uint32_t index;\r
+\r
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \r
+ clock */\r
+ RCC->AHB1ENR |= 0x000001F8;\r
+ \r
+ /* Connect PDx pins to FMC Alternate function */\r
+ GPIOD->AFR[0] = 0x000000CC;\r
+ GPIOD->AFR[1] = 0xCC000CCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xA02A000A;\r
+ /* Configure PDx pins speed to 50 MHz */ \r
+ GPIOD->OSPEEDR = 0xA02A000A;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x50150005;\r
+\r
+ /* Connect PEx pins to FMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00000CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAA800A;\r
+ /* Configure PEx pins speed to 50 MHz */ \r
+ GPIOE->OSPEEDR = 0xAAAA800A;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x55554005;\r
+\r
+ /* Connect PFx pins to FMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCCC000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAA800AAA;\r
+ /* Configure PFx pins speed to 50 MHz */ \r
+ GPIOF->OSPEEDR = 0xAA800AAA;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x55400555;\r
+\r
+ /* Connect PGx pins to FMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CC00CC;\r
+ GPIOG->AFR[1] = 0xC000000C;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x80020A0A;\r
+ /* Configure PGx pins speed to 50 MHz */ \r
+ GPIOG->OSPEEDR = 0x80020A0A;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x40010505;\r
+ \r
+ /* Connect PHx pins to FMC Alternate function */\r
+ GPIOH->AFR[0] = 0x00C0CC00;\r
+ GPIOH->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PHx pins in Alternate function mode */ \r
+ GPIOH->MODER = 0xAAAA08A0;\r
+ /* Configure PHx pins speed to 50 MHz */ \r
+ GPIOH->OSPEEDR = 0xAAAA08A0;\r
+ /* Configure PHx pins Output type to push-pull */ \r
+ GPIOH->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PHx pins */ \r
+ GPIOH->PUPDR = 0x55550450;\r
+ \r
+ /* Connect PIx pins to FMC Alternate function */\r
+ GPIOI->AFR[0] = 0xCCCCCCCC;\r
+ GPIOI->AFR[1] = 0x00000CC0;\r
+ /* Configure PIx pins in Alternate function mode */ \r
+ GPIOI->MODER = 0x0028AAAA;\r
+ /* Configure PIx pins speed to 50 MHz */ \r
+ GPIOI->OSPEEDR = 0x0028AAAA;\r
+ /* Configure PIx pins Output type to push-pull */ \r
+ GPIOI->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PIx pins */ \r
+ GPIOI->PUPDR = 0x00145555;\r
+ \r
+/*-- FMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FMC interface clock */\r
+ RCC->AHB3ENR |= 0x00000001;\r
+ \r
+ /* Configure and enable SDRAM bank1 */\r
+ FMC_Bank5_6->SDCR[0] = 0x000019E5;\r
+ FMC_Bank5_6->SDTR[0] = 0x01116361; \r
+ \r
+ /* SDRAM initialization sequence */\r
+ /* Clock enable command */\r
+ FMC_Bank5_6->SDCMR = 0x00000011; \r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+\r
+ /* Delay */\r
+ for (index = 0; index<1000; index++);\r
+ \r
+ /* PALL command */\r
+ FMC_Bank5_6->SDCMR = 0x00000012; \r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+ \r
+ /* Auto refresh command */\r
+ FMC_Bank5_6->SDCMR = 0x000000F3;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ }\r
+ \r
+ /* MRD register program */\r
+ FMC_Bank5_6->SDCMR = 0x00046014;\r
+ timeout = 0xFFFF;\r
+ while((tmpreg != 0) && (timeout-- > 0))\r
+ {\r
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
+ } \r
+ \r
+ /* Set refresh count */\r
+ tmpreg = FMC_Bank5_6->SDRTR;\r
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));\r
+ \r
+ /* Disable write protection */\r
+ tmpreg = FMC_Bank5_6->SDCR[0]; \r
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\r
+#endif /* DATA_IN_ExtSDRAM */\r
+\r
+#if defined(DATA_IN_ExtSRAM)\r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR |= 0x00000078;\r
+ \r
+ /* Connect PDx pins to FMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00CCC0CC;\r
+ GPIOD->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xAAAA0A8A;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xFFFF0FCF;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x55550545;\r
+\r
+ /* Connect PEx pins to FMC Alternate function */\r
+ GPIOE->AFR[0] = 0xC00CC0CC;\r
+ GPIOE->AFR[1] = 0xCCCCCCCC;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xAAAA828A;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xFFFFC3CF;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x55554145;\r
+\r
+ /* Connect PFx pins to FMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00CCCCCC;\r
+ GPIOF->AFR[1] = 0xCCCC0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xAA000AAA;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xFF000FFF;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x55000555;\r
+\r
+ /* Connect PGx pins to FMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00CCCCCC;\r
+ GPIOG->AFR[1] = 0x000000C0;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00200AAA;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0x00300FFF;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00100555;\r
+ \r
+/*-- FMC/FSMC Configuration --------------------------------------------------*/ \r
+ /* Enable the FMC/FSMC interface clock */\r
+ RCC->AHB3ENR |= 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FMC_Bank1->BTCR[4] = 0x00001091;\r
+ FMC_Bank1->BTCR[5] = 0x00110212;\r
+ FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; \r
+\r
+#endif /* DATA_IN_ExtSRAM */\r
+}\r
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and standard FreeRTOS hook functions.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes - these are needed here as the tick hook function is\r
+defined in this file. */\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "QueueSet.h"\r
+#include "TaskNotify.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configure the system clock for maximum speed.\r
+ */\r
+static void prvSystemClockConfig( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+GPIO_InitTypeDef GPIO_InitStruct;\r
+\r
+ /* Configure Flash prefetch and Instruction cache through ART accelerator. */\r
+ #if( ART_ACCLERATOR_ENABLE != 0 )\r
+ {\r
+ __HAL_FLASH_ART_ENABLE();\r
+ }\r
+ #endif /* ART_ACCLERATOR_ENABLE */\r
+\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping( NVIC_PRIORITYGROUP_4 );\r
+\r
+ /* Init the low level hardware. */\r
+ HAL_MspInit();\r
+\r
+ /* Configure the System clock to have a frequency of 200 MHz */\r
+ prvSystemClockConfig();\r
+\r
+ /* Enable GPIOB Clock (to be able to program the configuration\r
+ registers) and configure for LED output. */\r
+ __GPIOG_CLK_ENABLE();\r
+\r
+ GPIO_InitStruct.Pin = GPIO_PIN_6;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;\r
+ HAL_GPIO_Init( GPIOG, &GPIO_InitStruct );\r
+\r
+ /* MCO2 : Pin PC9 */\r
+ HAL_RCC_MCOConfig( RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSystemClockConfig( void )\r
+{\r
+ /* The system Clock is configured as follow :\r
+ System Clock source = PLL (HSE)\r
+ SYSCLK(Hz) = 200000000\r
+ HCLK(Hz) = 200000000\r
+ AHB Prescaler = 1\r
+ APB1 Prescaler = 4\r
+ APB2 Prescaler = 2\r
+ HSE Frequency(Hz) = 25000000\r
+ PLL_M = 25\r
+ PLL_N = 400\r
+ PLL_P = 2\r
+ PLL_Q = 7\r
+ VDD(V) = 3.3\r
+ Main regulator output voltage = Scale1 mode\r
+ Flash Latency(WS) = 7 */\r
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;\r
+ RCC_OscInitTypeDef RCC_OscInitStruct;\r
+\r
+ /* Enable HSE Oscillator and activate PLL with HSE as source */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r
+ RCC_OscInitStruct.PLL.PLLM = 25;\r
+ RCC_OscInitStruct.PLL.PLLN = 400;\r
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\r
+ RCC_OscInitStruct.PLL.PLLQ = 7;\r
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);\r
+\r
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2\r
+ clocks dividers */\r
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;\r
+ configASSERT( HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) == HAL_OK );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( uint32_t ulLine, const char *pcFile )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ ( void ) pcFile;\r
+ ( void ) ulLine;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ __NOP();\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 )\r
+ {\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Call the code that uses a mutex from an ISR. */\r
+ vInterruptSemaphorePeriodicTest();\r
+\r
+ /* Use a queue set from an ISR. */\r
+ vQueueSetAccessQueueSetFromISR();\r
+\r
+ /* Use task notifications from an ISR. */\r
+ xNotifyTaskFromISR();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\debugger\ST\STM32F4xx.dmac" --flash_loader "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\config\flashloader\ST\FlashSTM32F7xxx.board" --backend -B "--endian=little" "--cpu=Cortex-M7" "--fpu=VFPv5_sp" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\ST\STM32F7xxx.ddf" "--drv_verify_download" "--semihosting=none" "--device=STM32F7xxx" "--drv_communication=USB0" "--drv_interface_speed=auto" "--jlink_initial_speed=1000" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=0,0,2000000" \r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<crun>\r
+ <version>1</version>\r
+ <filter_entries>\r
+ <filter index="0" type="default">\r
+ <type>*</type>\r
+ <start_file>*</start_file>\r
+ <end_file>*</end_file>\r
+ <action_debugger>0</action_debugger>\r
+ <action_log>1</action_log>\r
+ </filter>\r
+ </filter_entries>\r
+</crun>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ <ColumnWidth0>20</ColumnWidth0>\r
+ <ColumnWidth1>1216</ColumnWidth1>\r
+ <ColumnWidth2>324</ColumnWidth2>\r
+ <ColumnWidth3>81</ColumnWidth3>\r
+ </Build>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>302</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <col-names>\r
+ \r
+ \r
+ <item>Disassembly</item><item>_I0</item></col-names>\r
+ <col-widths>\r
+ \r
+ \r
+ <item>500</item><item>20</item></col-widths>\r
+ <DisasmHistory/>\r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>\r
+ </Static>\r
+ <Windows>\r
+ \r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-17443-17461</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-16921-17471</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-28192-17464</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Blinky_Demo</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo/Common_Demo_Tasks</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>93</YPos2><SelStart2>6054</SelStart2><SelEnd2>6054</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>226</YPos2><SelStart2>11987</SelStart2><SelEnd2>11987</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Blinky_Demo\main_blinky.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>12</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\tasks.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>1570</YPos2><SelStart2>57257</SelStart2><SelEnd2>57276</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1\port.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>294</YPos2><SelStart2>13282</SelStart2><SelEnd2>13282</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\portable\IAR\ARM_CM7\r0p1\portasm.s</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>139</YPos2><SelStart2>5516</SelStart2><SelEnd2>5516</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\timers.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>397</YPos2><SelStart2>17641</SelStart2><SelEnd2>17641</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-026D8F98><key>iaridepm.enu1</key></Toolbar-026D8F98></Sizes></Row0><Row1><Sizes><Toolbar-1B29D7A8><key>debuggergui.enu1</key></Toolbar-1B29D7A8></Sizes></Row1></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>718</Bottom><Right>376</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>225000</sizeVertCX><sizeVertCY>731707</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd2></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Interrupts]\r
+Enabled=1\r
+[MemConfig]\r
+Base=1\r
+Manual=0\r
+Ddf=1\r
+TypeViol=0\r
+Stop=1\r
+[Trace1]\r
+Enabled=0\r
+ShowSource=1\r
+[Simulator]\r
+Freq=10000000\r
+MultiCoreRunAll=1\r
+[stlink]\r
+stlinkserialNo=2798FD0D\r
+stlinkfoundProbes=\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[SWOTraceHWSettings]\r
+OverrideDefaultClocks=0\r
+CpuClock=72000000\r
+ClockAutoDetect=1\r
+ClockWanted=2000000\r
+JtagSpeed=2000000\r
+Prescaler=36\r
+TimeStampPrescIndex=0\r
+TimeStampPrescData=0\r
+PcSampCYCTAP=1\r
+PcSampPOSTCNT=15\r
+PcSampIndex=0\r
+DataLogMode=0\r
+ITMportsEnable=0\r
+ITMportsTermIO=0\r
+ITMportsLogFile=0\r
+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[DebugChecksum]\r
+Checksum=785584338\r
+[CodeCoverage]\r
+Enabled=_ 0\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[JLinkDriver]\r
+CStepIntDis=_ 0\r
+[Trace2]\r
+Enabled=0\r
+ShowSource=0\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=0\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Bp0=_ 0 "EMUL_CODE" "{$PROJ_DIR$\Blinky_Demo\main_blinky.c}.179.2" 0 0 1 "" 0 "" 0\r
+Count=1\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>303</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <TerminalIO/>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ </Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-18739-8840</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/Portable</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-19869-16187</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab>\r
+ <Identity>TabID-13491-17330</Identity>\r
+ <TabName>Debug Log</TabName>\r
+ <Factory>Debug-Log</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>6054</SelStart2><SelEnd2>6054</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>64</YPos2><SelStart2>11987</SelStart2><SelEnd2>11987</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Blinky_Demo\main_blinky.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>66</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-026D8F98><key>iaridepm.enu1</key></Toolbar-026D8F98></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>619</Bottom><Right>377</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>225595</sizeVertCX><sizeVertCY>631098</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>321</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>323</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>328252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+[MainWindow]\r
+WindowPlacement=_ 16 0 1116 896 3\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file Template/stm32f7xx_hal_conf.h\r
+ * @author MCD Application Team\r
+ * @version V0.0.1\r
+ * @date 21-October-2014\r
+ * @brief HAL configuration template file. \r
+ * This file should be copied to the application folder and renamed\r
+ * to stm32f7xx_hal_conf.h.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CONF_H\r
+#define __STM32F7xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver \r
+ */\r
+#define HAL_MODULE_ENABLED \r
+#define HAL_ADC_MODULE_ENABLED \r
+#define HAL_CAN_MODULE_ENABLED\r
+#define HAL_CEC_MODULE_ENABLED \r
+#define HAL_CRC_MODULE_ENABLED \r
+#define HAL_CRYP_MODULE_ENABLED \r
+#define HAL_DAC_MODULE_ENABLED \r
+#define HAL_DCMI_MODULE_ENABLED \r
+#define HAL_DMA_MODULE_ENABLED\r
+#define HAL_DMA2D_MODULE_ENABLED \r
+//#define HAL_ETH_MODULE_ENABLED \r
+#define HAL_FLASH_MODULE_ENABLED \r
+//#define HAL_NAND_MODULE_ENABLED\r
+#define HAL_NOR_MODULE_ENABLED\r
+#define HAL_SRAM_MODULE_ENABLED\r
+#define HAL_SDRAM_MODULE_ENABLED\r
+#define HAL_HASH_MODULE_ENABLED \r
+#define HAL_GPIO_MODULE_ENABLED\r
+#define HAL_I2C_MODULE_ENABLED\r
+//#define HAL_I2S_MODULE_ENABLED \r
+//#define HAL_IWDG_MODULE_ENABLED \r
+#define HAL_LPTIM_MODULE_ENABLED\r
+#define HAL_LTDC_MODULE_ENABLED \r
+#define HAL_PWR_MODULE_ENABLED\r
+#define HAL_QSPI_MODULE_ENABLED \r
+#define HAL_RCC_MODULE_ENABLED \r
+#define HAL_RNG_MODULE_ENABLED \r
+#define HAL_RTC_MODULE_ENABLED\r
+//#define HAL_SAI_MODULE_ENABLED \r
+//#define HAL_SD_MODULE_ENABLED \r
+#define HAL_SPI_MODULE_ENABLED \r
+#define HAL_TIM_MODULE_ENABLED \r
+#define HAL_UART_MODULE_ENABLED \r
+#define HAL_USART_MODULE_ENABLED \r
+#define HAL_IRDA_MODULE_ENABLED \r
+#define HAL_SMARTCARD_MODULE_ENABLED \r
+//#define HAL_WWDG_MODULE_ENABLED \r
+#define HAL_CORTEX_MODULE_ENABLED\r
+//#define HAL_PCD_MODULE_ENABLED\r
+//#define HAL_HCD_MODULE_ENABLED\r
+\r
+/* ########################## HSE/HSI Values adaptation ##################### */\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief Internal Low Speed oscillator (LSI) value.\r
+ */\r
+#if !defined (LSI_VALUE) \r
+ #define LSI_VALUE ((uint32_t)40000) \r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+#endif /* LSE_VALUE */\r
+\r
+/**\r
+ * @brief External clock source for I2S peripheral\r
+ * This value is used by the I2S HAL module to compute the I2S clock source \r
+ * frequency, this source is inserted directly through I2S_CKIN pad. \r
+ */\r
+#if !defined (EXTERNAL_CLOCK_VALUE)\r
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* EXTERNAL_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */ \r
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */\r
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */\r
+#define USE_RTOS 0\r
+#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* ################## Ethernet peripheral configuration ##################### */\r
+\r
+/* Section 1 : Ethernet peripheral configuration */\r
+\r
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r
+#define MAC_ADDR0 2\r
+#define MAC_ADDR1 0\r
+#define MAC_ADDR2 0\r
+#define MAC_ADDR3 0\r
+#define MAC_ADDR4 0\r
+#define MAC_ADDR5 0\r
+\r
+/* Definition of the Ethernet driver buffers size and count */ \r
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */\r
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */\r
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */\r
+\r
+/* Section 2: PHY configuration section */\r
+\r
+/* DP83848 PHY Address*/ \r
+#define DP83848_PHY_ADDRESS 0x01\r
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)\r
+/* PHY Configuration delay */\r
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)\r
+\r
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)\r
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)\r
+\r
+/* Section 3: Common PHY Registers */\r
+\r
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */\r
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */\r
+ \r
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */\r
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */\r
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */\r
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */\r
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */\r
+\r
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */\r
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */\r
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */\r
+ \r
+/* Section 4: Extended PHY Registers */\r
+\r
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */\r
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */\r
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */\r
+ \r
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */\r
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */\r
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */\r
+\r
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */\r
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */\r
+\r
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */\r
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file \r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CAN_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_can.h"\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cec.h"\r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cryp.h" \r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_eth.h"\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sdram.h"\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CONF_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
#include "task.h"\r
#include "croutine.h"\r
\r
+/* Remove the whole file is co-routines are not being used. */\r
+#if( configUSE_CO_ROUTINES != 0 )\r
+\r
/*\r
* Some kernel aware debuggers require data to be viewed to be global, rather\r
* than file scope.\r
return xReturn;\r
}\r
\r
+#endif /* configUSE_CO_ROUTINES == 0 */\r
+\r
#error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
#endif\r
\r
-#ifndef configUSE_CO_ROUTINES\r
- #error Missing definition: configUSE_CO_ROUTINES must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
-#endif\r
-\r
#ifndef INCLUDE_vTaskPrioritySet\r
#error Missing definition: INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
#endif\r
#error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
#endif\r
\r
+#ifndef configMAX_PRIORITIES\r
+ #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\r
+#endif\r
+\r
+#ifndef configUSE_CO_ROUTINES\r
+ #define configUSE_CO_ROUTINES 0\r
+#endif\r
+\r
#if configUSE_CO_ROUTINES != 0\r
#ifndef configMAX_CO_ROUTINE_PRIORITIES\r
#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.\r
#endif\r
#endif\r
\r
-#ifndef configMAX_PRIORITIES\r
- #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\r
-#endif\r
-\r
#ifndef INCLUDE_xTaskGetIdleTaskHandle\r
#define INCLUDE_xTaskGetIdleTaskHandle 0\r
#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef __TI_VFP_SUPPORT__\r
+ #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
+#endif\r
+\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
+#endif\r
+\r
+/* Constants required to manipulate the core. Registers first... */\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+/* ...then bits in the registers. */\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+\r
+/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+setting. */\r
+const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortSysTickHandler( void );\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+extern void vPortStartFirstTask( void );\r
+\r
+/*\r
+ * Turn the VFP on.\r
+ */\r
+extern void vPortEnableVFP( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The number of SysTick increments that make up one tick period.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+\r
+ /* Offset added to account for the way the MCU uses the stack on entry/exit\r
+ of interrupts, and to ensure alignment. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
+\r
+ /* Save code space by skipping register initialisation. */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+\r
+ /* A save method is being used that requires each task to maintain its\r
+ own exec return value. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the lowest priority interrupts. */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Ensure the VFP is enabled - it should be anyway. */\r
+ vPortEnableVFP();\r
+\r
+ /* Lazy save always. */\r
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ configASSERT( uxCriticalNesting );\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known. */\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+ #pragma WEAK( vPortSuppressTicksAndSleep )\r
+ void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+ {\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ TickType_t xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __asm( " cpsid i" );\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_interrupt()\r
+ call above. */\r
+ __asm( " cpsie i" );\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __asm( " dsb" );\r
+ __asm( " wfi" );\r
+ __asm( " isb" );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Stop SysTick. Again, the time the SysTick is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
+ portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
+\r
+ /* Re-enable interrupts - see comments above __disable_interrupt()\r
+ call above. */\r
+ __asm( " cpsie i" );\r
+\r
+ if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt has already executed, and the SysTick\r
+ count reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be\r
+ processed as soon as this function exits, the tick value\r
+ maintained by the tick is stepped forward by one less than the\r
+ time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. The critical section is used to ensure the tick interrupt\r
+ can only execute once in the case that the reload register is near\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portENTER_CRITICAL();\r
+ {\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* #if configUSE_TICKLESS_IDLE */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+#pragma WEAK( vPortSetupTimerInterrupt )\r
+void vPortSetupTimerInterrupt( void )\r
+{\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ extern uint32_t ulPortGetIPSR( void );\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+\r
+ ulCurrentInterrupt = ulPortGetIPSR();\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+; All rights reserved\r
+;\r
+; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+;\r
+; ***************************************************************************\r
+; >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+; >>! distribute a combined work that includes FreeRTOS without being !<<\r
+; >>! obliged to provide the source code for proprietary components !<<\r
+; >>! outside of the FreeRTOS kernel. !<<\r
+; ***************************************************************************\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+; link: http://www.freertos.org/a00114.html\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS provides completely free yet professionally developed, *\r
+; * robust, strictly quality controlled, supported, and cross *\r
+; * platform software that is more than just the market leader, it *\r
+; * is the industry's de facto standard. *\r
+; * *\r
+; * Help yourself get started quickly while simultaneously helping *\r
+; * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+; * tutorial book, reference manual, or both: *\r
+; * http://www.FreeRTOS.org/Documentation *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+; the FAQ page "My application does not run, what could be wrong?". Have you\r
+; defined configASSERT()?\r
+;\r
+; http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+; embedded software for free we request you assist our global community by\r
+; participating in the support forum.\r
+;\r
+; http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+; be as productive as possible as early as possible. Now you can receive\r
+; FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+; Ltd, and the world's leading authority on the world's leading RTOS.\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+;\r
+; http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+; Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+; Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+; licenses offer ticketed support, indemnification and commercial middleware.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;\r
+; 1 tab == 4 spaces!\r
+;*/\r
+\r
+ .thumb\r
+\r
+ .ref pxCurrentTCB\r
+ .ref vTaskSwitchContext\r
+ .ref ulMaxSyscallInterruptPriority\r
+\r
+ .def xPortPendSVHandler\r
+ .def ulPortGetIPSR\r
+ .def vPortSVCHandler\r
+ .def vPortStartFirstTask\r
+ .def vPortEnableVFP\r
+\r
+NVICOffsetConst: .word 0xE000ED08\r
+CPACRConst: .word 0xE000ED88\r
+pxCurrentTCBConst: .word pxCurrentTCB\r
+ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority\r
+\r
+; -----------------------------------------------------------\r
+\r
+ .align 4\r
+ulPortGetIPSR: .asmfunc\r
+ mrs r0, ipsr\r
+ bx r14\r
+ .endasmfunc\r
+ ; -----------------------------------------------------------\r
+\r
+ .align 4\r
+vPortSetInterruptMask: .asmfunc\r
+ push {r0}\r
+ ldr r0, ulMaxSyscallInterruptPriorityConst\r
+ msr basepri, r0\r
+ pop {r0}\r
+ bx r14\r
+ .endasmfunc\r
+; -----------------------------------------------------------\r
+\r
+ .align 4\r
+xPortPendSVHandler: .asmfunc\r
+ mrs r0, psp\r
+ isb\r
+\r
+ ;/* Get the location of the current TCB. */\r
+ ldr r3, pxCurrentTCBConst\r
+ ldr r2, [r3]\r
+\r
+ ;/* Is the task using the FPU context? If so, push high vfp registers. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31}\r
+\r
+ ;/* Save the core registers. */\r
+ stmdb r0!, {r4-r11, r14}\r
+\r
+ ;/* Save the new top of stack into the first member of the TCB. */\r
+ str r0, [r2]\r
+\r
+ stmdb sp!, {r3}\r
+ ldr r0, ulMaxSyscallInterruptPriorityConst\r
+ ldr r1, [r0]\r
+ msr basepri, r1\r
+ dsb\r
+ isb\r
+ bl vTaskSwitchContext\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ ldmia sp!, {r3}\r
+\r
+ ;/* The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+\r
+ ;/* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+\r
+ ;/* Is the task using the FPU context? If so, pop the high vfp registers\r
+ ;too. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31}\r
+\r
+ msr psp, r0\r
+ isb\r
+ bx r14\r
+ .endasmfunc\r
+\r
+; -----------------------------------------------------------\r
+\r
+ .align 4\r
+vPortSVCHandler: .asmfunc\r
+ ;/* Get the location of the current TCB. */\r
+ ldr r3, pxCurrentTCBConst\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+ ;/* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+ msr psp, r0\r
+ isb\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ bx r14\r
+ .endasmfunc\r
+\r
+; -----------------------------------------------------------\r
+\r
+ .align 4\r
+vPortStartFirstTask: .asmfunc\r
+ ;/* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, NVICOffsetConst\r
+ ldr r0, [r0]\r
+ ldr r0, [r0]\r
+ ;/* Set the msp back to the start of the stack. */\r
+ msr msp, r0\r
+ ;/* Call SVC to start the first task. */\r
+ cpsie i\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc #0\r
+ .endasmfunc\r
+\r
+; -----------------------------------------------------------\r
+\r
+ .align 4\r
+vPortEnableVFP: .asmfunc\r
+ ;/* The FPU enable bits are in the CPACR. */\r
+ ldr.w r0, CPACRConst\r
+ ldr r1, [r0]\r
+\r
+ ;/* Enable CP10 and CP11 coprocessors, then save back. */\r
+ orr r1, r1, #( 0xf << 20 )\r
+ str r1, [r0]\r
+ bx r14\r
+ .endasmfunc\r
+\r
+ .end\r
+\r
+; -----------------------------------------------------------\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Scheduler utilities. */\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ __asm( " dsb" ); \\r
+ __asm( " isb" ); \\r
+}\r
+\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() \\r
+{ \\r
+ _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\r
+ __asm( " dsb" ); \\r
+ __asm( " isb" ); \\r
+}\r
+\r
+#define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( " isb" )\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) _set_interrupt_priority( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
#define portVECTACTIVE_MASK ( 0xFFUL )\r
\r
/* Constants required to manipulate the VFP. */\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
\r
/* Constants required to set up the initial stack. */\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
\r
/* The systick is a 24-bit counter. */\r
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
--- /dev/null
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\r
+The best option depends on the revision of the ARM Cortex-M7 core in use. The\r
+revision is specified by an 'r' number, and a 'p' number, so will look something\r
+like 'r0p1'. Check the documentation for the microcontroller in use to find the \r
+revision of the Cortex-M7 core used in that microcontroller. If in doubt, use \r
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used\r
+with all core revisions.\r
+\r
+The first option is to use the ARM Cortex-M4F port, and the second option is to\r
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\r
+\r
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\r
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \r
+the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.\r
+\r
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\r
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1\r
+directory.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef __VFP_FP__\r
+ #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
+#endif\r
+\r
+/* Constants required to manipulate the core. Registers first... */\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+/* ...then bits in the registers. */\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case is messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
+void xPortSysTickHandler( void );\r
+void vPortSVCHandler( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Function to enable the VFP.\r
+ */\r
+ static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The number of SysTick increments that make up one tick period.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+\r
+ /* Offset added to account for the way the MCU uses the stack on entry/exit\r
+ of interrupts, and to ensure alignment. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+\r
+ /* Save code space by skipping register initialisation. */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+\r
+ /* A save method is being used that requires each task to maintain its\r
+ own exec return value. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler( void )\r
+{\r
+ __asm volatile (\r
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */\r
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
+ " msr psp, r0 \n" /* Restore the task stack pointer. */\r
+ " isb \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPortStartFirstTask( void )\r
+{\r
+ __asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc 0 \n" /* System call to start first task. */\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the lowest priority interrupts. */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Ensure the VFP is enabled - it should be anyway. */\r
+ vPortEnableVFP();\r
+\r
+ /* Lazy save always. */\r
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+ /* Start the first task. */\r
+ prvPortStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing! Call the task\r
+ exit error function to prevent compiler warnings about a static function\r
+ not being called in the case that the application writer overrides this\r
+ functionality by defining configTASK_RETURN_ADDRESS. */\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ configASSERT( uxCriticalNesting );\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortPendSVHandler( void )\r
+{\r
+ /* This is a naked function. */\r
+\r
+ __asm volatile\r
+ (\r
+ " mrs r0, psp \n"\r
+ " isb \n"\r
+ " \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
+ " ldr r2, [r3] \n"\r
+ " \n"\r
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n"\r
+ " \n"\r
+ " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */\r
+ " \n"\r
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
+ " \n"\r
+ " stmdb sp!, {r3} \n"\r
+ " mov r0, %0 \n"\r
+ " cpsid i \n" /* Errata workaround. */\r
+ " msr basepri, r0 \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " cpsie i \n" /* Errata workaround. */\r
+ " bl vTaskSwitchContext \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " ldmia sp!, {r3} \n"\r
+ " \n"\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldr r0, [r1] \n"\r
+ " \n"\r
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */\r
+ " \n"\r
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n"\r
+ " \n"\r
+ " msr psp, r0 \n"\r
+ " isb \n"\r
+ " \n"\r
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r
+ #if WORKAROUND_PMU_CM001 == 1\r
+ " push { r14 } \n"\r
+ " pop { pc } \n"\r
+ #endif\r
+ #endif\r
+ " \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known. */\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+ {\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ TickType_t xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __asm volatile( "cpsid i" );\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "wfi" );\r
+ __asm volatile( "isb" );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Stop SysTick. Again, the time the SysTick is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
+ portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
+\r
+ if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt has already executed, and the SysTick\r
+ count reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be\r
+ processed as soon as this function exits, the tick value\r
+ maintained by the tick is stepped forward by one less than the\r
+ time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. The critical section is used to ensure the tick interrupt\r
+ can only execute once in the case that the reload register is near\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portENTER_CRITICAL();\r
+ {\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* #if configUSE_TICKLESS_IDLE */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
+{\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is a naked function. */\r
+static void vPortEnableVFP( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */\r
+ " ldr r1, [r0] \n"\r
+ " \n"\r
+ " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
+ " str r1, [r0] \n"\r
+ " bx r14 "\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Scheduler utilities. */\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ \\r
+ /* Barriers are normally not required but do ensure the code is completely \\r
+ within the specified behaviour for the architecture. */ \\r
+ __asm volatile( "dsb" ); \\r
+ __asm volatile( "isb" ); \\r
+}\r
+\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)\r
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Generic helper function. */\r
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\r
+ {\r
+ uint8_t ucReturn;\r
+\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ return ucReturn;\r
+ }\r
+\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline))\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI;\r
+\r
+ __asm volatile\r
+ (\r
+ " mov %0, %1 \n" \\r
+ " cpsid i \n" \\r
+ " msr basepri, %0 \n" \\r
+ " isb \n" \\r
+ " dsb \n" \\r
+ " cpsie i \n" \\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\r
+\r
+ __asm volatile\r
+ (\r
+ " mrs %0, basepri \n" \\r
+ " mov %1, %2 \n" \\r
+ " cpsid i \n" \\r
+ " msr basepri, %1 \n" \\r
+ " isb \n" \\r
+ " dsb \n" \\r
+ " cpsie i \n" \\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ );\r
+\r
+ /* This return will not be reached but is necessary to prevent compiler\r
+ warnings. */\r
+ return ulOriginalBASEPRI;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
*/\r
BaseType_t xPortStartScheduler( void )\r
{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
1 tab == 4 spaces!\r
*/\r
\r
-\r
#ifndef PORTMACRO_H\r
#define PORTMACRO_H\r
\r
--- /dev/null
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\r
+The best option depends on the revision of the ARM Cortex-M7 core in use. The\r
+revision is specified by an 'r' number, and a 'p' number, so will look something\r
+like 'r0p1'. Check the documentation for the microcontroller in use to find the \r
+revision of the Cortex-M7 core used in that microcontroller. If in doubt, use \r
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used\r
+with all core revisions.\r
+\r
+The first option is to use the ARM Cortex-M4F port, and the second option is to\r
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\r
+\r
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\r
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \r
+the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.\r
+\r
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\r
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1\r
+directory.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Compiler includes. */\r
+#include <intrinsics.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef __ARMVFP__\r
+ #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
+#endif\r
+\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
+#endif\r
+\r
+/* Constants required to manipulate the core. Registers first... */\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+/* ...then bits in the registers. */\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortSysTickHandler( void );\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+extern void vPortStartFirstTask( void );\r
+\r
+/*\r
+ * Turn the VFP on.\r
+ */\r
+extern void vPortEnableVFP( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The number of SysTick increments that make up one tick period.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+\r
+ /* Offset added to account for the way the MCU uses the stack on entry/exit\r
+ of interrupts, and to ensure alignment. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
+\r
+ /* Save code space by skipping register initialisation. */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+\r
+ /* A save method is being used that requires each task to maintain its\r
+ own exec return value. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the lowest priority interrupts. */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Ensure the VFP is enabled - it should be anyway. */\r
+ vPortEnableVFP();\r
+\r
+ /* Lazy save always. */\r
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+ /* Start the first task. */\r
+ vPortStartFirstTask();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ configASSERT( uxCriticalNesting );\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known. */\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+ __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+ {\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ TickType_t xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __disable_interrupt();\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_interrupt()\r
+ call above. */\r
+ __enable_interrupt();\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __DSB();\r
+ __WFI();\r
+ __ISB();\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Stop SysTick. Again, the time the SysTick is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
+ portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
+\r
+ /* Re-enable interrupts - see comments above __disable_interrupt()\r
+ call above. */\r
+ __enable_interrupt();\r
+\r
+ if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt has already executed, and the SysTick\r
+ count reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be\r
+ processed as soon as this function exits, the tick value\r
+ maintained by the tick is stepped forward by one less than the\r
+ time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. The critical section is used to ensure the tick interrupt\r
+ can only execute once in the case that the reload register is near\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portENTER_CRITICAL();\r
+ {\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* #if configUSE_TICKLESS_IDLE */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+__weak void vPortSetupTimerInterrupt( void )\r
+{\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if( configUSE_TICKLESS_IDLE == 1 )\r
+ {\r
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#include <FreeRTOSConfig.h>\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+\r
+ PUBLIC xPortPendSVHandler\r
+ PUBLIC vPortSVCHandler\r
+ PUBLIC vPortStartFirstTask\r
+ PUBLIC vPortEnableVFP\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xPortPendSVHandler:\r
+ mrs r0, psp\r
+ isb\r
+ /* Get the location of the current TCB. */\r
+ ldr r3, =pxCurrentTCB\r
+ ldr r2, [r3]\r
+\r
+ /* Is the task using the FPU context? If so, push high vfp registers. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31}\r
+\r
+ /* Save the core registers. */\r
+ stmdb r0!, {r4-r11, r14}\r
+\r
+ /* Save the new top of stack into the first member of the TCB. */\r
+ str r0, [r2]\r
+\r
+ stmdb sp!, {r3}\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ cpsid i\r
+ msr basepri, r0\r
+ dsb\r
+ isb\r
+ cpsie i\r
+ bl vTaskSwitchContext\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ ldmia sp!, {r3}\r
+\r
+ /* The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+\r
+ /* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+\r
+ /* Is the task using the FPU context? If so, pop the high vfp registers\r
+ too. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31}\r
+\r
+ msr psp, r0\r
+ isb\r
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\r
+ #if WORKAROUND_PMU_CM001 == 1\r
+ push { r14 }\r
+ pop { pc }\r
+ #endif\r
+ #endif\r
+\r
+ bx r14\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortSVCHandler:\r
+ /* Get the location of the current TCB. */\r
+ ldr r3, =pxCurrentTCB\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+ /* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+ msr psp, r0\r
+ isb\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ bx r14\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortStartFirstTask\r
+ /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, =0xE000ED08\r
+ ldr r0, [r0]\r
+ ldr r0, [r0]\r
+ /* Set the msp back to the start of the stack. */\r
+ msr msp, r0\r
+ /* Call SVC to start the first task. */\r
+ cpsie i\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortEnableVFP:\r
+ /* The FPU enable bits are in the CPACR. */\r
+ ldr.w r0, =0xE000ED88\r
+ ldr r1, [r0]\r
+\r
+ /* Enable CP10 and CP11 coprocessors, then save back. */\r
+ orr r1, r1, #( 0xf << 20 )\r
+ str r1, [r0]\r
+ bx r14\r
+\r
+\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Scheduler utilities. */\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ __DSB(); \\r
+ __ISB(); \\r
+}\r
+\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #include <intrinsics.h>\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() \\r
+{ \\r
+ /* Errata work around. */ \\r
+ __disable_interrupt(); \\r
+ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \\r
+ __DSB(); \\r
+ __ISB(); \\r
+ __enable_interrupt(); \\r
+}\r
+\r
+#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\r
+the source code because to do so would cause other compilers to generate\r
+warnings. */\r
+#pragma diag_suppress=Pe191\r
+#pragma diag_suppress=Pa082\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
\r
/* The size of the structure placed at the beginning of each allocated memory\r
block must by correctly byte aligned. */\r
-static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );\r
+static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( ( ( size_t ) portBYTE_ALIGNMENT_MASK ) - ( size_t ) 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );\r
\r
/* Create a couple of list links to mark the start and end of the list. */\r
static BlockLink_t xStart, *pxEnd = NULL;\r
if( ( ulAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\r
{\r
ulAddress += ( portBYTE_ALIGNMENT - 1 );\r
- ulAddress &= ~portBYTE_ALIGNMENT_MASK;\r
+ ulAddress &= ~( ( uint32_t ) portBYTE_ALIGNMENT_MASK );\r
xTotalHeapSize -= ulAddress - ( uint32_t ) ucHeap;\r
}\r
\r
at the end of the heap space. */\r
ulAddress = ( ( uint32_t ) pucAlignedHeap ) + xTotalHeapSize;\r
ulAddress -= xHeapStructSize;\r
- ulAddress &= ~portBYTE_ALIGNMENT_MASK;\r
+ ulAddress &= ~( ( uint32_t ) portBYTE_ALIGNMENT_MASK );\r
pxEnd = ( void * ) ulAddress;\r
pxEnd->xBlockSize = 0;\r
pxEnd->pxNextFreeBlock = NULL;\r
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
\r
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\r
+r0p1 port. */\r
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\r
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )\r
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )\r
+\r
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
\r
*/\r
BaseType_t xPortStartScheduler( void )\r
{\r
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
+\r
+ /* This port can be used on all revisions of the Cortex-M7 core other than\r
+ the r0p1 parts. r0p1 parts should use the port from the\r
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\r
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\r
+\r
#if( configASSERT_DEFINED == 1 )\r
{\r
volatile uint32_t ulOriginalPriority;\r
/* Read the value back to see how many bits stuck. */\r
ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
\r
+ /* The kernel interrupt priority should be set to the lowest\r
+ priority. */\r
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\r
+\r
/* Use the same mask on the maximum system call priority. */\r
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
\r
--- /dev/null
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.\r
+The best option depends on the revision of the ARM Cortex-M7 core in use. The\r
+revision is specified by an 'r' number, and a 'p' number, so will look something\r
+like 'r0p1'. Check the documentation for the microcontroller in use to find the \r
+revision of the Cortex-M7 core used in that microcontroller. If in doubt, use \r
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used\r
+with all core revisions.\r
+\r
+The first option is to use the ARM Cortex-M4F port, and the second option is to\r
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.\r
+\r
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be\r
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in \r
+the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.\r
+\r
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM\r
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1\r
+directory.
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM4F port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef __TARGET_FPU_VFP\r
+ #error This port can only be used when the project options are configured to enable hardware floating point support.\r
+#endif\r
+\r
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
+#endif\r
+\r
+#ifndef configSYSTICK_CLOCK_HZ\r
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
+ /* Ensure the SysTick is clocked at the same frequency as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#else\r
+ /* The way the SysTick is clocked is not modified in case it is not the same\r
+ as the core. */\r
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )\r
+#endif\r
+\r
+/* The __weak attribute does not work as you might expect with the Keil tools\r
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if\r
+the application writer wants to provide their own implementation of\r
+vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+is defined. */\r
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION\r
+ #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0\r
+#endif\r
+\r
+/* Constants required to manipulate the core. Registers first... */\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+/* ...then bits in the registers. */\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )\r
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )\r
+\r
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
+\r
+/* Constants required to check the validity of an interrupt priority. */\r
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )\r
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )\r
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )\r
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )\r
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )\r
+#define portPRIGROUP_SHIFT ( 8UL )\r
+\r
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
+#define portVECTACTIVE_MASK ( 0xFFUL )\r
+\r
+/* Constants required to manipulate the VFP. */\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+#define portINITIAL_EXEC_RETURN ( 0xfffffffd )\r
+\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#define portMISSED_COUNTS_FACTOR ( 45UL )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortPendSVHandler( void );\r
+void xPortSysTickHandler( void );\r
+void vPortSVCHandler( void );\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+static void prvStartFirstTask( void );\r
+\r
+/*\r
+ * Functions defined in portasm.s to enable the VFP.\r
+ */\r
+static void prvEnableVFP( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The number of SysTick increments that make up one tick period.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if configUSE_TICKLESS_IDLE == 1\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
+ * FreeRTOS API functions are not called from interrupts that have been assigned\r
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ */\r
+#if ( configASSERT_DEFINED == 1 )\r
+ static uint8_t ucMaxSysCallPriority = 0;\r
+ static uint32_t ulMaxPRIGROUPValue = 0;\r
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
+#endif /* configASSERT_DEFINED */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+\r
+ /* Offset added to account for the way the MCU uses the stack on entry/exit\r
+ of interrupts, and to ensure alignment. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */\r
+\r
+ /* Save code space by skipping register initialisation. */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+\r
+ /* A save method is being used that requires each task to maintain its\r
+ own exec return value. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
+\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( uxCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vPortSVCHandler( void )\r
+{\r
+ PRESERVE8\r
+\r
+ /* Get the location of the current TCB. */\r
+ ldr r3, =pxCurrentTCB\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+ /* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+ msr psp, r0\r
+ isb\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvStartFirstTask( void )\r
+{\r
+ PRESERVE8\r
+\r
+ /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, =0xE000ED08\r
+ ldr r0, [r0]\r
+ ldr r0, [r0]\r
+ /* Set the msp back to the start of the stack. */\r
+ msr msp, r0\r
+ /* Globally enable interrupts. */\r
+ cpsie i\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ /* Call SVC to start the first task. */\r
+ svc 0\r
+ nop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void prvEnableVFP( void )\r
+{\r
+ PRESERVE8\r
+\r
+ /* The FPU enable bits are in the CPACR. */\r
+ ldr.w r0, =0xE000ED88\r
+ ldr r1, [r0]\r
+\r
+ /* Enable CP10 and CP11 coprocessors, then save back. */\r
+ orr r1, r1, #( 0xf << 20 )\r
+ str r1, [r0]\r
+ bx r14\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine the maximum priority from which ISR safe FreeRTOS API\r
+ functions can be called. ISR safe functions are those that end in\r
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to\r
+ ensure interrupt entry is as fast and simple as possible.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to all\r
+ possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* The kernel interrupt priority should be set to the lowest \r
+ priority. */\r
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );\r
+ \r
+ /* Use the same mask on the maximum system call priority. */\r
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
+\r
+ /* Calculate the maximum acceptable priority group value for the number\r
+ of bits read back. */\r
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
+ {\r
+ ulMaxPRIGROUPValue--;\r
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Shift the priority group value back to its position within the AIRCR\r
+ register. */\r
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+ /* Make PendSV and SysTick the lowest priority interrupts. */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Ensure the VFP is enabled - it should be anyway. */\r
+ prvEnableVFP();\r
+\r
+ /* Lazy save always. */\r
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
+\r
+ /* Start the first task. */\r
+ prvStartFirstTask();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( uxCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( uxCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ configASSERT( uxCriticalNesting );\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void xPortPendSVHandler( void )\r
+{\r
+ extern uxCriticalNesting;\r
+ extern pxCurrentTCB;\r
+ extern vTaskSwitchContext;\r
+\r
+ PRESERVE8\r
+\r
+ mrs r0, psp\r
+ isb\r
+ /* Get the location of the current TCB. */\r
+ ldr r3, =pxCurrentTCB\r
+ ldr r2, [r3]\r
+\r
+ /* Is the task using the FPU context? If so, push high vfp registers. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31}\r
+\r
+ /* Save the core registers. */\r
+ stmdb r0!, {r4-r11, r14}\r
+\r
+ /* Save the new top of stack into the first member of the TCB. */\r
+ str r0, [r2]\r
+\r
+ stmdb sp!, {r3}\r
+ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ cpsid i\r
+ msr basepri, r0\r
+ dsb\r
+ isb\r
+ cpsie i\r
+ bl vTaskSwitchContext\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ ldmia sp!, {r3}\r
+\r
+ /* The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+\r
+ /* Pop the core registers. */\r
+ ldmia r0!, {r4-r11, r14}\r
+\r
+ /* Is the task using the FPU context? If so, pop the high vfp registers\r
+ too. */\r
+ tst r14, #0x10\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31}\r
+\r
+ msr psp, r0\r
+ isb\r
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */\r
+ #if WORKAROUND_PMU_CM001 == 1\r
+ push { r14 }\r
+ pop { pc }\r
+ nop\r
+ #endif\r
+ #endif\r
+\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
+ executes all interrupts must be unmasked. There is therefore no need to\r
+ save and then restore the interrupt mask value as its value is already\r
+ known. */\r
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TICKLESS_IDLE == 1\r
+\r
+ __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+ {\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
+ TickType_t xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __disable_irq();\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __dsb( portSY_FULL_READ_WRITE );\r
+ __wfi();\r
+ __isb( portSY_FULL_READ_WRITE );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Stop SysTick. Again, the time the SysTick is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
+ portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
+\r
+ /* Re-enable interrupts - see comments above __disable_irq() call\r
+ above. */\r
+ __enable_irq();\r
+\r
+ if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt has already executed, and the SysTick\r
+ count reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be\r
+ processed as soon as this function exits, the tick value\r
+ maintained by the tick is stepped forward by one less than the\r
+ time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. The critical section is used to ensure the tick interrupt\r
+ can only execute once in the case that the reload register is near\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portENTER_CRITICAL();\r
+ {\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* #if configUSE_TICKLESS_IDLE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the SysTick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0\r
+\r
+ void vPortSetupTimerInterrupt( void )\r
+ {\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if configUSE_TICKLESS_IDLE == 1\r
+ {\r
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
+ }\r
+\r
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm uint32_t vPortGetIPSR( void )\r
+{\r
+ PRESERVE8\r
+\r
+ mrs r0, ipsr\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ uint32_t ulCurrentInterrupt;\r
+ uint8_t ucCurrentPriority;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ ulCurrentInterrupt = vPortGetIPSR();\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
+ and therefore also guaranteed to be invalid.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ If the application only uses CMSIS libraries for interrupt\r
+ configuration then the correct setting can be achieved on all Cortex-M\r
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
+ scheduler. Note however that some vendor specific peripheral libraries\r
+ assume a non-zero priority group setting, in which cases using a value\r
+ of zero will result in unpredicable behaviour. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+\r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE ( 15 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Scheduler utilities. */\r
+#define portYIELD() \\r
+{ \\r
+ /* Set a PendSV to request a context switch. */ \\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \\r
+ \\r
+ /* Barriers are normally not required but do ensure the code is completely \\r
+ within the specified behaviour for the architecture. */ \\r
+ __dsb( portSY_FULL_READ_WRITE ); \\r
+ __isb( portSY_FULL_READ_WRITE ); \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section management. */\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()\r
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Tickless idle/low power functionality. */\r
+#ifndef portSUPPRESS_TICKS_AND_SLEEP\r
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Port specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )\r
+\r
+#endif /* taskRECORD_READY_PRIORITY */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE __forceinline\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\r
+{\r
+ __asm\r
+ {\r
+ /* Barrier instructions are not used as this function is only used to\r
+ lower the BASEPRI value. */\r
+ msr basepri, ulBASEPRI\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ cpsid i\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ cpsie i\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
+\r
+ __asm\r
+ {\r
+ /* Set BASEPRI to the max syscall priority to effect a critical\r
+ section. */\r
+ mrs ulReturn, basepri\r
+ cpsid i\r
+ msr basepri, ulNewBASEPRI\r
+ dsb\r
+ isb\r
+ cpsie i\r
+ }\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
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